drivers/net/wireless/wl12xx/wl1271_spi.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2009 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/crc7.h>
  27 #include <linux/spi/spi.h>
  28
  29 #include "wl1271.h"
  30 #include "wl12xx_80211.h"
  31 #include "wl1271_spi.h"
  32
  33 static int wl1271_translate_addr(struct wl1271 *wl, int addr)
  34 {
  35         /*
  36          * To translate, first check to which window of addresses the
  37          * particular address belongs. Then subtract the starting address
  38          * of that window from the address. Then, add offset of the
  39          * translated region.
  40          *
  41          * The translated regions occur next to each other in physical device
  42          * memory, so just add the sizes of the preceeding address regions to
  43          * get the offset to the new region.
  44          *
  45          * Currently, only the two first regions are addressed, and the
  46          * assumption is that all addresses will fall into either of those
  47          * two.
  48          */
  49         if ((addr >= wl->part.reg.start) &&
  50             (addr < wl->part.reg.start + wl->part.reg.size))
  51                 return addr - wl->part.reg.start + wl->part.mem.size;
  52         else
  53                 return addr - wl->part.mem.start;
  54 }
  55
  56 void wl1271_spi_reset(struct wl1271 *wl)
  57 {
  58         u8 *cmd;
  59         struct spi_transfer t;
  60         struct spi_message m;
  61
  62         cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
  63         if (!cmd) {
  64                 wl1271_error("could not allocate cmd for spi reset");
  65                 return;
  66         }
  67
  68         memset(&t, 0, sizeof(t));
  69         spi_message_init(&m);
  70
  71         memset(cmd, 0xff, WSPI_INIT_CMD_LEN);
  72
  73         t.tx_buf = cmd;
  74         t.len = WSPI_INIT_CMD_LEN;
  75         spi_message_add_tail(&t, &m);
  76
  77         spi_sync(wl->spi, &m);
  78
  79         wl1271_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
  80 }
  81
  82 void wl1271_spi_init(struct wl1271 *wl)
  83 {
  84         u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
  85         struct spi_transfer t;
  86         struct spi_message m;
  87
  88         cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
  89         if (!cmd) {
  90                 wl1271_error("could not allocate cmd for spi init");
  91                 return;
  92         }
  93
  94         memset(crc, 0, sizeof(crc));
  95         memset(&t, 0, sizeof(t));
  96         spi_message_init(&m);
  97
  98         /*
  99          * Set WSPI_INIT_COMMAND
 100          * the data is being send from the MSB to LSB
 101          */
 102         cmd[2] = 0xff;
 103         cmd[3] = 0xff;
 104         cmd[1] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
 105         cmd[0] = 0;
 106         cmd[7] = 0;
 107         cmd[6] |= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
 108         cmd[6] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
 109
 110         if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
 111                 cmd[5] |=  WSPI_INIT_CMD_DIS_FIXEDBUSY;
 112         else
 113                 cmd[5] |= WSPI_INIT_CMD_EN_FIXEDBUSY;
 114
 115         cmd[5] |= WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
 116                 | WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;
 117
 118         crc[0] = cmd[1];
 119         crc[1] = cmd[0];
 120         crc[2] = cmd[7];
 121         crc[3] = cmd[6];
 122         crc[4] = cmd[5];
 123
 124         cmd[4] |= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
 125         cmd[4] |= WSPI_INIT_CMD_END;
 126
 127         t.tx_buf = cmd;
 128         t.len = WSPI_INIT_CMD_LEN;
 129         spi_message_add_tail(&t, &m);
 130
 131         spi_sync(wl->spi, &m);
 132
 133         wl1271_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
 134 }
 135
 136 /* Set the SPI partitions to access the chip addresses
 137  *
 138  * To simplify driver code, a fixed (virtual) memory map is defined for
 139  * register and memory addresses. Because in the chipset, in different stages
 140  * of operation, those addresses will move around, an address translation
 141  * mechanism is required.
 142  *
 143  * There are four partitions (three memory and one register partition),
 144  * which are mapped to two different areas of the hardware memory.
 145  *
 146  *                                Virtual address
 147  *                                     space
 148  *
 149  *                                    |    |
 150  *                                 ...+----+--> mem.start
 151  *          Physical address    ...   |    |
 152  *               space       ...      |    | [PART_0]
 153  *                        ...         |    |
 154  *  00000000  <--+----+...         ...+----+--> mem.start + mem.size
 155  *               |    |         ...   |    |
 156  *               |MEM |      ...      |    |
 157  *               |    |   ...         |    |
 158  *  mem.size  <--+----+...            |    | {unused area)
 159  *               |    |   ...         |    |
 160  *               |REG |      ...      |    |
 161  *  mem.size     |    |         ...   |    |
 162  *      +     <--+----+...         ...+----+--> reg.start
 163  *  reg.size     |    |   ...         |    |
 164  *               |MEM2|      ...      |    | [PART_1]
 165  *               |    |         ...   |    |
 166  *                                 ...+----+--> reg.start + reg.size
 167  *                                    |    |
 168  *
 169  */
 170 int wl1271_set_partition(struct wl1271 *wl,
 171                          struct wl1271_partition_set *p)
 172 {
 173         /* copy partition info */
 174         memcpy(&wl->part, p, sizeof(*p));
 175
 176         wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
 177                      p->mem.start, p->mem.size);
 178         wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
 179                      p->reg.start, p->reg.size);
 180         wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
 181                      p->mem2.start, p->mem2.size);
 182         wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
 183                      p->mem3.start, p->mem3.size);
 184
 185         /* write partition info to the chipset */
 186         wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
 187         wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
 188         wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
 189         wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
 190         wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
 191         wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
 192         wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
 193
 194         return 0;
 195 }
 196
 197 #define WL1271_BUSY_WORD_TIMEOUT 1000
 198
 199 void wl1271_spi_read_busy(struct wl1271 *wl, void *buf, size_t len)
 200 {
 201         struct spi_transfer t[1];
 202         struct spi_message m;
 203         u32 *busy_buf;
 204         int num_busy_bytes = 0;
 205
 206         wl1271_info("spi read BUSY!");
 207
 208         /*
 209          * Look for the non-busy word in the read buffer, and if found,
 210          * read in the remaining data into the buffer.
 211          */
 212         busy_buf = (u32 *)buf;
 213         for (; (u32)busy_buf < (u32)buf + len; busy_buf++) {
 214                 num_busy_bytes += sizeof(u32);
 215                 if (*busy_buf & 0x1) {
 216                         spi_message_init(&m);
 217                         memset(t, 0, sizeof(t));
 218                         memmove(buf, busy_buf, len - num_busy_bytes);
 219                         t[0].rx_buf = buf + (len - num_busy_bytes);
 220                         t[0].len = num_busy_bytes;
 221                         spi_message_add_tail(&t[0], &m);
 222                         spi_sync(wl->spi, &m);
 223                         return;
 224                 }
 225         }
 226
 227         /*
 228          * Read further busy words from SPI until a non-busy word is
 229          * encountered, then read the data itself into the buffer.
 230          */
 231         wl1271_info("spi read BUSY-polling needed!");
 232
 233         num_busy_bytes = WL1271_BUSY_WORD_TIMEOUT;
 234         busy_buf = wl->buffer_busyword;
 235         while (num_busy_bytes) {
 236                 num_busy_bytes--;
 237                 spi_message_init(&m);
 238                 memset(t, 0, sizeof(t));
 239                 t[0].rx_buf = busy_buf;
 240                 t[0].len = sizeof(u32);
 241                 spi_message_add_tail(&t[0], &m);
 242                 spi_sync(wl->spi, &m);
 243
 244                 if (*busy_buf & 0x1) {
 245                         spi_message_init(&m);
 246                         memset(t, 0, sizeof(t));
 247                         t[0].rx_buf = buf;
 248                         t[0].len = len;
 249                         spi_message_add_tail(&t[0], &m);
 250                         spi_sync(wl->spi, &m);
 251                         return;
 252                 }
 253         }
 254
 255         /* The SPI bus is unresponsive, the read failed. */
 256         memset(buf, 0, len);
 257         wl1271_error("SPI read busy-word timeout!\n");
 258 }
 259
 260 void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf,
 261                          size_t len, bool fixed)
 262 {
 263         struct spi_transfer t[3];
 264         struct spi_message m;
 265         u32 *busy_buf;
 266         u32 *cmd;
 267
 268         cmd = &wl->buffer_cmd;
 269         busy_buf = wl->buffer_busyword;
 270
 271         *cmd = 0;
 272         *cmd |= WSPI_CMD_READ;
 273         *cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
 274         *cmd |= addr & WSPI_CMD_BYTE_ADDR;
 275
 276         if (fixed)
 277                 *cmd |= WSPI_CMD_FIXED;
 278
 279         spi_message_init(&m);
 280         memset(t, 0, sizeof(t));
 281
 282         t[0].tx_buf = cmd;
 283         t[0].len = 4;
 284         spi_message_add_tail(&t[0], &m);
 285
 286         /* Busy and non busy words read */
 287         t[1].rx_buf = busy_buf;
 288         t[1].len = WL1271_BUSY_WORD_LEN;
 289         spi_message_add_tail(&t[1], &m);
 290
 291         t[2].rx_buf = buf;
 292         t[2].len = len;
 293         spi_message_add_tail(&t[2], &m);
 294
 295         spi_sync(wl->spi, &m);
 296
 297         /* Check busy words */
 298         if (!(busy_buf[WL1271_BUSY_WORD_CNT - 1] & 0x1))
 299                 wl1271_spi_read_busy(wl, buf, len);
 300
 301         wl1271_dump(DEBUG_SPI, "spi_read cmd -> ", cmd, sizeof(*cmd));
 302         wl1271_dump(DEBUG_SPI, "spi_read buf <- ", buf, len);
 303 }
 304
 305 void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf,
 306                           size_t len, bool fixed)
 307 {
 308         struct spi_transfer t[2];
 309         struct spi_message m;
 310         u32 *cmd;
 311
 312         cmd = &wl->buffer_cmd;
 313
 314         *cmd = 0;
 315         *cmd |= WSPI_CMD_WRITE;
 316         *cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
 317         *cmd |= addr & WSPI_CMD_BYTE_ADDR;
 318
 319         if (fixed)
 320                 *cmd |= WSPI_CMD_FIXED;
 321
 322         spi_message_init(&m);
 323         memset(t, 0, sizeof(t));
 324
 325         t[0].tx_buf = cmd;
 326         t[0].len = sizeof(*cmd);
 327         spi_message_add_tail(&t[0], &m);
 328
 329         t[1].tx_buf = buf;
 330         t[1].len = len;
 331         spi_message_add_tail(&t[1], &m);
 332
 333         spi_sync(wl->spi, &m);
 334
 335         wl1271_dump(DEBUG_SPI, "spi_write cmd -> ", cmd, sizeof(*cmd));
 336         wl1271_dump(DEBUG_SPI, "spi_write buf -> ", buf, len);
 337 }
 338
 339 void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
 340                      bool fixed)
 341 {
 342         int physical;
 343
 344         physical = wl1271_translate_addr(wl, addr);
 345
 346         wl1271_spi_raw_read(wl, physical, buf, len, fixed);
 347 }
 348
 349 void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
 350                       bool fixed)
 351 {
 352         int physical;
 353
 354         physical = wl1271_translate_addr(wl, addr);
 355
 356         wl1271_spi_raw_write(wl, physical, buf, len, fixed);
 357 }
 358
 359 u32 wl1271_spi_read32(struct wl1271 *wl, int addr)
 360 {
 361         return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr));
 362 }
 363
 364 void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val)
 365 {
 366         wl1271_raw_write32(wl, wl1271_translate_addr(wl, addr), val);
 367 }
 368
 369 void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
 370 {
 371         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 372         addr = (addr >> 1) + 0x30000;
 373         wl1271_spi_write32(wl, OCP_POR_CTR, addr);
 374
 375         /* write value to OCP_POR_WDATA */
 376         wl1271_spi_write32(wl, OCP_DATA_WRITE, val);
 377
 378         /* write 1 to OCP_CMD */
 379         wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_WRITE);
 380 }
 381
 382 u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
 383 {
 384         u32 val;
 385         int timeout = OCP_CMD_LOOP;
 386
 387         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 388         addr = (addr >> 1) + 0x30000;
 389         wl1271_spi_write32(wl, OCP_POR_CTR, addr);
 390
 391         /* write 2 to OCP_CMD */
 392         wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_READ);
 393
 394         /* poll for data ready */
 395         do {
 396                 val = wl1271_spi_read32(wl, OCP_DATA_READ);
 397                 timeout--;
 398         } while (!(val & OCP_READY_MASK) && timeout);
 399
 400         if (!timeout) {
 401                 wl1271_warning("Top register access timed out.");
 402                 return 0xffff;
 403         }
 404
 405         /* check data status and return if OK */
 406         if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
 407                 return val & 0xffff;
 408         else {
 409                 wl1271_warning("Top register access returned error.");
 410                 return 0xffff;
 411         }
 412 }