drivers/staging/et131x/et1310_phy.c

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright * 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_phy.c - Routines for configuring and accessing the PHY
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright * 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #include "et131x_version.h"
  59 #include "et131x_defs.h"
  60
  61 #include <linux/pci.h>
  62 #include <linux/init.h>
  63 #include <linux/module.h>
  64 #include <linux/types.h>
  65 #include <linux/kernel.h>
  66
  67 #include <linux/sched.h>
  68 #include <linux/ptrace.h>
  69 #include <linux/slab.h>
  70 #include <linux/ctype.h>
  71 #include <linux/string.h>
  72 #include <linux/timer.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/in.h>
  75 #include <linux/delay.h>
  76 #include <linux/io.h>
  77 #include <linux/bitops.h>
  78 #include <asm/system.h>
  79
  80 #include <linux/netdevice.h>
  81 #include <linux/etherdevice.h>
  82 #include <linux/skbuff.h>
  83 #include <linux/if_arp.h>
  84 #include <linux/ioport.h>
  85 #include <linux/random.h>
  86
  87 #include "et1310_phy.h"
  88 #include "et1310_pm.h"
  89 #include "et1310_jagcore.h"
  90
  91 #include "et131x_adapter.h"
  92 #include "et131x_netdev.h"
  93 #include "et131x_initpci.h"
  94
  95 #include "et1310_address_map.h"
  96 #include "et1310_tx.h"
  97 #include "et1310_rx.h"
  98 #include "et1310_mac.h"
  99
 100 /* Prototypes for functions with local scope */
 101 static int et131x_xcvr_init(struct et131x_adapter *adapter);
 102
 103 /**
 104  * PhyMiRead - Read from the PHY through the MII Interface on the MAC
 105  * @adapter: pointer to our private adapter structure
 106  * @xcvrAddr: the address of the transciever
 107  * @xcvrReg: the register to read
 108  * @value: pointer to a 16-bit value in which the value will be stored
 109  *
 110  * Returns 0 on success, errno on failure (as defined in errno.h)
 111  */
 112 int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
 113               uint8_t xcvrReg, uint16_t *value)
 114 {
 115         struct _MAC_t __iomem *mac = &adapter->regs->mac;
 116         int status = 0;
 117         uint32_t delay;
 118         MII_MGMT_ADDR_t miiAddr;
 119         MII_MGMT_CMD_t miiCmd;
 120         MII_MGMT_INDICATOR_t miiIndicator;
 121
 122         /* Save a local copy of the registers we are dealing with so we can
 123          * set them back
 124          */
 125         miiAddr.value = readl(&mac->mii_mgmt_addr.value);
 126         miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
 127
 128         /* Stop the current operation */
 129         writel(0, &mac->mii_mgmt_cmd.value);
 130
 131         /* Set up the register we need to read from on the correct PHY */
 132         {
 133                 MII_MGMT_ADDR_t mii_mgmt_addr = { 0 };
 134
 135                 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
 136                 mii_mgmt_addr.bits.reg_addr = xcvrReg;
 137                 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
 138         }
 139
 140         /* Kick the read cycle off */
 141         delay = 0;
 142
 143         writel(0x1, &mac->mii_mgmt_cmd.value);
 144
 145         do {
 146                 udelay(50);
 147                 delay++;
 148                 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
 149         } while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) &&
 150                  delay < 50);
 151
 152         /* If we hit the max delay, we could not read the register */
 153         if (delay >= 50) {
 154                 dev_warn(&adapter->pdev->dev,
 155                             "xcvrReg 0x%08x could not be read\n", xcvrReg);
 156                 dev_warn(&adapter->pdev->dev, "status is  0x%08x\n",
 157                             miiIndicator.value);
 158
 159                 status = -EIO;
 160         }
 161
 162         /* If we hit here we were able to read the register and we need to
 163          * return the value to the caller
 164          */
 165         /* TODO: make this stuff a simple readw()?! */
 166         {
 167                 MII_MGMT_STAT_t mii_mgmt_stat;
 168
 169                 mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value);
 170                 *value = (uint16_t) mii_mgmt_stat.bits.phy_stat;
 171         }
 172
 173         /* Stop the read operation */
 174         writel(0, &mac->mii_mgmt_cmd.value);
 175
 176         /* set the registers we touched back to the state at which we entered
 177          * this function
 178          */
 179         writel(miiAddr.value, &mac->mii_mgmt_addr.value);
 180         writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
 181
 182         return status;
 183 }
 184
 185 /**
 186  * MiWrite - Write to a PHY register through the MII interface of the MAC
 187  * @adapter: pointer to our private adapter structure
 188  * @xcvrReg: the register to read
 189  * @value: 16-bit value to write
 190  *
 191  * Return 0 on success, errno on failure (as defined in errno.h)
 192  */
 193 int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
 194 {
 195         struct _MAC_t __iomem *mac = &adapter->regs->mac;
 196         int status = 0;
 197         uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
 198         uint32_t delay;
 199         MII_MGMT_ADDR_t miiAddr;
 200         MII_MGMT_CMD_t miiCmd;
 201         MII_MGMT_INDICATOR_t miiIndicator;
 202
 203         /* Save a local copy of the registers we are dealing with so we can
 204          * set them back
 205          */
 206         miiAddr.value = readl(&mac->mii_mgmt_addr.value);
 207         miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
 208
 209         /* Stop the current operation */
 210         writel(0, &mac->mii_mgmt_cmd.value);
 211
 212         /* Set up the register we need to write to on the correct PHY */
 213         {
 214                 MII_MGMT_ADDR_t mii_mgmt_addr;
 215
 216                 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
 217                 mii_mgmt_addr.bits.reg_addr = xcvrReg;
 218                 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
 219         }
 220
 221         /* Add the value to write to the registers to the mac */
 222         writel(value, &mac->mii_mgmt_ctrl.value);
 223         delay = 0;
 224
 225         do {
 226                 udelay(50);
 227                 delay++;
 228                 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
 229         } while (miiIndicator.bits.busy && delay < 100);
 230
 231         /* If we hit the max delay, we could not write the register */
 232         if (delay == 100) {
 233                 uint16_t TempValue;
 234
 235                 dev_warn(&adapter->pdev->dev,
 236                     "xcvrReg 0x%08x could not be written", xcvrReg);
 237                 dev_warn(&adapter->pdev->dev, "status is  0x%08x\n",
 238                             miiIndicator.value);
 239                 dev_warn(&adapter->pdev->dev, "command is  0x%08x\n",
 240                             readl(&mac->mii_mgmt_cmd.value));
 241
 242                 MiRead(adapter, xcvrReg, &TempValue);
 243
 244                 status = -EIO;
 245         }
 246
 247         /* Stop the write operation */
 248         writel(0, &mac->mii_mgmt_cmd.value);
 249
 250         /* set the registers we touched back to the state at which we entered
 251          * this function
 252          */
 253         writel(miiAddr.value, &mac->mii_mgmt_addr.value);
 254         writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
 255
 256         return status;
 257 }
 258
 259 /**
 260  * et131x_xcvr_find - Find the PHY ID
 261  * @adapter: pointer to our private adapter structure
 262  *
 263  * Returns 0 on success, errno on failure (as defined in errno.h)
 264  */
 265 int et131x_xcvr_find(struct et131x_adapter *adapter)
 266 {
 267         int status = -ENODEV;
 268         uint8_t xcvr_addr;
 269         MI_IDR1_t idr1;
 270         MI_IDR2_t idr2;
 271         uint32_t xcvr_id;
 272
 273         /* We need to get xcvr id and address we just get the first one */
 274         for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
 275                 /* Read the ID from the PHY */
 276                 PhyMiRead(adapter, xcvr_addr,
 277                           (uint8_t) offsetof(MI_REGS_t, idr1),
 278                           &idr1.value);
 279                 PhyMiRead(adapter, xcvr_addr,
 280                           (uint8_t) offsetof(MI_REGS_t, idr2),
 281                           &idr2.value);
 282
 283                 xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value);
 284
 285                 if ((idr1.value != 0) && (idr1.value != 0xffff)) {
 286                         adapter->Stats.xcvr_id = xcvr_id;
 287                         adapter->Stats.xcvr_addr = xcvr_addr;
 288
 289                         status = 0;
 290                         break;
 291                 }
 292         }
 293         return status;
 294 }
 295
 296 /**
 297  * et131x_setphy_normal - Set PHY for normal operation.
 298  * @adapter: pointer to our private adapter structure
 299  *
 300  * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
 301  * when going to D3 in WOL mode. Also used during initialization to set the
 302  * PHY for normal operation.
 303  */
 304 int et131x_setphy_normal(struct et131x_adapter *adapter)
 305 {
 306         int status;
 307
 308         /* Make sure the PHY is powered up */
 309         ET1310_PhyPowerDown(adapter, 0);
 310         status = et131x_xcvr_init(adapter);
 311         return status;
 312 }
 313
 314 /**
 315  * et131x_xcvr_init - Init the phy if we are setting it into force mode
 316  * @adapter: pointer to our private adapter structure
 317  *
 318  * Returns 0 on success, errno on failure (as defined in errno.h)
 319  */
 320 static int et131x_xcvr_init(struct et131x_adapter *adapter)
 321 {
 322         int status = 0;
 323         MI_IMR_t imr;
 324         MI_ISR_t isr;
 325         MI_LCR2_t lcr2;
 326
 327         /* Zero out the adapter structure variable representing BMSR */
 328         adapter->Bmsr.value = 0;
 329
 330         MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value);
 331
 332         MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value);
 333
 334         /* Set the link status interrupt only.  Bad behavior when link status
 335          * and auto neg are set, we run into a nested interrupt problem
 336          */
 337         imr.bits.int_en = 0x1;
 338         imr.bits.link_status = 0x1;
 339         imr.bits.autoneg_status = 0x1;
 340
 341         MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value);
 342
 343         /* Set the LED behavior such that LED 1 indicates speed (off =
 344          * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
 345          * link and activity (on for link, blink off for activity).
 346          *
 347          * NOTE: Some customizations have been added here for specific
 348          * vendors; The LED behavior is now determined by vendor data in the
 349          * EEPROM. However, the above description is the default.
 350          */
 351         if ((adapter->eepromData[1] & 0x4) == 0) {
 352                 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
 353                        &lcr2.value);
 354                 if ((adapter->eepromData[1] & 0x8) == 0)
 355                         lcr2.bits.led_tx_rx = 0x3;
 356                 else
 357                         lcr2.bits.led_tx_rx = 0x4;
 358                 lcr2.bits.led_link = 0xa;
 359                 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
 360                         lcr2.value);
 361         }
 362
 363         /* Determine if we need to go into a force mode and set it */
 364         if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) {
 365                 if ((adapter->RegistryFlowControl == TxOnly) ||
 366                     (adapter->RegistryFlowControl == Both)) {
 367                         ET1310_PhyAccessMiBit(adapter,
 368                                               TRUEPHY_BIT_SET, 4, 11, NULL);
 369                 } else {
 370                         ET1310_PhyAccessMiBit(adapter,
 371                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 372                 }
 373
 374                 if (adapter->RegistryFlowControl == Both) {
 375                         ET1310_PhyAccessMiBit(adapter,
 376                                               TRUEPHY_BIT_SET, 4, 10, NULL);
 377                 } else {
 378                         ET1310_PhyAccessMiBit(adapter,
 379                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 380                 }
 381
 382                 /* Set the phy to autonegotiation */
 383                 ET1310_PhyAutoNeg(adapter, true);
 384
 385                 /* NOTE - Do we need this? */
 386                 ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
 387                 return status;
 388         } else {
 389                 ET1310_PhyAutoNeg(adapter, false);
 390
 391                 /* Set to the correct force mode. */
 392                 if (adapter->AiForceDpx != 1) {
 393                         if ((adapter->RegistryFlowControl == TxOnly) ||
 394                             (adapter->RegistryFlowControl == Both)) {
 395                                 ET1310_PhyAccessMiBit(adapter,
 396                                                       TRUEPHY_BIT_SET, 4, 11,
 397                                                       NULL);
 398                         } else {
 399                                 ET1310_PhyAccessMiBit(adapter,
 400                                                       TRUEPHY_BIT_CLEAR, 4, 11,
 401                                                       NULL);
 402                         }
 403
 404                         if (adapter->RegistryFlowControl == Both) {
 405                                 ET1310_PhyAccessMiBit(adapter,
 406                                                       TRUEPHY_BIT_SET, 4, 10,
 407                                                       NULL);
 408                         } else {
 409                                 ET1310_PhyAccessMiBit(adapter,
 410                                                       TRUEPHY_BIT_CLEAR, 4, 10,
 411                                                       NULL);
 412                         }
 413                 } else {
 414                         ET1310_PhyAccessMiBit(adapter,
 415                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 416                         ET1310_PhyAccessMiBit(adapter,
 417                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 418                 }
 419
 420                 switch (adapter->AiForceSpeed) {
 421                 case 10:
 422                         if (adapter->AiForceDpx == 1)
 423                                 TPAL_SetPhy10HalfDuplex(adapter);
 424                         else if (adapter->AiForceDpx == 2)
 425                                 TPAL_SetPhy10FullDuplex(adapter);
 426                         else
 427                                 TPAL_SetPhy10Force(adapter);
 428                         break;
 429                 case 100:
 430                         if (adapter->AiForceDpx == 1)
 431                                 TPAL_SetPhy100HalfDuplex(adapter);
 432                         else if (adapter->AiForceDpx == 2)
 433                                 TPAL_SetPhy100FullDuplex(adapter);
 434                         else
 435                                 TPAL_SetPhy100Force(adapter);
 436                         break;
 437                 case 1000:
 438                         TPAL_SetPhy1000FullDuplex(adapter);
 439                         break;
 440                 }
 441
 442                 return status;
 443         }
 444 }
 445
 446 void et131x_Mii_check(struct et131x_adapter *etdev,
 447                       MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
 448 {
 449         uint8_t link_status;
 450         uint32_t autoneg_status;
 451         uint32_t speed;
 452         uint32_t duplex;
 453         uint32_t mdi_mdix;
 454         uint32_t masterslave;
 455         uint32_t polarity;
 456         unsigned long flags;
 457
 458         if (bmsr_ints.bits.link_status) {
 459                 if (bmsr.bits.link_status) {
 460                         etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
 461
 462                         /* Update our state variables and indicate the
 463                          * connected state
 464                          */
 465                         spin_lock_irqsave(&etdev->Lock, flags);
 466
 467                         etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
 468                         etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
 469
 470                         spin_unlock_irqrestore(&etdev->Lock, flags);
 471
 472                         /* Don't indicate state if we're in loopback mode */
 473                         if (etdev->RegistryPhyLoopbk == false)
 474                                 netif_carrier_on(etdev->netdev);
 475                 } else {
 476                         dev_warn(&etdev->pdev->dev,
 477                             "Link down - cable problem ?\n");
 478
 479                         if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
 480                                 /* NOTE - Is there a way to query this without
 481                                  * TruePHY?
 482                                  * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
 483                                  */
 484                                 uint16_t Register18;
 485
 486                                 MiRead(etdev, 0x12, &Register18);
 487                                 MiWrite(etdev, 0x12, Register18 | 0x4);
 488                                 MiWrite(etdev, 0x10, Register18 | 0x8402);
 489                                 MiWrite(etdev, 0x11, Register18 | 511);
 490                                 MiWrite(etdev, 0x12, Register18);
 491                         }
 492
 493                         /* For the first N seconds of life, we are in "link
 494                          * detection" When we are in this state, we should
 495                          * only report "connected". When the LinkDetection
 496                          * Timer expires, we can report disconnected (handled
 497                          * in the LinkDetectionDPC).
 498                          */
 499                         if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
 500                           (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
 501                                 spin_lock_irqsave(&etdev->Lock, flags);
 502                                 etdev->MediaState =
 503                                     NETIF_STATUS_MEDIA_DISCONNECT;
 504                                 spin_unlock_irqrestore(&etdev->Lock,
 505                                                        flags);
 506
 507                                 /* Only indicate state if we're in loopback
 508                                  * mode
 509                                  */
 510                                 if (etdev->RegistryPhyLoopbk == false)
 511                                         netif_carrier_off(etdev->netdev);
 512                         }
 513
 514                         etdev->linkspeed = 0;
 515                         etdev->duplex_mode = 0;
 516
 517                         /* Free the packets being actively sent & stopped */
 518                         et131x_free_busy_send_packets(etdev);
 519
 520                         /* Re-initialize the send structures */
 521                         et131x_init_send(etdev);
 522
 523                         /* Reset the RFD list and re-start RU */
 524                         et131x_reset_recv(etdev);
 525
 526                         /*
 527                          * Bring the device back to the state it was during
 528                          * init prior to autonegotiation being complete. This
 529                          * way, when we get the auto-neg complete interrupt,
 530                          * we can complete init by calling ConfigMacREGS2.
 531                          */
 532                         et131x_soft_reset(etdev);
 533
 534                         /* Setup ET1310 as per the documentation */
 535                         et131x_adapter_setup(etdev);
 536
 537                         /* Setup the PHY into coma mode until the cable is
 538                          * plugged back in
 539                          */
 540                         if (etdev->RegistryPhyComa == 1)
 541                                 EnablePhyComa(etdev);
 542                 }
 543         }
 544
 545         if (bmsr_ints.bits.auto_neg_complete ||
 546             (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
 547                 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
 548                         ET1310_PhyLinkStatus(etdev,
 549                                              &link_status, &autoneg_status,
 550                                              &speed, &duplex, &mdi_mdix,
 551                                              &masterslave, &polarity);
 552
 553                         etdev->linkspeed = speed;
 554                         etdev->duplex_mode = duplex;
 555
 556                         etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
 557
 558                         if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
 559                                 /*
 560                                  * NOTE - Is there a way to query this without
 561                                  * TruePHY?
 562                                  * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
 563                                  */
 564                                 uint16_t Register18;
 565
 566                                 MiRead(etdev, 0x12, &Register18);
 567                                 MiWrite(etdev, 0x12, Register18 | 0x4);
 568                                 MiWrite(etdev, 0x10, Register18 | 0x8402);
 569                                 MiWrite(etdev, 0x11, Register18 | 511);
 570                                 MiWrite(etdev, 0x12, Register18);
 571                         }
 572
 573                         ConfigFlowControl(etdev);
 574
 575                         if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
 576                                         etdev->RegistryJumboPacket > 2048)
 577                                 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
 578                                                                    0x2000);
 579
 580                         SetRxDmaTimer(etdev);
 581                         ConfigMACRegs2(etdev);
 582                 }
 583         }
 584 }
 585
 586 /**
 587  * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
 588  * @etdev: pointer to the adapter structure
 589  *
 590  * Also sets the MAC so it is syncd up properly
 591  */
 592 void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *etdev)
 593 {
 594         /* Power down PHY */
 595         ET1310_PhyPowerDown(etdev, 1);
 596
 597         /* First we need to turn off all other advertisement */
 598         ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 599
 600         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 601
 602         /* Set our advertise values accordingly */
 603         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF);
 604
 605         /* Power up PHY */
 606         ET1310_PhyPowerDown(etdev, 0);
 607 }
 608
 609 /**
 610  * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode.
 611  * @etdev: pointer to the adapter structure
 612  *
 613  * Also sets the MAC so it is syncd up properly
 614  */
 615 void TPAL_SetPhy10FullDuplex(struct et131x_adapter *etdev)
 616 {
 617         /* Power down PHY */
 618         ET1310_PhyPowerDown(etdev, 1);
 619
 620         /* First we need to turn off all other advertisement */
 621         ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 622
 623         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 624
 625         /* Set our advertise values accordingly */
 626         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
 627
 628         /* Power up PHY */
 629         ET1310_PhyPowerDown(etdev, 0);
 630 }
 631
 632 /**
 633  * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
 634  * @etdev: pointer to the adapter structure
 635  */
 636 void TPAL_SetPhy10Force(struct et131x_adapter *etdev)
 637 {
 638         /* Power down PHY */
 639         ET1310_PhyPowerDown(etdev, 1);
 640
 641         /* Disable autoneg */
 642         ET1310_PhyAutoNeg(etdev, false);
 643
 644         /* Disable all advertisement */
 645         ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 646         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 647         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 648
 649         /* Force 10 Mbps */
 650         ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
 651
 652         /* Force Full duplex */
 653         ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
 654
 655         /* Power up PHY */
 656         ET1310_PhyPowerDown(etdev, 0);
 657 }
 658
 659 /**
 660  * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode.
 661  * @etdev: pointer to the adapter structure
 662  *
 663  * Also sets the MAC so it is syncd up properly.
 664  */
 665 void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *etdev)
 666 {
 667         /* Power down PHY */
 668         ET1310_PhyPowerDown(etdev, 1);
 669
 670         /* first we need to turn off all other advertisement */
 671         ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 672
 673         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 674
 675         /* Set our advertise values accordingly */
 676         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF);
 677
 678         /* Set speed */
 679         ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
 680
 681         /* Power up PHY */
 682         ET1310_PhyPowerDown(etdev, 0);
 683 }
 684
 685 /**
 686  * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode.
 687  * @etdev: pointer to the adapter structure
 688  *
 689  * Also sets the MAC so it is syncd up properly
 690  */
 691 void TPAL_SetPhy100FullDuplex(struct et131x_adapter *etdev)
 692 {
 693         /* Power down PHY */
 694         ET1310_PhyPowerDown(etdev, 1);
 695
 696         /* First we need to turn off all other advertisement */
 697         ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 698
 699         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 700
 701         /* Set our advertise values accordingly */
 702         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
 703
 704         /* Power up PHY */
 705         ET1310_PhyPowerDown(etdev, 0);
 706 }
 707
 708 /**
 709  * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
 710  * @etdev: pointer to the adapter structure
 711  */
 712 void TPAL_SetPhy100Force(struct et131x_adapter *etdev)
 713 {
 714         /* Power down PHY */
 715         ET1310_PhyPowerDown(etdev, 1);
 716
 717         /* Disable autoneg */
 718         ET1310_PhyAutoNeg(etdev, false);
 719
 720         /* Disable all advertisement */
 721         ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 722         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 723         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 724
 725         /* Force 100 Mbps */
 726         ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
 727
 728         /* Force Full duplex */
 729         ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
 730
 731         /* Power up PHY */
 732         ET1310_PhyPowerDown(etdev, 0);
 733 }
 734
 735 /**
 736  * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode
 737  * @etdev: pointer to the adapter structure
 738  *
 739  * Also sets the MAC so it is syncd up properly.
 740  */
 741 void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *etdev)
 742 {
 743         /* Power down PHY */
 744         ET1310_PhyPowerDown(etdev, 1);
 745
 746         /* first we need to turn off all other advertisement */
 747         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 748
 749         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 750
 751         /* set our advertise values accordingly */
 752         ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
 753
 754         /* power up PHY */
 755         ET1310_PhyPowerDown(etdev, 0);
 756 }
 757
 758 /**
 759  * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
 760  * @etdev: pointer to the adapter structure
 761  */
 762 void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev)
 763 {
 764         /* Power down PHY */
 765         ET1310_PhyPowerDown(etdev, 1);
 766
 767         /* Turn on advertisement of all capabilities */
 768         ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH);
 769
 770         ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH);
 771
 772         if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
 773                 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
 774         else
 775                 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 776
 777         /* Make sure auto-neg is ON (it is disabled in FORCE modes) */
 778         ET1310_PhyAutoNeg(etdev, true);
 779
 780         /* Power up PHY */
 781         ET1310_PhyPowerDown(etdev, 0);
 782 }
 783
 784
 785 /*
 786  * The routines which follow provide low-level access to the PHY, and are used
 787  * primarily by the routines above (although there are a few places elsewhere
 788  * in the driver where this level of access is required).
 789  */
 790
 791 static const uint16_t ConfigPhy[25][2] = {
 792         /* Reg      Value      Register */
 793         /* Addr                         */
 794         {0x880B, 0x0926},       /* AfeIfCreg4B1000Msbs */
 795         {0x880C, 0x0926},       /* AfeIfCreg4B100Msbs */
 796         {0x880D, 0x0926},       /* AfeIfCreg4B10Msbs */
 797
 798         {0x880E, 0xB4D3},       /* AfeIfCreg4B1000Lsbs */
 799         {0x880F, 0xB4D3},       /* AfeIfCreg4B100Lsbs */
 800         {0x8810, 0xB4D3},       /* AfeIfCreg4B10Lsbs */
 801
 802         {0x8805, 0xB03E},       /* AfeIfCreg3B1000Msbs */
 803         {0x8806, 0xB03E},       /* AfeIfCreg3B100Msbs */
 804         {0x8807, 0xFF00},       /* AfeIfCreg3B10Msbs */
 805
 806         {0x8808, 0xE090},       /* AfeIfCreg3B1000Lsbs */
 807         {0x8809, 0xE110},       /* AfeIfCreg3B100Lsbs */
 808         {0x880A, 0x0000},       /* AfeIfCreg3B10Lsbs */
 809
 810         {0x300D, 1},            /* DisableNorm */
 811
 812         {0x280C, 0x0180},       /* LinkHoldEnd */
 813
 814         {0x1C21, 0x0002},       /* AlphaM */
 815
 816         {0x3821, 6},            /* FfeLkgTx0 */
 817         {0x381D, 1},            /* FfeLkg1g4 */
 818         {0x381E, 1},            /* FfeLkg1g5 */
 819         {0x381F, 1},            /* FfeLkg1g6 */
 820         {0x3820, 1},            /* FfeLkg1g7 */
 821
 822         {0x8402, 0x01F0},       /* Btinact */
 823         {0x800E, 20},           /* LftrainTime */
 824         {0x800F, 24},           /* DvguardTime */
 825         {0x8010, 46},           /* IdlguardTime */
 826
 827         {0, 0}
 828
 829 };
 830
 831 /* condensed version of the phy initialization routine */
 832 void ET1310_PhyInit(struct et131x_adapter *etdev)
 833 {
 834         uint16_t data, index;
 835
 836         if (etdev == NULL)
 837                 return;
 838
 839         /* get the identity (again ?) */
 840         MiRead(etdev, PHY_ID_1, &data);
 841         MiRead(etdev, PHY_ID_2, &data);
 842
 843         /* what does this do/achieve ? */
 844         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
 845         MiWrite(etdev, PHY_MPHY_CONTROL_REG,    0x0006);
 846
 847         /* read modem register 0402, should I do something with the return
 848            data ? */
 849         MiWrite(etdev, PHY_INDEX_REG, 0x0402);
 850         MiRead(etdev, PHY_DATA_REG, &data);
 851
 852         /* what does this do/achieve ? */
 853         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
 854
 855         /* get the identity (again ?) */
 856         MiRead(etdev, PHY_ID_1, &data);
 857         MiRead(etdev, PHY_ID_2, &data);
 858
 859         /* what does this achieve ? */
 860         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
 861         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
 862
 863         /* read modem register 0402, should I do something with
 864            the return data? */
 865         MiWrite(etdev, PHY_INDEX_REG, 0x0402);
 866         MiRead(etdev, PHY_DATA_REG, &data);
 867
 868         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
 869
 870         /* what does this achieve (should return 0x1040) */
 871         MiRead(etdev, PHY_CONTROL, &data);
 872         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
 873         MiWrite(etdev, PHY_CONTROL, 0x1840);
 874
 875         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
 876
 877         /* here the writing of the array starts.... */
 878         index = 0;
 879         while (ConfigPhy[index][0] != 0x0000) {
 880                 /* write value */
 881                 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
 882                 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
 883
 884                 /* read it back */
 885                 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
 886                 MiRead(etdev, PHY_DATA_REG, &data);
 887
 888                 /* do a check on the value read back ? */
 889                 index++;
 890         }
 891         /* here the writing of the array ends... */
 892
 893         MiRead(etdev, PHY_CONTROL, &data);              /* 0x1840 */
 894         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
 895         MiWrite(etdev, PHY_CONTROL, 0x1040);
 896         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
 897 }
 898
 899 void ET1310_PhyReset(struct et131x_adapter *etdev)
 900 {
 901         MiWrite(etdev, PHY_CONTROL, 0x8000);
 902 }
 903
 904 void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
 905 {
 906         uint16_t data;
 907
 908         MiRead(etdev, PHY_CONTROL, &data);
 909
 910         if (down == false) {
 911                 /* Power UP */
 912                 data &= ~0x0800;
 913                 MiWrite(etdev, PHY_CONTROL, data);
 914         } else {
 915                 /* Power DOWN */
 916                 data |= 0x0800;
 917                 MiWrite(etdev, PHY_CONTROL, data);
 918         }
 919 }
 920
 921 void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
 922 {
 923         uint16_t data;
 924
 925         MiRead(etdev, PHY_CONTROL, &data);
 926
 927         if (enable == true) {
 928                 /* Autonegotiation ON */
 929                 data |= 0x1000;
 930                 MiWrite(etdev, PHY_CONTROL, data);
 931         } else {
 932                 /* Autonegotiation OFF */
 933                 data &= ~0x1000;
 934                 MiWrite(etdev, PHY_CONTROL, data);
 935         }
 936 }
 937
 938 void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, uint16_t duplex)
 939 {
 940         uint16_t data;
 941
 942         MiRead(etdev, PHY_CONTROL, &data);
 943
 944         if (duplex == TRUEPHY_DUPLEX_FULL) {
 945                 /* Set Full Duplex */
 946                 data |= 0x100;
 947                 MiWrite(etdev, PHY_CONTROL, data);
 948         } else {
 949                 /* Set Half Duplex */
 950                 data &= ~0x100;
 951                 MiWrite(etdev, PHY_CONTROL, data);
 952         }
 953 }
 954
 955 void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, uint16_t speed)
 956 {
 957         uint16_t data;
 958
 959         /* Read the PHY control register */
 960         MiRead(etdev, PHY_CONTROL, &data);
 961
 962         /* Clear all Speed settings (Bits 6, 13) */
 963         data &= ~0x2040;
 964
 965         /* Reset the speed bits based on user selection */
 966         switch (speed) {
 967         case TRUEPHY_SPEED_10MBPS:
 968                 /* Bits already cleared above, do nothing */
 969                 break;
 970
 971         case TRUEPHY_SPEED_100MBPS:
 972                 /* 100M == Set bit 13 */
 973                 data |= 0x2000;
 974                 break;
 975
 976         case TRUEPHY_SPEED_1000MBPS:
 977         default:
 978                 data |= 0x0040;
 979                 break;
 980         }
 981
 982         /* Write back the new speed */
 983         MiWrite(etdev, PHY_CONTROL, data);
 984 }
 985
 986 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
 987                                   uint16_t duplex)
 988 {
 989         uint16_t data;
 990
 991         /* Read the PHY 1000 Base-T Control Register */
 992         MiRead(etdev, PHY_1000_CONTROL, &data);
 993
 994         /* Clear Bits 8,9 */
 995         data &= ~0x0300;
 996
 997         switch (duplex) {
 998         case TRUEPHY_ADV_DUPLEX_NONE:
 999                 /* Duplex already cleared, do nothing */
1000                 break;
1001
1002         case TRUEPHY_ADV_DUPLEX_FULL:
1003                 /* Set Bit 9 */
1004                 data |= 0x0200;
1005                 break;
1006
1007         case TRUEPHY_ADV_DUPLEX_HALF:
1008                 /* Set Bit 8 */
1009                 data |= 0x0100;
1010                 break;
1011
1012         case TRUEPHY_ADV_DUPLEX_BOTH:
1013         default:
1014                 data |= 0x0300;
1015                 break;
1016         }
1017
1018         /* Write back advertisement */
1019         MiWrite(etdev, PHY_1000_CONTROL, data);
1020 }
1021
1022 void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
1023                                  uint16_t duplex)
1024 {
1025         uint16_t data;
1026
1027         /* Read the Autonegotiation Register (10/100) */
1028         MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
1029
1030         /* Clear bits 7,8 */
1031         data &= ~0x0180;
1032
1033         switch (duplex) {
1034         case TRUEPHY_ADV_DUPLEX_NONE:
1035                 /* Duplex already cleared, do nothing */
1036                 break;
1037
1038         case TRUEPHY_ADV_DUPLEX_FULL:
1039                 /* Set Bit 8 */
1040                 data |= 0x0100;
1041                 break;
1042
1043         case TRUEPHY_ADV_DUPLEX_HALF:
1044                 /* Set Bit 7 */
1045                 data |= 0x0080;
1046                 break;
1047
1048         case TRUEPHY_ADV_DUPLEX_BOTH:
1049         default:
1050                 /* Set Bits 7,8 */
1051                 data |= 0x0180;
1052                 break;
1053         }
1054
1055         /* Write back advertisement */
1056         MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
1057 }
1058
1059 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
1060                                 uint16_t duplex)
1061 {
1062         uint16_t data;
1063
1064         /* Read the Autonegotiation Register (10/100) */
1065         MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
1066
1067         /* Clear bits 5,6 */
1068         data &= ~0x0060;
1069
1070         switch (duplex) {
1071         case TRUEPHY_ADV_DUPLEX_NONE:
1072                 /* Duplex already cleared, do nothing */
1073                 break;
1074
1075         case TRUEPHY_ADV_DUPLEX_FULL:
1076                 /* Set Bit 6 */
1077                 data |= 0x0040;
1078                 break;
1079
1080         case TRUEPHY_ADV_DUPLEX_HALF:
1081                 /* Set Bit 5 */
1082                 data |= 0x0020;
1083                 break;
1084
1085         case TRUEPHY_ADV_DUPLEX_BOTH:
1086         default:
1087                 /* Set Bits 5,6 */
1088                 data |= 0x0060;
1089                 break;
1090         }
1091
1092         /* Write back advertisement */
1093         MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
1094 }
1095
1096 void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
1097                           uint8_t *link_status,
1098                           uint32_t *autoneg,
1099                           uint32_t *linkspeed,
1100                           uint32_t *duplex_mode,
1101                           uint32_t *mdi_mdix,
1102                           uint32_t *masterslave, uint32_t *polarity)
1103 {
1104         uint16_t mistatus = 0;
1105         uint16_t is1000BaseT = 0;
1106         uint16_t vmi_phystatus = 0;
1107         uint16_t control = 0;
1108
1109         MiRead(etdev, PHY_STATUS, &mistatus);
1110         MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
1111         MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
1112         MiRead(etdev, PHY_CONTROL, &control);
1113
1114         if (link_status) {
1115                 *link_status =
1116                     (unsigned char)((vmi_phystatus & 0x0040) ? 1 : 0);
1117         }
1118
1119         if (autoneg) {
1120                 *autoneg =
1121                     (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
1122                                             TRUEPHY_ANEG_COMPLETE :
1123                                             TRUEPHY_ANEG_NOT_COMPLETE) :
1124                     TRUEPHY_ANEG_DISABLED;
1125         }
1126
1127         if (linkspeed)
1128                 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
1129
1130         if (duplex_mode)
1131                 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
1132
1133         if (mdi_mdix)
1134                 /* NOTE: Need to complete this */
1135                 *mdi_mdix = 0;
1136
1137         if (masterslave) {
1138                 *masterslave =
1139                     (is1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
1140                     TRUEPHY_CFG_SLAVE;
1141         }
1142
1143         if (polarity) {
1144                 *polarity =
1145                     (vmi_phystatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
1146                     TRUEPHY_POLARITY_NORMAL;
1147         }
1148 }
1149
1150 void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
1151                         uint16_t regnum, uint16_t andMask, uint16_t orMask)
1152 {
1153         uint16_t reg;
1154
1155         /* Read the requested register */
1156         MiRead(etdev, regnum, &reg);
1157
1158         /* Apply the AND mask */
1159         reg &= andMask;
1160
1161         /* Apply the OR mask */
1162         reg |= orMask;
1163
1164         /* Write the value back to the register */
1165         MiWrite(etdev, regnum, reg);
1166 }
1167
1168 void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, uint16_t action,
1169                            uint16_t regnum, uint16_t bitnum, uint8_t *value)
1170 {
1171         uint16_t reg;
1172         uint16_t mask = 0;
1173
1174         /* Create a mask to isolate the requested bit */
1175         mask = 0x0001 << bitnum;
1176
1177         /* Read the requested register */
1178         MiRead(etdev, regnum, &reg);
1179
1180         switch (action) {
1181         case TRUEPHY_BIT_READ:
1182                 if (value != NULL)
1183                         *value = (reg & mask) >> bitnum;
1184                 break;
1185
1186         case TRUEPHY_BIT_SET:
1187                 reg |= mask;
1188                 MiWrite(etdev, regnum, reg);
1189                 break;
1190
1191         case TRUEPHY_BIT_CLEAR:
1192                 reg &= ~mask;
1193                 MiWrite(etdev, regnum, reg);
1194                 break;
1195
1196         default:
1197                 break;
1198         }
1199 }