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mm-only debug patch...
[mmotm.git] / arch / arm / plat-s3c64xx / s3c6400-clock.c
blob9745852261e03a7c149bbc46b83001607a2a9d7e
1 /* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 based common clock support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/sysdev.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <mach/map.h>
27
28 #include <plat/cpu-freq.h>
29
30 #include <plat/regs-clock.h>
31 #include <plat/clock.h>
32 #include <plat/cpu.h>
33 #include <plat/pll.h>
34
35 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
36 * ext_xtal_mux for want of an actual name from the manual.
37 */
38
39 static struct clk clk_ext_xtal_mux = {
40 .name = "ext_xtal",
41 .id = -1,
42 };
43
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
47
48 #define clk_fout_mpll clk_mpll
49
50 struct clk_sources {
51 unsigned int nr_sources;
52 struct clk **sources;
53 };
54
55 struct clksrc_clk {
56 struct clk clk;
57 unsigned int mask;
58 unsigned int shift;
59
60 struct clk_sources *sources;
61
62 unsigned int divider_shift;
63 void __iomem *reg_divider;
64 };
65
66 static struct clk clk_fout_apll = {
67 .name = "fout_apll",
68 .id = -1,
69 };
70
71 static struct clk *clk_src_apll_list[] = {
72 [0] = &clk_fin_apll,
73 [1] = &clk_fout_apll,
74 };
75
76 static struct clk_sources clk_src_apll = {
77 .sources = clk_src_apll_list,
78 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
79 };
80
81 static struct clksrc_clk clk_mout_apll = {
82 .clk = {
83 .name = "mout_apll",
84 .id = -1,
85 },
86 .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
87 .mask = S3C6400_CLKSRC_APLL_MOUT,
88 .sources = &clk_src_apll,
89 };
90
91 static struct clk clk_fout_epll = {
92 .name = "fout_epll",
93 .id = -1,
94 };
95
96 static struct clk *clk_src_epll_list[] = {
97 [0] = &clk_fin_epll,
98 [1] = &clk_fout_epll,
99 };
100
101 static struct clk_sources clk_src_epll = {
102 .sources = clk_src_epll_list,
103 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
104 };
105
106 static struct clksrc_clk clk_mout_epll = {
107 .clk = {
108 .name = "mout_epll",
109 .id = -1,
110 },
111 .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
112 .mask = S3C6400_CLKSRC_EPLL_MOUT,
113 .sources = &clk_src_epll,
114 };
115
116 static struct clk *clk_src_mpll_list[] = {
117 [0] = &clk_fin_mpll,
118 [1] = &clk_fout_mpll,
119 };
120
121 static struct clk_sources clk_src_mpll = {
122 .sources = clk_src_mpll_list,
123 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
124 };
125
126 static struct clksrc_clk clk_mout_mpll = {
127 .clk = {
128 .name = "mout_mpll",
129 .id = -1,
130 },
131 .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
132 .mask = S3C6400_CLKSRC_MPLL_MOUT,
133 .sources = &clk_src_mpll,
134 };
135
136 static unsigned int armclk_mask;
137
138 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
139 {
140 unsigned long rate = clk_get_rate(clk->parent);
141 u32 clkdiv;
142
143 /* divisor mask starts at bit0, so no need to shift */
144 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
145
146 return rate / (clkdiv + 1);
147 }
148
149 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
150 unsigned long rate)
151 {
152 unsigned long parent = clk_get_rate(clk->parent);
153 u32 div;
154
155 if (parent < rate)
156 return parent;
157
158 div = (parent / rate) - 1;
159 if (div > armclk_mask)
160 div = armclk_mask;
161
162 return parent / (div + 1);
163 }
164
165 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
166 {
167 unsigned long parent = clk_get_rate(clk->parent);
168 u32 div;
169 u32 val;
170
171 if (rate < parent / (armclk_mask + 1))
172 return -EINVAL;
173
174 rate = clk_round_rate(clk, rate);
175 div = clk_get_rate(clk->parent) / rate;
176
177 val = __raw_readl(S3C_CLK_DIV0);
178 val &= ~armclk_mask;
179 val |= (div - 1);
180 __raw_writel(val, S3C_CLK_DIV0);
181
182 return 0;
183
184 }
185
186 static struct clk clk_arm = {
187 .name = "armclk",
188 .id = -1,
189 .parent = &clk_mout_apll.clk,
190 .get_rate = s3c64xx_clk_arm_get_rate,
191 .set_rate = s3c64xx_clk_arm_set_rate,
192 .round_rate = s3c64xx_clk_arm_round_rate,
193 };
194
195 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
196 {
197 unsigned long rate = clk_get_rate(clk->parent);
198
199 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
200
201 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
202 rate /= 2;
203
204 return rate;
205 }
206
207 static struct clk clk_dout_mpll = {
208 .name = "dout_mpll",
209 .id = -1,
210 .parent = &clk_mout_mpll.clk,
211 .get_rate = s3c64xx_clk_doutmpll_get_rate,
212 };
213
214 static struct clk *clkset_spi_mmc_list[] = {
215 &clk_mout_epll.clk,
216 &clk_dout_mpll,
217 &clk_fin_epll,
218 &clk_27m,
219 };
220
221 static struct clk_sources clkset_spi_mmc = {
222 .sources = clkset_spi_mmc_list,
223 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
224 };
225
226 static struct clk *clkset_irda_list[] = {
227 &clk_mout_epll.clk,
228 &clk_dout_mpll,
229 NULL,
230 &clk_27m,
231 };
232
233 static struct clk_sources clkset_irda = {
234 .sources = clkset_irda_list,
235 .nr_sources = ARRAY_SIZE(clkset_irda_list),
236 };
237
238 static struct clk *clkset_uart_list[] = {
239 &clk_mout_epll.clk,
240 &clk_dout_mpll,
241 NULL,
242 NULL
243 };
244
245 static struct clk_sources clkset_uart = {
246 .sources = clkset_uart_list,
247 .nr_sources = ARRAY_SIZE(clkset_uart_list),
248 };
249
250 static struct clk *clkset_uhost_list[] = {
251 &clk_48m,
252 &clk_mout_epll.clk,
253 &clk_dout_mpll,
254 &clk_fin_epll,
255 };
256
257 static struct clk_sources clkset_uhost = {
258 .sources = clkset_uhost_list,
259 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
260 };
261
262
263 /* The peripheral clocks are all controlled via clocksource followed
264 * by an optional divider and gate stage. We currently roll this into
265 * one clock which hides the intermediate clock from the mux.
266 *
267 * Note, the JPEG clock can only be an even divider...
268 *
269 * The scaler and LCD clocks depend on the S3C64XX version, and also
270 * have a common parent divisor so are not included here.
271 */
272
273 static inline struct clksrc_clk *to_clksrc(struct clk *clk)
274 {
275 return container_of(clk, struct clksrc_clk, clk);
276 }
277
278 static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
279 {
280 struct clksrc_clk *sclk = to_clksrc(clk);
281 unsigned long rate = clk_get_rate(clk->parent);
282 u32 clkdiv = __raw_readl(sclk->reg_divider);
283
284 clkdiv >>= sclk->divider_shift;
285 clkdiv &= 0xf;
286 clkdiv++;
287
288 rate /= clkdiv;
289 return rate;
290 }
291
292 static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
293 {
294 struct clksrc_clk *sclk = to_clksrc(clk);
295 void __iomem *reg = sclk->reg_divider;
296 unsigned int div;
297 u32 val;
298
299 rate = clk_round_rate(clk, rate);
300 div = clk_get_rate(clk->parent) / rate;
301 if (div > 16)
302 return -EINVAL;
303
304 val = __raw_readl(reg);
305 val &= ~(0xf << sclk->divider_shift);
306 val |= (div - 1) << sclk->divider_shift;
307 __raw_writel(val, reg);
308
309 return 0;
310 }
311
312 static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
313 {
314 struct clksrc_clk *sclk = to_clksrc(clk);
315 struct clk_sources *srcs = sclk->sources;
316 u32 clksrc = __raw_readl(S3C_CLK_SRC);
317 int src_nr = -1;
318 int ptr;
319
320 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
321 if (srcs->sources[ptr] == parent) {
322 src_nr = ptr;
323 break;
324 }
325
326 if (src_nr >= 0) {
327 clksrc &= ~sclk->mask;
328 clksrc |= src_nr << sclk->shift;
329
330 __raw_writel(clksrc, S3C_CLK_SRC);
331
332 clk->parent = parent;
333 return 0;
334 }
335
336 return -EINVAL;
337 }
338
339 static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
340 unsigned long rate)
341 {
342 unsigned long parent_rate = clk_get_rate(clk->parent);
343 int div;
344
345 if (rate > parent_rate)
346 rate = parent_rate;
347 else {
348 div = parent_rate / rate;
349
350 if (div == 0)
351 div = 1;
352 if (div > 16)
353 div = 16;
354
355 rate = parent_rate / div;
356 }
357
358 return rate;
359 }
360
361 static struct clksrc_clk clk_mmc0 = {
362 .clk = {
363 .name = "mmc_bus",
364 .id = 0,
365 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
366 .enable = s3c64xx_sclk_ctrl,
367 .set_parent = s3c64xx_setparent_clksrc,
368 .get_rate = s3c64xx_getrate_clksrc,
369 .set_rate = s3c64xx_setrate_clksrc,
370 .round_rate = s3c64xx_roundrate_clksrc,
371 },
372 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
373 .mask = S3C6400_CLKSRC_MMC0_MASK,
374 .sources = &clkset_spi_mmc,
375 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
376 .reg_divider = S3C_CLK_DIV1,
377 };
378
379 static struct clksrc_clk clk_mmc1 = {
380 .clk = {
381 .name = "mmc_bus",
382 .id = 1,
383 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
384 .enable = s3c64xx_sclk_ctrl,
385 .get_rate = s3c64xx_getrate_clksrc,
386 .set_rate = s3c64xx_setrate_clksrc,
387 .set_parent = s3c64xx_setparent_clksrc,
388 .round_rate = s3c64xx_roundrate_clksrc,
389 },
390 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
391 .mask = S3C6400_CLKSRC_MMC1_MASK,
392 .sources = &clkset_spi_mmc,
393 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
394 .reg_divider = S3C_CLK_DIV1,
395 };
396
397 static struct clksrc_clk clk_mmc2 = {
398 .clk = {
399 .name = "mmc_bus",
400 .id = 2,
401 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
402 .enable = s3c64xx_sclk_ctrl,
403 .get_rate = s3c64xx_getrate_clksrc,
404 .set_rate = s3c64xx_setrate_clksrc,
405 .set_parent = s3c64xx_setparent_clksrc,
406 .round_rate = s3c64xx_roundrate_clksrc,
407 },
408 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
409 .mask = S3C6400_CLKSRC_MMC2_MASK,
410 .sources = &clkset_spi_mmc,
411 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
412 .reg_divider = S3C_CLK_DIV1,
413 };
414
415 static struct clksrc_clk clk_usbhost = {
416 .clk = {
417 .name = "usb-bus-host",
418 .id = -1,
419 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
420 .enable = s3c64xx_sclk_ctrl,
421 .set_parent = s3c64xx_setparent_clksrc,
422 .get_rate = s3c64xx_getrate_clksrc,
423 .set_rate = s3c64xx_setrate_clksrc,
424 .round_rate = s3c64xx_roundrate_clksrc,
425 },
426 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
427 .mask = S3C6400_CLKSRC_UHOST_MASK,
428 .sources = &clkset_uhost,
429 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
430 .reg_divider = S3C_CLK_DIV1,
431 };
432
433 static struct clksrc_clk clk_uart_uclk1 = {
434 .clk = {
435 .name = "uclk1",
436 .id = -1,
437 .ctrlbit = S3C_CLKCON_SCLK_UART,
438 .enable = s3c64xx_sclk_ctrl,
439 .set_parent = s3c64xx_setparent_clksrc,
440 .get_rate = s3c64xx_getrate_clksrc,
441 .set_rate = s3c64xx_setrate_clksrc,
442 .round_rate = s3c64xx_roundrate_clksrc,
443 },
444 .shift = S3C6400_CLKSRC_UART_SHIFT,
445 .mask = S3C6400_CLKSRC_UART_MASK,
446 .sources = &clkset_uart,
447 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
448 .reg_divider = S3C_CLK_DIV2,
449 };
450
451 /* Where does UCLK0 come from? */
452
453 static struct clksrc_clk clk_spi0 = {
454 .clk = {
455 .name = "spi-bus",
456 .id = 0,
457 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
458 .enable = s3c64xx_sclk_ctrl,
459 .set_parent = s3c64xx_setparent_clksrc,
460 .get_rate = s3c64xx_getrate_clksrc,
461 .set_rate = s3c64xx_setrate_clksrc,
462 .round_rate = s3c64xx_roundrate_clksrc,
463 },
464 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
465 .mask = S3C6400_CLKSRC_SPI0_MASK,
466 .sources = &clkset_spi_mmc,
467 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
468 .reg_divider = S3C_CLK_DIV2,
469 };
470
471 static struct clksrc_clk clk_spi1 = {
472 .clk = {
473 .name = "spi-bus",
474 .id = 1,
475 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
476 .enable = s3c64xx_sclk_ctrl,
477 .set_parent = s3c64xx_setparent_clksrc,
478 .get_rate = s3c64xx_getrate_clksrc,
479 .set_rate = s3c64xx_setrate_clksrc,
480 .round_rate = s3c64xx_roundrate_clksrc,
481 },
482 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
483 .mask = S3C6400_CLKSRC_SPI1_MASK,
484 .sources = &clkset_spi_mmc,
485 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
486 .reg_divider = S3C_CLK_DIV2,
487 };
488
489 static struct clk clk_iis_cd0 = {
490 .name = "iis_cdclk0",
491 .id = -1,
492 };
493
494 static struct clk clk_iis_cd1 = {
495 .name = "iis_cdclk1",
496 .id = -1,
497 };
498
499 static struct clk clk_pcm_cd = {
500 .name = "pcm_cdclk",
501 .id = -1,
502 };
503
504 static struct clk *clkset_audio0_list[] = {
505 [0] = &clk_mout_epll.clk,
506 [1] = &clk_dout_mpll,
507 [2] = &clk_fin_epll,
508 [3] = &clk_iis_cd0,
509 [4] = &clk_pcm_cd,
510 };
511
512 static struct clk_sources clkset_audio0 = {
513 .sources = clkset_audio0_list,
514 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
515 };
516
517 static struct clksrc_clk clk_audio0 = {
518 .clk = {
519 .name = "audio-bus",
520 .id = 0,
521 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
522 .enable = s3c64xx_sclk_ctrl,
523 .set_parent = s3c64xx_setparent_clksrc,
524 .get_rate = s3c64xx_getrate_clksrc,
525 .set_rate = s3c64xx_setrate_clksrc,
526 .round_rate = s3c64xx_roundrate_clksrc,
527 },
528 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
529 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
530 .sources = &clkset_audio0,
531 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
532 .reg_divider = S3C_CLK_DIV2,
533 };
534
535 static struct clk *clkset_audio1_list[] = {
536 [0] = &clk_mout_epll.clk,
537 [1] = &clk_dout_mpll,
538 [2] = &clk_fin_epll,
539 [3] = &clk_iis_cd1,
540 [4] = &clk_pcm_cd,
541 };
542
543 static struct clk_sources clkset_audio1 = {
544 .sources = clkset_audio1_list,
545 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
546 };
547
548 static struct clksrc_clk clk_audio1 = {
549 .clk = {
550 .name = "audio-bus",
551 .id = 1,
552 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
553 .enable = s3c64xx_sclk_ctrl,
554 .set_parent = s3c64xx_setparent_clksrc,
555 .get_rate = s3c64xx_getrate_clksrc,
556 .set_rate = s3c64xx_setrate_clksrc,
557 .round_rate = s3c64xx_roundrate_clksrc,
558 },
559 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
560 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
561 .sources = &clkset_audio1,
562 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
563 .reg_divider = S3C_CLK_DIV2,
564 };
565
566 static struct clksrc_clk clk_irda = {
567 .clk = {
568 .name = "irda-bus",
569 .id = 0,
570 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
571 .enable = s3c64xx_sclk_ctrl,
572 .set_parent = s3c64xx_setparent_clksrc,
573 .get_rate = s3c64xx_getrate_clksrc,
574 .set_rate = s3c64xx_setrate_clksrc,
575 .round_rate = s3c64xx_roundrate_clksrc,
576 },
577 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
578 .mask = S3C6400_CLKSRC_IRDA_MASK,
579 .sources = &clkset_irda,
580 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
581 .reg_divider = S3C_CLK_DIV2,
582 };
583
584 static struct clk *clkset_camif_list[] = {
585 &clk_h2,
586 };
587
588 static struct clk_sources clkset_camif = {
589 .sources = clkset_camif_list,
590 .nr_sources = ARRAY_SIZE(clkset_camif_list),
591 };
592
593 static struct clksrc_clk clk_camif = {
594 .clk = {
595 .name = "camera",
596 .id = -1,
597 .ctrlbit = S3C_CLKCON_SCLK_CAM,
598 .enable = s3c64xx_sclk_ctrl,
599 .set_parent = s3c64xx_setparent_clksrc,
600 .get_rate = s3c64xx_getrate_clksrc,
601 .set_rate = s3c64xx_setrate_clksrc,
602 .round_rate = s3c64xx_roundrate_clksrc,
603 },
604 .shift = 0,
605 .mask = 0,
606 .sources = &clkset_camif,
607 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
608 .reg_divider = S3C_CLK_DIV0,
609 };
610
611 /* Clock initialisation code */
612
613 static struct clksrc_clk *init_parents[] = {
614 &clk_mout_apll,
615 &clk_mout_epll,
616 &clk_mout_mpll,
617 &clk_mmc0,
618 &clk_mmc1,
619 &clk_mmc2,
620 &clk_usbhost,
621 &clk_uart_uclk1,
622 &clk_spi0,
623 &clk_spi1,
624 &clk_audio0,
625 &clk_audio1,
626 &clk_irda,
627 &clk_camif,
628 };
629
630 static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
631 {
632 struct clk_sources *srcs = clk->sources;
633 u32 clksrc = __raw_readl(S3C_CLK_SRC);
634
635 clksrc &= clk->mask;
636 clksrc >>= clk->shift;
637
638 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
639 printk(KERN_ERR "%s: bad source %d\n",
640 clk->clk.name, clksrc);
641 return;
642 }
643
644 clk->clk.parent = srcs->sources[clksrc];
645
646 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
647 clk->clk.name, clk->clk.parent->name, clksrc,
648 clk_get_rate(&clk->clk));
649 }
650
651 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
652
653 void __init_or_cpufreq s3c6400_setup_clocks(void)
654 {
655 struct clk *xtal_clk;
656 unsigned long xtal;
657 unsigned long fclk;
658 unsigned long hclk;
659 unsigned long hclk2;
660 unsigned long pclk;
661 unsigned long epll;
662 unsigned long apll;
663 unsigned long mpll;
664 unsigned int ptr;
665 u32 clkdiv0;
666
667 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
668
669 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
670 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
671
672 xtal_clk = clk_get(NULL, "xtal");
673 BUG_ON(IS_ERR(xtal_clk));
674
675 xtal = clk_get_rate(xtal_clk);
676 clk_put(xtal_clk);
677
678 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
679
680 epll = s3c6400_get_epll(xtal);
681 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
682 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
683
684 fclk = mpll;
685
686 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
687 apll, mpll, epll);
688
689 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
690 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
691 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
692
693 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
694 hclk2, hclk, pclk);
695
696 clk_fout_mpll.rate = mpll;
697 clk_fout_epll.rate = epll;
698 clk_fout_apll.rate = apll;
699
700 clk_h2.rate = hclk2;
701 clk_h.rate = hclk;
702 clk_p.rate = pclk;
703 clk_f.rate = fclk;
704
705 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
706 s3c6400_set_clksrc(init_parents[ptr]);
707 }
708
709 static struct clk *clks[] __initdata = {
710 &clk_ext_xtal_mux,
711 &clk_iis_cd0,
712 &clk_iis_cd1,
713 &clk_pcm_cd,
714 &clk_mout_epll.clk,
715 &clk_fout_epll,
716 &clk_mout_mpll.clk,
717 &clk_dout_mpll,
718 &clk_mmc0.clk,
719 &clk_mmc1.clk,
720 &clk_mmc2.clk,
721 &clk_usbhost.clk,
722 &clk_uart_uclk1.clk,
723 &clk_spi0.clk,
724 &clk_spi1.clk,
725 &clk_audio0.clk,
726 &clk_audio1.clk,
727 &clk_irda.clk,
728 &clk_camif.clk,
729 &clk_arm,
730 };
731
732 /**
733 * s3c6400_register_clocks - register clocks for s3c6400 and above
734 * @armclk_divlimit: Divisor mask for ARMCLK
735 *
736 * Register the clocks for the S3C6400 and above SoC range, such
737 * as ARMCLK and the clocks which have divider chains attached.
738 *
739 * This call does not setup the clocks, which is left to the
740 * s3c6400_setup_clocks() call which may be needed by the cpufreq
741 * or resume code to re-set the clocks if the bootloader has changed
742 * them.
743 */
744 void __init s3c6400_register_clocks(unsigned armclk_divlimit)
745 {
746 struct clk *clkp;
747 int ret;
748 int ptr;
749
750 armclk_mask = armclk_divlimit;
751
752 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
753 clkp = clks[ptr];
754 ret = s3c24xx_register_clock(clkp);
755 if (ret < 0) {
756 printk(KERN_ERR "Failed to register clock %s (%d)\n",
757 clkp->name, ret);
758 }
759 }
760
761 clk_mpll.parent = &clk_mout_mpll.clk;
762 clk_epll.parent = &clk_mout_epll.clk;
763 }
mm of the moment repository