mm-only debug patch...
[mmotm.git] / arch / m68knommu / platform / 5206 / config.c
blob9c335465e66de1a0e9a4d4e59ae53c4369810d05
1 /***************************************************************************/
3 /*
4 * linux/arch/m68knommu/platform/5206/config.c
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com)
8 */
10 /***************************************************************************/
12 #include <linux/kernel.h>
13 #include <linux/param.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <asm/machdep.h>
17 #include <asm/coldfire.h>
18 #include <asm/mcfsim.h>
19 #include <asm/mcfuart.h>
21 /***************************************************************************/
23 static struct mcf_platform_uart m5206_uart_platform[] = {
25 .mapbase = MCF_MBAR + MCFUART_BASE1,
26 .irq = 73,
29 .mapbase = MCF_MBAR + MCFUART_BASE2,
30 .irq = 74,
32 { },
35 static struct platform_device m5206_uart = {
36 .name = "mcfuart",
37 .id = 0,
38 .dev.platform_data = m5206_uart_platform,
41 static struct platform_device *m5206_devices[] __initdata = {
42 &m5206_uart,
45 /***************************************************************************/
47 static void __init m5206_uart_init_line(int line, int irq)
49 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_mapirq2imr(irq, MCFINTC_UART1);
60 static void __init m5206_uarts_init(void)
62 const int nrlines = ARRAY_SIZE(m5206_uart_platform);
63 int line;
65 for (line = 0; (line < nrlines); line++)
66 m5206_uart_init_line(line, m5206_uart_platform[line].irq);
69 /***************************************************************************/
71 static void __init m5206_timers_init(void)
73 /* Timer1 is always used as system timer */
74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
78 #ifdef CONFIG_HIGHPROFILE
79 /* Timer2 is to be used as a high speed profile timer */
80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83 #endif
86 /***************************************************************************/
88 void m5206_cpu_reset(void)
90 local_irq_disable();
91 /* Set watchdog to soft reset, and enabled */
92 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
93 for (;;)
94 /* wait for watchdog to timeout */;
97 /***************************************************************************/
99 void __init config_BSP(char *commandp, int size)
101 mach_reset = m5206_cpu_reset;
102 m5206_timers_init();
103 m5206_uarts_init();
105 /* Only support the external interrupts on their primary level */
106 mcf_mapirq2imr(25, MCFINTC_EINT1);
107 mcf_mapirq2imr(28, MCFINTC_EINT4);
108 mcf_mapirq2imr(31, MCFINTC_EINT7);
111 /***************************************************************************/
113 static int __init init_BSP(void)
115 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
116 return 0;
119 arch_initcall(init_BSP);
121 /***************************************************************************/