| blob | 2b86c03aa84187cb5857974fba2cb949e349ce93 |
1 /*
2 * Exception handling for Microblaze
3 *
4 * Rewriten interrupt handling
5 *
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
8 *
9 * uClinux customisation (C) 2005 John Williams
10 *
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
15 * Rewritten for PReP
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
30 *
31 * Original code
32 * Copyright (C) 2004 Xilinx, Inc.
33 *
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
37 */
39 /*
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
47 *
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
50 * - Unalignment
51 * - Instruction bus error
52 * - Data bus error
53 * - Illegal instruction opcode
54 * - Divide-by-zero
55 *
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
61 *
62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
64 * exceptions. JW
65 */
67 #include <asm/exceptions.h>
68 #include <asm/unistd.h>
69 #include <asm/page.h>
71 #include <asm/entry.h>
72 #include <asm/current.h>
73 #include <linux/linkage.h>
75 #include <asm/mmu.h>
76 #include <asm/pgtable.h>
77 #include <asm/signal.h>
78 #include <asm/asm-offsets.h>
80 /* Helpful Macros */
81 #ifndef CONFIG_MMU
82 #define EX_HANDLER_STACK_SIZ (4*19)
83 #endif
84 #define NUM_TO_REG(num) r ## num
86 #ifdef CONFIG_MMU
87 #define RESTORE_STATE \
88 lwi r5, r1, 0; \
89 mts rmsr, r5; \
90 nop; \
91 lwi r3, r1, PT_R3; \
92 lwi r4, r1, PT_R4; \
93 lwi r5, r1, PT_R5; \
94 lwi r6, r1, PT_R6; \
95 lwi r11, r1, PT_R11; \
96 lwi r31, r1, PT_R31; \
97 lwi r1, r0, TOPHYS(r0_ram + 0);
98 #endif /* CONFIG_MMU */
100 #define LWREG_NOP \
101 bri ex_handler_unhandled; \
102 nop;
104 #define SWREG_NOP \
105 bri ex_handler_unhandled; \
106 nop;
108 /* FIXME this is weird - for noMMU kernel is not possible to use brid
109 * instruction which can shorten executed time
110 */
112 /* r3 is the source */
113 #define R3_TO_LWREG_V(regnum) \
114 swi r3, r1, 4 * regnum; \
115 bri ex_handler_done;
117 /* r3 is the source */
118 #define R3_TO_LWREG(regnum) \
119 or NUM_TO_REG (regnum), r0, r3; \
120 bri ex_handler_done;
122 /* r3 is the target */
123 #define SWREG_TO_R3_V(regnum) \
124 lwi r3, r1, 4 * regnum; \
125 bri ex_sw_tail;
127 /* r3 is the target */
128 #define SWREG_TO_R3(regnum) \
129 or r3, r0, NUM_TO_REG (regnum); \
130 bri ex_sw_tail;
132 #ifdef CONFIG_MMU
133 #define R3_TO_LWREG_VM_V(regnum) \
134 brid ex_lw_end_vm; \
135 swi r3, r7, 4 * regnum;
137 #define R3_TO_LWREG_VM(regnum) \
138 brid ex_lw_end_vm; \
139 or NUM_TO_REG (regnum), r0, r3;
141 #define SWREG_TO_R3_VM_V(regnum) \
142 brid ex_sw_tail_vm; \
143 lwi r3, r7, 4 * regnum;
145 #define SWREG_TO_R3_VM(regnum) \
146 brid ex_sw_tail_vm; \
147 or r3, r0, NUM_TO_REG (regnum);
149 /* Shift right instruction depending on available configuration */
150 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
151 #define BSRLI(rD, rA, imm) \
152 bsrli rD, rA, imm
153 #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
154 #define BSRLI(rD, rA, imm) \
155 ori rD, r0, (1 << imm); \
156 idivu rD, rD, rA
157 #else
158 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
159 /* Only the used shift constants defined here - add more if needed */
160 #define BSRLI2(rD, rA) \
161 srl rD, rA; /* << 1 */ \
162 srl rD, rD; /* << 2 */
163 #define BSRLI10(rD, rA) \
164 srl rD, rA; /* << 1 */ \
165 srl rD, rD; /* << 2 */ \
166 srl rD, rD; /* << 3 */ \
167 srl rD, rD; /* << 4 */ \
168 srl rD, rD; /* << 5 */ \
169 srl rD, rD; /* << 6 */ \
170 srl rD, rD; /* << 7 */ \
171 srl rD, rD; /* << 8 */ \
172 srl rD, rD; /* << 9 */ \
173 srl rD, rD /* << 10 */
174 #define BSRLI20(rD, rA) \
175 BSRLI10(rD, rA); \
176 BSRLI10(rD, rD)
177 #endif
178 #endif /* CONFIG_MMU */
180 .extern other_exception_handler /* Defined in exception.c */
182 /*
183 * hw_exception_handler - Handler for exceptions
184 *
185 * Exception handler notes:
186 * - Handles all exceptions
187 * - Does not handle unaligned exceptions during load into r17, r1, r0.
188 * - Does not handle unaligned exceptions during store from r17 (cannot be
189 * done) and r1 (slows down common case)
190 *
191 * Relevant register structures
192 *
193 * EAR - |----|----|----|----|----|----|----|----|
194 * - < ## 32 bit faulting address ## >
195 *
196 * ESR - |----|----|----|----|----| - | - |-----|-----|
197 * - W S REG EXC
198 *
199 *
200 * STACK FRAME STRUCTURE (for NO_MMU)
201 * ---------------------------------
202 *
203 * +-------------+ + 0
204 * | MSR |
205 * +-------------+ + 4
206 * | r1 |
207 * | . |
208 * | . |
209 * | . |
210 * | . |
211 * | r18 |
212 * +-------------+ + 76
213 * | . |
214 * | . |
215 *
216 * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S
217 * which is used for storing register values - old style was, that value were
218 * stored in stack but in case of failure you lost information about register.
219 * Currently you can see register value in memory in specific place.
220 * In compare to with previous solution the speed should be the same.
221 *
222 * MMU exception handler has different handling compare to no MMU kernel.
223 * Exception handler use jump table for directing of what happen. For MMU kernel
224 * is this approach better because MMU relate exception are handled by asm code
225 * in this file. In compare to with MMU expect of unaligned exception
226 * is everything handled by C code.
227 */
229 /*
230 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
231 * and clobbered so care should be taken to restore them if someone is going to
232 * return from exception
233 */
235 /* wrappers to restore state before coming to entry.S */
237 #ifdef CONFIG_MMU
238 .section .rodata
239 .align 4
240 _MB_HW_ExceptionVectorTable:
241 /* 0 - Undefined */
242 .long TOPHYS(ex_handler_unhandled)
243 /* 1 - Unaligned data access exception */
244 .long TOPHYS(handle_unaligned_ex)
245 /* 2 - Illegal op-code exception */
246 .long TOPHYS(full_exception_trapw)
247 /* 3 - Instruction bus error exception */
248 .long TOPHYS(full_exception_trapw)
249 /* 4 - Data bus error exception */
250 .long TOPHYS(full_exception_trapw)
251 /* 5 - Divide by zero exception */
252 .long TOPHYS(full_exception_trapw)
253 /* 6 - Floating point unit exception */
254 .long TOPHYS(full_exception_trapw)
255 /* 7 - Privileged instruction exception */
256 .long TOPHYS(full_exception_trapw)
257 /* 8 - 15 - Undefined */
258 .long TOPHYS(ex_handler_unhandled)
259 .long TOPHYS(ex_handler_unhandled)
260 .long TOPHYS(ex_handler_unhandled)
261 .long TOPHYS(ex_handler_unhandled)
262 .long TOPHYS(ex_handler_unhandled)
263 .long TOPHYS(ex_handler_unhandled)
264 .long TOPHYS(ex_handler_unhandled)
265 .long TOPHYS(ex_handler_unhandled)
266 /* 16 - Data storage exception */
267 .long TOPHYS(handle_data_storage_exception)
268 /* 17 - Instruction storage exception */
269 .long TOPHYS(handle_instruction_storage_exception)
270 /* 18 - Data TLB miss exception */
271 .long TOPHYS(handle_data_tlb_miss_exception)
272 /* 19 - Instruction TLB miss exception */
273 .long TOPHYS(handle_instruction_tlb_miss_exception)
274 /* 20 - 31 - Undefined */
275 .long TOPHYS(ex_handler_unhandled)
276 .long TOPHYS(ex_handler_unhandled)
277 .long TOPHYS(ex_handler_unhandled)
278 .long TOPHYS(ex_handler_unhandled)
279 .long TOPHYS(ex_handler_unhandled)
280 .long TOPHYS(ex_handler_unhandled)
281 .long TOPHYS(ex_handler_unhandled)
282 .long TOPHYS(ex_handler_unhandled)
283 .long TOPHYS(ex_handler_unhandled)
284 .long TOPHYS(ex_handler_unhandled)
285 .long TOPHYS(ex_handler_unhandled)
286 .long TOPHYS(ex_handler_unhandled)
287 #endif
289 .global _hw_exception_handler
290 .section .text
291 .align 4
292 .ent _hw_exception_handler
293 _hw_exception_handler:
294 #ifndef CONFIG_MMU
295 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
296 #else
297 swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */
298 /* Save date to kernel memory. Here is the problem
299 * when you came from user space */
300 ori r1, r0, TOPHYS(r0_ram + 28);
301 #endif
302 swi r3, r1, PT_R3
303 swi r4, r1, PT_R4
304 swi r5, r1, PT_R5
305 swi r6, r1, PT_R6
307 #ifdef CONFIG_MMU
308 swi r11, r1, PT_R11
309 swi r31, r1, PT_R31
310 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
311 #endif
313 mfs r5, rmsr;
314 nop
315 swi r5, r1, 0;
316 mfs r3, resr
317 nop
318 mfs r4, rear;
319 nop
321 #ifndef CONFIG_MMU
322 andi r5, r3, 0x1000; /* Check ESR[DS] */
323 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
324 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
325 nop
326 not_in_delay_slot:
327 swi r17, r1, PT_R17
328 #endif
330 andi r5, r3, 0x1F; /* Extract ESR[EXC] */
332 #ifdef CONFIG_MMU
333 /* Calculate exception vector offset = r5 << 2 */
334 addk r6, r5, r5; /* << 1 */
335 addk r6, r6, r6; /* << 2 */
337 /* counting which exception happen */
338 lwi r5, r0, 0x200 + TOPHYS(r0_ram)
339 addi r5, r5, 1
340 swi r5, r0, 0x200 + TOPHYS(r0_ram)
341 lwi r5, r6, 0x200 + TOPHYS(r0_ram)
342 addi r5, r5, 1
343 swi r5, r6, 0x200 + TOPHYS(r0_ram)
344 /* end */
345 /* Load the HW Exception vector */
346 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
347 bra r6
349 full_exception_trapw:
350 RESTORE_STATE
351 bri full_exception_trap
352 #else
353 /* Exceptions enabled here. This will allow nested exceptions */
354 mfs r6, rmsr;
355 nop
356 swi r6, r1, 0; /* RMSR_OFFSET */
357 ori r6, r6, 0x100; /* Turn ON the EE bit */
358 andi r6, r6, ~2; /* Disable interrupts */
359 mts rmsr, r6;
360 nop
362 xori r6, r5, 1; /* 00001 = Unaligned Exception */
363 /* Jump to unalignment exception handler */
364 beqi r6, handle_unaligned_ex;
366 handle_other_ex: /* Handle Other exceptions here */
367 /* Save other volatiles before we make procedure calls below */
368 swi r7, r1, PT_R7
369 swi r8, r1, PT_R8
370 swi r9, r1, PT_R9
371 swi r10, r1, PT_R10
372 swi r11, r1, PT_R11
373 swi r12, r1, PT_R12
374 swi r14, r1, PT_R14
375 swi r15, r1, PT_R15
376 swi r18, r1, PT_R18
378 or r5, r1, r0
379 andi r6, r3, 0x1F; /* Load ESR[EC] */
380 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
381 swi r7, r1, PT_MODE
382 mfs r7, rfsr
383 nop
384 addk r8, r17, r0; /* Load exception address */
385 bralid r15, full_exception; /* Branch to the handler */
386 nop;
387 mts rfsr, r0; /* Clear sticky fsr */
388 nop
390 /*
391 * Trigger execution of the signal handler by enabling
392 * interrupts and calling an invalid syscall.
393 */
394 mfs r5, rmsr;
395 nop
396 ori r5, r5, 2;
397 mts rmsr, r5; /* enable interrupt */
398 nop
399 addi r12, r0, __NR_syscalls;
400 brki r14, 0x08;
401 mfs r5, rmsr; /* disable interrupt */
402 nop
403 andi r5, r5, ~2;
404 mts rmsr, r5;
405 nop
407 lwi r7, r1, PT_R7
408 lwi r8, r1, PT_R8
409 lwi r9, r1, PT_R9
410 lwi r10, r1, PT_R10
411 lwi r11, r1, PT_R11
412 lwi r12, r1, PT_R12
413 lwi r14, r1, PT_R14
414 lwi r15, r1, PT_R15
415 lwi r18, r1, PT_R18
417 bri ex_handler_done; /* Complete exception handling */
418 #endif
420 /* 0x01 - Unaligned data access exception
421 * This occurs when a word access is not aligned on a word boundary,
422 * or when a 16-bit access is not aligned on a 16-bit boundary.
423 * This handler perform the access, and returns, except for MMU when
424 * the unaligned address is last on a 4k page or the physical address is
425 * not found in the page table, in which case unaligned_data_trap is called.
426 */
427 handle_unaligned_ex:
428 /* Working registers already saved: R3, R4, R5, R6
429 * R3 = ESR
430 * R4 = EAR
431 */
432 #ifdef CONFIG_MMU
433 andi r6, r3, 0x1000 /* Check ESR[DS] */
434 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
435 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
436 nop
437 _no_delayslot:
438 /* jump to high level unaligned handler */
439 RESTORE_STATE;
440 bri unaligned_data_trap
441 #endif
442 andi r6, r3, 0x3E0; /* Mask and extract the register operand */
443 srl r6, r6; /* r6 >> 5 */
444 srl r6, r6;
445 srl r6, r6;
446 srl r6, r6;
447 srl r6, r6;
448 /* Store the register operand in a temporary location */
449 sbi r6, r0, TOPHYS(ex_reg_op);
451 andi r6, r3, 0x400; /* Extract ESR[S] */
452 bnei r6, ex_sw;
453 ex_lw:
454 andi r6, r3, 0x800; /* Extract ESR[W] */
455 beqi r6, ex_lhw;
456 lbui r5, r4, 0; /* Exception address in r4 */
457 /* Load a word, byte-by-byte from destination address
458 and save it in tmp space */
459 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
460 lbui r5, r4, 1;
461 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
462 lbui r5, r4, 2;
463 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
464 lbui r5, r4, 3;
465 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
466 /* Get the destination register value into r3 */
467 lwi r3, r0, TOPHYS(ex_tmp_data_loc_0);
468 bri ex_lw_tail;
469 ex_lhw:
470 lbui r5, r4, 0; /* Exception address in r4 */
471 /* Load a half-word, byte-by-byte from destination
472 address and save it in tmp space */
473 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
474 lbui r5, r4, 1;
475 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
476 /* Get the destination register value into r3 */
477 lhui r3, r0, TOPHYS(ex_tmp_data_loc_0);
478 ex_lw_tail:
479 /* Get the destination register number into r5 */
480 lbui r5, r0, TOPHYS(ex_reg_op);
481 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
482 la r6, r0, TOPHYS(lw_table);
483 addk r5, r5, r5;
484 addk r5, r5, r5;
485 addk r5, r5, r5;
486 addk r5, r5, r6;
487 bra r5;
488 ex_lw_end: /* Exception handling of load word, ends */
489 ex_sw:
490 /* Get the destination register number into r5 */
491 lbui r5, r0, TOPHYS(ex_reg_op);
492 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
493 la r6, r0, TOPHYS(sw_table);
494 add r5, r5, r5;
495 add r5, r5, r5;
496 add r5, r5, r5;
497 add r5, r5, r6;
498 bra r5;
499 ex_sw_tail:
500 mfs r6, resr;
501 nop
502 andi r6, r6, 0x800; /* Extract ESR[W] */
503 beqi r6, ex_shw;
504 /* Get the word - delay slot */
505 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
506 /* Store the word, byte-by-byte into destination address */
507 lbui r3, r0, TOPHYS(ex_tmp_data_loc_0);
508 sbi r3, r4, 0;
509 lbui r3, r0, TOPHYS(ex_tmp_data_loc_1);
510 sbi r3, r4, 1;
511 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
512 sbi r3, r4, 2;
513 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
514 sbi r3, r4, 3;
515 bri ex_handler_done;
517 ex_shw:
518 /* Store the lower half-word, byte-by-byte into destination address */
519 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
520 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
521 sbi r3, r4, 0;
522 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
523 sbi r3, r4, 1;
524 ex_sw_end: /* Exception handling of store word, ends. */
526 ex_handler_done:
527 #ifndef CONFIG_MMU
528 lwi r5, r1, 0 /* RMSR */
529 mts rmsr, r5
530 nop
531 lwi r3, r1, PT_R3
532 lwi r4, r1, PT_R4
533 lwi r5, r1, PT_R5
534 lwi r6, r1, PT_R6
535 lwi r17, r1, PT_R17
537 rted r17, 0
538 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
539 #else
540 RESTORE_STATE;
541 rted r17, 0
542 nop
543 #endif
545 #ifdef CONFIG_MMU
546 /* Exception vector entry code. This code runs with address translation
547 * turned off (i.e. using physical addresses). */
549 /* Exception vectors. */
551 /* 0x10 - Data Storage Exception
552 * This happens for just a few reasons. U0 set (but we don't do that),
553 * or zone protection fault (user violation, write to protected page).
554 * If this is just an update of modified status, we do that quickly
555 * and exit. Otherwise, we call heavyweight functions to do the work.
556 */
557 handle_data_storage_exception:
558 /* Working registers already saved: R3, R4, R5, R6
559 * R3 = ESR
560 */
561 mfs r11, rpid
562 nop
563 bri 4
564 mfs r3, rear /* Get faulting address */
565 nop
566 /* If we are faulting a kernel address, we have to use the
567 * kernel page tables.
568 */
569 ori r4, r0, CONFIG_KERNEL_START
570 cmpu r4, r3, r4
571 bgti r4, ex3
572 /* First, check if it was a zone fault (which means a user
573 * tried to access a kernel or read-protected page - always
574 * a SEGV). All other faults here must be stores, so no
575 * need to check ESR_S as well. */
576 mfs r4, resr
577 nop
578 andi r4, r4, 0x800 /* ESR_Z - zone protection */
579 bnei r4, ex2
581 ori r4, r0, swapper_pg_dir
582 mts rpid, r0 /* TLB will have 0 TID */
583 nop
584 bri ex4
586 /* Get the PGD for the current thread. */
587 ex3:
588 /* First, check if it was a zone fault (which means a user
589 * tried to access a kernel or read-protected page - always
590 * a SEGV). All other faults here must be stores, so no
591 * need to check ESR_S as well. */
592 mfs r4, resr
593 nop
594 andi r4, r4, 0x800 /* ESR_Z */
595 bnei r4, ex2
596 /* get current task address */
597 addi r4 ,CURRENT_TASK, TOPHYS(0);
598 lwi r4, r4, TASK_THREAD+PGDIR
599 ex4:
600 tophys(r4,r4)
601 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
602 andi r5, r5, 0xffc
603 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
604 or r4, r4, r5
605 lwi r4, r4, 0 /* Get L1 entry */
606 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
607 beqi r5, ex2 /* Bail if no table */
609 tophys(r5,r5)
610 BSRLI(r6,r3,10) /* Compute PTE address */
611 andi r6, r6, 0xffc
612 andi r5, r5, 0xfffff003
613 or r5, r5, r6
614 lwi r4, r5, 0 /* Get Linux PTE */
616 andi r6, r4, _PAGE_RW /* Is it writeable? */
617 beqi r6, ex2 /* Bail if not */
619 /* Update 'changed' */
620 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
621 swi r4, r5, 0 /* Update Linux page table */
623 /* Most of the Linux PTE is ready to load into the TLB LO.
624 * We set ZSEL, where only the LS-bit determines user access.
625 * We set execute, because we don't have the granularity to
626 * properly set this at the page level (Linux problem).
627 * If shared is set, we cause a zero PID->TID load.
628 * Many of these bits are software only. Bits we don't set
629 * here we (properly should) assume have the appropriate value.
630 */
631 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
632 ori r4, r4, _PAGE_HWEXEC /* make it executable */
634 /* find the TLB index that caused the fault. It has to be here*/
635 mts rtlbsx, r3
636 nop
637 mfs r5, rtlbx /* DEBUG: TBD */
638 nop
639 mts rtlblo, r4 /* Load TLB LO */
640 nop
641 /* Will sync shadow TLBs */
643 /* Done...restore registers and get out of here. */
644 mts rpid, r11
645 nop
646 bri 4
648 RESTORE_STATE;
649 rted r17, 0
650 nop
651 ex2:
652 /* The bailout. Restore registers to pre-exception conditions
653 * and call the heavyweights to help us out. */
654 mts rpid, r11
655 nop
656 bri 4
657 RESTORE_STATE;
658 bri page_fault_data_trap
661 /* 0x11 - Instruction Storage Exception
662 * This is caused by a fetch from non-execute or guarded pages. */
663 handle_instruction_storage_exception:
664 /* Working registers already saved: R3, R4, R5, R6
665 * R3 = ESR
666 */
668 mfs r3, rear /* Get faulting address */
669 nop
670 RESTORE_STATE;
671 bri page_fault_instr_trap
673 /* 0x12 - Data TLB Miss Exception
674 * As the name implies, translation is not in the MMU, so search the
675 * page tables and fix it. The only purpose of this function is to
676 * load TLB entries from the page table if they exist.
677 */
678 handle_data_tlb_miss_exception:
679 /* Working registers already saved: R3, R4, R5, R6
680 * R3 = ESR
681 */
682 mfs r11, rpid
683 nop
684 bri 4
685 mfs r3, rear /* Get faulting address */
686 nop
688 /* If we are faulting a kernel address, we have to use the
689 * kernel page tables. */
690 ori r4, r0, CONFIG_KERNEL_START
691 cmpu r4, r3, r4
692 bgti r4, ex5
693 ori r4, r0, swapper_pg_dir
694 mts rpid, r0 /* TLB will have 0 TID */
695 nop
696 bri ex6
698 /* Get the PGD for the current thread. */
699 ex5:
700 /* get current task address */
701 addi r4 ,CURRENT_TASK, TOPHYS(0);
702 lwi r4, r4, TASK_THREAD+PGDIR
703 ex6:
704 tophys(r4,r4)
705 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
706 andi r5, r5, 0xffc
707 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
708 or r4, r4, r5
709 lwi r4, r4, 0 /* Get L1 entry */
710 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
711 beqi r5, ex7 /* Bail if no table */
713 tophys(r5,r5)
714 BSRLI(r6,r3,10) /* Compute PTE address */
715 andi r6, r6, 0xffc
716 andi r5, r5, 0xfffff003
717 or r5, r5, r6
718 lwi r4, r5, 0 /* Get Linux PTE */
720 andi r6, r4, _PAGE_PRESENT
721 beqi r6, ex7
723 ori r4, r4, _PAGE_ACCESSED
724 swi r4, r5, 0
726 /* Most of the Linux PTE is ready to load into the TLB LO.
727 * We set ZSEL, where only the LS-bit determines user access.
728 * We set execute, because we don't have the granularity to
729 * properly set this at the page level (Linux problem).
730 * If shared is set, we cause a zero PID->TID load.
731 * Many of these bits are software only. Bits we don't set
732 * here we (properly should) assume have the appropriate value.
733 */
734 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
736 bri finish_tlb_load
737 ex7:
738 /* The bailout. Restore registers to pre-exception conditions
739 * and call the heavyweights to help us out.
740 */
741 mts rpid, r11
742 nop
743 bri 4
744 RESTORE_STATE;
745 bri page_fault_data_trap
747 /* 0x13 - Instruction TLB Miss Exception
748 * Nearly the same as above, except we get our information from
749 * different registers and bailout to a different point.
750 */
751 handle_instruction_tlb_miss_exception:
752 /* Working registers already saved: R3, R4, R5, R6
753 * R3 = ESR
754 */
755 mfs r11, rpid
756 nop
757 bri 4
758 mfs r3, rear /* Get faulting address */
759 nop
761 /* If we are faulting a kernel address, we have to use the
762 * kernel page tables.
763 */
764 ori r4, r0, CONFIG_KERNEL_START
765 cmpu r4, r3, r4
766 bgti r4, ex8
767 ori r4, r0, swapper_pg_dir
768 mts rpid, r0 /* TLB will have 0 TID */
769 nop
770 bri ex9
772 /* Get the PGD for the current thread. */
773 ex8:
774 /* get current task address */
775 addi r4 ,CURRENT_TASK, TOPHYS(0);
776 lwi r4, r4, TASK_THREAD+PGDIR
777 ex9:
778 tophys(r4,r4)
779 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
780 andi r5, r5, 0xffc
781 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
782 or r4, r4, r5
783 lwi r4, r4, 0 /* Get L1 entry */
784 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
785 beqi r5, ex10 /* Bail if no table */
787 tophys(r5,r5)
788 BSRLI(r6,r3,10) /* Compute PTE address */
789 andi r6, r6, 0xffc
790 andi r5, r5, 0xfffff003
791 or r5, r5, r6
792 lwi r4, r5, 0 /* Get Linux PTE */
794 andi r6, r4, _PAGE_PRESENT
795 beqi r6, ex7
797 ori r4, r4, _PAGE_ACCESSED
798 swi r4, r5, 0
800 /* Most of the Linux PTE is ready to load into the TLB LO.
801 * We set ZSEL, where only the LS-bit determines user access.
802 * We set execute, because we don't have the granularity to
803 * properly set this at the page level (Linux problem).
804 * If shared is set, we cause a zero PID->TID load.
805 * Many of these bits are software only. Bits we don't set
806 * here we (properly should) assume have the appropriate value.
807 */
808 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
810 bri finish_tlb_load
811 ex10:
812 /* The bailout. Restore registers to pre-exception conditions
813 * and call the heavyweights to help us out.
814 */
815 mts rpid, r11
816 nop
817 bri 4
818 RESTORE_STATE;
819 bri page_fault_instr_trap
821 /* Both the instruction and data TLB miss get to this point to load the TLB.
822 * r3 - EA of fault
823 * r4 - TLB LO (info from Linux PTE)
824 * r5, r6 - available to use
825 * PID - loaded with proper value when we get here
826 * Upon exit, we reload everything and RFI.
827 * A common place to load the TLB.
828 */
829 tlb_index:
830 .long 1 /* MS: storing last used tlb index */
831 finish_tlb_load:
832 /* MS: load the last used TLB index. */
833 lwi r5, r0, TOPHYS(tlb_index)
834 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
836 /* MS: FIXME this is potential fault, because this is mask not count */
837 andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
838 ori r6, r0, 1
839 cmp r31, r5, r6
840 blti r31, sem
841 addik r5, r6, 1
842 sem:
843 /* MS: save back current TLB index */
844 swi r5, r0, TOPHYS(tlb_index)
846 ori r4, r4, _PAGE_HWEXEC /* make it executable */
847 mts rtlbx, r5 /* MS: save current TLB */
848 nop
849 mts rtlblo, r4 /* MS: save to TLB LO */
850 nop
852 /* Create EPN. This is the faulting address plus a static
853 * set of bits. These are size, valid, E, U0, and ensure
854 * bits 20 and 21 are zero.
855 */
856 andi r3, r3, 0xfffff000
857 ori r3, r3, 0x0c0
858 mts rtlbhi, r3 /* Load TLB HI */
859 nop
861 /* Done...restore registers and get out of here. */
862 ex12:
863 mts rpid, r11
864 nop
865 bri 4
866 RESTORE_STATE;
867 rted r17, 0
868 nop
870 /* extern void giveup_fpu(struct task_struct *prev)
871 *
872 * The MicroBlaze processor may have an FPU, so this should not just
873 * return: TBD.
874 */
875 .globl giveup_fpu;
876 .align 4;
877 giveup_fpu:
878 bralid r15,0 /* TBD */
879 nop
881 /* At present, this routine just hangs. - extern void abort(void) */
882 .globl abort;
883 .align 4;
884 abort:
885 br r0
887 .globl set_context;
888 .align 4;
889 set_context:
890 mts rpid, r5 /* Shadow TLBs are automatically */
891 nop
892 bri 4 /* flushed by changing PID */
893 rtsd r15,8
894 nop
896 #endif
897 .end _hw_exception_handler
899 #ifdef CONFIG_MMU
900 /* Unaligned data access exception last on a 4k page for MMU.
901 * When this is called, we are in virtual mode with exceptions enabled
902 * and registers 1-13,15,17,18 saved.
903 *
904 * R3 = ESR
905 * R4 = EAR
906 * R7 = pointer to saved registers (struct pt_regs *regs)
907 *
908 * This handler perform the access, and returns via ret_from_exc.
909 */
910 .global _unaligned_data_exception
911 .ent _unaligned_data_exception
912 _unaligned_data_exception:
913 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
914 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
915 andi r6, r3, 0x400; /* Extract ESR[S] */
916 bneid r6, ex_sw_vm;
917 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
918 ex_lw_vm:
919 beqid r6, ex_lhw_vm;
920 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
921 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
922 la r6, r0, ex_tmp_data_loc_0;
923 sbi r5, r6, 0;
924 load2: lbui r5, r4, 1;
925 sbi r5, r6, 1;
926 load3: lbui r5, r4, 2;
927 sbi r5, r6, 2;
928 load4: lbui r5, r4, 3;
929 sbi r5, r6, 3;
930 brid ex_lw_tail_vm;
931 /* Get the destination register value into r3 - delay slot */
932 lwi r3, r6, 0;
933 ex_lhw_vm:
934 /* Load a half-word, byte-by-byte from destination address and
935 * save it in tmp space */
936 la r6, r0, ex_tmp_data_loc_0;
937 sbi r5, r6, 0;
938 load5: lbui r5, r4, 1;
939 sbi r5, r6, 1;
940 lhui r3, r6, 0; /* Get the destination register value into r3 */
941 ex_lw_tail_vm:
942 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
943 addik r5, r8, lw_table_vm;
944 bra r5;
945 ex_lw_end_vm: /* Exception handling of load word, ends */
946 brai ret_from_exc;
947 ex_sw_vm:
948 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
949 addik r5, r8, sw_table_vm;
950 bra r5;
951 ex_sw_tail_vm:
952 la r5, r0, ex_tmp_data_loc_0;
953 beqid r6, ex_shw_vm;
954 swi r3, r5, 0; /* Get the word - delay slot */
955 /* Store the word, byte-by-byte into destination address */
956 lbui r3, r5, 0;
957 store1: sbi r3, r4, 0;
958 lbui r3, r5, 1;
959 store2: sbi r3, r4, 1;
960 lbui r3, r5, 2;
961 store3: sbi r3, r4, 2;
962 lbui r3, r5, 3;
963 brid ret_from_exc;
964 store4: sbi r3, r4, 3; /* Delay slot */
965 ex_shw_vm:
966 /* Store the lower half-word, byte-by-byte into destination address */
967 lbui r3, r5, 2;
968 store5: sbi r3, r4, 0;
969 lbui r3, r5, 3;
970 brid ret_from_exc;
971 store6: sbi r3, r4, 1; /* Delay slot */
972 ex_sw_end_vm: /* Exception handling of store word, ends. */
974 /* We have to prevent cases that get/put_user macros get unaligned pointer
975 * to bad page area. We have to find out which origin instruction caused it
976 * and called fixup for that origin instruction not instruction in unaligned
977 * handler */
978 ex_unaligned_fixup:
979 ori r5, r7, 0 /* setup pointer to pt_regs */
980 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
981 addik r6, r6, -4 /* for finding proper fixup */
982 swi r6, r7, PT_PC; /* a save back it to PT_PC */
983 addik r7, r0, SIGSEGV
984 /* call bad_page_fault for finding aligned fixup, fixup address is saved
985 * in PT_PC which is used as return address from exception */
986 la r15, r0, ret_from_exc-8 /* setup return address */
987 brid bad_page_fault
988 nop
990 /* We prevent all load/store because it could failed any attempt to access */
991 .section __ex_table,"a";
992 .word load1,ex_unaligned_fixup;
993 .word load2,ex_unaligned_fixup;
994 .word load3,ex_unaligned_fixup;
995 .word load4,ex_unaligned_fixup;
996 .word load5,ex_unaligned_fixup;
997 .word store1,ex_unaligned_fixup;
998 .word store2,ex_unaligned_fixup;
999 .word store3,ex_unaligned_fixup;
1000 .word store4,ex_unaligned_fixup;
1001 .word store5,ex_unaligned_fixup;
1002 .word store6,ex_unaligned_fixup;
1003 .previous;
1004 .end _unaligned_data_exception
1005 #endif /* CONFIG_MMU */
1007 ex_handler_unhandled:
1008 /* FIXME add handle function for unhandled exception - dump register */
1009 bri 0
1011 /*
1012 * hw_exception_handler Jump Table
1013 * - Contains code snippets for each register that caused the unalign exception
1014 * - Hence exception handler is NOT self-modifying
1015 * - Separate table for load exceptions and store exceptions.
1016 * - Each table is of size: (8 * 32) = 256 bytes
1017 */
1019 .section .text
1020 .align 4
1021 lw_table:
1022 lw_r0: R3_TO_LWREG (0);
1023 lw_r1: LWREG_NOP;
1024 lw_r2: R3_TO_LWREG (2);
1025 lw_r3: R3_TO_LWREG_V (3);
1026 lw_r4: R3_TO_LWREG_V (4);
1027 lw_r5: R3_TO_LWREG_V (5);
1028 lw_r6: R3_TO_LWREG_V (6);
1029 lw_r7: R3_TO_LWREG (7);
1030 lw_r8: R3_TO_LWREG (8);
1031 lw_r9: R3_TO_LWREG (9);
1032 lw_r10: R3_TO_LWREG (10);
1033 lw_r11: R3_TO_LWREG (11);
1034 lw_r12: R3_TO_LWREG (12);
1035 lw_r13: R3_TO_LWREG (13);
1036 lw_r14: R3_TO_LWREG (14);
1037 lw_r15: R3_TO_LWREG (15);
1038 lw_r16: R3_TO_LWREG (16);
1039 lw_r17: LWREG_NOP;
1040 lw_r18: R3_TO_LWREG (18);
1041 lw_r19: R3_TO_LWREG (19);
1042 lw_r20: R3_TO_LWREG (20);
1043 lw_r21: R3_TO_LWREG (21);
1044 lw_r22: R3_TO_LWREG (22);
1045 lw_r23: R3_TO_LWREG (23);
1046 lw_r24: R3_TO_LWREG (24);
1047 lw_r25: R3_TO_LWREG (25);
1048 lw_r26: R3_TO_LWREG (26);
1049 lw_r27: R3_TO_LWREG (27);
1050 lw_r28: R3_TO_LWREG (28);
1051 lw_r29: R3_TO_LWREG (29);
1052 lw_r30: R3_TO_LWREG (30);
1053 #ifdef CONFIG_MMU
1054 lw_r31: R3_TO_LWREG_V (31);
1055 #else
1056 lw_r31: R3_TO_LWREG (31);
1057 #endif
1059 sw_table:
1060 sw_r0: SWREG_TO_R3 (0);
1061 sw_r1: SWREG_NOP;
1062 sw_r2: SWREG_TO_R3 (2);
1063 sw_r3: SWREG_TO_R3_V (3);
1064 sw_r4: SWREG_TO_R3_V (4);
1065 sw_r5: SWREG_TO_R3_V (5);
1066 sw_r6: SWREG_TO_R3_V (6);
1067 sw_r7: SWREG_TO_R3 (7);
1068 sw_r8: SWREG_TO_R3 (8);
1069 sw_r9: SWREG_TO_R3 (9);
1070 sw_r10: SWREG_TO_R3 (10);
1071 sw_r11: SWREG_TO_R3 (11);
1072 sw_r12: SWREG_TO_R3 (12);
1073 sw_r13: SWREG_TO_R3 (13);
1074 sw_r14: SWREG_TO_R3 (14);
1075 sw_r15: SWREG_TO_R3 (15);
1076 sw_r16: SWREG_TO_R3 (16);
1077 sw_r17: SWREG_NOP;
1078 sw_r18: SWREG_TO_R3 (18);
1079 sw_r19: SWREG_TO_R3 (19);
1080 sw_r20: SWREG_TO_R3 (20);
1081 sw_r21: SWREG_TO_R3 (21);
1082 sw_r22: SWREG_TO_R3 (22);
1083 sw_r23: SWREG_TO_R3 (23);
1084 sw_r24: SWREG_TO_R3 (24);
1085 sw_r25: SWREG_TO_R3 (25);
1086 sw_r26: SWREG_TO_R3 (26);
1087 sw_r27: SWREG_TO_R3 (27);
1088 sw_r28: SWREG_TO_R3 (28);
1089 sw_r29: SWREG_TO_R3 (29);
1090 sw_r30: SWREG_TO_R3 (30);
1091 #ifdef CONFIG_MMU
1092 sw_r31: SWREG_TO_R3_V (31);
1093 #else
1094 sw_r31: SWREG_TO_R3 (31);
1095 #endif
1097 #ifdef CONFIG_MMU
1098 lw_table_vm:
1099 lw_r0_vm: R3_TO_LWREG_VM (0);
1100 lw_r1_vm: R3_TO_LWREG_VM_V (1);
1101 lw_r2_vm: R3_TO_LWREG_VM_V (2);
1102 lw_r3_vm: R3_TO_LWREG_VM_V (3);
1103 lw_r4_vm: R3_TO_LWREG_VM_V (4);
1104 lw_r5_vm: R3_TO_LWREG_VM_V (5);
1105 lw_r6_vm: R3_TO_LWREG_VM_V (6);
1106 lw_r7_vm: R3_TO_LWREG_VM_V (7);
1107 lw_r8_vm: R3_TO_LWREG_VM_V (8);
1108 lw_r9_vm: R3_TO_LWREG_VM_V (9);
1109 lw_r10_vm: R3_TO_LWREG_VM_V (10);
1110 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1111 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1112 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1113 lw_r14_vm: R3_TO_LWREG_VM (14);
1114 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1115 lw_r16_vm: R3_TO_LWREG_VM (16);
1116 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1117 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1118 lw_r19_vm: R3_TO_LWREG_VM (19);
1119 lw_r20_vm: R3_TO_LWREG_VM (20);
1120 lw_r21_vm: R3_TO_LWREG_VM (21);
1121 lw_r22_vm: R3_TO_LWREG_VM (22);
1122 lw_r23_vm: R3_TO_LWREG_VM (23);
1123 lw_r24_vm: R3_TO_LWREG_VM (24);
1124 lw_r25_vm: R3_TO_LWREG_VM (25);
1125 lw_r26_vm: R3_TO_LWREG_VM (26);
1126 lw_r27_vm: R3_TO_LWREG_VM (27);
1127 lw_r28_vm: R3_TO_LWREG_VM (28);
1128 lw_r29_vm: R3_TO_LWREG_VM (29);
1129 lw_r30_vm: R3_TO_LWREG_VM (30);
1130 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1132 sw_table_vm:
1133 sw_r0_vm: SWREG_TO_R3_VM (0);
1134 sw_r1_vm: SWREG_TO_R3_VM_V (1);
1135 sw_r2_vm: SWREG_TO_R3_VM_V (2);
1136 sw_r3_vm: SWREG_TO_R3_VM_V (3);
1137 sw_r4_vm: SWREG_TO_R3_VM_V (4);
1138 sw_r5_vm: SWREG_TO_R3_VM_V (5);
1139 sw_r6_vm: SWREG_TO_R3_VM_V (6);
1140 sw_r7_vm: SWREG_TO_R3_VM_V (7);
1141 sw_r8_vm: SWREG_TO_R3_VM_V (8);
1142 sw_r9_vm: SWREG_TO_R3_VM_V (9);
1143 sw_r10_vm: SWREG_TO_R3_VM_V (10);
1144 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1145 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1146 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1147 sw_r14_vm: SWREG_TO_R3_VM (14);
1148 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1149 sw_r16_vm: SWREG_TO_R3_VM (16);
1150 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1151 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1152 sw_r19_vm: SWREG_TO_R3_VM (19);
1153 sw_r20_vm: SWREG_TO_R3_VM (20);
1154 sw_r21_vm: SWREG_TO_R3_VM (21);
1155 sw_r22_vm: SWREG_TO_R3_VM (22);
1156 sw_r23_vm: SWREG_TO_R3_VM (23);
1157 sw_r24_vm: SWREG_TO_R3_VM (24);
1158 sw_r25_vm: SWREG_TO_R3_VM (25);
1159 sw_r26_vm: SWREG_TO_R3_VM (26);
1160 sw_r27_vm: SWREG_TO_R3_VM (27);
1161 sw_r28_vm: SWREG_TO_R3_VM (28);
1162 sw_r29_vm: SWREG_TO_R3_VM (29);
1163 sw_r30_vm: SWREG_TO_R3_VM (30);
1164 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1165 #endif /* CONFIG_MMU */
1167 /* Temporary data structures used in the handler */
1168 .section .data
1169 .align 4
1170 ex_tmp_data_loc_0:
1171 .byte 0
1172 ex_tmp_data_loc_1:
1173 .byte 0
1174 ex_tmp_data_loc_2:
1175 .byte 0
1176 ex_tmp_data_loc_3:
1177 .byte 0
1178 ex_reg_op:
1179 .byte 0