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mm-only debug patch...
[mmotm.git] / arch / mips / pci / ops-tx4927.c
blob5989e747527f2e4e67f591b93a1f4eb2f16652f3
1 /*
2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
3 *
4 * Based on linux/arch/mips/pci/ops-tx4938.c,
5 * linux/arch/mips/pci/fixup-rbtx4938.c,
6 * linux/arch/mips/txx9/rbtx4938/setup.c,
7 * and RBTX49xx patch from CELF patch archive.
8 *
9 * 2003-2005 (c) MontaVista Software, Inc.
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
20 #include <asm/txx9/pci.h>
21 #include <asm/txx9/tx4927pcic.h>
22
23 static struct {
24 struct pci_controller *channel;
25 struct tx4927_pcic_reg __iomem *pcicptr;
26 } pcicptrs[2]; /* TX4938 has 2 pcic */
27
28 static void __init set_tx4927_pcicptr(struct pci_controller *channel,
29 struct tx4927_pcic_reg __iomem *pcicptr)
30 {
31 int i;
32
33 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
34 if (pcicptrs[i].channel == channel) {
35 pcicptrs[i].pcicptr = pcicptr;
36 return;
37 }
38 }
39 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
40 if (!pcicptrs[i].channel) {
41 pcicptrs[i].channel = channel;
42 pcicptrs[i].pcicptr = pcicptr;
43 return;
44 }
45 }
46 BUG();
47 }
48
49 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
50 struct pci_controller *channel)
51 {
52 int i;
53
54 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
55 if (pcicptrs[i].channel == channel)
56 return pcicptrs[i].pcicptr;
57 }
58 return NULL;
59 }
60
61 static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
62 struct tx4927_pcic_reg __iomem *pcicptr)
63 {
64 if (bus->parent == NULL &&
65 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
66 return -1;
67 __raw_writel(((bus->number & 0xff) << 0x10)
68 | ((devfn & 0xff) << 0x08) | (where & 0xfc)
69 | (bus->parent ? 1 : 0),
70 &pcicptr->g2pcfgadrs);
71 /* clear M_ABORT and Disable M_ABORT Int. */
72 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
73 | (PCI_STATUS_REC_MASTER_ABORT << 16),
74 &pcicptr->pcistatus);
75 return 0;
76 }
77
78 static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
79 {
80 int code = PCIBIOS_SUCCESSFUL;
81
82 /* wait write cycle completion before checking error status */
83 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
84 ;
85 if (__raw_readl(&pcicptr->pcistatus)
86 & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
87 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
88 | (PCI_STATUS_REC_MASTER_ABORT << 16),
89 &pcicptr->pcistatus);
90 /* flush write buffer */
91 iob();
92 code = PCIBIOS_DEVICE_NOT_FOUND;
93 }
94 return code;
95 }
96
97 static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
98 {
99 #ifdef __BIG_ENDIAN
100 offset ^= 3;
101 #endif
102 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
103 }
104 static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
105 {
106 #ifdef __BIG_ENDIAN
107 offset ^= 2;
108 #endif
109 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
110 }
111 static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
112 {
113 return __raw_readl(&pcicptr->g2pcfgdata);
114 }
115 static void icd_writeb(u8 val, int offset,
116 struct tx4927_pcic_reg __iomem *pcicptr)
117 {
118 #ifdef __BIG_ENDIAN
119 offset ^= 3;
120 #endif
121 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
122 }
123 static void icd_writew(u16 val, int offset,
124 struct tx4927_pcic_reg __iomem *pcicptr)
125 {
126 #ifdef __BIG_ENDIAN
127 offset ^= 2;
128 #endif
129 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
130 }
131 static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
132 {
133 __raw_writel(val, &pcicptr->g2pcfgdata);
134 }
135
136 static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
137 {
138 struct pci_controller *channel = bus->sysdata;
139 return get_tx4927_pcicptr(channel);
140 }
141
142 static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
143 int where, int size, u32 *val)
144 {
145 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
146
147 if (mkaddr(bus, devfn, where, pcicptr)) {
148 *val = 0xffffffff;
149 return -1;
150 }
151 switch (size) {
152 case 1:
153 *val = icd_readb(where & 3, pcicptr);
154 break;
155 case 2:
156 *val = icd_readw(where & 3, pcicptr);
157 break;
158 default:
159 *val = icd_readl(pcicptr);
160 }
161 return check_abort(pcicptr);
162 }
163
164 static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
165 int where, int size, u32 val)
166 {
167 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
168
169 if (mkaddr(bus, devfn, where, pcicptr))
170 return -1;
171 switch (size) {
172 case 1:
173 icd_writeb(val, where & 3, pcicptr);
174 break;
175 case 2:
176 icd_writew(val, where & 3, pcicptr);
177 break;
178 default:
179 icd_writel(val, pcicptr);
180 }
181 return check_abort(pcicptr);
182 }
183
184 static struct pci_ops tx4927_pci_ops = {
185 .read = tx4927_pci_config_read,
186 .write = tx4927_pci_config_write,
187 };
188
189 static struct {
190 u8 trdyto;
191 u8 retryto;
192 u16 gbwc;
193 } tx4927_pci_opts __devinitdata = {
194 .trdyto = 0,
195 .retryto = 0,
196 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
197 };
198
199 char *__devinit tx4927_pcibios_setup(char *str)
200 {
201 unsigned long val;
202
203 if (!strncmp(str, "trdyto=", 7)) {
204 if (strict_strtoul(str + 7, 0, &val) == 0)
205 tx4927_pci_opts.trdyto = val;
206 return NULL;
207 }
208 if (!strncmp(str, "retryto=", 8)) {
209 if (strict_strtoul(str + 8, 0, &val) == 0)
210 tx4927_pci_opts.retryto = val;
211 return NULL;
212 }
213 if (!strncmp(str, "gbwc=", 5)) {
214 if (strict_strtoul(str + 5, 0, &val) == 0)
215 tx4927_pci_opts.gbwc = val;
216 return NULL;
217 }
218 return str;
219 }
220
221 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
222 struct pci_controller *channel, int extarb)
223 {
224 int i;
225 unsigned long flags;
226
227 set_tx4927_pcicptr(channel, pcicptr);
228
229 if (!channel->pci_ops)
230 printk(KERN_INFO
231 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
232 __raw_readl(&pcicptr->pciid) >> 16,
233 __raw_readl(&pcicptr->pciid) & 0xffff,
234 __raw_readl(&pcicptr->pciccrev) & 0xff,
235 extarb ? "External" : "Internal");
236 channel->pci_ops = &tx4927_pci_ops;
237
238 local_irq_save(flags);
239
240 /* Disable All Initiator Space */
241 __raw_writel(__raw_readl(&pcicptr->pciccfg)
242 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
243 | TX4927_PCIC_PCICCFG_G2PMEN(1)
244 | TX4927_PCIC_PCICCFG_G2PMEN(2)
245 | TX4927_PCIC_PCICCFG_G2PIOEN),
246 &pcicptr->pciccfg);
247
248 /* GB->PCI mappings */
249 __raw_writel((channel->io_resource->end - channel->io_resource->start)
250 >> 4,
251 &pcicptr->g2piomask);
252 ____raw_writeq((channel->io_resource->start +
253 channel->io_map_base - IO_BASE) |
254 #ifdef __BIG_ENDIAN
255 TX4927_PCIC_G2PIOGBASE_ECHG
256 #else
257 TX4927_PCIC_G2PIOGBASE_BSDIS
258 #endif
259 , &pcicptr->g2piogbase);
260 ____raw_writeq(channel->io_resource->start - channel->io_offset,
261 &pcicptr->g2piopbase);
262 for (i = 0; i < 3; i++) {
263 __raw_writel(0, &pcicptr->g2pmmask[i]);
264 ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
265 ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
266 }
267 if (channel->mem_resource->end) {
268 __raw_writel((channel->mem_resource->end
269 - channel->mem_resource->start) >> 4,
270 &pcicptr->g2pmmask[0]);
271 ____raw_writeq(channel->mem_resource->start |
272 #ifdef __BIG_ENDIAN
273 TX4927_PCIC_G2PMnGBASE_ECHG
274 #else
275 TX4927_PCIC_G2PMnGBASE_BSDIS
276 #endif
277 , &pcicptr->g2pmgbase[0]);
278 ____raw_writeq(channel->mem_resource->start -
279 channel->mem_offset,
280 &pcicptr->g2pmpbase[0]);
281 }
282 /* PCI->GB mappings (I/O 256B) */
283 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
284 ____raw_writeq(0, &pcicptr->p2giogbase);
285 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
286 __raw_writel(0, &pcicptr->p2gm0plbase);
287 __raw_writel(0, &pcicptr->p2gm0pubase);
288 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
289 #ifdef __BIG_ENDIAN
290 TX4927_PCIC_P2GMnGBASE_TECHG
291 #else
292 TX4927_PCIC_P2GMnGBASE_TBSDIS
293 #endif
294 , &pcicptr->p2gmgbase[0]);
295 /* PCI->GB mappings (MEM 16MB) */
296 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
297 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
298 ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
299 /* PCI->GB mappings (MEM 1MB) */
300 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
301 ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
302
303 /* Clear all (including IRBER) except for GBWC */
304 __raw_writel((tx4927_pci_opts.gbwc << 16)
305 & TX4927_PCIC_PCICCFG_GBWC_MASK,
306 &pcicptr->pciccfg);
307 /* Enable Initiator Memory Space */
308 if (channel->mem_resource->end)
309 __raw_writel(__raw_readl(&pcicptr->pciccfg)
310 | TX4927_PCIC_PCICCFG_G2PMEN(0),
311 &pcicptr->pciccfg);
312 /* Enable Initiator I/O Space */
313 if (channel->io_resource->end)
314 __raw_writel(__raw_readl(&pcicptr->pciccfg)
315 | TX4927_PCIC_PCICCFG_G2PIOEN,
316 &pcicptr->pciccfg);
317 /* Enable Initiator Config */
318 __raw_writel(__raw_readl(&pcicptr->pciccfg)
319 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
320 &pcicptr->pciccfg);
321
322 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
323 __raw_writel(0, &pcicptr->pcicfg1);
324
325 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
326 | (tx4927_pci_opts.trdyto & 0xff)
327 | ((tx4927_pci_opts.retryto & 0xff) << 8),
328 &pcicptr->g2ptocnt);
329
330 /* Clear All Local Bus Status */
331 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
332 /* Enable All Local Bus Interrupts */
333 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
334 /* Clear All Initiator Status */
335 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
336 /* Enable All Initiator Interrupts */
337 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
338 /* Clear All PCI Status Error */
339 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
340 | (TX4927_PCIC_PCISTATUS_ALL << 16),
341 &pcicptr->pcistatus);
342 /* Enable All PCI Status Error Interrupts */
343 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
344
345 if (!extarb) {
346 /* Reset Bus Arbiter */
347 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
348 __raw_writel(0, &pcicptr->pbabm);
349 /* Enable Bus Arbiter */
350 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
351 }
352
353 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
354 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
355 &pcicptr->pcistatus);
356 local_irq_restore(flags);
357
358 printk(KERN_DEBUG
359 "PCI: COMMAND=%04x,PCIMASK=%04x,"
360 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
361 __raw_readl(&pcicptr->pcistatus) & 0xffff,
362 __raw_readl(&pcicptr->pcimask) & 0xffff,
363 __raw_readl(&pcicptr->g2ptocnt) & 0xff,
364 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
365 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
366 }
367
368 static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
369 {
370 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
371 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
372 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
373 static struct {
374 __u32 flag;
375 const char *str;
376 } pcistat_tbl[] = {
377 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
378 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
379 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
380 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
381 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
382 { PCI_STATUS_PARITY, "MasterParityError" },
383 }, g2pstat_tbl[] = {
384 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
385 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
386 }, pcicstat_tbl[] = {
387 { TX4927_PCIC_PCICSTATUS_PME, "PME" },
388 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
389 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
390 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
391 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
392 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
393 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
394 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
395 };
396 int i, cont;
397
398 printk(KERN_ERR "");
399 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
400 printk(KERN_CONT "pcistat:%04x(", pcistatus);
401 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
402 if (pcistatus & pcistat_tbl[i].flag)
403 printk(KERN_CONT "%s%s",
404 cont++ ? " " : "", pcistat_tbl[i].str);
405 printk(KERN_CONT ") ");
406 }
407 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
408 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
409 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
410 if (g2pstatus & g2pstat_tbl[i].flag)
411 printk(KERN_CONT "%s%s",
412 cont++ ? " " : "", g2pstat_tbl[i].str);
413 printk(KERN_CONT ") ");
414 }
415 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
416 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
417 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
418 if (pcicstatus & pcicstat_tbl[i].flag)
419 printk(KERN_CONT "%s%s",
420 cont++ ? " " : "", pcicstat_tbl[i].str);
421 printk(KERN_CONT ")");
422 }
423 printk(KERN_CONT "\n");
424 }
425
426 void tx4927_report_pcic_status(void)
427 {
428 int i;
429
430 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
431 if (pcicptrs[i].pcicptr)
432 tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
433 }
434 }
435
436 static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
437 {
438 int i;
439 __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
440
441 printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
442 for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
443 if (i % 32 == 0) {
444 printk(KERN_CONT "\n");
445 printk(KERN_INFO "%04x:", i);
446 }
447 /* skip registers with side-effects */
448 if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
449 || i == offsetof(struct tx4927_pcic_reg, g2pspc)
450 || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
451 || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
452 printk(KERN_CONT " XXXXXXXX");
453 continue;
454 }
455 printk(KERN_CONT " %08x", __raw_readl(preg));
456 }
457 printk(KERN_CONT "\n");
458 }
459
460 void tx4927_dump_pcic_settings(void)
461 {
462 int i;
463
464 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
465 if (pcicptrs[i].pcicptr)
466 tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
467 }
468 }
469
470 irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
471 {
472 struct pt_regs *regs = get_irq_regs();
473 struct tx4927_pcic_reg __iomem *pcicptr =
474 (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
475
476 if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
477 printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
478 (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
479 tx4927_report_pcic_status1(pcicptr);
480 }
481 if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
482 /* clear all pci errors */
483 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
484 | (TX4927_PCIC_PCISTATUS_ALL << 16),
485 &pcicptr->pcistatus);
486 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
487 __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
488 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
489 return IRQ_HANDLED;
490 }
491 console_verbose();
492 tx4927_dump_pcic_settings1(pcicptr);
493 panic("PCI error.");
494 }
495
496 #ifdef CONFIG_TOSHIBA_FPCIB0
497 static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
498 {
499 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
500
501 if (!pcicptr)
502 return;
503 if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
504 /* Reset Bus Arbiter */
505 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
506 /*
507 * swap reqBP and reqXP (raise priority of SLC90E66).
508 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
509 * PCI Backplane board.
510 */
511 __raw_writel(0x72543610, &pcicptr->pbareqport);
512 __raw_writel(0, &pcicptr->pbabm);
513 /* Use Fixed ParkMaster (required by SLC90E66) */
514 __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
515 /* Enable Bus Arbiter */
516 __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
517 TX4927_PCIC_PBACFG_PBAEN,
518 &pcicptr->pbacfg);
519 printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
520 __raw_readl(&pcicptr->pbareqport));
521 }
522 }
523 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
525 tx4927_quirk_slc90e66_bridge);
526 #endif
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