arch/powerpc/kernel/setup_32.c

   1 /*
   2  * Common prep/pmac/chrp boot and setup code.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/string.h>
   7 #include <linux/sched.h>
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/reboot.h>
  11 #include <linux/delay.h>
  12 #include <linux/initrd.h>
  13 #include <linux/tty.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/root_dev.h>
  17 #include <linux/cpu.h>
  18 #include <linux/console.h>
  19 #include <linux/lmb.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/prom.h>
  23 #include <asm/processor.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/setup.h>
  26 #include <asm/smp.h>
  27 #include <asm/elf.h>
  28 #include <asm/cputable.h>
  29 #include <asm/bootx.h>
  30 #include <asm/btext.h>
  31 #include <asm/machdep.h>
  32 #include <asm/uaccess.h>
  33 #include <asm/system.h>
  34 #include <asm/pmac_feature.h>
  35 #include <asm/sections.h>
  36 #include <asm/nvram.h>
  37 #include <asm/xmon.h>
  38 #include <asm/time.h>
  39 #include <asm/serial.h>
  40 #include <asm/udbg.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/swiotlb.h>
  43
  44 #include "setup.h"
  45
  46 #define DBG(fmt...)
  47
  48 extern void bootx_init(unsigned long r4, unsigned long phys);
  49
  50 int boot_cpuid;
  51 EXPORT_SYMBOL_GPL(boot_cpuid);
  52 int boot_cpuid_phys;
  53
  54 int smp_hw_index[NR_CPUS];
  55
  56 unsigned long ISA_DMA_THRESHOLD;
  57 unsigned int DMA_MODE_READ;
  58 unsigned int DMA_MODE_WRITE;
  59
  60 #ifdef CONFIG_VGA_CONSOLE
  61 unsigned long vgacon_remap_base;
  62 EXPORT_SYMBOL(vgacon_remap_base);
  63 #endif
  64
  65 /*
  66  * These are used in binfmt_elf.c to put aux entries on the stack
  67  * for each elf executable being started.
  68  */
  69 int dcache_bsize;
  70 int icache_bsize;
  71 int ucache_bsize;
  72
  73 /*
  74  * We're called here very early in the boot.  We determine the machine
  75  * type and call the appropriate low-level setup functions.
  76  *  -- Cort <cort@fsmlabs.com>
  77  *
  78  * Note that the kernel may be running at an address which is different
  79  * from the address that it was linked at, so we must use RELOC/PTRRELOC
  80  * to access static data (including strings).  -- paulus
  81  */
  82 notrace unsigned long __init early_init(unsigned long dt_ptr)
  83 {
  84         unsigned long offset = reloc_offset();
  85         struct cpu_spec *spec;
  86
  87         /* First zero the BSS -- use memset_io, some platforms don't have
  88          * caches on yet */
  89         memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
  90                         __bss_stop - __bss_start);
  91
  92         /*
  93          * Identify the CPU type and fix up code sections
  94          * that depend on which cpu we have.
  95          */
  96         spec = identify_cpu(offset, mfspr(SPRN_PVR));
  97
  98         do_feature_fixups(spec->cpu_features,
  99                           PTRRELOC(&__start___ftr_fixup),
 100                           PTRRELOC(&__stop___ftr_fixup));
 101
 102         do_feature_fixups(spec->mmu_features,
 103                           PTRRELOC(&__start___mmu_ftr_fixup),
 104                           PTRRELOC(&__stop___mmu_ftr_fixup));
 105
 106         do_lwsync_fixups(spec->cpu_features,
 107                          PTRRELOC(&__start___lwsync_fixup),
 108                          PTRRELOC(&__stop___lwsync_fixup));
 109
 110         return KERNELBASE + offset;
 111 }
 112
 113
 114 /*
 115  * Find out what kind of machine we're on and save any data we need
 116  * from the early boot process (devtree is copied on pmac by prom_init()).
 117  * This is called very early on the boot process, after a minimal
 118  * MMU environment has been set up but before MMU_init is called.
 119  */
 120 notrace void __init machine_init(unsigned long dt_ptr)
 121 {
 122         lockdep_init();
 123
 124         /* Enable early debugging if any specified (see udbg.h) */
 125         udbg_early_init();
 126
 127         /* Do some early initialization based on the flat device tree */
 128         early_init_devtree(__va(dt_ptr));
 129
 130         probe_machine();
 131
 132         setup_kdump_trampoline();
 133
 134 #ifdef CONFIG_6xx
 135         if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
 136             cpu_has_feature(CPU_FTR_CAN_NAP))
 137                 ppc_md.power_save = ppc6xx_idle;
 138 #endif
 139
 140 #ifdef CONFIG_E500
 141         if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
 142             cpu_has_feature(CPU_FTR_CAN_NAP))
 143                 ppc_md.power_save = e500_idle;
 144 #endif
 145         if (ppc_md.progress)
 146                 ppc_md.progress("id mach(): done", 0x200);
 147 }
 148
 149 #ifdef CONFIG_BOOKE_WDT
 150 /* Checks wdt=x and wdt_period=xx command-line option */
 151 notrace int __init early_parse_wdt(char *p)
 152 {
 153         if (p && strncmp(p, "0", 1) != 0)
 154                booke_wdt_enabled = 1;
 155
 156         return 0;
 157 }
 158 early_param("wdt", early_parse_wdt);
 159
 160 int __init early_parse_wdt_period (char *p)
 161 {
 162         if (p)
 163                 booke_wdt_period = simple_strtoul(p, NULL, 0);
 164
 165         return 0;
 166 }
 167 early_param("wdt_period", early_parse_wdt_period);
 168 #endif  /* CONFIG_BOOKE_WDT */
 169
 170 /* Checks "l2cr=xxxx" command-line option */
 171 int __init ppc_setup_l2cr(char *str)
 172 {
 173         if (cpu_has_feature(CPU_FTR_L2CR)) {
 174                 unsigned long val = simple_strtoul(str, NULL, 0);
 175                 printk(KERN_INFO "l2cr set to %lx\n", val);
 176                 _set_L2CR(0);           /* force invalidate by disable cache */
 177                 _set_L2CR(val);         /* and enable it */
 178         }
 179         return 1;
 180 }
 181 __setup("l2cr=", ppc_setup_l2cr);
 182
 183 /* Checks "l3cr=xxxx" command-line option */
 184 int __init ppc_setup_l3cr(char *str)
 185 {
 186         if (cpu_has_feature(CPU_FTR_L3CR)) {
 187                 unsigned long val = simple_strtoul(str, NULL, 0);
 188                 printk(KERN_INFO "l3cr set to %lx\n", val);
 189                 _set_L3CR(val);         /* and enable it */
 190         }
 191         return 1;
 192 }
 193 __setup("l3cr=", ppc_setup_l3cr);
 194
 195 #ifdef CONFIG_GENERIC_NVRAM
 196
 197 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
 198 unsigned char nvram_read_byte(int addr)
 199 {
 200         if (ppc_md.nvram_read_val)
 201                 return ppc_md.nvram_read_val(addr);
 202         return 0xff;
 203 }
 204 EXPORT_SYMBOL(nvram_read_byte);
 205
 206 void nvram_write_byte(unsigned char val, int addr)
 207 {
 208         if (ppc_md.nvram_write_val)
 209                 ppc_md.nvram_write_val(addr, val);
 210 }
 211 EXPORT_SYMBOL(nvram_write_byte);
 212
 213 ssize_t nvram_get_size(void)
 214 {
 215         if (ppc_md.nvram_size)
 216                 return ppc_md.nvram_size();
 217         return -1;
 218 }
 219 EXPORT_SYMBOL(nvram_get_size);
 220
 221 void nvram_sync(void)
 222 {
 223         if (ppc_md.nvram_sync)
 224                 ppc_md.nvram_sync();
 225 }
 226 EXPORT_SYMBOL(nvram_sync);
 227
 228 #endif /* CONFIG_NVRAM */
 229
 230 int __init ppc_init(void)
 231 {
 232         /* clear the progress line */
 233         if (ppc_md.progress)
 234                 ppc_md.progress("             ", 0xffff);
 235
 236         /* call platform init */
 237         if (ppc_md.init != NULL) {
 238                 ppc_md.init();
 239         }
 240         return 0;
 241 }
 242
 243 arch_initcall(ppc_init);
 244
 245 #ifdef CONFIG_IRQSTACKS
 246 static void __init irqstack_early_init(void)
 247 {
 248         unsigned int i;
 249
 250         /* interrupt stacks must be in lowmem, we get that for free on ppc32
 251          * as the lmb is limited to lowmem by LMB_REAL_LIMIT */
 252         for_each_possible_cpu(i) {
 253                 softirq_ctx[i] = (struct thread_info *)
 254                         __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
 255                 hardirq_ctx[i] = (struct thread_info *)
 256                         __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
 257         }
 258 }
 259 #else
 260 #define irqstack_early_init()
 261 #endif
 262
 263 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 264 static void __init exc_lvl_early_init(void)
 265 {
 266         unsigned int i;
 267
 268         /* interrupt stacks must be in lowmem, we get that for free on ppc32
 269          * as the lmb is limited to lowmem by LMB_REAL_LIMIT */
 270         for_each_possible_cpu(i) {
 271                 critirq_ctx[i] = (struct thread_info *)
 272                         __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
 273 #ifdef CONFIG_BOOKE
 274                 dbgirq_ctx[i] = (struct thread_info *)
 275                         __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
 276                 mcheckirq_ctx[i] = (struct thread_info *)
 277                         __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
 278 #endif
 279         }
 280 }
 281 #else
 282 #define exc_lvl_early_init()
 283 #endif
 284
 285 /* Warning, IO base is not yet inited */
 286 void __init setup_arch(char **cmdline_p)
 287 {
 288         *cmdline_p = cmd_line;
 289
 290         /* so udelay does something sensible, assume <= 1000 bogomips */
 291         loops_per_jiffy = 500000000 / HZ;
 292
 293         unflatten_device_tree();
 294         check_for_initrd();
 295
 296         if (ppc_md.init_early)
 297                 ppc_md.init_early();
 298
 299         find_legacy_serial_ports();
 300
 301         smp_setup_cpu_maps();
 302
 303         /* Register early console */
 304         register_early_udbg_console();
 305
 306         xmon_setup();
 307
 308         /*
 309          * Set cache line size based on type of cpu as a default.
 310          * Systems with OF can look in the properties on the cpu node(s)
 311          * for a possibly more accurate value.
 312          */
 313         dcache_bsize = cur_cpu_spec->dcache_bsize;
 314         icache_bsize = cur_cpu_spec->icache_bsize;
 315         ucache_bsize = 0;
 316         if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
 317                 ucache_bsize = icache_bsize = dcache_bsize;
 318
 319         /* reboot on panic */
 320         panic_timeout = 180;
 321
 322         if (ppc_md.panic)
 323                 setup_panic();
 324
 325         init_mm.start_code = (unsigned long)_stext;
 326         init_mm.end_code = (unsigned long) _etext;
 327         init_mm.end_data = (unsigned long) _edata;
 328         init_mm.brk = klimit;
 329
 330         exc_lvl_early_init();
 331
 332         irqstack_early_init();
 333
 334         /* set up the bootmem stuff with available memory */
 335         do_init_bootmem();
 336         if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
 337
 338 #ifdef CONFIG_DUMMY_CONSOLE
 339         conswitchp = &dummy_con;
 340 #endif
 341
 342         if (ppc_md.setup_arch)
 343                 ppc_md.setup_arch();
 344         if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
 345
 346 #ifdef CONFIG_SWIOTLB
 347         if (ppc_swiotlb_enable)
 348                 swiotlb_init();
 349 #endif
 350
 351         paging_init();
 352
 353         /* Initialize the MMU context management stuff */
 354         mmu_context_init();
 355
 356 }