mm-only debug patch...
[mmotm.git] / arch / sh / boards / board-polaris.c
blob62607eb5100444985c164b29df04ccaec9d980da
1 /*
2 * June 2006 steve.glendinning@smsc.com
4 * Polaris-specific resource declaration
6 */
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/platform_device.h>
12 #include <linux/smsc911x.h>
13 #include <linux/io.h>
14 #include <asm/irq.h>
15 #include <asm/machvec.h>
16 #include <asm/heartbeat.h>
17 #include <cpu/gpio.h>
18 #include <mach-se/mach/se.h>
20 #define BCR2 (0xFFFFFF62)
21 #define WCR2 (0xFFFFFF66)
22 #define AREA5_WAIT_CTRL (0x1C00)
23 #define WAIT_STATES_10 (0x7)
25 static struct resource smsc911x_resources[] = {
26 [0] = {
27 .name = "smsc911x-memory",
28 .start = PA_EXT5,
29 .end = PA_EXT5 + 0x1fff,
30 .flags = IORESOURCE_MEM,
32 [1] = {
33 .name = "smsc911x-irq",
34 .start = IRQ0_IRQ,
35 .end = IRQ0_IRQ,
36 .flags = IORESOURCE_IRQ,
40 static struct smsc911x_platform_config smsc911x_config = {
41 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
42 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
43 .flags = SMSC911X_USE_32BIT,
44 .phy_interface = PHY_INTERFACE_MODE_MII,
47 static struct platform_device smsc911x_device = {
48 .name = "smsc911x",
49 .id = 0,
50 .num_resources = ARRAY_SIZE(smsc911x_resources),
51 .resource = smsc911x_resources,
52 .dev = {
53 .platform_data = &smsc911x_config,
57 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
59 static struct heartbeat_data heartbeat_data = {
60 .bit_pos = heartbeat_bit_pos,
61 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
62 .regsize = 8,
65 static struct resource heartbeat_resources[] = {
66 [0] = {
67 .start = PORT_PCDR,
68 .end = PORT_PCDR,
69 .flags = IORESOURCE_MEM,
73 static struct platform_device heartbeat_device = {
74 .name = "heartbeat",
75 .id = -1,
76 .dev = {
77 .platform_data = &heartbeat_data,
79 .num_resources = ARRAY_SIZE(heartbeat_resources),
80 .resource = heartbeat_resources,
83 static struct platform_device *polaris_devices[] __initdata = {
84 &smsc911x_device,
85 &heartbeat_device,
88 static int __init polaris_initialise(void)
90 u16 wcr, bcr_mask;
92 printk(KERN_INFO "Configuring Polaris external bus\n");
94 /* Configure area 5 with 2 wait states */
95 wcr = ctrl_inw(WCR2);
96 wcr &= (~AREA5_WAIT_CTRL);
97 wcr |= (WAIT_STATES_10 << 10);
98 ctrl_outw(wcr, WCR2);
100 /* Configure area 5 for 32-bit access */
101 bcr_mask = ctrl_inw(BCR2);
102 bcr_mask |= 1 << 10;
103 ctrl_outw(bcr_mask, BCR2);
105 return platform_add_devices(polaris_devices,
106 ARRAY_SIZE(polaris_devices));
108 arch_initcall(polaris_initialise);
110 static struct ipr_data ipr_irq_table[] = {
111 /* External IRQs */
112 { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */
113 { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */
116 static unsigned long ipr_offsets[] = {
117 INTC_IPRC
120 static struct ipr_desc ipr_irq_desc = {
121 .ipr_offsets = ipr_offsets,
122 .nr_offsets = ARRAY_SIZE(ipr_offsets),
124 .ipr_data = ipr_irq_table,
125 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
126 .chip = {
127 .name = "sh7709-ext",
131 static void __init init_polaris_irq(void)
133 /* Disable all interrupts */
134 ctrl_outw(0, BCR_ILCRA);
135 ctrl_outw(0, BCR_ILCRB);
136 ctrl_outw(0, BCR_ILCRC);
137 ctrl_outw(0, BCR_ILCRD);
138 ctrl_outw(0, BCR_ILCRE);
139 ctrl_outw(0, BCR_ILCRF);
140 ctrl_outw(0, BCR_ILCRG);
142 register_ipr_controller(&ipr_irq_desc);
145 static struct sh_machine_vector mv_polaris __initmv = {
146 .mv_name = "Polaris",
147 .mv_nr_irqs = 61,
148 .mv_init_irq = init_polaris_irq,