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mm-only debug patch...
[mmotm.git] / drivers / dma / ipu / ipu_idmac.c
blob9a5bc1a7389e61abc82e78aee287934f13c2eef7
1 /*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/err.h>
15 #include <linux/spinlock.h>
16 #include <linux/delay.h>
17 #include <linux/list.h>
18 #include <linux/clk.h>
19 #include <linux/vmalloc.h>
20 #include <linux/string.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23
24 #include <mach/ipu.h>
25
26 #include "ipu_intern.h"
27
28 #define FS_VF_IN_VALID 0x00000002
29 #define FS_ENC_IN_VALID 0x00000001
30
31 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
32 bool wait_for_stop);
33
34 /*
35 * There can be only one, we could allocate it dynamically, but then we'd have
36 * to add an extra parameter to some functions, and use something as ugly as
37 * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
38 * in the ISR
39 */
40 static struct ipu ipu_data;
41
42 #define to_ipu(id) container_of(id, struct ipu, idmac)
43
44 static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
45 {
46 return __raw_readl(ipu->reg_ic + reg);
47 }
48
49 #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
50
51 static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
52 {
53 __raw_writel(value, ipu->reg_ic + reg);
54 }
55
56 #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
57
58 static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
59 {
60 return __raw_readl(ipu->reg_ipu + reg);
61 }
62
63 static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
64 {
65 __raw_writel(value, ipu->reg_ipu + reg);
66 }
67
68 /*****************************************************************************
69 * IPU / IC common functions
70 */
71 static void dump_idmac_reg(struct ipu *ipu)
72 {
73 dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
74 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
75 idmac_read_icreg(ipu, IDMAC_CONF),
76 idmac_read_icreg(ipu, IC_CONF),
77 idmac_read_icreg(ipu, IDMAC_CHA_EN),
78 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
79 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
80 dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
81 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
82 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
83 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
84 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
85 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
86 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
87 }
88
89 static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
90 {
91 switch (fmt) {
92 case IPU_PIX_FMT_GENERIC: /* generic data */
93 case IPU_PIX_FMT_RGB332:
94 case IPU_PIX_FMT_YUV420P:
95 case IPU_PIX_FMT_YUV422P:
96 default:
97 return 1;
98 case IPU_PIX_FMT_RGB565:
99 case IPU_PIX_FMT_YUYV:
100 case IPU_PIX_FMT_UYVY:
101 return 2;
102 case IPU_PIX_FMT_BGR24:
103 case IPU_PIX_FMT_RGB24:
104 return 3;
105 case IPU_PIX_FMT_GENERIC_32: /* generic data */
106 case IPU_PIX_FMT_BGR32:
107 case IPU_PIX_FMT_RGB32:
108 case IPU_PIX_FMT_ABGR32:
109 return 4;
110 }
111 }
112
113 /* Enable direct write to memory by the Camera Sensor Interface */
114 static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
115 {
116 uint32_t ic_conf, mask;
117
118 switch (channel) {
119 case IDMAC_IC_0:
120 mask = IC_CONF_PRPENC_EN;
121 break;
122 case IDMAC_IC_7:
123 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
124 break;
125 default:
126 return;
127 }
128 ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
129 idmac_write_icreg(ipu, ic_conf, IC_CONF);
130 }
131
132 /* Called under spin_lock_irqsave(&ipu_data.lock) */
133 static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
134 {
135 uint32_t ic_conf, mask;
136
137 switch (channel) {
138 case IDMAC_IC_0:
139 mask = IC_CONF_PRPENC_EN;
140 break;
141 case IDMAC_IC_7:
142 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
143 break;
144 default:
145 return;
146 }
147 ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
148 idmac_write_icreg(ipu, ic_conf, IC_CONF);
149 }
150
151 static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
152 {
153 uint32_t stat = TASK_STAT_IDLE;
154 uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
155
156 switch (channel) {
157 case IDMAC_IC_7:
158 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
159 TSTAT_CSI2MEM_OFFSET;
160 break;
161 case IDMAC_IC_0:
162 case IDMAC_SDC_0:
163 case IDMAC_SDC_1:
164 default:
165 break;
166 }
167 return stat;
168 }
169
170 struct chan_param_mem_planar {
171 /* Word 0 */
172 u32 xv:10;
173 u32 yv:10;
174 u32 xb:12;
175
176 u32 yb:12;
177 u32 res1:2;
178 u32 nsb:1;
179 u32 lnpb:6;
180 u32 ubo_l:11;
181
182 u32 ubo_h:15;
183 u32 vbo_l:17;
184
185 u32 vbo_h:9;
186 u32 res2:3;
187 u32 fw:12;
188 u32 fh_l:8;
189
190 u32 fh_h:4;
191 u32 res3:28;
192
193 /* Word 1 */
194 u32 eba0;
195
196 u32 eba1;
197
198 u32 bpp:3;
199 u32 sl:14;
200 u32 pfs:3;
201 u32 bam:3;
202 u32 res4:2;
203 u32 npb:6;
204 u32 res5:1;
205
206 u32 sat:2;
207 u32 res6:30;
208 } __attribute__ ((packed));
209
210 struct chan_param_mem_interleaved {
211 /* Word 0 */
212 u32 xv:10;
213 u32 yv:10;
214 u32 xb:12;
215
216 u32 yb:12;
217 u32 sce:1;
218 u32 res1:1;
219 u32 nsb:1;
220 u32 lnpb:6;
221 u32 sx:10;
222 u32 sy_l:1;
223
224 u32 sy_h:9;
225 u32 ns:10;
226 u32 sm:10;
227 u32 sdx_l:3;
228
229 u32 sdx_h:2;
230 u32 sdy:5;
231 u32 sdrx:1;
232 u32 sdry:1;
233 u32 sdr1:1;
234 u32 res2:2;
235 u32 fw:12;
236 u32 fh_l:8;
237
238 u32 fh_h:4;
239 u32 res3:28;
240
241 /* Word 1 */
242 u32 eba0;
243
244 u32 eba1;
245
246 u32 bpp:3;
247 u32 sl:14;
248 u32 pfs:3;
249 u32 bam:3;
250 u32 res4:2;
251 u32 npb:6;
252 u32 res5:1;
253
254 u32 sat:2;
255 u32 scc:1;
256 u32 ofs0:5;
257 u32 ofs1:5;
258 u32 ofs2:5;
259 u32 ofs3:5;
260 u32 wid0:3;
261 u32 wid1:3;
262 u32 wid2:3;
263
264 u32 wid3:3;
265 u32 dec_sel:1;
266 u32 res6:28;
267 } __attribute__ ((packed));
268
269 union chan_param_mem {
270 struct chan_param_mem_planar pp;
271 struct chan_param_mem_interleaved ip;
272 };
273
274 static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
275 u32 u_offset, u32 v_offset)
276 {
277 params->pp.ubo_l = u_offset & 0x7ff;
278 params->pp.ubo_h = u_offset >> 11;
279 params->pp.vbo_l = v_offset & 0x1ffff;
280 params->pp.vbo_h = v_offset >> 17;
281 }
282
283 static void ipu_ch_param_set_size(union chan_param_mem *params,
284 uint32_t pixel_fmt, uint16_t width,
285 uint16_t height, uint16_t stride)
286 {
287 u32 u_offset;
288 u32 v_offset;
289
290 params->pp.fw = width - 1;
291 params->pp.fh_l = height - 1;
292 params->pp.fh_h = (height - 1) >> 8;
293 params->pp.sl = stride - 1;
294
295 switch (pixel_fmt) {
296 case IPU_PIX_FMT_GENERIC:
297 /*Represents 8-bit Generic data */
298 params->pp.bpp = 3;
299 params->pp.pfs = 7;
300 params->pp.npb = 31;
301 params->pp.sat = 2; /* SAT = use 32-bit access */
302 break;
303 case IPU_PIX_FMT_GENERIC_32:
304 /*Represents 32-bit Generic data */
305 params->pp.bpp = 0;
306 params->pp.pfs = 7;
307 params->pp.npb = 7;
308 params->pp.sat = 2; /* SAT = use 32-bit access */
309 break;
310 case IPU_PIX_FMT_RGB565:
311 params->ip.bpp = 2;
312 params->ip.pfs = 4;
313 params->ip.npb = 7;
314 params->ip.sat = 2; /* SAT = 32-bit access */
315 params->ip.ofs0 = 0; /* Red bit offset */
316 params->ip.ofs1 = 5; /* Green bit offset */
317 params->ip.ofs2 = 11; /* Blue bit offset */
318 params->ip.ofs3 = 16; /* Alpha bit offset */
319 params->ip.wid0 = 4; /* Red bit width - 1 */
320 params->ip.wid1 = 5; /* Green bit width - 1 */
321 params->ip.wid2 = 4; /* Blue bit width - 1 */
322 break;
323 case IPU_PIX_FMT_BGR24:
324 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
325 params->ip.pfs = 4;
326 params->ip.npb = 7;
327 params->ip.sat = 2; /* SAT = 32-bit access */
328 params->ip.ofs0 = 0; /* Red bit offset */
329 params->ip.ofs1 = 8; /* Green bit offset */
330 params->ip.ofs2 = 16; /* Blue bit offset */
331 params->ip.ofs3 = 24; /* Alpha bit offset */
332 params->ip.wid0 = 7; /* Red bit width - 1 */
333 params->ip.wid1 = 7; /* Green bit width - 1 */
334 params->ip.wid2 = 7; /* Blue bit width - 1 */
335 break;
336 case IPU_PIX_FMT_RGB24:
337 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
338 params->ip.pfs = 4;
339 params->ip.npb = 7;
340 params->ip.sat = 2; /* SAT = 32-bit access */
341 params->ip.ofs0 = 16; /* Red bit offset */
342 params->ip.ofs1 = 8; /* Green bit offset */
343 params->ip.ofs2 = 0; /* Blue bit offset */
344 params->ip.ofs3 = 24; /* Alpha bit offset */
345 params->ip.wid0 = 7; /* Red bit width - 1 */
346 params->ip.wid1 = 7; /* Green bit width - 1 */
347 params->ip.wid2 = 7; /* Blue bit width - 1 */
348 break;
349 case IPU_PIX_FMT_BGRA32:
350 case IPU_PIX_FMT_BGR32:
351 params->ip.bpp = 0;
352 params->ip.pfs = 4;
353 params->ip.npb = 7;
354 params->ip.sat = 2; /* SAT = 32-bit access */
355 params->ip.ofs0 = 8; /* Red bit offset */
356 params->ip.ofs1 = 16; /* Green bit offset */
357 params->ip.ofs2 = 24; /* Blue bit offset */
358 params->ip.ofs3 = 0; /* Alpha bit offset */
359 params->ip.wid0 = 7; /* Red bit width - 1 */
360 params->ip.wid1 = 7; /* Green bit width - 1 */
361 params->ip.wid2 = 7; /* Blue bit width - 1 */
362 params->ip.wid3 = 7; /* Alpha bit width - 1 */
363 break;
364 case IPU_PIX_FMT_RGBA32:
365 case IPU_PIX_FMT_RGB32:
366 params->ip.bpp = 0;
367 params->ip.pfs = 4;
368 params->ip.npb = 7;
369 params->ip.sat = 2; /* SAT = 32-bit access */
370 params->ip.ofs0 = 24; /* Red bit offset */
371 params->ip.ofs1 = 16; /* Green bit offset */
372 params->ip.ofs2 = 8; /* Blue bit offset */
373 params->ip.ofs3 = 0; /* Alpha bit offset */
374 params->ip.wid0 = 7; /* Red bit width - 1 */
375 params->ip.wid1 = 7; /* Green bit width - 1 */
376 params->ip.wid2 = 7; /* Blue bit width - 1 */
377 params->ip.wid3 = 7; /* Alpha bit width - 1 */
378 break;
379 case IPU_PIX_FMT_ABGR32:
380 params->ip.bpp = 0;
381 params->ip.pfs = 4;
382 params->ip.npb = 7;
383 params->ip.sat = 2; /* SAT = 32-bit access */
384 params->ip.ofs0 = 8; /* Red bit offset */
385 params->ip.ofs1 = 16; /* Green bit offset */
386 params->ip.ofs2 = 24; /* Blue bit offset */
387 params->ip.ofs3 = 0; /* Alpha bit offset */
388 params->ip.wid0 = 7; /* Red bit width - 1 */
389 params->ip.wid1 = 7; /* Green bit width - 1 */
390 params->ip.wid2 = 7; /* Blue bit width - 1 */
391 params->ip.wid3 = 7; /* Alpha bit width - 1 */
392 break;
393 case IPU_PIX_FMT_UYVY:
394 params->ip.bpp = 2;
395 params->ip.pfs = 6;
396 params->ip.npb = 7;
397 params->ip.sat = 2; /* SAT = 32-bit access */
398 break;
399 case IPU_PIX_FMT_YUV420P2:
400 case IPU_PIX_FMT_YUV420P:
401 params->ip.bpp = 3;
402 params->ip.pfs = 3;
403 params->ip.npb = 7;
404 params->ip.sat = 2; /* SAT = 32-bit access */
405 u_offset = stride * height;
406 v_offset = u_offset + u_offset / 4;
407 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
408 break;
409 case IPU_PIX_FMT_YVU422P:
410 params->ip.bpp = 3;
411 params->ip.pfs = 2;
412 params->ip.npb = 7;
413 params->ip.sat = 2; /* SAT = 32-bit access */
414 v_offset = stride * height;
415 u_offset = v_offset + v_offset / 2;
416 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
417 break;
418 case IPU_PIX_FMT_YUV422P:
419 params->ip.bpp = 3;
420 params->ip.pfs = 2;
421 params->ip.npb = 7;
422 params->ip.sat = 2; /* SAT = 32-bit access */
423 u_offset = stride * height;
424 v_offset = u_offset + u_offset / 2;
425 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
426 break;
427 default:
428 dev_err(ipu_data.dev,
429 "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
430 break;
431 }
432
433 params->pp.nsb = 1;
434 }
435
436 static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
437 uint16_t burst_pixels)
438 {
439 params->pp.npb = burst_pixels - 1;
440 }
441
442 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
443 dma_addr_t buf0, dma_addr_t buf1)
444 {
445 params->pp.eba0 = buf0;
446 params->pp.eba1 = buf1;
447 }
448
449 static void ipu_ch_param_set_rotation(union chan_param_mem *params,
450 enum ipu_rotate_mode rotate)
451 {
452 params->pp.bam = rotate;
453 }
454
455 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
456 uint32_t num_words)
457 {
458 for (; num_words > 0; num_words--) {
459 dev_dbg(ipu_data.dev,
460 "write param mem - addr = 0x%08X, data = 0x%08X\n",
461 addr, *data);
462 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
463 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
464 addr++;
465 if ((addr & 0x7) == 5) {
466 addr &= ~0x7; /* set to word 0 */
467 addr += 8; /* increment to next row */
468 }
469 }
470 }
471
472 static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
473 uint32_t *resize_coeff,
474 uint32_t *downsize_coeff)
475 {
476 uint32_t temp_size;
477 uint32_t temp_downsize;
478
479 *resize_coeff = 1 << 13;
480 *downsize_coeff = 1 << 13;
481
482 /* Cannot downsize more than 8:1 */
483 if (out_size << 3 < in_size)
484 return -EINVAL;
485
486 /* compute downsizing coefficient */
487 temp_downsize = 0;
488 temp_size = in_size;
489 while (temp_size >= out_size * 2 && temp_downsize < 2) {
490 temp_size >>= 1;
491 temp_downsize++;
492 }
493 *downsize_coeff = temp_downsize;
494
495 /*
496 * compute resizing coefficient using the following formula:
497 * resize_coeff = M*(SI -1)/(SO - 1)
498 * where M = 2^13, SI - input size, SO - output size
499 */
500 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
501 if (*resize_coeff >= 16384L) {
502 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
503 *resize_coeff = 0x3FFF;
504 }
505
506 dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
507 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
508 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
509 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
510
511 return 0;
512 }
513
514 static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
515 {
516 switch (fmt) {
517 case IPU_PIX_FMT_RGB565:
518 case IPU_PIX_FMT_BGR24:
519 case IPU_PIX_FMT_RGB24:
520 case IPU_PIX_FMT_BGR32:
521 case IPU_PIX_FMT_RGB32:
522 return IPU_COLORSPACE_RGB;
523 default:
524 return IPU_COLORSPACE_YCBCR;
525 }
526 }
527
528 static int ipu_ic_init_prpenc(struct ipu *ipu,
529 union ipu_channel_param *params, bool src_is_csi)
530 {
531 uint32_t reg, ic_conf;
532 uint32_t downsize_coeff, resize_coeff;
533 enum ipu_color_space in_fmt, out_fmt;
534
535 /* Setup vertical resizing */
536 calc_resize_coeffs(params->video.in_height,
537 params->video.out_height,
538 &resize_coeff, &downsize_coeff);
539 reg = (downsize_coeff << 30) | (resize_coeff << 16);
540
541 /* Setup horizontal resizing */
542 calc_resize_coeffs(params->video.in_width,
543 params->video.out_width,
544 &resize_coeff, &downsize_coeff);
545 reg |= (downsize_coeff << 14) | resize_coeff;
546
547 /* Setup color space conversion */
548 in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
549 out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
550
551 /*
552 * Colourspace conversion unsupported yet - see _init_csc() in
553 * Freescale sources
554 */
555 if (in_fmt != out_fmt) {
556 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
557 return -EOPNOTSUPP;
558 }
559
560 idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
561
562 ic_conf = idmac_read_icreg(ipu, IC_CONF);
563
564 if (src_is_csi)
565 ic_conf &= ~IC_CONF_RWS_EN;
566 else
567 ic_conf |= IC_CONF_RWS_EN;
568
569 idmac_write_icreg(ipu, ic_conf, IC_CONF);
570
571 return 0;
572 }
573
574 static uint32_t dma_param_addr(uint32_t dma_ch)
575 {
576 /* Channel Parameter Memory */
577 return 0x10000 | (dma_ch << 4);
578 }
579
580 static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
581 bool prio)
582 {
583 u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
584
585 if (prio)
586 reg |= 1UL << channel;
587 else
588 reg &= ~(1UL << channel);
589
590 idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
591
592 dump_idmac_reg(ipu);
593 }
594
595 static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
596 {
597 uint32_t mask;
598
599 switch (channel) {
600 case IDMAC_IC_0:
601 case IDMAC_IC_7:
602 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
603 break;
604 case IDMAC_SDC_0:
605 case IDMAC_SDC_1:
606 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
607 break;
608 default:
609 mask = 0;
610 break;
611 }
612
613 return mask;
614 }
615
616 /**
617 * ipu_enable_channel() - enable an IPU channel.
618 * @idmac: IPU DMAC context.
619 * @ichan: IDMAC channel.
620 * @return: 0 on success or negative error code on failure.
621 */
622 static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
623 {
624 struct ipu *ipu = to_ipu(idmac);
625 enum ipu_channel channel = ichan->dma_chan.chan_id;
626 uint32_t reg;
627 unsigned long flags;
628
629 spin_lock_irqsave(&ipu->lock, flags);
630
631 /* Reset to buffer 0 */
632 idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
633 ichan->active_buffer = 0;
634 ichan->status = IPU_CHANNEL_ENABLED;
635
636 switch (channel) {
637 case IDMAC_SDC_0:
638 case IDMAC_SDC_1:
639 case IDMAC_IC_7:
640 ipu_channel_set_priority(ipu, channel, true);
641 default:
642 break;
643 }
644
645 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
646
647 idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
648
649 ipu_ic_enable_task(ipu, channel);
650
651 spin_unlock_irqrestore(&ipu->lock, flags);
652 return 0;
653 }
654
655 /**
656 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
657 * @ichan: IDMAC channel.
658 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
659 * @width: width of buffer in pixels.
660 * @height: height of buffer in pixels.
661 * @stride: stride length of buffer in pixels.
662 * @rot_mode: rotation mode of buffer. A rotation setting other than
663 * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
664 * rotation channels.
665 * @phyaddr_0: buffer 0 physical address.
666 * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
667 * NULL enables double buffering mode.
668 * @return: 0 on success or negative error code on failure.
669 */
670 static int ipu_init_channel_buffer(struct idmac_channel *ichan,
671 enum pixel_fmt pixel_fmt,
672 uint16_t width, uint16_t height,
673 uint32_t stride,
674 enum ipu_rotate_mode rot_mode,
675 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
676 {
677 enum ipu_channel channel = ichan->dma_chan.chan_id;
678 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
679 struct ipu *ipu = to_ipu(idmac);
680 union chan_param_mem params = {};
681 unsigned long flags;
682 uint32_t reg;
683 uint32_t stride_bytes;
684
685 stride_bytes = stride * bytes_per_pixel(pixel_fmt);
686
687 if (stride_bytes % 4) {
688 dev_err(ipu->dev,
689 "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
690 stride, stride_bytes);
691 return -EINVAL;
692 }
693
694 /* IC channel's stride must be a multiple of 8 pixels */
695 if ((channel <= IDMAC_IC_13) && (stride % 8)) {
696 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
697 return -EINVAL;
698 }
699
700 /* Build parameter memory data for DMA channel */
701 ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
702 ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
703 ipu_ch_param_set_rotation(&params, rot_mode);
704 /* Some channels (rotation) have restriction on burst length */
705 switch (channel) {
706 case IDMAC_IC_7: /* Hangs with burst 8, 16, other values
707 invalid - Table 44-30 */
708 /*
709 ipu_ch_param_set_burst_size(&params, 8);
710 */
711 break;
712 case IDMAC_SDC_0:
713 case IDMAC_SDC_1:
714 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
715 ipu_ch_param_set_burst_size(&params, 16);
716 break;
717 case IDMAC_IC_0:
718 default:
719 break;
720 }
721
722 spin_lock_irqsave(&ipu->lock, flags);
723
724 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
725
726 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
727
728 if (phyaddr_1)
729 reg |= 1UL << channel;
730 else
731 reg &= ~(1UL << channel);
732
733 idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
734
735 ichan->status = IPU_CHANNEL_READY;
736
737 spin_unlock_irqrestore(&ipu->lock, flags);
738
739 return 0;
740 }
741
742 /**
743 * ipu_select_buffer() - mark a channel's buffer as ready.
744 * @channel: channel ID.
745 * @buffer_n: buffer number to mark ready.
746 */
747 static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
748 {
749 /* No locking - this is a write-one-to-set register, cleared by IPU */
750 if (buffer_n == 0)
751 /* Mark buffer 0 as ready. */
752 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
753 else
754 /* Mark buffer 1 as ready. */
755 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
756 }
757
758 /**
759 * ipu_update_channel_buffer() - update physical address of a channel buffer.
760 * @ichan: IDMAC channel.
761 * @buffer_n: buffer number to update.
762 * 0 or 1 are the only valid values.
763 * @phyaddr: buffer physical address.
764 * @return: Returns 0 on success or negative error code on failure. This
765 * function will fail if the buffer is set to ready.
766 */
767 /* Called under spin_lock(_irqsave)(&ichan->lock) */
768 static int ipu_update_channel_buffer(struct idmac_channel *ichan,
769 int buffer_n, dma_addr_t phyaddr)
770 {
771 enum ipu_channel channel = ichan->dma_chan.chan_id;
772 uint32_t reg;
773 unsigned long flags;
774
775 spin_lock_irqsave(&ipu_data.lock, flags);
776
777 if (buffer_n == 0) {
778 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
779 if (reg & (1UL << channel)) {
780 ipu_ic_disable_task(&ipu_data, channel);
781 ichan->status = IPU_CHANNEL_READY;
782 }
783
784 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
785 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
786 0x0008UL, IPU_IMA_ADDR);
787 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
788 } else {
789 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
790 if (reg & (1UL << channel)) {
791 ipu_ic_disable_task(&ipu_data, channel);
792 ichan->status = IPU_CHANNEL_READY;
793 }
794
795 /* Check if double-buffering is already enabled */
796 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
797
798 if (!(reg & (1UL << channel)))
799 idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
800 IPU_CHA_DB_MODE_SEL);
801
802 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
803 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
804 0x0009UL, IPU_IMA_ADDR);
805 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
806 }
807
808 spin_unlock_irqrestore(&ipu_data.lock, flags);
809
810 return 0;
811 }
812
813 /* Called under spin_lock_irqsave(&ichan->lock) */
814 static int ipu_submit_buffer(struct idmac_channel *ichan,
815 struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
816 {
817 unsigned int chan_id = ichan->dma_chan.chan_id;
818 struct device *dev = &ichan->dma_chan.dev->device;
819 int ret;
820
821 if (async_tx_test_ack(&desc->txd))
822 return -EINTR;
823
824 /*
825 * On first invocation this shouldn't be necessary, the call to
826 * ipu_init_channel_buffer() above will set addresses for us, so we
827 * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
828 * doing it again shouldn't hurt either.
829 */
830 ret = ipu_update_channel_buffer(ichan, buf_idx,
831 sg_dma_address(sg));
832
833 if (ret < 0) {
834 dev_err(dev, "Updating sg %p on channel 0x%x buffer %d failed!\n",
835 sg, chan_id, buf_idx);
836 return ret;
837 }
838
839 ipu_select_buffer(chan_id, buf_idx);
840 dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
841 sg, chan_id, buf_idx);
842
843 return 0;
844 }
845
846 /* Called under spin_lock_irqsave(&ichan->lock) */
847 static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
848 struct idmac_tx_desc *desc)
849 {
850 struct scatterlist *sg;
851 int i, ret = 0;
852
853 for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
854 if (!ichan->sg[i]) {
855 ichan->sg[i] = sg;
856
857 ret = ipu_submit_buffer(ichan, desc, sg, i);
858 if (ret < 0)
859 return ret;
860
861 sg = sg_next(sg);
862 }
863 }
864
865 return ret;
866 }
867
868 static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
869 {
870 struct idmac_tx_desc *desc = to_tx_desc(tx);
871 struct idmac_channel *ichan = to_idmac_chan(tx->chan);
872 struct idmac *idmac = to_idmac(tx->chan->device);
873 struct ipu *ipu = to_ipu(idmac);
874 struct device *dev = &ichan->dma_chan.dev->device;
875 dma_cookie_t cookie;
876 unsigned long flags;
877 int ret;
878
879 /* Sanity check */
880 if (!list_empty(&desc->list)) {
881 /* The descriptor doesn't belong to client */
882 dev_err(dev, "Descriptor %p not prepared!\n", tx);
883 return -EBUSY;
884 }
885
886 mutex_lock(&ichan->chan_mutex);
887
888 async_tx_clear_ack(tx);
889
890 if (ichan->status < IPU_CHANNEL_READY) {
891 struct idmac_video_param *video = &ichan->params.video;
892 /*
893 * Initial buffer assignment - the first two sg-entries from
894 * the descriptor will end up in the IDMAC buffers
895 */
896 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
897 sg_dma_address(&desc->sg[1]);
898
899 WARN_ON(ichan->sg[0] || ichan->sg[1]);
900
901 cookie = ipu_init_channel_buffer(ichan,
902 video->out_pixel_fmt,
903 video->out_width,
904 video->out_height,
905 video->out_stride,
906 IPU_ROTATE_NONE,
907 sg_dma_address(&desc->sg[0]),
908 dma_1);
909 if (cookie < 0)
910 goto out;
911 }
912
913 dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
914
915 cookie = ichan->dma_chan.cookie;
916
917 if (++cookie < 0)
918 cookie = 1;
919
920 /* from dmaengine.h: "last cookie value returned to client" */
921 ichan->dma_chan.cookie = cookie;
922 tx->cookie = cookie;
923
924 /* ipu->lock can be taken under ichan->lock, but not v.v. */
925 spin_lock_irqsave(&ichan->lock, flags);
926
927 list_add_tail(&desc->list, &ichan->queue);
928 /* submit_buffers() atomically verifies and fills empty sg slots */
929 ret = ipu_submit_channel_buffers(ichan, desc);
930
931 spin_unlock_irqrestore(&ichan->lock, flags);
932
933 if (ret < 0) {
934 cookie = ret;
935 goto dequeue;
936 }
937
938 if (ichan->status < IPU_CHANNEL_ENABLED) {
939 ret = ipu_enable_channel(idmac, ichan);
940 if (ret < 0) {
941 cookie = ret;
942 goto dequeue;
943 }
944 }
945
946 dump_idmac_reg(ipu);
947
948 dequeue:
949 if (cookie < 0) {
950 spin_lock_irqsave(&ichan->lock, flags);
951 list_del_init(&desc->list);
952 spin_unlock_irqrestore(&ichan->lock, flags);
953 tx->cookie = cookie;
954 ichan->dma_chan.cookie = cookie;
955 }
956
957 out:
958 mutex_unlock(&ichan->chan_mutex);
959
960 return cookie;
961 }
962
963 /* Called with ichan->chan_mutex held */
964 static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
965 {
966 struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
967 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
968
969 if (!desc)
970 return -ENOMEM;
971
972 /* No interrupts, just disable the tasklet for a moment */
973 tasklet_disable(&to_ipu(idmac)->tasklet);
974
975 ichan->n_tx_desc = n;
976 ichan->desc = desc;
977 INIT_LIST_HEAD(&ichan->queue);
978 INIT_LIST_HEAD(&ichan->free_list);
979
980 while (n--) {
981 struct dma_async_tx_descriptor *txd = &desc->txd;
982
983 memset(txd, 0, sizeof(*txd));
984 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
985 txd->tx_submit = idmac_tx_submit;
986
987 list_add(&desc->list, &ichan->free_list);
988
989 desc++;
990 }
991
992 tasklet_enable(&to_ipu(idmac)->tasklet);
993
994 return 0;
995 }
996
997 /**
998 * ipu_init_channel() - initialize an IPU channel.
999 * @idmac: IPU DMAC context.
1000 * @ichan: pointer to the channel object.
1001 * @return 0 on success or negative error code on failure.
1002 */
1003 static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
1004 {
1005 union ipu_channel_param *params = &ichan->params;
1006 uint32_t ipu_conf;
1007 enum ipu_channel channel = ichan->dma_chan.chan_id;
1008 unsigned long flags;
1009 uint32_t reg;
1010 struct ipu *ipu = to_ipu(idmac);
1011 int ret = 0, n_desc = 0;
1012
1013 dev_dbg(ipu->dev, "init channel = %d\n", channel);
1014
1015 if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
1016 channel != IDMAC_IC_7)
1017 return -EINVAL;
1018
1019 spin_lock_irqsave(&ipu->lock, flags);
1020
1021 switch (channel) {
1022 case IDMAC_IC_7:
1023 n_desc = 16;
1024 reg = idmac_read_icreg(ipu, IC_CONF);
1025 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
1026 break;
1027 case IDMAC_IC_0:
1028 n_desc = 16;
1029 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
1030 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
1031 ret = ipu_ic_init_prpenc(ipu, params, true);
1032 break;
1033 case IDMAC_SDC_0:
1034 case IDMAC_SDC_1:
1035 n_desc = 4;
1036 default:
1037 break;
1038 }
1039
1040 ipu->channel_init_mask |= 1L << channel;
1041
1042 /* Enable IPU sub module */
1043 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
1044 ipu_channel_conf_mask(channel);
1045 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1046
1047 spin_unlock_irqrestore(&ipu->lock, flags);
1048
1049 if (n_desc && !ichan->desc)
1050 ret = idmac_desc_alloc(ichan, n_desc);
1051
1052 dump_idmac_reg(ipu);
1053
1054 return ret;
1055 }
1056
1057 /**
1058 * ipu_uninit_channel() - uninitialize an IPU channel.
1059 * @idmac: IPU DMAC context.
1060 * @ichan: pointer to the channel object.
1061 */
1062 static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1063 {
1064 enum ipu_channel channel = ichan->dma_chan.chan_id;
1065 unsigned long flags;
1066 uint32_t reg;
1067 unsigned long chan_mask = 1UL << channel;
1068 uint32_t ipu_conf;
1069 struct ipu *ipu = to_ipu(idmac);
1070
1071 spin_lock_irqsave(&ipu->lock, flags);
1072
1073 if (!(ipu->channel_init_mask & chan_mask)) {
1074 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1075 channel);
1076 spin_unlock_irqrestore(&ipu->lock, flags);
1077 return;
1078 }
1079
1080 /* Reset the double buffer */
1081 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1082 idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1083
1084 ichan->sec_chan_en = false;
1085
1086 switch (channel) {
1087 case IDMAC_IC_7:
1088 reg = idmac_read_icreg(ipu, IC_CONF);
1089 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1090 IC_CONF);
1091 break;
1092 case IDMAC_IC_0:
1093 reg = idmac_read_icreg(ipu, IC_CONF);
1094 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1095 IC_CONF);
1096 break;
1097 case IDMAC_SDC_0:
1098 case IDMAC_SDC_1:
1099 default:
1100 break;
1101 }
1102
1103 ipu->channel_init_mask &= ~(1L << channel);
1104
1105 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1106 ~ipu_channel_conf_mask(channel);
1107 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1108
1109 spin_unlock_irqrestore(&ipu->lock, flags);
1110
1111 ichan->n_tx_desc = 0;
1112 vfree(ichan->desc);
1113 ichan->desc = NULL;
1114 }
1115
1116 /**
1117 * ipu_disable_channel() - disable an IPU channel.
1118 * @idmac: IPU DMAC context.
1119 * @ichan: channel object pointer.
1120 * @wait_for_stop: flag to set whether to wait for channel end of frame or
1121 * return immediately.
1122 * @return: 0 on success or negative error code on failure.
1123 */
1124 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1125 bool wait_for_stop)
1126 {
1127 enum ipu_channel channel = ichan->dma_chan.chan_id;
1128 struct ipu *ipu = to_ipu(idmac);
1129 uint32_t reg;
1130 unsigned long flags;
1131 unsigned long chan_mask = 1UL << channel;
1132 unsigned int timeout;
1133
1134 if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1135 timeout = 40;
1136 /* This waiting always fails. Related to spurious irq problem */
1137 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1138 (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1139 timeout--;
1140 msleep(10);
1141
1142 if (!timeout) {
1143 dev_dbg(ipu->dev,
1144 "Warning: timeout waiting for channel %u to "
1145 "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1146 "busy = 0x%08X, tstat = 0x%08X\n", channel,
1147 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1148 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1149 idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1150 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1151 break;
1152 }
1153 }
1154 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1155 }
1156 /* SDC BG and FG must be disabled before DMA is disabled */
1157 if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1158 channel == IDMAC_SDC_1)) {
1159 for (timeout = 5;
1160 timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1161 msleep(5);
1162 }
1163
1164 spin_lock_irqsave(&ipu->lock, flags);
1165
1166 /* Disable IC task */
1167 ipu_ic_disable_task(ipu, channel);
1168
1169 /* Disable DMA channel(s) */
1170 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1171 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1172
1173 /*
1174 * Problem (observed with channel DMAIC_7): after enabling the channel
1175 * and initialising buffers, there comes an interrupt with current still
1176 * pointing at buffer 0, whereas it should use buffer 0 first and only
1177 * generate an interrupt when it is done, then current should already
1178 * point to buffer 1. This spurious interrupt also comes on channel
1179 * DMASDC_0. With DMAIC_7 normally, is we just leave the ISR after the
1180 * first interrupt, there comes the second with current correctly
1181 * pointing to buffer 1 this time. But sometimes this second interrupt
1182 * doesn't come and the channel hangs. Clearing BUFx_RDY when disabling
1183 * the channel seems to prevent the channel from hanging, but it doesn't
1184 * prevent the spurious interrupt. This might also be unsafe. Think
1185 * about the IDMAC controller trying to switch to a buffer, when we
1186 * clear the ready bit, and re-enable it a moment later.
1187 */
1188 reg = idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY);
1189 idmac_write_ipureg(ipu, 0, IPU_CHA_BUF0_RDY);
1190 idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF0_RDY);
1191
1192 reg = idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY);
1193 idmac_write_ipureg(ipu, 0, IPU_CHA_BUF1_RDY);
1194 idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF1_RDY);
1195
1196 spin_unlock_irqrestore(&ipu->lock, flags);
1197
1198 return 0;
1199 }
1200
1201 static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1202 struct idmac_tx_desc **desc, struct scatterlist *sg)
1203 {
1204 struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1205
1206 if (sgnew)
1207 /* next sg-element in this list */
1208 return sgnew;
1209
1210 if ((*desc)->list.next == &ichan->queue)
1211 /* No more descriptors on the queue */
1212 return NULL;
1213
1214 /* Fetch next descriptor */
1215 *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1216 return (*desc)->sg;
1217 }
1218
1219 /*
1220 * We have several possibilities here:
1221 * current BUF next BUF
1222 *
1223 * not last sg next not last sg
1224 * not last sg next last sg
1225 * last sg first sg from next descriptor
1226 * last sg NULL
1227 *
1228 * Besides, the descriptor queue might be empty or not. We process all these
1229 * cases carefully.
1230 */
1231 static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1232 {
1233 struct idmac_channel *ichan = dev_id;
1234 struct device *dev = &ichan->dma_chan.dev->device;
1235 unsigned int chan_id = ichan->dma_chan.chan_id;
1236 struct scatterlist **sg, *sgnext, *sgnew = NULL;
1237 /* Next transfer descriptor */
1238 struct idmac_tx_desc *desc, *descnew;
1239 dma_async_tx_callback callback;
1240 void *callback_param;
1241 bool done = false;
1242 u32 ready0, ready1, curbuf, err;
1243 unsigned long flags;
1244
1245 /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1246
1247 dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1248
1249 spin_lock_irqsave(&ipu_data.lock, flags);
1250
1251 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1252 ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1253 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1254 err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1255
1256 if (err & (1 << chan_id)) {
1257 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1258 spin_unlock_irqrestore(&ipu_data.lock, flags);
1259 /*
1260 * Doing this
1261 * ichan->sg[0] = ichan->sg[1] = NULL;
1262 * you can force channel re-enable on the next tx_submit(), but
1263 * this is dirty - think about descriptors with multiple
1264 * sg elements.
1265 */
1266 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1267 chan_id, ready0, ready1, curbuf);
1268 return IRQ_HANDLED;
1269 }
1270 spin_unlock_irqrestore(&ipu_data.lock, flags);
1271
1272 /* Other interrupts do not interfere with this channel */
1273 spin_lock(&ichan->lock);
1274 if (unlikely(chan_id != IDMAC_SDC_0 && chan_id != IDMAC_SDC_1 &&
1275 ((curbuf >> chan_id) & 1) == ichan->active_buffer &&
1276 !list_is_last(ichan->queue.next, &ichan->queue))) {
1277 int i = 100;
1278
1279 /* This doesn't help. See comment in ipu_disable_channel() */
1280 while (--i) {
1281 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1282 if (((curbuf >> chan_id) & 1) != ichan->active_buffer)
1283 break;
1284 cpu_relax();
1285 }
1286
1287 if (!i) {
1288 spin_unlock(&ichan->lock);
1289 dev_dbg(dev,
1290 "IRQ on active buffer on channel %x, active "
1291 "%d, ready %x, %x, current %x!\n", chan_id,
1292 ichan->active_buffer, ready0, ready1, curbuf);
1293 return IRQ_NONE;
1294 } else
1295 dev_dbg(dev,
1296 "Buffer deactivated on channel %x, active "
1297 "%d, ready %x, %x, current %x, rest %d!\n", chan_id,
1298 ichan->active_buffer, ready0, ready1, curbuf, i);
1299 }
1300
1301 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1302 (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1303 )) {
1304 spin_unlock(&ichan->lock);
1305 dev_dbg(dev,
1306 "IRQ with active buffer still ready on channel %x, "
1307 "active %d, ready %x, %x!\n", chan_id,
1308 ichan->active_buffer, ready0, ready1);
1309 return IRQ_NONE;
1310 }
1311
1312 if (unlikely(list_empty(&ichan->queue))) {
1313 ichan->sg[ichan->active_buffer] = NULL;
1314 spin_unlock(&ichan->lock);
1315 dev_err(dev,
1316 "IRQ without queued buffers on channel %x, active %d, "
1317 "ready %x, %x!\n", chan_id,
1318 ichan->active_buffer, ready0, ready1);
1319 return IRQ_NONE;
1320 }
1321
1322 /*
1323 * active_buffer is a software flag, it shows which buffer we are
1324 * currently expecting back from the hardware, IDMAC should be
1325 * processing the other buffer already
1326 */
1327 sg = &ichan->sg[ichan->active_buffer];
1328 sgnext = ichan->sg[!ichan->active_buffer];
1329
1330 if (!*sg) {
1331 spin_unlock(&ichan->lock);
1332 return IRQ_HANDLED;
1333 }
1334
1335 desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1336 descnew = desc;
1337
1338 dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
1339 irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
1340
1341 /* Find the descriptor of sgnext */
1342 sgnew = idmac_sg_next(ichan, &descnew, *sg);
1343 if (sgnext != sgnew)
1344 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1345
1346 /*
1347 * if sgnext == NULL sg must be the last element in a scatterlist and
1348 * queue must be empty
1349 */
1350 if (unlikely(!sgnext)) {
1351 if (!WARN_ON(sg_next(*sg)))
1352 dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1353 ichan->sg[!ichan->active_buffer] = sgnew;
1354
1355 if (unlikely(sgnew)) {
1356 ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
1357 } else {
1358 spin_lock_irqsave(&ipu_data.lock, flags);
1359 ipu_ic_disable_task(&ipu_data, chan_id);
1360 spin_unlock_irqrestore(&ipu_data.lock, flags);
1361 ichan->status = IPU_CHANNEL_READY;
1362 /* Continue to check for complete descriptor */
1363 }
1364 }
1365
1366 /* Calculate and submit the next sg element */
1367 sgnew = idmac_sg_next(ichan, &descnew, sgnew);
1368
1369 if (unlikely(!sg_next(*sg)) || !sgnext) {
1370 /*
1371 * Last element in scatterlist done, remove from the queue,
1372 * _init for debugging
1373 */
1374 list_del_init(&desc->list);
1375 done = true;
1376 }
1377
1378 *sg = sgnew;
1379
1380 if (likely(sgnew) &&
1381 ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
1382 callback = desc->txd.callback;
1383 callback_param = desc->txd.callback_param;
1384 spin_unlock(&ichan->lock);
1385 callback(callback_param);
1386 spin_lock(&ichan->lock);
1387 }
1388
1389 /* Flip the active buffer - even if update above failed */
1390 ichan->active_buffer = !ichan->active_buffer;
1391 if (done)
1392 ichan->completed = desc->txd.cookie;
1393
1394 callback = desc->txd.callback;
1395 callback_param = desc->txd.callback_param;
1396
1397 spin_unlock(&ichan->lock);
1398
1399 if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1400 callback(callback_param);
1401
1402 return IRQ_HANDLED;
1403 }
1404
1405 static void ipu_gc_tasklet(unsigned long arg)
1406 {
1407 struct ipu *ipu = (struct ipu *)arg;
1408 int i;
1409
1410 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1411 struct idmac_channel *ichan = ipu->channel + i;
1412 struct idmac_tx_desc *desc;
1413 unsigned long flags;
1414 struct scatterlist *sg;
1415 int j, k;
1416
1417 for (j = 0; j < ichan->n_tx_desc; j++) {
1418 desc = ichan->desc + j;
1419 spin_lock_irqsave(&ichan->lock, flags);
1420 if (async_tx_test_ack(&desc->txd)) {
1421 list_move(&desc->list, &ichan->free_list);
1422 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1423 if (ichan->sg[0] == sg)
1424 ichan->sg[0] = NULL;
1425 else if (ichan->sg[1] == sg)
1426 ichan->sg[1] = NULL;
1427 }
1428 async_tx_clear_ack(&desc->txd);
1429 }
1430 spin_unlock_irqrestore(&ichan->lock, flags);
1431 }
1432 }
1433 }
1434
1435 /* Allocate and initialise a transfer descriptor. */
1436 static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1437 struct scatterlist *sgl, unsigned int sg_len,
1438 enum dma_data_direction direction, unsigned long tx_flags)
1439 {
1440 struct idmac_channel *ichan = to_idmac_chan(chan);
1441 struct idmac_tx_desc *desc = NULL;
1442 struct dma_async_tx_descriptor *txd = NULL;
1443 unsigned long flags;
1444
1445 /* We only can handle these three channels so far */
1446 if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1447 chan->chan_id != IDMAC_IC_7)
1448 return NULL;
1449
1450 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
1451 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1452 return NULL;
1453 }
1454
1455 mutex_lock(&ichan->chan_mutex);
1456
1457 spin_lock_irqsave(&ichan->lock, flags);
1458 if (!list_empty(&ichan->free_list)) {
1459 desc = list_entry(ichan->free_list.next,
1460 struct idmac_tx_desc, list);
1461
1462 list_del_init(&desc->list);
1463
1464 desc->sg_len = sg_len;
1465 desc->sg = sgl;
1466 txd = &desc->txd;
1467 txd->flags = tx_flags;
1468 }
1469 spin_unlock_irqrestore(&ichan->lock, flags);
1470
1471 mutex_unlock(&ichan->chan_mutex);
1472
1473 tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1474
1475 return txd;
1476 }
1477
1478 /* Re-select the current buffer and re-activate the channel */
1479 static void idmac_issue_pending(struct dma_chan *chan)
1480 {
1481 struct idmac_channel *ichan = to_idmac_chan(chan);
1482 struct idmac *idmac = to_idmac(chan->device);
1483 struct ipu *ipu = to_ipu(idmac);
1484 unsigned long flags;
1485
1486 /* This is not always needed, but doesn't hurt either */
1487 spin_lock_irqsave(&ipu->lock, flags);
1488 ipu_select_buffer(chan->chan_id, ichan->active_buffer);
1489 spin_unlock_irqrestore(&ipu->lock, flags);
1490
1491 /*
1492 * Might need to perform some parts of initialisation from
1493 * ipu_enable_channel(), but not all, we do not want to reset to buffer
1494 * 0, don't need to set priority again either, but re-enabling the task
1495 * and the channel might be a good idea.
1496 */
1497 }
1498
1499 static void __idmac_terminate_all(struct dma_chan *chan)
1500 {
1501 struct idmac_channel *ichan = to_idmac_chan(chan);
1502 struct idmac *idmac = to_idmac(chan->device);
1503 unsigned long flags;
1504 int i;
1505
1506 ipu_disable_channel(idmac, ichan,
1507 ichan->status >= IPU_CHANNEL_ENABLED);
1508
1509 tasklet_disable(&to_ipu(idmac)->tasklet);
1510
1511 /* ichan->queue is modified in ISR, have to spinlock */
1512 spin_lock_irqsave(&ichan->lock, flags);
1513 list_splice_init(&ichan->queue, &ichan->free_list);
1514
1515 if (ichan->desc)
1516 for (i = 0; i < ichan->n_tx_desc; i++) {
1517 struct idmac_tx_desc *desc = ichan->desc + i;
1518 if (list_empty(&desc->list))
1519 /* Descriptor was prepared, but not submitted */
1520 list_add(&desc->list, &ichan->free_list);
1521
1522 async_tx_clear_ack(&desc->txd);
1523 }
1524
1525 ichan->sg[0] = NULL;
1526 ichan->sg[1] = NULL;
1527 spin_unlock_irqrestore(&ichan->lock, flags);
1528
1529 tasklet_enable(&to_ipu(idmac)->tasklet);
1530
1531 ichan->status = IPU_CHANNEL_INITIALIZED;
1532 }
1533
1534 static void idmac_terminate_all(struct dma_chan *chan)
1535 {
1536 struct idmac_channel *ichan = to_idmac_chan(chan);
1537
1538 mutex_lock(&ichan->chan_mutex);
1539
1540 __idmac_terminate_all(chan);
1541
1542 mutex_unlock(&ichan->chan_mutex);
1543 }
1544
1545 #ifdef DEBUG
1546 static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1547 {
1548 struct idmac_channel *ichan = dev_id;
1549 printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1550 irq, ichan->dma_chan.chan_id);
1551 disable_irq_nosync(irq);
1552 return IRQ_HANDLED;
1553 }
1554
1555 static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1556 {
1557 struct idmac_channel *ichan = dev_id;
1558 printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1559 irq, ichan->dma_chan.chan_id);
1560 disable_irq_nosync(irq);
1561 return IRQ_HANDLED;
1562 }
1563
1564 static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1565 #endif
1566
1567 static int idmac_alloc_chan_resources(struct dma_chan *chan)
1568 {
1569 struct idmac_channel *ichan = to_idmac_chan(chan);
1570 struct idmac *idmac = to_idmac(chan->device);
1571 int ret;
1572
1573 /* dmaengine.c now guarantees to only offer free channels */
1574 BUG_ON(chan->client_count > 1);
1575 WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1576
1577 chan->cookie = 1;
1578 ichan->completed = -ENXIO;
1579
1580 ret = ipu_irq_map(chan->chan_id);
1581 if (ret < 0)
1582 goto eimap;
1583
1584 ichan->eof_irq = ret;
1585
1586 /*
1587 * Important to first disable the channel, because maybe someone
1588 * used it before us, e.g., the bootloader
1589 */
1590 ipu_disable_channel(idmac, ichan, true);
1591
1592 ret = ipu_init_channel(idmac, ichan);
1593 if (ret < 0)
1594 goto eichan;
1595
1596 ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1597 ichan->eof_name, ichan);
1598 if (ret < 0)
1599 goto erirq;
1600
1601 #ifdef DEBUG
1602 if (chan->chan_id == IDMAC_IC_7) {
1603 ic_sof = ipu_irq_map(69);
1604 if (ic_sof > 0)
1605 request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1606 ic_eof = ipu_irq_map(70);
1607 if (ic_eof > 0)
1608 request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1609 }
1610 #endif
1611
1612 ichan->status = IPU_CHANNEL_INITIALIZED;
1613
1614 dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1615 chan->chan_id, ichan->eof_irq);
1616
1617 return ret;
1618
1619 erirq:
1620 ipu_uninit_channel(idmac, ichan);
1621 eichan:
1622 ipu_irq_unmap(chan->chan_id);
1623 eimap:
1624 return ret;
1625 }
1626
1627 static void idmac_free_chan_resources(struct dma_chan *chan)
1628 {
1629 struct idmac_channel *ichan = to_idmac_chan(chan);
1630 struct idmac *idmac = to_idmac(chan->device);
1631
1632 mutex_lock(&ichan->chan_mutex);
1633
1634 __idmac_terminate_all(chan);
1635
1636 if (ichan->status > IPU_CHANNEL_FREE) {
1637 #ifdef DEBUG
1638 if (chan->chan_id == IDMAC_IC_7) {
1639 if (ic_sof > 0) {
1640 free_irq(ic_sof, ichan);
1641 ipu_irq_unmap(69);
1642 ic_sof = -EINVAL;
1643 }
1644 if (ic_eof > 0) {
1645 free_irq(ic_eof, ichan);
1646 ipu_irq_unmap(70);
1647 ic_eof = -EINVAL;
1648 }
1649 }
1650 #endif
1651 free_irq(ichan->eof_irq, ichan);
1652 ipu_irq_unmap(chan->chan_id);
1653 }
1654
1655 ichan->status = IPU_CHANNEL_FREE;
1656
1657 ipu_uninit_channel(idmac, ichan);
1658
1659 mutex_unlock(&ichan->chan_mutex);
1660
1661 tasklet_schedule(&to_ipu(idmac)->tasklet);
1662 }
1663
1664 static enum dma_status idmac_is_tx_complete(struct dma_chan *chan,
1665 dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used)
1666 {
1667 struct idmac_channel *ichan = to_idmac_chan(chan);
1668
1669 if (done)
1670 *done = ichan->completed;
1671 if (used)
1672 *used = chan->cookie;
1673 if (cookie != chan->cookie)
1674 return DMA_ERROR;
1675 return DMA_SUCCESS;
1676 }
1677
1678 static int __init ipu_idmac_init(struct ipu *ipu)
1679 {
1680 struct idmac *idmac = &ipu->idmac;
1681 struct dma_device *dma = &idmac->dma;
1682 int i;
1683
1684 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1685 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1686
1687 /* Compulsory common fields */
1688 dma->dev = ipu->dev;
1689 dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
1690 dma->device_free_chan_resources = idmac_free_chan_resources;
1691 dma->device_is_tx_complete = idmac_is_tx_complete;
1692 dma->device_issue_pending = idmac_issue_pending;
1693
1694 /* Compulsory for DMA_SLAVE fields */
1695 dma->device_prep_slave_sg = idmac_prep_slave_sg;
1696 dma->device_terminate_all = idmac_terminate_all;
1697
1698 INIT_LIST_HEAD(&dma->channels);
1699 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1700 struct idmac_channel *ichan = ipu->channel + i;
1701 struct dma_chan *dma_chan = &ichan->dma_chan;
1702
1703 spin_lock_init(&ichan->lock);
1704 mutex_init(&ichan->chan_mutex);
1705
1706 ichan->status = IPU_CHANNEL_FREE;
1707 ichan->sec_chan_en = false;
1708 ichan->completed = -ENXIO;
1709 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1710
1711 dma_chan->device = &idmac->dma;
1712 dma_chan->cookie = 1;
1713 dma_chan->chan_id = i;
1714 list_add_tail(&dma_chan->device_node, &dma->channels);
1715 }
1716
1717 idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1718
1719 return dma_async_device_register(&idmac->dma);
1720 }
1721
1722 static void __exit ipu_idmac_exit(struct ipu *ipu)
1723 {
1724 int i;
1725 struct idmac *idmac = &ipu->idmac;
1726
1727 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1728 struct idmac_channel *ichan = ipu->channel + i;
1729
1730 idmac_terminate_all(&ichan->dma_chan);
1731 idmac_prep_slave_sg(&ichan->dma_chan, NULL, 0, DMA_NONE, 0);
1732 }
1733
1734 dma_async_device_unregister(&idmac->dma);
1735 }
1736
1737 /*****************************************************************************
1738 * IPU common probe / remove
1739 */
1740
1741 static int __init ipu_probe(struct platform_device *pdev)
1742 {
1743 struct ipu_platform_data *pdata = pdev->dev.platform_data;
1744 struct resource *mem_ipu, *mem_ic;
1745 int ret;
1746
1747 spin_lock_init(&ipu_data.lock);
1748
1749 mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1750 mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1751 if (!pdata || !mem_ipu || !mem_ic)
1752 return -EINVAL;
1753
1754 ipu_data.dev = &pdev->dev;
1755
1756 platform_set_drvdata(pdev, &ipu_data);
1757
1758 ret = platform_get_irq(pdev, 0);
1759 if (ret < 0)
1760 goto err_noirq;
1761
1762 ipu_data.irq_fn = ret;
1763 ret = platform_get_irq(pdev, 1);
1764 if (ret < 0)
1765 goto err_noirq;
1766
1767 ipu_data.irq_err = ret;
1768 ipu_data.irq_base = pdata->irq_base;
1769
1770 dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1771 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1772
1773 /* Remap IPU common registers */
1774 ipu_data.reg_ipu = ioremap(mem_ipu->start,
1775 mem_ipu->end - mem_ipu->start + 1);
1776 if (!ipu_data.reg_ipu) {
1777 ret = -ENOMEM;
1778 goto err_ioremap_ipu;
1779 }
1780
1781 /* Remap Image Converter and Image DMA Controller registers */
1782 ipu_data.reg_ic = ioremap(mem_ic->start,
1783 mem_ic->end - mem_ic->start + 1);
1784 if (!ipu_data.reg_ic) {
1785 ret = -ENOMEM;
1786 goto err_ioremap_ic;
1787 }
1788
1789 /* Get IPU clock */
1790 ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
1791 if (IS_ERR(ipu_data.ipu_clk)) {
1792 ret = PTR_ERR(ipu_data.ipu_clk);
1793 goto err_clk_get;
1794 }
1795
1796 /* Make sure IPU HSP clock is running */
1797 clk_enable(ipu_data.ipu_clk);
1798
1799 /* Disable all interrupts */
1800 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1801 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1802 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1803 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1804 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1805
1806 dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1807 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1808
1809 ret = ipu_irq_attach_irq(&ipu_data, pdev);
1810 if (ret < 0)
1811 goto err_attach_irq;
1812
1813 /* Initialize DMA engine */
1814 ret = ipu_idmac_init(&ipu_data);
1815 if (ret < 0)
1816 goto err_idmac_init;
1817
1818 tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1819
1820 ipu_data.dev = &pdev->dev;
1821
1822 dev_dbg(ipu_data.dev, "IPU initialized\n");
1823
1824 return 0;
1825
1826 err_idmac_init:
1827 err_attach_irq:
1828 ipu_irq_detach_irq(&ipu_data, pdev);
1829 clk_disable(ipu_data.ipu_clk);
1830 clk_put(ipu_data.ipu_clk);
1831 err_clk_get:
1832 iounmap(ipu_data.reg_ic);
1833 err_ioremap_ic:
1834 iounmap(ipu_data.reg_ipu);
1835 err_ioremap_ipu:
1836 err_noirq:
1837 dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1838 return ret;
1839 }
1840
1841 static int __exit ipu_remove(struct platform_device *pdev)
1842 {
1843 struct ipu *ipu = platform_get_drvdata(pdev);
1844
1845 ipu_idmac_exit(ipu);
1846 ipu_irq_detach_irq(ipu, pdev);
1847 clk_disable(ipu->ipu_clk);
1848 clk_put(ipu->ipu_clk);
1849 iounmap(ipu->reg_ic);
1850 iounmap(ipu->reg_ipu);
1851 tasklet_kill(&ipu->tasklet);
1852 platform_set_drvdata(pdev, NULL);
1853
1854 return 0;
1855 }
1856
1857 /*
1858 * We need two MEM resources - with IPU-common and Image Converter registers,
1859 * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1860 */
1861 static struct platform_driver ipu_platform_driver = {
1862 .driver = {
1863 .name = "ipu-core",
1864 .owner = THIS_MODULE,
1865 },
1866 .remove = __exit_p(ipu_remove),
1867 };
1868
1869 static int __init ipu_init(void)
1870 {
1871 return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1872 }
1873 subsys_initcall(ipu_init);
1874
1875 MODULE_DESCRIPTION("IPU core driver");
1876 MODULE_LICENSE("GPL v2");
1877 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1878 MODULE_ALIAS("platform:ipu-core");
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