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mm-only debug patch...
[mmotm.git] / drivers / gpu / drm / radeon / radeon_legacy_crtc.c
blobd22a195cf152e909be43b1bc312e83af8341ae00
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
30 #include "radeon.h"
31 #include "atom.h"
32
33 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
34 struct drm_display_mode *mode,
35 struct drm_display_mode *adjusted_mode)
36 {
37 struct drm_device *dev = crtc->dev;
38 struct radeon_device *rdev = dev->dev_private;
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 int xres = mode->hdisplay;
41 int yres = mode->vdisplay;
42 bool hscale = true, vscale = true;
43 int hsync_wid;
44 int vsync_wid;
45 int hsync_start;
46 int blank_width;
47 u32 scale, inc, crtc_more_cntl;
48 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
49 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
50 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
51 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
52
53 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
54 (RADEON_VERT_STRETCH_RESERVED |
55 RADEON_VERT_AUTO_RATIO_INC);
56 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
57 (RADEON_HORZ_FP_LOOP_STRETCH |
58 RADEON_HORZ_AUTO_RATIO_INC);
59
60 crtc_more_cntl = 0;
61 if ((rdev->family == CHIP_RS100) ||
62 (rdev->family == CHIP_RS200)) {
63 /* This is to workaround the asic bug for RMX, some versions
64 of BIOS dosen't have this register initialized correctly. */
65 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
66 }
67
68
69 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
70 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
71
72 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
73 if (!hsync_wid)
74 hsync_wid = 1;
75 hsync_start = mode->crtc_hsync_start - 8;
76
77 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
78 | ((hsync_wid & 0x3f) << 16)
79 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
80 ? RADEON_CRTC_H_SYNC_POL
81 : 0));
82
83 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
84 | ((mode->crtc_vdisplay - 1) << 16));
85
86 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
87 if (!vsync_wid)
88 vsync_wid = 1;
89
90 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
91 | ((vsync_wid & 0x1f) << 16)
92 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
93 ? RADEON_CRTC_V_SYNC_POL
94 : 0));
95
96 fp_horz_vert_active = 0;
97
98 if (native_mode->hdisplay == 0 ||
99 native_mode->vdisplay == 0) {
100 hscale = false;
101 vscale = false;
102 } else {
103 if (xres > native_mode->hdisplay)
104 xres = native_mode->hdisplay;
105 if (yres > native_mode->vdisplay)
106 yres = native_mode->vdisplay;
107
108 if (xres == native_mode->hdisplay)
109 hscale = false;
110 if (yres == native_mode->vdisplay)
111 vscale = false;
112 }
113
114 switch (radeon_crtc->rmx_type) {
115 case RMX_FULL:
116 case RMX_ASPECT:
117 if (!hscale)
118 fp_horz_stretch |= ((xres/8-1) << 16);
119 else {
120 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
121 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
122 / native_mode->hdisplay + 1;
123 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
124 RADEON_HORZ_STRETCH_BLEND |
125 RADEON_HORZ_STRETCH_ENABLE |
126 ((native_mode->hdisplay/8-1) << 16));
127 }
128
129 if (!vscale)
130 fp_vert_stretch |= ((yres-1) << 12);
131 else {
132 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
133 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
134 / native_mode->vdisplay + 1;
135 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
136 RADEON_VERT_STRETCH_ENABLE |
137 RADEON_VERT_STRETCH_BLEND |
138 ((native_mode->vdisplay-1) << 12));
139 }
140 break;
141 case RMX_CENTER:
142 fp_horz_stretch |= ((xres/8-1) << 16);
143 fp_vert_stretch |= ((yres-1) << 12);
144
145 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
146 RADEON_CRTC_AUTO_VERT_CENTER_EN);
147
148 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
149 if (blank_width > 110)
150 blank_width = 110;
151
152 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
153 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
154
155 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
156 if (!hsync_wid)
157 hsync_wid = 1;
158
159 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
160 | ((hsync_wid & 0x3f) << 16)
161 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
162 ? RADEON_CRTC_H_SYNC_POL
163 : 0));
164
165 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
166 | ((mode->crtc_vdisplay - 1) << 16));
167
168 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
169 if (!vsync_wid)
170 vsync_wid = 1;
171
172 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
173 | ((vsync_wid & 0x1f) << 16)
174 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
175 ? RADEON_CRTC_V_SYNC_POL
176 : 0)));
177
178 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
179 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
180 break;
181 case RMX_OFF:
182 default:
183 fp_horz_stretch |= ((xres/8-1) << 16);
184 fp_vert_stretch |= ((yres-1) << 12);
185 break;
186 }
187
188 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
189 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
190 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
191 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
192 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
193 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
194 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
195 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
196 }
197
198 void radeon_restore_common_regs(struct drm_device *dev)
199 {
200 /* don't need this yet */
201 }
202
203 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
204 {
205 struct radeon_device *rdev = dev->dev_private;
206 int i = 0;
207
208 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
209 the cause yet, but this workaround will mask the problem for now.
210 Other chips usually will pass at the very first test, so the
211 workaround shouldn't have any effect on them. */
212 for (i = 0;
213 (i < 10000 &&
214 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
215 i++);
216 }
217
218 static void radeon_pll_write_update(struct drm_device *dev)
219 {
220 struct radeon_device *rdev = dev->dev_private;
221
222 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
223
224 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
225 RADEON_PPLL_ATOMIC_UPDATE_W,
226 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
227 }
228
229 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
230 {
231 struct radeon_device *rdev = dev->dev_private;
232 int i = 0;
233
234
235 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
236 the cause yet, but this workaround will mask the problem for now.
237 Other chips usually will pass at the very first test, so the
238 workaround shouldn't have any effect on them. */
239 for (i = 0;
240 (i < 10000 &&
241 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
242 i++);
243 }
244
245 static void radeon_pll2_write_update(struct drm_device *dev)
246 {
247 struct radeon_device *rdev = dev->dev_private;
248
249 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
250
251 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
252 RADEON_P2PLL_ATOMIC_UPDATE_W,
253 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
254 }
255
256 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
257 uint16_t fb_div)
258 {
259 unsigned int vcoFreq;
260
261 if (!ref_div)
262 return 1;
263
264 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
265
266 /*
267 * This is horribly crude: the VCO frequency range is divided into
268 * 3 parts, each part having a fixed PLL gain value.
269 */
270 if (vcoFreq >= 30000)
271 /*
272 * [300..max] MHz : 7
273 */
274 return 7;
275 else if (vcoFreq >= 18000)
276 /*
277 * [180..300) MHz : 4
278 */
279 return 4;
280 else
281 /*
282 * [0..180) MHz : 1
283 */
284 return 1;
285 }
286
287 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
288 {
289 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
290 struct drm_device *dev = crtc->dev;
291 struct radeon_device *rdev = dev->dev_private;
292 uint32_t mask;
293
294 if (radeon_crtc->crtc_id)
295 mask = (RADEON_CRTC2_EN |
296 RADEON_CRTC2_DISP_DIS |
297 RADEON_CRTC2_VSYNC_DIS |
298 RADEON_CRTC2_HSYNC_DIS |
299 RADEON_CRTC2_DISP_REQ_EN_B);
300 else
301 mask = (RADEON_CRTC_DISPLAY_DIS |
302 RADEON_CRTC_VSYNC_DIS |
303 RADEON_CRTC_HSYNC_DIS);
304
305 switch (mode) {
306 case DRM_MODE_DPMS_ON:
307 if (radeon_crtc->crtc_id)
308 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
309 else {
310 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
311 RADEON_CRTC_DISP_REQ_EN_B));
312 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
313 }
314 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
315 radeon_crtc_load_lut(crtc);
316 break;
317 case DRM_MODE_DPMS_STANDBY:
318 case DRM_MODE_DPMS_SUSPEND:
319 case DRM_MODE_DPMS_OFF:
320 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
321 if (radeon_crtc->crtc_id)
322 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
323 else {
324 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
325 RADEON_CRTC_DISP_REQ_EN_B));
326 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
327 }
328 break;
329 }
330 }
331
332 /* properly set crtc bpp when using atombios */
333 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
334 {
335 struct drm_device *dev = crtc->dev;
336 struct radeon_device *rdev = dev->dev_private;
337 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
338 int format;
339 uint32_t crtc_gen_cntl;
340 uint32_t disp_merge_cntl;
341 uint32_t crtc_pitch;
342
343 switch (crtc->fb->bits_per_pixel) {
344 case 8:
345 format = 2;
346 break;
347 case 15: /* 555 */
348 format = 3;
349 break;
350 case 16: /* 565 */
351 format = 4;
352 break;
353 case 24: /* RGB */
354 format = 5;
355 break;
356 case 32: /* xRGB */
357 format = 6;
358 break;
359 default:
360 return;
361 }
362
363 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
364 ((crtc->fb->bits_per_pixel * 8) - 1)) /
365 (crtc->fb->bits_per_pixel * 8));
366 crtc_pitch |= crtc_pitch << 16;
367
368 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
369
370 switch (radeon_crtc->crtc_id) {
371 case 0:
372 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
373 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
374 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
375
376 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
377 crtc_gen_cntl |= (format << 8);
378 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
379 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
380 break;
381 case 1:
382 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
383 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
384 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
385
386 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
387 crtc_gen_cntl |= (format << 8);
388 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
389 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
390 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
391 break;
392 }
393 }
394
395 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
396 struct drm_framebuffer *old_fb)
397 {
398 struct drm_device *dev = crtc->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
401 struct radeon_framebuffer *radeon_fb;
402 struct drm_gem_object *obj;
403 uint64_t base;
404 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
405 uint32_t crtc_pitch, pitch_pixels;
406 uint32_t tiling_flags;
407 int format;
408 uint32_t gen_cntl_reg, gen_cntl_val;
409
410 DRM_DEBUG("\n");
411
412 radeon_fb = to_radeon_framebuffer(crtc->fb);
413
414 switch (crtc->fb->bits_per_pixel) {
415 case 8:
416 format = 2;
417 break;
418 case 15: /* 555 */
419 format = 3;
420 break;
421 case 16: /* 565 */
422 format = 4;
423 break;
424 case 24: /* RGB */
425 format = 5;
426 break;
427 case 32: /* xRGB */
428 format = 6;
429 break;
430 default:
431 return false;
432 }
433
434 obj = radeon_fb->obj;
435 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
436 return -EINVAL;
437 }
438 /* if scanout was in GTT this really wouldn't work */
439 /* crtc offset is from display base addr not FB location */
440 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
441
442 base -= radeon_crtc->legacy_display_base_addr;
443
444 crtc_offset_cntl = 0;
445
446 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
447 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
448 ((crtc->fb->bits_per_pixel * 8) - 1)) /
449 (crtc->fb->bits_per_pixel * 8));
450 crtc_pitch |= crtc_pitch << 16;
451
452 radeon_object_get_tiling_flags(obj->driver_private,
453 &tiling_flags, NULL);
454 if (tiling_flags & RADEON_TILING_MICRO)
455 DRM_ERROR("trying to scanout microtiled buffer\n");
456
457 if (tiling_flags & RADEON_TILING_MACRO) {
458 if (ASIC_IS_R300(rdev))
459 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
460 R300_CRTC_MICRO_TILE_BUFFER_DIS |
461 R300_CRTC_MACRO_TILE_EN);
462 else
463 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
464 } else {
465 if (ASIC_IS_R300(rdev))
466 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
467 R300_CRTC_MICRO_TILE_BUFFER_DIS |
468 R300_CRTC_MACRO_TILE_EN);
469 else
470 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
471 }
472
473 if (tiling_flags & RADEON_TILING_MACRO) {
474 if (ASIC_IS_R300(rdev)) {
475 crtc_tile_x0_y0 = x | (y << 16);
476 base &= ~0x7ff;
477 } else {
478 int byteshift = crtc->fb->bits_per_pixel >> 4;
479 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
480 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
481 crtc_offset_cntl |= (y % 16);
482 }
483 } else {
484 int offset = y * pitch_pixels + x;
485 switch (crtc->fb->bits_per_pixel) {
486 case 8:
487 offset *= 1;
488 break;
489 case 15:
490 case 16:
491 offset *= 2;
492 break;
493 case 24:
494 offset *= 3;
495 break;
496 case 32:
497 offset *= 4;
498 break;
499 default:
500 return false;
501 }
502 base += offset;
503 }
504
505 base &= ~7;
506
507 if (radeon_crtc->crtc_id == 1)
508 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
509 else
510 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
511
512 gen_cntl_val = RREG32(gen_cntl_reg);
513 gen_cntl_val &= ~(0xf << 8);
514 gen_cntl_val |= (format << 8);
515 WREG32(gen_cntl_reg, gen_cntl_val);
516
517 crtc_offset = (u32)base;
518
519 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
520
521 if (ASIC_IS_R300(rdev)) {
522 if (radeon_crtc->crtc_id)
523 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
524 else
525 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
526 }
527 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
528 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
529 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
530
531 if (old_fb && old_fb != crtc->fb) {
532 radeon_fb = to_radeon_framebuffer(old_fb);
533 radeon_gem_object_unpin(radeon_fb->obj);
534 }
535
536 /* Bytes per pixel may have changed */
537 radeon_bandwidth_update(rdev);
538
539 return 0;
540 }
541
542 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct radeon_device *rdev = dev->dev_private;
546 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
547 struct drm_encoder *encoder;
548 int format;
549 int hsync_start;
550 int hsync_wid;
551 int vsync_wid;
552 uint32_t crtc_h_total_disp;
553 uint32_t crtc_h_sync_strt_wid;
554 uint32_t crtc_v_total_disp;
555 uint32_t crtc_v_sync_strt_wid;
556 bool is_tv = false;
557
558 DRM_DEBUG("\n");
559 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
560 if (encoder->crtc == crtc) {
561 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
562 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
563 is_tv = true;
564 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
565 break;
566 }
567 }
568 }
569
570 switch (crtc->fb->bits_per_pixel) {
571 case 8:
572 format = 2;
573 break;
574 case 15: /* 555 */
575 format = 3;
576 break;
577 case 16: /* 565 */
578 format = 4;
579 break;
580 case 24: /* RGB */
581 format = 5;
582 break;
583 case 32: /* xRGB */
584 format = 6;
585 break;
586 default:
587 return false;
588 }
589
590 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
591 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
592
593 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
594 if (!hsync_wid)
595 hsync_wid = 1;
596 hsync_start = mode->crtc_hsync_start - 8;
597
598 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
599 | ((hsync_wid & 0x3f) << 16)
600 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
601 ? RADEON_CRTC_H_SYNC_POL
602 : 0));
603
604 /* This works for double scan mode. */
605 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
606 | ((mode->crtc_vdisplay - 1) << 16));
607
608 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
609 if (!vsync_wid)
610 vsync_wid = 1;
611
612 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
613 | ((vsync_wid & 0x1f) << 16)
614 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
615 ? RADEON_CRTC_V_SYNC_POL
616 : 0));
617
618 /* TODO -> Dell Server */
619 if (0) {
620 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
621 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
622 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
623 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
624
625 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
626 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
627
628 /* For CRT on DAC2, don't turn it on if BIOS didn't
629 enable it, even it's detected.
630 */
631 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
632 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
633 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
634
635 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
636 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
637 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
638 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
639 }
640
641 if (radeon_crtc->crtc_id) {
642 uint32_t crtc2_gen_cntl;
643 uint32_t disp2_merge_cntl;
644
645 /* check to see if TV DAC is enabled for another crtc and keep it enabled */
646 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
647 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
648 else
649 crtc2_gen_cntl = 0;
650
651 crtc2_gen_cntl |= ((format << 8)
652 | RADEON_CRTC2_VSYNC_DIS
653 | RADEON_CRTC2_HSYNC_DIS
654 | RADEON_CRTC2_DISP_DIS
655 | RADEON_CRTC2_DISP_REQ_EN_B
656 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
657 ? RADEON_CRTC2_DBL_SCAN_EN
658 : 0)
659 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
660 ? RADEON_CRTC2_CSYNC_EN
661 : 0)
662 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
663 ? RADEON_CRTC2_INTERLACE_EN
664 : 0));
665
666 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
667 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
668
669 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
670 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
671 } else {
672 uint32_t crtc_gen_cntl;
673 uint32_t crtc_ext_cntl;
674 uint32_t disp_merge_cntl;
675
676 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
677 | (format << 8)
678 | RADEON_CRTC_DISP_REQ_EN_B
679 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
680 ? RADEON_CRTC_DBL_SCAN_EN
681 : 0)
682 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
683 ? RADEON_CRTC_CSYNC_EN
684 : 0)
685 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
686 ? RADEON_CRTC_INTERLACE_EN
687 : 0));
688
689 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
690 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
691 RADEON_CRTC_VSYNC_DIS |
692 RADEON_CRTC_HSYNC_DIS |
693 RADEON_CRTC_DISPLAY_DIS);
694
695 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
696 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
697
698 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
699 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
700 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
701 }
702
703 if (is_tv)
704 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
705 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
706 &crtc_v_sync_strt_wid);
707
708 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
709 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
710 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
711 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
712
713 return true;
714 }
715
716 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
717 {
718 struct drm_device *dev = crtc->dev;
719 struct radeon_device *rdev = dev->dev_private;
720 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
721 struct drm_encoder *encoder;
722 uint32_t feedback_div = 0;
723 uint32_t frac_fb_div = 0;
724 uint32_t reference_div = 0;
725 uint32_t post_divider = 0;
726 uint32_t freq = 0;
727 uint8_t pll_gain;
728 int pll_flags = RADEON_PLL_LEGACY;
729 bool use_bios_divs = false;
730 /* PLL registers */
731 uint32_t pll_ref_div = 0;
732 uint32_t pll_fb_post_div = 0;
733 uint32_t htotal_cntl = 0;
734 bool is_tv = false;
735 struct radeon_pll *pll;
736
737 struct {
738 int divider;
739 int bitvalue;
740 } *post_div, post_divs[] = {
741 /* From RAGE 128 VR/RAGE 128 GL Register
742 * Reference Manual (Technical Reference
743 * Manual P/N RRG-G04100-C Rev. 0.04), page
744 * 3-17 (PLL_DIV_[3:0]).
745 */
746 { 1, 0 }, /* VCLK_SRC */
747 { 2, 1 }, /* VCLK_SRC/2 */
748 { 4, 2 }, /* VCLK_SRC/4 */
749 { 8, 3 }, /* VCLK_SRC/8 */
750 { 3, 4 }, /* VCLK_SRC/3 */
751 { 16, 5 }, /* VCLK_SRC/16 */
752 { 6, 6 }, /* VCLK_SRC/6 */
753 { 12, 7 }, /* VCLK_SRC/12 */
754 { 0, 0 }
755 };
756
757 if (radeon_crtc->crtc_id)
758 pll = &rdev->clock.p2pll;
759 else
760 pll = &rdev->clock.p1pll;
761
762 if (mode->clock > 200000) /* range limits??? */
763 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
764 else
765 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
766
767 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
768 if (encoder->crtc == crtc) {
769 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
770
771 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
772 is_tv = true;
773 break;
774 }
775
776 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
777 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
778 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
779 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
780 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
781 if (lvds) {
782 if (lvds->use_bios_dividers) {
783 pll_ref_div = lvds->panel_ref_divider;
784 pll_fb_post_div = (lvds->panel_fb_divider |
785 (lvds->panel_post_divider << 16));
786 htotal_cntl = 0;
787 use_bios_divs = true;
788 }
789 }
790 pll_flags |= RADEON_PLL_USE_REF_DIV;
791 }
792 }
793 }
794
795 DRM_DEBUG("\n");
796
797 if (!use_bios_divs) {
798 radeon_compute_pll(pll, mode->clock,
799 &freq, &feedback_div, &frac_fb_div,
800 &reference_div, &post_divider,
801 pll_flags);
802
803 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
804 if (post_div->divider == post_divider)
805 break;
806 }
807
808 if (!post_div->divider)
809 post_div = &post_divs[0];
810
811 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
812 (unsigned)freq,
813 feedback_div,
814 reference_div,
815 post_divider);
816
817 pll_ref_div = reference_div;
818 #if defined(__powerpc__) && (0) /* TODO */
819 /* apparently programming this otherwise causes a hang??? */
820 if (info->MacModel == RADEON_MAC_IBOOK)
821 pll_fb_post_div = 0x000600ad;
822 else
823 #endif
824 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
825
826 htotal_cntl = mode->htotal & 0x7;
827
828 }
829
830 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
831 pll_ref_div & 0x3ff,
832 pll_fb_post_div & 0x7ff);
833
834 if (radeon_crtc->crtc_id) {
835 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
836 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
837 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
838
839 if (is_tv) {
840 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
841 &pll_ref_div, &pll_fb_post_div,
842 &pixclks_cntl);
843 }
844
845 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
846 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
847 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
848
849 WREG32_PLL_P(RADEON_P2PLL_CNTL,
850 RADEON_P2PLL_RESET
851 | RADEON_P2PLL_ATOMIC_UPDATE_EN
852 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
853 ~(RADEON_P2PLL_RESET
854 | RADEON_P2PLL_ATOMIC_UPDATE_EN
855 | RADEON_P2PLL_PVG_MASK));
856
857 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
858 pll_ref_div,
859 ~RADEON_P2PLL_REF_DIV_MASK);
860
861 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
862 pll_fb_post_div,
863 ~RADEON_P2PLL_FB0_DIV_MASK);
864
865 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
866 pll_fb_post_div,
867 ~RADEON_P2PLL_POST0_DIV_MASK);
868
869 radeon_pll2_write_update(dev);
870 radeon_pll2_wait_for_read_update_complete(dev);
871
872 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
873
874 WREG32_PLL_P(RADEON_P2PLL_CNTL,
875 0,
876 ~(RADEON_P2PLL_RESET
877 | RADEON_P2PLL_SLEEP
878 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
879
880 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
881 (unsigned)pll_ref_div,
882 (unsigned)pll_fb_post_div,
883 (unsigned)htotal_cntl,
884 RREG32_PLL(RADEON_P2PLL_CNTL));
885 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
886 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
887 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
888 (unsigned)((pll_fb_post_div &
889 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
890
891 mdelay(50); /* Let the clock to lock */
892
893 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
894 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
895 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
896
897 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
898 } else {
899 uint32_t pixclks_cntl;
900
901
902 if (is_tv) {
903 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
904 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
905 &pll_fb_post_div, &pixclks_cntl);
906 }
907
908 if (rdev->flags & RADEON_IS_MOBILITY) {
909 /* A temporal workaround for the occational blanking on certain laptop panels.
910 This appears to related to the PLL divider registers (fail to lock?).
911 It occurs even when all dividers are the same with their old settings.
912 In this case we really don't need to fiddle with PLL registers.
913 By doing this we can avoid the blanking problem with some panels.
914 */
915 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
916 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
917 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
918 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
919 RADEON_PLL_DIV_SEL,
920 ~(RADEON_PLL_DIV_SEL));
921 r100_pll_errata_after_index(rdev);
922 return;
923 }
924 }
925
926 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
927 RADEON_VCLK_SRC_SEL_CPUCLK,
928 ~(RADEON_VCLK_SRC_SEL_MASK));
929 WREG32_PLL_P(RADEON_PPLL_CNTL,
930 RADEON_PPLL_RESET
931 | RADEON_PPLL_ATOMIC_UPDATE_EN
932 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
933 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
934 ~(RADEON_PPLL_RESET
935 | RADEON_PPLL_ATOMIC_UPDATE_EN
936 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
937 | RADEON_PPLL_PVG_MASK));
938
939 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
940 RADEON_PLL_DIV_SEL,
941 ~(RADEON_PLL_DIV_SEL));
942 r100_pll_errata_after_index(rdev);
943
944 if (ASIC_IS_R300(rdev) ||
945 (rdev->family == CHIP_RS300) ||
946 (rdev->family == CHIP_RS400) ||
947 (rdev->family == CHIP_RS480)) {
948 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
949 /* When restoring console mode, use saved PPLL_REF_DIV
950 * setting.
951 */
952 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
953 pll_ref_div,
954 0);
955 } else {
956 /* R300 uses ref_div_acc field as real ref divider */
957 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
958 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
959 ~R300_PPLL_REF_DIV_ACC_MASK);
960 }
961 } else
962 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
963 pll_ref_div,
964 ~RADEON_PPLL_REF_DIV_MASK);
965
966 WREG32_PLL_P(RADEON_PPLL_DIV_3,
967 pll_fb_post_div,
968 ~RADEON_PPLL_FB3_DIV_MASK);
969
970 WREG32_PLL_P(RADEON_PPLL_DIV_3,
971 pll_fb_post_div,
972 ~RADEON_PPLL_POST3_DIV_MASK);
973
974 radeon_pll_write_update(dev);
975 radeon_pll_wait_for_read_update_complete(dev);
976
977 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
978
979 WREG32_PLL_P(RADEON_PPLL_CNTL,
980 0,
981 ~(RADEON_PPLL_RESET
982 | RADEON_PPLL_SLEEP
983 | RADEON_PPLL_ATOMIC_UPDATE_EN
984 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
985
986 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
987 pll_ref_div,
988 pll_fb_post_div,
989 (unsigned)htotal_cntl,
990 RREG32_PLL(RADEON_PPLL_CNTL));
991 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
992 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
993 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
994 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
995
996 mdelay(50); /* Let the clock to lock */
997
998 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
999 RADEON_VCLK_SRC_SEL_PPLLCLK,
1000 ~(RADEON_VCLK_SRC_SEL_MASK));
1001
1002 if (is_tv)
1003 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1004 }
1005 }
1006
1007 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1008 struct drm_display_mode *mode,
1009 struct drm_display_mode *adjusted_mode)
1010 {
1011 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1012 return false;
1013 return true;
1014 }
1015
1016 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1017 struct drm_display_mode *mode,
1018 struct drm_display_mode *adjusted_mode,
1019 int x, int y, struct drm_framebuffer *old_fb)
1020 {
1021 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1022
1023 /* TODO TV */
1024 radeon_crtc_set_base(crtc, x, y, old_fb);
1025 radeon_set_crtc_timing(crtc, adjusted_mode);
1026 radeon_set_pll(crtc, adjusted_mode);
1027 if (radeon_crtc->crtc_id == 0) {
1028 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1029 } else {
1030 if (radeon_crtc->rmx_type != RMX_OFF) {
1031 /* FIXME: only first crtc has rmx what should we
1032 * do ?
1033 */
1034 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1035 }
1036 }
1037 return 0;
1038 }
1039
1040 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1041 {
1042 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1043 }
1044
1045 static void radeon_crtc_commit(struct drm_crtc *crtc)
1046 {
1047 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1048 }
1049
1050 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1051 .dpms = radeon_crtc_dpms,
1052 .mode_fixup = radeon_crtc_mode_fixup,
1053 .mode_set = radeon_crtc_mode_set,
1054 .mode_set_base = radeon_crtc_set_base,
1055 .prepare = radeon_crtc_prepare,
1056 .commit = radeon_crtc_commit,
1057 .load_lut = radeon_crtc_load_lut,
1058 };
1059
1060
1061 void radeon_legacy_init_crtc(struct drm_device *dev,
1062 struct radeon_crtc *radeon_crtc)
1063 {
1064 if (radeon_crtc->crtc_id == 1)
1065 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1066 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1067 }
mm of the moment repository