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mm-only debug patch...
[mmotm.git] / drivers / net / wireless / ath / ath9k / main.c
blob69cf702b18c2109afe3ff2241b485cb01f3cd666
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19 #include "btcoex.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
32 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33 module_param_named(debug, ath9k_debug, uint, 0);
34 MODULE_PARM_DESC(debug, "Debugging mask");
35
36 /* We use the hw_value as an index into our private channel structure */
37
38 #define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 20, \
42 }
43
44 #define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
47 .hw_value = (_idx), \
48 .max_power = 20, \
49 }
50
51 /* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
54 * this static */
55 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
70 };
71
72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
75 * this static */
76 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105 };
106
107 static void ath_cache_conf_rate(struct ath_softc *sc,
108 struct ieee80211_conf *conf)
109 {
110 switch (conf->channel->band) {
111 case IEEE80211_BAND_2GHZ:
112 if (conf_is_ht20(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
115 else if (conf_is_ht40_minus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
118 else if (conf_is_ht40_plus(conf))
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
121 else
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11G];
124 break;
125 case IEEE80211_BAND_5GHZ:
126 if (conf_is_ht20(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
129 else if (conf_is_ht40_minus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
132 else if (conf_is_ht40_plus(conf))
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
135 else
136 sc->cur_rate_table =
137 sc->hw_rate_table[ATH9K_MODE_11A];
138 break;
139 default:
140 BUG_ON(1);
141 break;
142 }
143 }
144
145 static void ath_update_txpow(struct ath_softc *sc)
146 {
147 struct ath_hw *ah = sc->sc_ah;
148 u32 txpow;
149
150 if (sc->curtxpow != sc->config.txpowlimit) {
151 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
152 /* read back in case value is clamped */
153 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
154 sc->curtxpow = txpow;
155 }
156 }
157
158 static u8 parse_mpdudensity(u8 mpdudensity)
159 {
160 /*
161 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
162 * 0 for no restriction
163 * 1 for 1/4 us
164 * 2 for 1/2 us
165 * 3 for 1 us
166 * 4 for 2 us
167 * 5 for 4 us
168 * 6 for 8 us
169 * 7 for 16 us
170 */
171 switch (mpdudensity) {
172 case 0:
173 return 0;
174 case 1:
175 case 2:
176 case 3:
177 /* Our lower layer calculations limit our precision to
178 1 microsecond */
179 return 1;
180 case 4:
181 return 2;
182 case 5:
183 return 4;
184 case 6:
185 return 8;
186 case 7:
187 return 16;
188 default:
189 return 0;
190 }
191 }
192
193 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
194 {
195 const struct ath_rate_table *rate_table = NULL;
196 struct ieee80211_supported_band *sband;
197 struct ieee80211_rate *rate;
198 int i, maxrates;
199
200 switch (band) {
201 case IEEE80211_BAND_2GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
203 break;
204 case IEEE80211_BAND_5GHZ:
205 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
206 break;
207 default:
208 break;
209 }
210
211 if (rate_table == NULL)
212 return;
213
214 sband = &sc->sbands[band];
215 rate = sc->rates[band];
216
217 if (rate_table->rate_cnt > ATH_RATE_MAX)
218 maxrates = ATH_RATE_MAX;
219 else
220 maxrates = rate_table->rate_cnt;
221
222 for (i = 0; i < maxrates; i++) {
223 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
224 rate[i].hw_value = rate_table->info[i].ratecode;
225 if (rate_table->info[i].short_preamble) {
226 rate[i].hw_value_short = rate_table->info[i].ratecode |
227 rate_table->info[i].short_preamble;
228 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 }
230 sband->n_bitrates++;
231
232 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
233 "Rate: %2dMbps, ratecode: %2d\n",
234 rate[i].bitrate / 10, rate[i].hw_value);
235 }
236 }
237
238 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
239 struct ieee80211_hw *hw)
240 {
241 struct ieee80211_channel *curchan = hw->conf.channel;
242 struct ath9k_channel *channel;
243 u8 chan_idx;
244
245 chan_idx = curchan->hw_value;
246 channel = &sc->sc_ah->channels[chan_idx];
247 ath9k_update_ichannel(sc, hw, channel);
248 return channel;
249 }
250
251 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
252 {
253 unsigned long flags;
254 bool ret;
255
256 spin_lock_irqsave(&sc->sc_pm_lock, flags);
257 ret = ath9k_hw_setpower(sc->sc_ah, mode);
258 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
259
260 return ret;
261 }
262
263 void ath9k_ps_wakeup(struct ath_softc *sc)
264 {
265 unsigned long flags;
266
267 spin_lock_irqsave(&sc->sc_pm_lock, flags);
268 if (++sc->ps_usecount != 1)
269 goto unlock;
270
271 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
272
273 unlock:
274 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
275 }
276
277 void ath9k_ps_restore(struct ath_softc *sc)
278 {
279 unsigned long flags;
280
281 spin_lock_irqsave(&sc->sc_pm_lock, flags);
282 if (--sc->ps_usecount != 0)
283 goto unlock;
284
285 if (sc->ps_enabled &&
286 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
287 SC_OP_WAIT_FOR_CAB |
288 SC_OP_WAIT_FOR_PSPOLL_DATA |
289 SC_OP_WAIT_FOR_TX_ACK)))
290 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
291
292 unlock:
293 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
294 }
295
296 /*
297 * Set/change channels. If the channel is really being changed, it's done
298 * by reseting the chip. To accomplish this we must first cleanup any pending
299 * DMA, then restart stuff.
300 */
301 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
302 struct ath9k_channel *hchan)
303 {
304 struct ath_hw *ah = sc->sc_ah;
305 struct ath_common *common = ath9k_hw_common(ah);
306 struct ieee80211_conf *conf = &common->hw->conf;
307 bool fastcc = true, stopped;
308 struct ieee80211_channel *channel = hw->conf.channel;
309 int r;
310
311 if (sc->sc_flags & SC_OP_INVALID)
312 return -EIO;
313
314 ath9k_ps_wakeup(sc);
315
316 /*
317 * This is only performed if the channel settings have
318 * actually changed.
319 *
320 * To switch channels clear any pending DMA operations;
321 * wait long enough for the RX fifo to drain, reset the
322 * hardware at the new frequency, and then re-enable
323 * the relevant bits of the h/w.
324 */
325 ath9k_hw_set_interrupts(ah, 0);
326 ath_drain_all_txq(sc, false);
327 stopped = ath_stoprecv(sc);
328
329 /* XXX: do not flush receive queue here. We don't want
330 * to flush data frames already in queue because of
331 * changing channel. */
332
333 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
334 fastcc = false;
335
336 ath_print(common, ATH_DBG_CONFIG,
337 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
338 sc->sc_ah->curchan->channel,
339 channel->center_freq, conf_is_ht40(conf));
340
341 spin_lock_bh(&sc->sc_resetlock);
342
343 r = ath9k_hw_reset(ah, hchan, fastcc);
344 if (r) {
345 ath_print(common, ATH_DBG_FATAL,
346 "Unable to reset channel (%u Mhz) "
347 "reset status %d\n",
348 channel->center_freq, r);
349 spin_unlock_bh(&sc->sc_resetlock);
350 goto ps_restore;
351 }
352 spin_unlock_bh(&sc->sc_resetlock);
353
354 sc->sc_flags &= ~SC_OP_FULL_RESET;
355
356 if (ath_startrecv(sc) != 0) {
357 ath_print(common, ATH_DBG_FATAL,
358 "Unable to restart recv logic\n");
359 r = -EIO;
360 goto ps_restore;
361 }
362
363 ath_cache_conf_rate(sc, &hw->conf);
364 ath_update_txpow(sc);
365 ath9k_hw_set_interrupts(ah, sc->imask);
366
367 ps_restore:
368 ath9k_ps_restore(sc);
369 return r;
370 }
371
372 /*
373 * This routine performs the periodic noise floor calibration function
374 * that is used to adjust and optimize the chip performance. This
375 * takes environmental changes (location, temperature) into account.
376 * When the task is complete, it reschedules itself depending on the
377 * appropriate interval that was calculated.
378 */
379 static void ath_ani_calibrate(unsigned long data)
380 {
381 struct ath_softc *sc = (struct ath_softc *)data;
382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
384 bool longcal = false;
385 bool shortcal = false;
386 bool aniflag = false;
387 unsigned int timestamp = jiffies_to_msecs(jiffies);
388 u32 cal_interval, short_cal_interval;
389
390 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
391 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
392
393 /*
394 * don't calibrate when we're scanning.
395 * we are most likely not on our home channel.
396 */
397 spin_lock(&sc->ani_lock);
398 if (sc->sc_flags & SC_OP_SCANNING)
399 goto set_timer;
400
401 /* Only calibrate if awake */
402 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
403 goto set_timer;
404
405 ath9k_ps_wakeup(sc);
406
407 /* Long calibration runs independently of short calibration. */
408 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
409 longcal = true;
410 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
411 sc->ani.longcal_timer = timestamp;
412 }
413
414 /* Short calibration applies only while caldone is false */
415 if (!sc->ani.caldone) {
416 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
417 shortcal = true;
418 ath_print(common, ATH_DBG_ANI,
419 "shortcal @%lu\n", jiffies);
420 sc->ani.shortcal_timer = timestamp;
421 sc->ani.resetcal_timer = timestamp;
422 }
423 } else {
424 if ((timestamp - sc->ani.resetcal_timer) >=
425 ATH_RESTART_CALINTERVAL) {
426 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
427 if (sc->ani.caldone)
428 sc->ani.resetcal_timer = timestamp;
429 }
430 }
431
432 /* Verify whether we must check ANI */
433 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
434 aniflag = true;
435 sc->ani.checkani_timer = timestamp;
436 }
437
438 /* Skip all processing if there's nothing to do. */
439 if (longcal || shortcal || aniflag) {
440 /* Call ANI routine if necessary */
441 if (aniflag)
442 ath9k_hw_ani_monitor(ah, ah->curchan);
443
444 /* Perform calibration if necessary */
445 if (longcal || shortcal) {
446 sc->ani.caldone =
447 ath9k_hw_calibrate(ah,
448 ah->curchan,
449 common->rx_chainmask,
450 longcal);
451
452 if (longcal)
453 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
454 ah->curchan);
455
456 ath_print(common, ATH_DBG_ANI,
457 " calibrate chan %u/%x nf: %d\n",
458 ah->curchan->channel,
459 ah->curchan->channelFlags,
460 sc->ani.noise_floor);
461 }
462 }
463
464 ath9k_ps_restore(sc);
465
466 set_timer:
467 spin_unlock(&sc->ani_lock);
468 /*
469 * Set timer interval based on previous results.
470 * The interval must be the shortest necessary to satisfy ANI,
471 * short calibration and long calibration.
472 */
473 cal_interval = ATH_LONG_CALINTERVAL;
474 if (sc->sc_ah->config.enable_ani)
475 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
476 if (!sc->ani.caldone)
477 cal_interval = min(cal_interval, (u32)short_cal_interval);
478
479 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
480 }
481
482 static void ath_start_ani(struct ath_softc *sc)
483 {
484 unsigned long timestamp = jiffies_to_msecs(jiffies);
485
486 sc->ani.longcal_timer = timestamp;
487 sc->ani.shortcal_timer = timestamp;
488 sc->ani.checkani_timer = timestamp;
489
490 mod_timer(&sc->ani.timer,
491 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
492 }
493
494 /*
495 * Update tx/rx chainmask. For legacy association,
496 * hard code chainmask to 1x1, for 11n association, use
497 * the chainmask configuration, for bt coexistence, use
498 * the chainmask configuration even in legacy mode.
499 */
500 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
501 {
502 struct ath_hw *ah = sc->sc_ah;
503 struct ath_common *common = ath9k_hw_common(ah);
504
505 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
507 common->tx_chainmask = ah->caps.tx_chainmask;
508 common->rx_chainmask = ah->caps.rx_chainmask;
509 } else {
510 common->tx_chainmask = 1;
511 common->rx_chainmask = 1;
512 }
513
514 ath_print(common, ATH_DBG_CONFIG,
515 "tx chmask: %d, rx chmask: %d\n",
516 common->tx_chainmask,
517 common->rx_chainmask);
518 }
519
520 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
521 {
522 struct ath_node *an;
523
524 an = (struct ath_node *)sta->drv_priv;
525
526 if (sc->sc_flags & SC_OP_TXAGGR) {
527 ath_tx_node_init(sc, an);
528 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
529 sta->ht_cap.ampdu_factor);
530 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
531 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
532 }
533 }
534
535 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
536 {
537 struct ath_node *an = (struct ath_node *)sta->drv_priv;
538
539 if (sc->sc_flags & SC_OP_TXAGGR)
540 ath_tx_node_cleanup(sc, an);
541 }
542
543 static void ath9k_tasklet(unsigned long data)
544 {
545 struct ath_softc *sc = (struct ath_softc *)data;
546 struct ath_hw *ah = sc->sc_ah;
547 struct ath_common *common = ath9k_hw_common(ah);
548
549 u32 status = sc->intrstatus;
550
551 ath9k_ps_wakeup(sc);
552
553 if (status & ATH9K_INT_FATAL) {
554 ath_reset(sc, false);
555 ath9k_ps_restore(sc);
556 return;
557 }
558
559 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
560 spin_lock_bh(&sc->rx.rxflushlock);
561 ath_rx_tasklet(sc, 0);
562 spin_unlock_bh(&sc->rx.rxflushlock);
563 }
564
565 if (status & ATH9K_INT_TX)
566 ath_tx_tasklet(sc);
567
568 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
569 /*
570 * TSF sync does not look correct; remain awake to sync with
571 * the next Beacon.
572 */
573 ath_print(common, ATH_DBG_PS,
574 "TSFOOR - Sync with next Beacon\n");
575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
576 }
577
578 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
579 if (status & ATH9K_INT_GENTIMER)
580 ath_gen_timer_isr(sc->sc_ah);
581
582 /* re-enable hardware interrupt */
583 ath9k_hw_set_interrupts(ah, sc->imask);
584 ath9k_ps_restore(sc);
585 }
586
587 irqreturn_t ath_isr(int irq, void *dev)
588 {
589 #define SCHED_INTR ( \
590 ATH9K_INT_FATAL | \
591 ATH9K_INT_RXORN | \
592 ATH9K_INT_RXEOL | \
593 ATH9K_INT_RX | \
594 ATH9K_INT_TX | \
595 ATH9K_INT_BMISS | \
596 ATH9K_INT_CST | \
597 ATH9K_INT_TSFOOR | \
598 ATH9K_INT_GENTIMER)
599
600 struct ath_softc *sc = dev;
601 struct ath_hw *ah = sc->sc_ah;
602 enum ath9k_int status;
603 bool sched = false;
604
605 /*
606 * The hardware is not ready/present, don't
607 * touch anything. Note this can happen early
608 * on if the IRQ is shared.
609 */
610 if (sc->sc_flags & SC_OP_INVALID)
611 return IRQ_NONE;
612
613
614 /* shared irq, not for us */
615
616 if (!ath9k_hw_intrpend(ah))
617 return IRQ_NONE;
618
619 /*
620 * Figure out the reason(s) for the interrupt. Note
621 * that the hal returns a pseudo-ISR that may include
622 * bits we haven't explicitly enabled so we mask the
623 * value to insure we only process bits we requested.
624 */
625 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
626 status &= sc->imask; /* discard unasked-for bits */
627
628 /*
629 * If there are no status bits set, then this interrupt was not
630 * for me (should have been caught above).
631 */
632 if (!status)
633 return IRQ_NONE;
634
635 /* Cache the status */
636 sc->intrstatus = status;
637
638 if (status & SCHED_INTR)
639 sched = true;
640
641 /*
642 * If a FATAL or RXORN interrupt is received, we have to reset the
643 * chip immediately.
644 */
645 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
646 goto chip_reset;
647
648 if (status & ATH9K_INT_SWBA)
649 tasklet_schedule(&sc->bcon_tasklet);
650
651 if (status & ATH9K_INT_TXURN)
652 ath9k_hw_updatetxtriglevel(ah, true);
653
654 if (status & ATH9K_INT_MIB) {
655 /*
656 * Disable interrupts until we service the MIB
657 * interrupt; otherwise it will continue to
658 * fire.
659 */
660 ath9k_hw_set_interrupts(ah, 0);
661 /*
662 * Let the hal handle the event. We assume
663 * it will clear whatever condition caused
664 * the interrupt.
665 */
666 ath9k_hw_procmibevent(ah);
667 ath9k_hw_set_interrupts(ah, sc->imask);
668 }
669
670 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
671 if (status & ATH9K_INT_TIM_TIMER) {
672 /* Clear RxAbort bit so that we can
673 * receive frames */
674 ath9k_setpower(sc, ATH9K_PM_AWAKE);
675 ath9k_hw_setrxabort(sc->sc_ah, 0);
676 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
677 }
678
679 chip_reset:
680
681 ath_debug_stat_interrupt(sc, status);
682
683 if (sched) {
684 /* turn off every interrupt except SWBA */
685 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
686 tasklet_schedule(&sc->intr_tq);
687 }
688
689 return IRQ_HANDLED;
690
691 #undef SCHED_INTR
692 }
693
694 static u32 ath_get_extchanmode(struct ath_softc *sc,
695 struct ieee80211_channel *chan,
696 enum nl80211_channel_type channel_type)
697 {
698 u32 chanmode = 0;
699
700 switch (chan->band) {
701 case IEEE80211_BAND_2GHZ:
702 switch(channel_type) {
703 case NL80211_CHAN_NO_HT:
704 case NL80211_CHAN_HT20:
705 chanmode = CHANNEL_G_HT20;
706 break;
707 case NL80211_CHAN_HT40PLUS:
708 chanmode = CHANNEL_G_HT40PLUS;
709 break;
710 case NL80211_CHAN_HT40MINUS:
711 chanmode = CHANNEL_G_HT40MINUS;
712 break;
713 }
714 break;
715 case IEEE80211_BAND_5GHZ:
716 switch(channel_type) {
717 case NL80211_CHAN_NO_HT:
718 case NL80211_CHAN_HT20:
719 chanmode = CHANNEL_A_HT20;
720 break;
721 case NL80211_CHAN_HT40PLUS:
722 chanmode = CHANNEL_A_HT40PLUS;
723 break;
724 case NL80211_CHAN_HT40MINUS:
725 chanmode = CHANNEL_A_HT40MINUS;
726 break;
727 }
728 break;
729 default:
730 break;
731 }
732
733 return chanmode;
734 }
735
736 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
737 struct ath9k_keyval *hk, const u8 *addr,
738 bool authenticator)
739 {
740 const u8 *key_rxmic;
741 const u8 *key_txmic;
742
743 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
744 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
745
746 if (addr == NULL) {
747 /*
748 * Group key installation - only two key cache entries are used
749 * regardless of splitmic capability since group key is only
750 * used either for TX or RX.
751 */
752 if (authenticator) {
753 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
754 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
755 } else {
756 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
757 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
758 }
759 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
760 }
761 if (!sc->splitmic) {
762 /* TX and RX keys share the same key cache entry. */
763 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
764 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
765 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
766 }
767
768 /* Separate key cache entries for TX and RX */
769
770 /* TX key goes at first index, RX key at +32. */
771 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
772 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
773 /* TX MIC entry failed. No need to proceed further */
774 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
775 "Setting TX MIC Key Failed\n");
776 return 0;
777 }
778
779 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
780 /* XXX delete tx key on failure? */
781 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
782 }
783
784 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
785 {
786 int i;
787
788 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
789 if (test_bit(i, sc->keymap) ||
790 test_bit(i + 64, sc->keymap))
791 continue; /* At least one part of TKIP key allocated */
792 if (sc->splitmic &&
793 (test_bit(i + 32, sc->keymap) ||
794 test_bit(i + 64 + 32, sc->keymap)))
795 continue; /* At least one part of TKIP key allocated */
796
797 /* Found a free slot for a TKIP key */
798 return i;
799 }
800 return -1;
801 }
802
803 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
804 {
805 int i;
806
807 /* First, try to find slots that would not be available for TKIP. */
808 if (sc->splitmic) {
809 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
810 if (!test_bit(i, sc->keymap) &&
811 (test_bit(i + 32, sc->keymap) ||
812 test_bit(i + 64, sc->keymap) ||
813 test_bit(i + 64 + 32, sc->keymap)))
814 return i;
815 if (!test_bit(i + 32, sc->keymap) &&
816 (test_bit(i, sc->keymap) ||
817 test_bit(i + 64, sc->keymap) ||
818 test_bit(i + 64 + 32, sc->keymap)))
819 return i + 32;
820 if (!test_bit(i + 64, sc->keymap) &&
821 (test_bit(i , sc->keymap) ||
822 test_bit(i + 32, sc->keymap) ||
823 test_bit(i + 64 + 32, sc->keymap)))
824 return i + 64;
825 if (!test_bit(i + 64 + 32, sc->keymap) &&
826 (test_bit(i, sc->keymap) ||
827 test_bit(i + 32, sc->keymap) ||
828 test_bit(i + 64, sc->keymap)))
829 return i + 64 + 32;
830 }
831 } else {
832 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
833 if (!test_bit(i, sc->keymap) &&
834 test_bit(i + 64, sc->keymap))
835 return i;
836 if (test_bit(i, sc->keymap) &&
837 !test_bit(i + 64, sc->keymap))
838 return i + 64;
839 }
840 }
841
842 /* No partially used TKIP slots, pick any available slot */
843 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
844 /* Do not allow slots that could be needed for TKIP group keys
845 * to be used. This limitation could be removed if we know that
846 * TKIP will not be used. */
847 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
848 continue;
849 if (sc->splitmic) {
850 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
851 continue;
852 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
853 continue;
854 }
855
856 if (!test_bit(i, sc->keymap))
857 return i; /* Found a free slot for a key */
858 }
859
860 /* No free slot found */
861 return -1;
862 }
863
864 static int ath_key_config(struct ath_softc *sc,
865 struct ieee80211_vif *vif,
866 struct ieee80211_sta *sta,
867 struct ieee80211_key_conf *key)
868 {
869 struct ath9k_keyval hk;
870 const u8 *mac = NULL;
871 int ret = 0;
872 int idx;
873
874 memset(&hk, 0, sizeof(hk));
875
876 switch (key->alg) {
877 case ALG_WEP:
878 hk.kv_type = ATH9K_CIPHER_WEP;
879 break;
880 case ALG_TKIP:
881 hk.kv_type = ATH9K_CIPHER_TKIP;
882 break;
883 case ALG_CCMP:
884 hk.kv_type = ATH9K_CIPHER_AES_CCM;
885 break;
886 default:
887 return -EOPNOTSUPP;
888 }
889
890 hk.kv_len = key->keylen;
891 memcpy(hk.kv_val, key->key, key->keylen);
892
893 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
894 /* For now, use the default keys for broadcast keys. This may
895 * need to change with virtual interfaces. */
896 idx = key->keyidx;
897 } else if (key->keyidx) {
898 if (WARN_ON(!sta))
899 return -EOPNOTSUPP;
900 mac = sta->addr;
901
902 if (vif->type != NL80211_IFTYPE_AP) {
903 /* Only keyidx 0 should be used with unicast key, but
904 * allow this for client mode for now. */
905 idx = key->keyidx;
906 } else
907 return -EIO;
908 } else {
909 if (WARN_ON(!sta))
910 return -EOPNOTSUPP;
911 mac = sta->addr;
912
913 if (key->alg == ALG_TKIP)
914 idx = ath_reserve_key_cache_slot_tkip(sc);
915 else
916 idx = ath_reserve_key_cache_slot(sc);
917 if (idx < 0)
918 return -ENOSPC; /* no free key cache entries */
919 }
920
921 if (key->alg == ALG_TKIP)
922 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
923 vif->type == NL80211_IFTYPE_AP);
924 else
925 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
926
927 if (!ret)
928 return -EIO;
929
930 set_bit(idx, sc->keymap);
931 if (key->alg == ALG_TKIP) {
932 set_bit(idx + 64, sc->keymap);
933 if (sc->splitmic) {
934 set_bit(idx + 32, sc->keymap);
935 set_bit(idx + 64 + 32, sc->keymap);
936 }
937 }
938
939 return idx;
940 }
941
942 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
943 {
944 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
945 if (key->hw_key_idx < IEEE80211_WEP_NKID)
946 return;
947
948 clear_bit(key->hw_key_idx, sc->keymap);
949 if (key->alg != ALG_TKIP)
950 return;
951
952 clear_bit(key->hw_key_idx + 64, sc->keymap);
953 if (sc->splitmic) {
954 clear_bit(key->hw_key_idx + 32, sc->keymap);
955 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
956 }
957 }
958
959 static void setup_ht_cap(struct ath_softc *sc,
960 struct ieee80211_sta_ht_cap *ht_info)
961 {
962 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
963 u8 tx_streams, rx_streams;
964
965 ht_info->ht_supported = true;
966 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
967 IEEE80211_HT_CAP_SM_PS |
968 IEEE80211_HT_CAP_SGI_40 |
969 IEEE80211_HT_CAP_DSSSCCK40;
970
971 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
972 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
973
974 /* set up supported mcs set */
975 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
976 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
977 1 : 2;
978 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
979 1 : 2;
980
981 if (tx_streams != rx_streams) {
982 ath_print(common, ATH_DBG_CONFIG,
983 "TX streams %d, RX streams: %d\n",
984 tx_streams, rx_streams);
985 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
986 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
987 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
988 }
989
990 ht_info->mcs.rx_mask[0] = 0xff;
991 if (rx_streams >= 2)
992 ht_info->mcs.rx_mask[1] = 0xff;
993
994 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
995 }
996
997 static void ath9k_bss_assoc_info(struct ath_softc *sc,
998 struct ieee80211_vif *vif,
999 struct ieee80211_bss_conf *bss_conf)
1000 {
1001 struct ath_hw *ah = sc->sc_ah;
1002 struct ath_common *common = ath9k_hw_common(ah);
1003
1004 if (bss_conf->assoc) {
1005 ath_print(common, ATH_DBG_CONFIG,
1006 "Bss Info ASSOC %d, bssid: %pM\n",
1007 bss_conf->aid, common->curbssid);
1008
1009 /* New association, store aid */
1010 common->curaid = bss_conf->aid;
1011 ath9k_hw_write_associd(ah);
1012
1013 /*
1014 * Request a re-configuration of Beacon related timers
1015 * on the receipt of the first Beacon frame (i.e.,
1016 * after time sync with the AP).
1017 */
1018 sc->sc_flags |= SC_OP_BEACON_SYNC;
1019
1020 /* Configure the beacon */
1021 ath_beacon_config(sc, vif);
1022
1023 /* Reset rssi stats */
1024 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1025
1026 ath_start_ani(sc);
1027 } else {
1028 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1029 common->curaid = 0;
1030 /* Stop ANI */
1031 del_timer_sync(&sc->ani.timer);
1032 }
1033 }
1034
1035 /********************************/
1036 /* LED functions */
1037 /********************************/
1038
1039 static void ath_led_blink_work(struct work_struct *work)
1040 {
1041 struct ath_softc *sc = container_of(work, struct ath_softc,
1042 ath_led_blink_work.work);
1043
1044 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1045 return;
1046
1047 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1048 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1049 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1050 else
1051 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1052 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1053
1054 ieee80211_queue_delayed_work(sc->hw,
1055 &sc->ath_led_blink_work,
1056 (sc->sc_flags & SC_OP_LED_ON) ?
1057 msecs_to_jiffies(sc->led_off_duration) :
1058 msecs_to_jiffies(sc->led_on_duration));
1059
1060 sc->led_on_duration = sc->led_on_cnt ?
1061 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1062 ATH_LED_ON_DURATION_IDLE;
1063 sc->led_off_duration = sc->led_off_cnt ?
1064 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1065 ATH_LED_OFF_DURATION_IDLE;
1066 sc->led_on_cnt = sc->led_off_cnt = 0;
1067 if (sc->sc_flags & SC_OP_LED_ON)
1068 sc->sc_flags &= ~SC_OP_LED_ON;
1069 else
1070 sc->sc_flags |= SC_OP_LED_ON;
1071 }
1072
1073 static void ath_led_brightness(struct led_classdev *led_cdev,
1074 enum led_brightness brightness)
1075 {
1076 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1077 struct ath_softc *sc = led->sc;
1078
1079 switch (brightness) {
1080 case LED_OFF:
1081 if (led->led_type == ATH_LED_ASSOC ||
1082 led->led_type == ATH_LED_RADIO) {
1083 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1084 (led->led_type == ATH_LED_RADIO));
1085 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1086 if (led->led_type == ATH_LED_RADIO)
1087 sc->sc_flags &= ~SC_OP_LED_ON;
1088 } else {
1089 sc->led_off_cnt++;
1090 }
1091 break;
1092 case LED_FULL:
1093 if (led->led_type == ATH_LED_ASSOC) {
1094 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1095 ieee80211_queue_delayed_work(sc->hw,
1096 &sc->ath_led_blink_work, 0);
1097 } else if (led->led_type == ATH_LED_RADIO) {
1098 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1099 sc->sc_flags |= SC_OP_LED_ON;
1100 } else {
1101 sc->led_on_cnt++;
1102 }
1103 break;
1104 default:
1105 break;
1106 }
1107 }
1108
1109 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1110 char *trigger)
1111 {
1112 int ret;
1113
1114 led->sc = sc;
1115 led->led_cdev.name = led->name;
1116 led->led_cdev.default_trigger = trigger;
1117 led->led_cdev.brightness_set = ath_led_brightness;
1118
1119 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1120 if (ret)
1121 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1122 "Failed to register led:%s", led->name);
1123 else
1124 led->registered = 1;
1125 return ret;
1126 }
1127
1128 static void ath_unregister_led(struct ath_led *led)
1129 {
1130 if (led->registered) {
1131 led_classdev_unregister(&led->led_cdev);
1132 led->registered = 0;
1133 }
1134 }
1135
1136 static void ath_deinit_leds(struct ath_softc *sc)
1137 {
1138 ath_unregister_led(&sc->assoc_led);
1139 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1140 ath_unregister_led(&sc->tx_led);
1141 ath_unregister_led(&sc->rx_led);
1142 ath_unregister_led(&sc->radio_led);
1143 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1144 }
1145
1146 static void ath_init_leds(struct ath_softc *sc)
1147 {
1148 char *trigger;
1149 int ret;
1150
1151 if (AR_SREV_9287(sc->sc_ah))
1152 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1153 else
1154 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1155
1156 /* Configure gpio 1 for output */
1157 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1158 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1159 /* LED off, active low */
1160 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1161
1162 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1163
1164 trigger = ieee80211_get_radio_led_name(sc->hw);
1165 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1166 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1167 ret = ath_register_led(sc, &sc->radio_led, trigger);
1168 sc->radio_led.led_type = ATH_LED_RADIO;
1169 if (ret)
1170 goto fail;
1171
1172 trigger = ieee80211_get_assoc_led_name(sc->hw);
1173 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1174 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1175 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1176 sc->assoc_led.led_type = ATH_LED_ASSOC;
1177 if (ret)
1178 goto fail;
1179
1180 trigger = ieee80211_get_tx_led_name(sc->hw);
1181 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1182 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1183 ret = ath_register_led(sc, &sc->tx_led, trigger);
1184 sc->tx_led.led_type = ATH_LED_TX;
1185 if (ret)
1186 goto fail;
1187
1188 trigger = ieee80211_get_rx_led_name(sc->hw);
1189 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1190 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1191 ret = ath_register_led(sc, &sc->rx_led, trigger);
1192 sc->rx_led.led_type = ATH_LED_RX;
1193 if (ret)
1194 goto fail;
1195
1196 return;
1197
1198 fail:
1199 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1200 ath_deinit_leds(sc);
1201 }
1202
1203 void ath_radio_enable(struct ath_softc *sc)
1204 {
1205 struct ath_hw *ah = sc->sc_ah;
1206 struct ath_common *common = ath9k_hw_common(ah);
1207 struct ieee80211_channel *channel = sc->hw->conf.channel;
1208 int r;
1209
1210 ath9k_ps_wakeup(sc);
1211 ath9k_hw_configpcipowersave(ah, 0, 0);
1212
1213 if (!ah->curchan)
1214 ah->curchan = ath_get_curchannel(sc, sc->hw);
1215
1216 spin_lock_bh(&sc->sc_resetlock);
1217 r = ath9k_hw_reset(ah, ah->curchan, false);
1218 if (r) {
1219 ath_print(common, ATH_DBG_FATAL,
1220 "Unable to reset channel %u (%uMhz) ",
1221 "reset status %d\n",
1222 channel->center_freq, r);
1223 }
1224 spin_unlock_bh(&sc->sc_resetlock);
1225
1226 ath_update_txpow(sc);
1227 if (ath_startrecv(sc) != 0) {
1228 ath_print(common, ATH_DBG_FATAL,
1229 "Unable to restart recv logic\n");
1230 return;
1231 }
1232
1233 if (sc->sc_flags & SC_OP_BEACONS)
1234 ath_beacon_config(sc, NULL); /* restart beacons */
1235
1236 /* Re-Enable interrupts */
1237 ath9k_hw_set_interrupts(ah, sc->imask);
1238
1239 /* Enable LED */
1240 ath9k_hw_cfg_output(ah, ah->led_pin,
1241 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1242 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1243
1244 ieee80211_wake_queues(sc->hw);
1245 ath9k_ps_restore(sc);
1246 }
1247
1248 void ath_radio_disable(struct ath_softc *sc)
1249 {
1250 struct ath_hw *ah = sc->sc_ah;
1251 struct ieee80211_channel *channel = sc->hw->conf.channel;
1252 int r;
1253
1254 ath9k_ps_wakeup(sc);
1255 ieee80211_stop_queues(sc->hw);
1256
1257 /* Disable LED */
1258 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1259 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1260
1261 /* Disable interrupts */
1262 ath9k_hw_set_interrupts(ah, 0);
1263
1264 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1265 ath_stoprecv(sc); /* turn off frame recv */
1266 ath_flushrecv(sc); /* flush recv queue */
1267
1268 if (!ah->curchan)
1269 ah->curchan = ath_get_curchannel(sc, sc->hw);
1270
1271 spin_lock_bh(&sc->sc_resetlock);
1272 r = ath9k_hw_reset(ah, ah->curchan, false);
1273 if (r) {
1274 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1275 "Unable to reset channel %u (%uMhz) "
1276 "reset status %d\n",
1277 channel->center_freq, r);
1278 }
1279 spin_unlock_bh(&sc->sc_resetlock);
1280
1281 ath9k_hw_phy_disable(ah);
1282 ath9k_hw_configpcipowersave(ah, 1, 1);
1283 ath9k_ps_restore(sc);
1284 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1285 }
1286
1287 /*******************/
1288 /* Rfkill */
1289 /*******************/
1290
1291 static bool ath_is_rfkill_set(struct ath_softc *sc)
1292 {
1293 struct ath_hw *ah = sc->sc_ah;
1294
1295 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1296 ah->rfkill_polarity;
1297 }
1298
1299 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1300 {
1301 struct ath_wiphy *aphy = hw->priv;
1302 struct ath_softc *sc = aphy->sc;
1303 bool blocked = !!ath_is_rfkill_set(sc);
1304
1305 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1306 }
1307
1308 static void ath_start_rfkill_poll(struct ath_softc *sc)
1309 {
1310 struct ath_hw *ah = sc->sc_ah;
1311
1312 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1313 wiphy_rfkill_start_polling(sc->hw->wiphy);
1314 }
1315
1316 static void ath9k_uninit_hw(struct ath_softc *sc)
1317 {
1318 struct ath_hw *ah = sc->sc_ah;
1319
1320 BUG_ON(!ah);
1321
1322 ath9k_exit_debug(ah);
1323 ath9k_hw_detach(ah);
1324 sc->sc_ah = NULL;
1325 }
1326
1327 static void ath_clean_core(struct ath_softc *sc)
1328 {
1329 struct ieee80211_hw *hw = sc->hw;
1330 struct ath_hw *ah = sc->sc_ah;
1331 int i = 0;
1332
1333 ath9k_ps_wakeup(sc);
1334
1335 dev_dbg(sc->dev, "Detach ATH hw\n");
1336
1337 ath_deinit_leds(sc);
1338 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1339
1340 for (i = 0; i < sc->num_sec_wiphy; i++) {
1341 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1342 if (aphy == NULL)
1343 continue;
1344 sc->sec_wiphy[i] = NULL;
1345 ieee80211_unregister_hw(aphy->hw);
1346 ieee80211_free_hw(aphy->hw);
1347 }
1348 ieee80211_unregister_hw(hw);
1349 ath_rx_cleanup(sc);
1350 ath_tx_cleanup(sc);
1351
1352 tasklet_kill(&sc->intr_tq);
1353 tasklet_kill(&sc->bcon_tasklet);
1354
1355 if (!(sc->sc_flags & SC_OP_INVALID))
1356 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1357
1358 /* cleanup tx queues */
1359 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1360 if (ATH_TXQ_SETUP(sc, i))
1361 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1362
1363 if ((sc->btcoex.no_stomp_timer) &&
1364 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1365 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1366 }
1367
1368 void ath_detach(struct ath_softc *sc)
1369 {
1370 ath_clean_core(sc);
1371 ath9k_uninit_hw(sc);
1372 }
1373
1374 void ath_cleanup(struct ath_softc *sc)
1375 {
1376 struct ath_hw *ah = sc->sc_ah;
1377 struct ath_common *common = ath9k_hw_common(ah);
1378
1379 ath_clean_core(sc);
1380 free_irq(sc->irq, sc);
1381 ath_bus_cleanup(common);
1382 kfree(sc->sec_wiphy);
1383 ieee80211_free_hw(sc->hw);
1384
1385 ath9k_uninit_hw(sc);
1386 }
1387
1388 static int ath9k_reg_notifier(struct wiphy *wiphy,
1389 struct regulatory_request *request)
1390 {
1391 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1392 struct ath_wiphy *aphy = hw->priv;
1393 struct ath_softc *sc = aphy->sc;
1394 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1395
1396 return ath_reg_notifier_apply(wiphy, request, reg);
1397 }
1398
1399 /*
1400 * Detects if there is any priority bt traffic
1401 */
1402 static void ath_detect_bt_priority(struct ath_softc *sc)
1403 {
1404 struct ath_btcoex *btcoex = &sc->btcoex;
1405 struct ath_hw *ah = sc->sc_ah;
1406
1407 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1408 btcoex->bt_priority_cnt++;
1409
1410 if (time_after(jiffies, btcoex->bt_priority_time +
1411 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1412 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1413 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1414 "BT priority traffic detected");
1415 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1416 } else {
1417 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1418 }
1419
1420 btcoex->bt_priority_cnt = 0;
1421 btcoex->bt_priority_time = jiffies;
1422 }
1423 }
1424
1425 /*
1426 * Configures appropriate weight based on stomp type.
1427 */
1428 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1429 enum ath_stomp_type stomp_type)
1430 {
1431 struct ath_hw *ah = sc->sc_ah;
1432
1433 switch (stomp_type) {
1434 case ATH_BTCOEX_STOMP_ALL:
1435 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1436 AR_STOMP_ALL_WLAN_WGHT);
1437 break;
1438 case ATH_BTCOEX_STOMP_LOW:
1439 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1440 AR_STOMP_LOW_WLAN_WGHT);
1441 break;
1442 case ATH_BTCOEX_STOMP_NONE:
1443 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1444 AR_STOMP_NONE_WLAN_WGHT);
1445 break;
1446 default:
1447 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1448 "Invalid Stomptype\n");
1449 break;
1450 }
1451
1452 ath9k_hw_btcoex_enable(ah);
1453 }
1454
1455 static void ath9k_gen_timer_start(struct ath_hw *ah,
1456 struct ath_gen_timer *timer,
1457 u32 timer_next,
1458 u32 timer_period)
1459 {
1460 struct ath_common *common = ath9k_hw_common(ah);
1461 struct ath_softc *sc = (struct ath_softc *) common->priv;
1462
1463 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1464
1465 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1466 ath9k_hw_set_interrupts(ah, 0);
1467 sc->imask |= ATH9K_INT_GENTIMER;
1468 ath9k_hw_set_interrupts(ah, sc->imask);
1469 }
1470 }
1471
1472 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1473 {
1474 struct ath_common *common = ath9k_hw_common(ah);
1475 struct ath_softc *sc = (struct ath_softc *) common->priv;
1476 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1477
1478 ath9k_hw_gen_timer_stop(ah, timer);
1479
1480 /* if no timer is enabled, turn off interrupt mask */
1481 if (timer_table->timer_mask.val == 0) {
1482 ath9k_hw_set_interrupts(ah, 0);
1483 sc->imask &= ~ATH9K_INT_GENTIMER;
1484 ath9k_hw_set_interrupts(ah, sc->imask);
1485 }
1486 }
1487
1488 /*
1489 * This is the master bt coex timer which runs for every
1490 * 45ms, bt traffic will be given priority during 55% of this
1491 * period while wlan gets remaining 45%
1492 */
1493 static void ath_btcoex_period_timer(unsigned long data)
1494 {
1495 struct ath_softc *sc = (struct ath_softc *) data;
1496 struct ath_hw *ah = sc->sc_ah;
1497 struct ath_btcoex *btcoex = &sc->btcoex;
1498
1499 ath_detect_bt_priority(sc);
1500
1501 spin_lock_bh(&btcoex->btcoex_lock);
1502
1503 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1504
1505 spin_unlock_bh(&btcoex->btcoex_lock);
1506
1507 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1508 if (btcoex->hw_timer_enabled)
1509 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1510
1511 ath9k_gen_timer_start(ah,
1512 btcoex->no_stomp_timer,
1513 (ath9k_hw_gettsf32(ah) +
1514 btcoex->btcoex_no_stomp),
1515 btcoex->btcoex_no_stomp * 10);
1516 btcoex->hw_timer_enabled = true;
1517 }
1518
1519 mod_timer(&btcoex->period_timer, jiffies +
1520 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1521 }
1522
1523 /*
1524 * Generic tsf based hw timer which configures weight
1525 * registers to time slice between wlan and bt traffic
1526 */
1527 static void ath_btcoex_no_stomp_timer(void *arg)
1528 {
1529 struct ath_softc *sc = (struct ath_softc *)arg;
1530 struct ath_hw *ah = sc->sc_ah;
1531 struct ath_btcoex *btcoex = &sc->btcoex;
1532
1533 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1534 "no stomp timer running \n");
1535
1536 spin_lock_bh(&btcoex->btcoex_lock);
1537
1538 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1539 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1540 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1541 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1542
1543 spin_unlock_bh(&btcoex->btcoex_lock);
1544 }
1545
1546 static int ath_init_btcoex_timer(struct ath_softc *sc)
1547 {
1548 struct ath_btcoex *btcoex = &sc->btcoex;
1549
1550 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1551 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1552 btcoex->btcoex_period / 100;
1553
1554 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1555 (unsigned long) sc);
1556
1557 spin_lock_init(&btcoex->btcoex_lock);
1558
1559 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1560 ath_btcoex_no_stomp_timer,
1561 ath_btcoex_no_stomp_timer,
1562 (void *) sc, AR_FIRST_NDP_TIMER);
1563
1564 if (!btcoex->no_stomp_timer)
1565 return -ENOMEM;
1566
1567 return 0;
1568 }
1569
1570 /*
1571 * Read and write, they both share the same lock. We do this to serialize
1572 * reads and writes on Atheros 802.11n PCI devices only. This is required
1573 * as the FIFO on these devices can only accept sanely 2 requests. After
1574 * that the device goes bananas. Serializing the reads/writes prevents this
1575 * from happening.
1576 */
1577
1578 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1579 {
1580 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1581 struct ath_common *common = ath9k_hw_common(ah);
1582 struct ath_softc *sc = (struct ath_softc *) common->priv;
1583
1584 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1585 unsigned long flags;
1586 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1587 iowrite32(val, sc->mem + reg_offset);
1588 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1589 } else
1590 iowrite32(val, sc->mem + reg_offset);
1591 }
1592
1593 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1594 {
1595 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1596 struct ath_common *common = ath9k_hw_common(ah);
1597 struct ath_softc *sc = (struct ath_softc *) common->priv;
1598 u32 val;
1599
1600 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1601 unsigned long flags;
1602 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1603 val = ioread32(sc->mem + reg_offset);
1604 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1605 } else
1606 val = ioread32(sc->mem + reg_offset);
1607 return val;
1608 }
1609
1610 static const struct ath_ops ath9k_common_ops = {
1611 .read = ath9k_ioread32,
1612 .write = ath9k_iowrite32,
1613 };
1614
1615 /*
1616 * Initialize and fill ath_softc, ath_sofct is the
1617 * "Software Carrier" struct. Historically it has existed
1618 * to allow the separation between hardware specific
1619 * variables (now in ath_hw) and driver specific variables.
1620 */
1621 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1622 const struct ath_bus_ops *bus_ops)
1623 {
1624 struct ath_hw *ah = NULL;
1625 struct ath_common *common;
1626 int r = 0, i;
1627 int csz = 0;
1628 int qnum;
1629
1630 /* XXX: hardware will not be ready until ath_open() being called */
1631 sc->sc_flags |= SC_OP_INVALID;
1632
1633 spin_lock_init(&sc->wiphy_lock);
1634 spin_lock_init(&sc->sc_resetlock);
1635 spin_lock_init(&sc->sc_serial_rw);
1636 spin_lock_init(&sc->ani_lock);
1637 spin_lock_init(&sc->sc_pm_lock);
1638 mutex_init(&sc->mutex);
1639 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1640 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1641 (unsigned long)sc);
1642
1643 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1644 if (!ah)
1645 return -ENOMEM;
1646
1647 ah->hw_version.devid = devid;
1648 ah->hw_version.subsysid = subsysid;
1649 sc->sc_ah = ah;
1650
1651 common = ath9k_hw_common(ah);
1652 common->ops = &ath9k_common_ops;
1653 common->bus_ops = bus_ops;
1654 common->ah = ah;
1655 common->hw = sc->hw;
1656 common->priv = sc;
1657 common->debug_mask = ath9k_debug;
1658
1659 /*
1660 * Cache line size is used to size and align various
1661 * structures used to communicate with the hardware.
1662 */
1663 ath_read_cachesize(common, &csz);
1664 /* XXX assert csz is non-zero */
1665 common->cachelsz = csz << 2; /* convert to bytes */
1666
1667 r = ath9k_hw_init(ah);
1668 if (r) {
1669 ath_print(common, ATH_DBG_FATAL,
1670 "Unable to initialize hardware; "
1671 "initialization status: %d\n", r);
1672 goto bad_free_hw;
1673 }
1674
1675 if (ath9k_init_debug(ah) < 0) {
1676 ath_print(common, ATH_DBG_FATAL,
1677 "Unable to create debugfs files\n");
1678 goto bad_free_hw;
1679 }
1680
1681 /* Get the hardware key cache size. */
1682 sc->keymax = ah->caps.keycache_size;
1683 if (sc->keymax > ATH_KEYMAX) {
1684 ath_print(common, ATH_DBG_ANY,
1685 "Warning, using only %u entries in %u key cache\n",
1686 ATH_KEYMAX, sc->keymax);
1687 sc->keymax = ATH_KEYMAX;
1688 }
1689
1690 /*
1691 * Reset the key cache since some parts do not
1692 * reset the contents on initial power up.
1693 */
1694 for (i = 0; i < sc->keymax; i++)
1695 ath9k_hw_keyreset(ah, (u16) i);
1696
1697 /* default to MONITOR mode */
1698 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1699
1700 /* Setup rate tables */
1701
1702 ath_rate_attach(sc);
1703 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1704 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1705
1706 /*
1707 * Allocate hardware transmit queues: one queue for
1708 * beacon frames and one data queue for each QoS
1709 * priority. Note that the hal handles reseting
1710 * these queues at the needed time.
1711 */
1712 sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
1713 if (sc->beacon.beaconq == -1) {
1714 ath_print(common, ATH_DBG_FATAL,
1715 "Unable to setup a beacon xmit queue\n");
1716 r = -EIO;
1717 goto bad2;
1718 }
1719 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1720 if (sc->beacon.cabq == NULL) {
1721 ath_print(common, ATH_DBG_FATAL,
1722 "Unable to setup CAB xmit queue\n");
1723 r = -EIO;
1724 goto bad2;
1725 }
1726
1727 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1728 ath_cabq_update(sc);
1729
1730 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1731 sc->tx.hwq_map[i] = -1;
1732
1733 /* Setup data queues */
1734 /* NB: ensure BK queue is the lowest priority h/w queue */
1735 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1736 ath_print(common, ATH_DBG_FATAL,
1737 "Unable to setup xmit queue for BK traffic\n");
1738 r = -EIO;
1739 goto bad2;
1740 }
1741
1742 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1743 ath_print(common, ATH_DBG_FATAL,
1744 "Unable to setup xmit queue for BE traffic\n");
1745 r = -EIO;
1746 goto bad2;
1747 }
1748 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1749 ath_print(common, ATH_DBG_FATAL,
1750 "Unable to setup xmit queue for VI traffic\n");
1751 r = -EIO;
1752 goto bad2;
1753 }
1754 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1755 ath_print(common, ATH_DBG_FATAL,
1756 "Unable to setup xmit queue for VO traffic\n");
1757 r = -EIO;
1758 goto bad2;
1759 }
1760
1761 /* Initializes the noise floor to a reasonable default value.
1762 * Later on this will be updated during ANI processing. */
1763
1764 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1765 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1766
1767 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1768 ATH9K_CIPHER_TKIP, NULL)) {
1769 /*
1770 * Whether we should enable h/w TKIP MIC.
1771 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1772 * report WMM capable, so it's always safe to turn on
1773 * TKIP MIC in this case.
1774 */
1775 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1776 0, 1, NULL);
1777 }
1778
1779 /*
1780 * Check whether the separate key cache entries
1781 * are required to handle both tx+rx MIC keys.
1782 * With split mic keys the number of stations is limited
1783 * to 27 otherwise 59.
1784 */
1785 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1786 ATH9K_CIPHER_TKIP, NULL)
1787 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1788 ATH9K_CIPHER_MIC, NULL)
1789 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1790 0, NULL))
1791 sc->splitmic = 1;
1792
1793 /* turn on mcast key search if possible */
1794 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1795 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1796 1, NULL);
1797
1798 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1799
1800 /* 11n Capabilities */
1801 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1802 sc->sc_flags |= SC_OP_TXAGGR;
1803 sc->sc_flags |= SC_OP_RXAGGR;
1804 }
1805
1806 common->tx_chainmask = ah->caps.tx_chainmask;
1807 common->rx_chainmask = ah->caps.rx_chainmask;
1808
1809 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1810 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1811
1812 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1813 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1814
1815 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1816
1817 /* initialize beacon slots */
1818 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1819 sc->beacon.bslot[i] = NULL;
1820 sc->beacon.bslot_aphy[i] = NULL;
1821 }
1822
1823 /* setup channels and rates */
1824
1825 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1826 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1827 sc->rates[IEEE80211_BAND_2GHZ];
1828 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1829 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1830 ARRAY_SIZE(ath9k_2ghz_chantable);
1831
1832 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1833 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1834 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1835 sc->rates[IEEE80211_BAND_5GHZ];
1836 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1837 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1838 ARRAY_SIZE(ath9k_5ghz_chantable);
1839 }
1840
1841 switch (ah->btcoex_hw.scheme) {
1842 case ATH_BTCOEX_CFG_NONE:
1843 break;
1844 case ATH_BTCOEX_CFG_2WIRE:
1845 ath9k_hw_btcoex_init_2wire(ah);
1846 break;
1847 case ATH_BTCOEX_CFG_3WIRE:
1848 ath9k_hw_btcoex_init_3wire(ah);
1849 r = ath_init_btcoex_timer(sc);
1850 if (r)
1851 goto bad2;
1852 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1853 ath9k_hw_init_btcoex_hw(ah, qnum);
1854 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1855 break;
1856 default:
1857 WARN_ON(1);
1858 break;
1859 }
1860
1861 return 0;
1862 bad2:
1863 /* cleanup tx queues */
1864 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1865 if (ATH_TXQ_SETUP(sc, i))
1866 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1867
1868 bad_free_hw:
1869 ath9k_uninit_hw(sc);
1870 return r;
1871 }
1872
1873 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1874 {
1875 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1876 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1877 IEEE80211_HW_SIGNAL_DBM |
1878 IEEE80211_HW_AMPDU_AGGREGATION |
1879 IEEE80211_HW_SUPPORTS_PS |
1880 IEEE80211_HW_PS_NULLFUNC_STACK |
1881 IEEE80211_HW_SPECTRUM_MGMT;
1882
1883 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1884 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1885
1886 hw->wiphy->interface_modes =
1887 BIT(NL80211_IFTYPE_AP) |
1888 BIT(NL80211_IFTYPE_STATION) |
1889 BIT(NL80211_IFTYPE_ADHOC) |
1890 BIT(NL80211_IFTYPE_MESH_POINT);
1891
1892 hw->queues = 4;
1893 hw->max_rates = 4;
1894 hw->channel_change_time = 5000;
1895 hw->max_listen_interval = 10;
1896 /* Hardware supports 10 but we use 4 */
1897 hw->max_rate_tries = 4;
1898 hw->sta_data_size = sizeof(struct ath_node);
1899 hw->vif_data_size = sizeof(struct ath_vif);
1900
1901 hw->rate_control_algorithm = "ath9k_rate_control";
1902
1903 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1904 &sc->sbands[IEEE80211_BAND_2GHZ];
1905 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1906 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1907 &sc->sbands[IEEE80211_BAND_5GHZ];
1908 }
1909
1910 /* Device driver core initialization */
1911 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1912 const struct ath_bus_ops *bus_ops)
1913 {
1914 struct ieee80211_hw *hw = sc->hw;
1915 struct ath_common *common;
1916 struct ath_hw *ah;
1917 int error = 0, i;
1918 struct ath_regulatory *reg;
1919
1920 dev_dbg(sc->dev, "Attach ATH hw\n");
1921
1922 error = ath_init_softc(devid, sc, subsysid, bus_ops);
1923 if (error != 0)
1924 return error;
1925
1926 ah = sc->sc_ah;
1927 common = ath9k_hw_common(ah);
1928
1929 /* get mac address from hardware and set in mac80211 */
1930
1931 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1932
1933 ath_set_hw_capab(sc, hw);
1934
1935 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1936 ath9k_reg_notifier);
1937 if (error)
1938 return error;
1939
1940 reg = &common->regulatory;
1941
1942 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1943 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1944 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1945 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1946 }
1947
1948 /* initialize tx/rx engine */
1949 error = ath_tx_init(sc, ATH_TXBUF);
1950 if (error != 0)
1951 goto error_attach;
1952
1953 error = ath_rx_init(sc, ATH_RXBUF);
1954 if (error != 0)
1955 goto error_attach;
1956
1957 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1958 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1959 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1960
1961 error = ieee80211_register_hw(hw);
1962
1963 if (!ath_is_world_regd(reg)) {
1964 error = regulatory_hint(hw->wiphy, reg->alpha2);
1965 if (error)
1966 goto error_attach;
1967 }
1968
1969 /* Initialize LED control */
1970 ath_init_leds(sc);
1971
1972 ath_start_rfkill_poll(sc);
1973
1974 return 0;
1975
1976 error_attach:
1977 /* cleanup tx queues */
1978 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1979 if (ATH_TXQ_SETUP(sc, i))
1980 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1981
1982 ath9k_uninit_hw(sc);
1983
1984 return error;
1985 }
1986
1987 int ath_reset(struct ath_softc *sc, bool retry_tx)
1988 {
1989 struct ath_hw *ah = sc->sc_ah;
1990 struct ath_common *common = ath9k_hw_common(ah);
1991 struct ieee80211_hw *hw = sc->hw;
1992 int r;
1993
1994 ath9k_hw_set_interrupts(ah, 0);
1995 ath_drain_all_txq(sc, retry_tx);
1996 ath_stoprecv(sc);
1997 ath_flushrecv(sc);
1998
1999 spin_lock_bh(&sc->sc_resetlock);
2000 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
2001 if (r)
2002 ath_print(common, ATH_DBG_FATAL,
2003 "Unable to reset hardware; reset status %d\n", r);
2004 spin_unlock_bh(&sc->sc_resetlock);
2005
2006 if (ath_startrecv(sc) != 0)
2007 ath_print(common, ATH_DBG_FATAL,
2008 "Unable to start recv logic\n");
2009
2010 /*
2011 * We may be doing a reset in response to a request
2012 * that changes the channel so update any state that
2013 * might change as a result.
2014 */
2015 ath_cache_conf_rate(sc, &hw->conf);
2016
2017 ath_update_txpow(sc);
2018
2019 if (sc->sc_flags & SC_OP_BEACONS)
2020 ath_beacon_config(sc, NULL); /* restart beacons */
2021
2022 ath9k_hw_set_interrupts(ah, sc->imask);
2023
2024 if (retry_tx) {
2025 int i;
2026 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2027 if (ATH_TXQ_SETUP(sc, i)) {
2028 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2029 ath_txq_schedule(sc, &sc->tx.txq[i]);
2030 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2031 }
2032 }
2033 }
2034
2035 return r;
2036 }
2037
2038 /*
2039 * This function will allocate both the DMA descriptor structure, and the
2040 * buffers it contains. These are used to contain the descriptors used
2041 * by the system.
2042 */
2043 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2044 struct list_head *head, const char *name,
2045 int nbuf, int ndesc)
2046 {
2047 #define DS2PHYS(_dd, _ds) \
2048 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2049 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2050 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2051 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2052 struct ath_desc *ds;
2053 struct ath_buf *bf;
2054 int i, bsize, error;
2055
2056 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2057 name, nbuf, ndesc);
2058
2059 INIT_LIST_HEAD(head);
2060 /* ath_desc must be a multiple of DWORDs */
2061 if ((sizeof(struct ath_desc) % 4) != 0) {
2062 ath_print(common, ATH_DBG_FATAL,
2063 "ath_desc not DWORD aligned\n");
2064 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2065 error = -ENOMEM;
2066 goto fail;
2067 }
2068
2069 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2070
2071 /*
2072 * Need additional DMA memory because we can't use
2073 * descriptors that cross the 4K page boundary. Assume
2074 * one skipped descriptor per 4K page.
2075 */
2076 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2077 u32 ndesc_skipped =
2078 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2079 u32 dma_len;
2080
2081 while (ndesc_skipped) {
2082 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2083 dd->dd_desc_len += dma_len;
2084
2085 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2086 };
2087 }
2088
2089 /* allocate descriptors */
2090 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2091 &dd->dd_desc_paddr, GFP_KERNEL);
2092 if (dd->dd_desc == NULL) {
2093 error = -ENOMEM;
2094 goto fail;
2095 }
2096 ds = dd->dd_desc;
2097 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2098 name, ds, (u32) dd->dd_desc_len,
2099 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2100
2101 /* allocate buffers */
2102 bsize = sizeof(struct ath_buf) * nbuf;
2103 bf = kzalloc(bsize, GFP_KERNEL);
2104 if (bf == NULL) {
2105 error = -ENOMEM;
2106 goto fail2;
2107 }
2108 dd->dd_bufptr = bf;
2109
2110 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2111 bf->bf_desc = ds;
2112 bf->bf_daddr = DS2PHYS(dd, ds);
2113
2114 if (!(sc->sc_ah->caps.hw_caps &
2115 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2116 /*
2117 * Skip descriptor addresses which can cause 4KB
2118 * boundary crossing (addr + length) with a 32 dword
2119 * descriptor fetch.
2120 */
2121 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2122 BUG_ON((caddr_t) bf->bf_desc >=
2123 ((caddr_t) dd->dd_desc +
2124 dd->dd_desc_len));
2125
2126 ds += ndesc;
2127 bf->bf_desc = ds;
2128 bf->bf_daddr = DS2PHYS(dd, ds);
2129 }
2130 }
2131 list_add_tail(&bf->list, head);
2132 }
2133 return 0;
2134 fail2:
2135 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2136 dd->dd_desc_paddr);
2137 fail:
2138 memset(dd, 0, sizeof(*dd));
2139 return error;
2140 #undef ATH_DESC_4KB_BOUND_CHECK
2141 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2142 #undef DS2PHYS
2143 }
2144
2145 void ath_descdma_cleanup(struct ath_softc *sc,
2146 struct ath_descdma *dd,
2147 struct list_head *head)
2148 {
2149 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2150 dd->dd_desc_paddr);
2151
2152 INIT_LIST_HEAD(head);
2153 kfree(dd->dd_bufptr);
2154 memset(dd, 0, sizeof(*dd));
2155 }
2156
2157 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2158 {
2159 int qnum;
2160
2161 switch (queue) {
2162 case 0:
2163 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2164 break;
2165 case 1:
2166 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2167 break;
2168 case 2:
2169 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2170 break;
2171 case 3:
2172 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2173 break;
2174 default:
2175 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2176 break;
2177 }
2178
2179 return qnum;
2180 }
2181
2182 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2183 {
2184 int qnum;
2185
2186 switch (queue) {
2187 case ATH9K_WME_AC_VO:
2188 qnum = 0;
2189 break;
2190 case ATH9K_WME_AC_VI:
2191 qnum = 1;
2192 break;
2193 case ATH9K_WME_AC_BE:
2194 qnum = 2;
2195 break;
2196 case ATH9K_WME_AC_BK:
2197 qnum = 3;
2198 break;
2199 default:
2200 qnum = -1;
2201 break;
2202 }
2203
2204 return qnum;
2205 }
2206
2207 /* XXX: Remove me once we don't depend on ath9k_channel for all
2208 * this redundant data */
2209 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2210 struct ath9k_channel *ichan)
2211 {
2212 struct ieee80211_channel *chan = hw->conf.channel;
2213 struct ieee80211_conf *conf = &hw->conf;
2214
2215 ichan->channel = chan->center_freq;
2216 ichan->chan = chan;
2217
2218 if (chan->band == IEEE80211_BAND_2GHZ) {
2219 ichan->chanmode = CHANNEL_G;
2220 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2221 } else {
2222 ichan->chanmode = CHANNEL_A;
2223 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2224 }
2225
2226 if (conf_is_ht(conf))
2227 ichan->chanmode = ath_get_extchanmode(sc, chan,
2228 conf->channel_type);
2229 }
2230
2231 /**********************/
2232 /* mac80211 callbacks */
2233 /**********************/
2234
2235 /*
2236 * (Re)start btcoex timers
2237 */
2238 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2239 {
2240 struct ath_btcoex *btcoex = &sc->btcoex;
2241 struct ath_hw *ah = sc->sc_ah;
2242
2243 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2244 "Starting btcoex timers");
2245
2246 /* make sure duty cycle timer is also stopped when resuming */
2247 if (btcoex->hw_timer_enabled)
2248 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2249
2250 btcoex->bt_priority_cnt = 0;
2251 btcoex->bt_priority_time = jiffies;
2252 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2253
2254 mod_timer(&btcoex->period_timer, jiffies);
2255 }
2256
2257 static int ath9k_start(struct ieee80211_hw *hw)
2258 {
2259 struct ath_wiphy *aphy = hw->priv;
2260 struct ath_softc *sc = aphy->sc;
2261 struct ath_hw *ah = sc->sc_ah;
2262 struct ath_common *common = ath9k_hw_common(ah);
2263 struct ieee80211_channel *curchan = hw->conf.channel;
2264 struct ath9k_channel *init_channel;
2265 int r;
2266
2267 ath_print(common, ATH_DBG_CONFIG,
2268 "Starting driver with initial channel: %d MHz\n",
2269 curchan->center_freq);
2270
2271 mutex_lock(&sc->mutex);
2272
2273 if (ath9k_wiphy_started(sc)) {
2274 if (sc->chan_idx == curchan->hw_value) {
2275 /*
2276 * Already on the operational channel, the new wiphy
2277 * can be marked active.
2278 */
2279 aphy->state = ATH_WIPHY_ACTIVE;
2280 ieee80211_wake_queues(hw);
2281 } else {
2282 /*
2283 * Another wiphy is on another channel, start the new
2284 * wiphy in paused state.
2285 */
2286 aphy->state = ATH_WIPHY_PAUSED;
2287 ieee80211_stop_queues(hw);
2288 }
2289 mutex_unlock(&sc->mutex);
2290 return 0;
2291 }
2292 aphy->state = ATH_WIPHY_ACTIVE;
2293
2294 /* setup initial channel */
2295
2296 sc->chan_idx = curchan->hw_value;
2297
2298 init_channel = ath_get_curchannel(sc, hw);
2299
2300 /* Reset SERDES registers */
2301 ath9k_hw_configpcipowersave(ah, 0, 0);
2302
2303 /*
2304 * The basic interface to setting the hardware in a good
2305 * state is ``reset''. On return the hardware is known to
2306 * be powered up and with interrupts disabled. This must
2307 * be followed by initialization of the appropriate bits
2308 * and then setup of the interrupt mask.
2309 */
2310 spin_lock_bh(&sc->sc_resetlock);
2311 r = ath9k_hw_reset(ah, init_channel, false);
2312 if (r) {
2313 ath_print(common, ATH_DBG_FATAL,
2314 "Unable to reset hardware; reset status %d "
2315 "(freq %u MHz)\n", r,
2316 curchan->center_freq);
2317 spin_unlock_bh(&sc->sc_resetlock);
2318 goto mutex_unlock;
2319 }
2320 spin_unlock_bh(&sc->sc_resetlock);
2321
2322 /*
2323 * This is needed only to setup initial state
2324 * but it's best done after a reset.
2325 */
2326 ath_update_txpow(sc);
2327
2328 /*
2329 * Setup the hardware after reset:
2330 * The receive engine is set going.
2331 * Frame transmit is handled entirely
2332 * in the frame output path; there's nothing to do
2333 * here except setup the interrupt mask.
2334 */
2335 if (ath_startrecv(sc) != 0) {
2336 ath_print(common, ATH_DBG_FATAL,
2337 "Unable to start recv logic\n");
2338 r = -EIO;
2339 goto mutex_unlock;
2340 }
2341
2342 /* Setup our intr mask. */
2343 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2344 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2345 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2346
2347 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2348 sc->imask |= ATH9K_INT_GTT;
2349
2350 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2351 sc->imask |= ATH9K_INT_CST;
2352
2353 ath_cache_conf_rate(sc, &hw->conf);
2354
2355 sc->sc_flags &= ~SC_OP_INVALID;
2356
2357 /* Disable BMISS interrupt when we're not associated */
2358 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2359 ath9k_hw_set_interrupts(ah, sc->imask);
2360
2361 ieee80211_wake_queues(hw);
2362
2363 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2364
2365 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2366 !ah->btcoex_hw.enabled) {
2367 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2368 AR_STOMP_LOW_WLAN_WGHT);
2369 ath9k_hw_btcoex_enable(ah);
2370
2371 if (common->bus_ops->bt_coex_prep)
2372 common->bus_ops->bt_coex_prep(common);
2373 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2374 ath9k_btcoex_timer_resume(sc);
2375 }
2376
2377 mutex_unlock:
2378 mutex_unlock(&sc->mutex);
2379
2380 return r;
2381 }
2382
2383 static int ath9k_tx(struct ieee80211_hw *hw,
2384 struct sk_buff *skb)
2385 {
2386 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2387 struct ath_wiphy *aphy = hw->priv;
2388 struct ath_softc *sc = aphy->sc;
2389 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2390 struct ath_tx_control txctl;
2391 int hdrlen, padsize;
2392
2393 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2394 ath_print(common, ATH_DBG_XMIT,
2395 "ath9k: %s: TX in unexpected wiphy state "
2396 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2397 goto exit;
2398 }
2399
2400 if (sc->ps_enabled) {
2401 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2402 /*
2403 * mac80211 does not set PM field for normal data frames, so we
2404 * need to update that based on the current PS mode.
2405 */
2406 if (ieee80211_is_data(hdr->frame_control) &&
2407 !ieee80211_is_nullfunc(hdr->frame_control) &&
2408 !ieee80211_has_pm(hdr->frame_control)) {
2409 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2410 "while in PS mode\n");
2411 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2412 }
2413 }
2414
2415 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2416 /*
2417 * We are using PS-Poll and mac80211 can request TX while in
2418 * power save mode. Need to wake up hardware for the TX to be
2419 * completed and if needed, also for RX of buffered frames.
2420 */
2421 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2422 ath9k_ps_wakeup(sc);
2423 ath9k_hw_setrxabort(sc->sc_ah, 0);
2424 if (ieee80211_is_pspoll(hdr->frame_control)) {
2425 ath_print(common, ATH_DBG_PS,
2426 "Sending PS-Poll to pick a buffered frame\n");
2427 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2428 } else {
2429 ath_print(common, ATH_DBG_PS,
2430 "Wake up to complete TX\n");
2431 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2432 }
2433 /*
2434 * The actual restore operation will happen only after
2435 * the sc_flags bit is cleared. We are just dropping
2436 * the ps_usecount here.
2437 */
2438 ath9k_ps_restore(sc);
2439 }
2440
2441 memset(&txctl, 0, sizeof(struct ath_tx_control));
2442
2443 /*
2444 * As a temporary workaround, assign seq# here; this will likely need
2445 * to be cleaned up to work better with Beacon transmission and virtual
2446 * BSSes.
2447 */
2448 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2449 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2450 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2451 sc->tx.seq_no += 0x10;
2452 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2453 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2454 }
2455
2456 /* Add the padding after the header if this is not already done */
2457 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2458 if (hdrlen & 3) {
2459 padsize = hdrlen % 4;
2460 if (skb_headroom(skb) < padsize)
2461 return -1;
2462 skb_push(skb, padsize);
2463 memmove(skb->data, skb->data + padsize, hdrlen);
2464 }
2465
2466 /* Check if a tx queue is available */
2467
2468 txctl.txq = ath_test_get_txq(sc, skb);
2469 if (!txctl.txq)
2470 goto exit;
2471
2472 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2473
2474 if (ath_tx_start(hw, skb, &txctl) != 0) {
2475 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2476 goto exit;
2477 }
2478
2479 return 0;
2480 exit:
2481 dev_kfree_skb_any(skb);
2482 return 0;
2483 }
2484
2485 /*
2486 * Pause btcoex timer and bt duty cycle timer
2487 */
2488 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2489 {
2490 struct ath_btcoex *btcoex = &sc->btcoex;
2491 struct ath_hw *ah = sc->sc_ah;
2492
2493 del_timer_sync(&btcoex->period_timer);
2494
2495 if (btcoex->hw_timer_enabled)
2496 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2497
2498 btcoex->hw_timer_enabled = false;
2499 }
2500
2501 static void ath9k_stop(struct ieee80211_hw *hw)
2502 {
2503 struct ath_wiphy *aphy = hw->priv;
2504 struct ath_softc *sc = aphy->sc;
2505 struct ath_hw *ah = sc->sc_ah;
2506 struct ath_common *common = ath9k_hw_common(ah);
2507
2508 mutex_lock(&sc->mutex);
2509
2510 aphy->state = ATH_WIPHY_INACTIVE;
2511
2512 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2513 cancel_delayed_work_sync(&sc->tx_complete_work);
2514
2515 if (!sc->num_sec_wiphy) {
2516 cancel_delayed_work_sync(&sc->wiphy_work);
2517 cancel_work_sync(&sc->chan_work);
2518 }
2519
2520 if (sc->sc_flags & SC_OP_INVALID) {
2521 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2522 mutex_unlock(&sc->mutex);
2523 return;
2524 }
2525
2526 if (ath9k_wiphy_started(sc)) {
2527 mutex_unlock(&sc->mutex);
2528 return; /* another wiphy still in use */
2529 }
2530
2531 if (ah->btcoex_hw.enabled) {
2532 ath9k_hw_btcoex_disable(ah);
2533 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2534 ath9k_btcoex_timer_pause(sc);
2535 }
2536
2537 /* make sure h/w will not generate any interrupt
2538 * before setting the invalid flag. */
2539 ath9k_hw_set_interrupts(ah, 0);
2540
2541 if (!(sc->sc_flags & SC_OP_INVALID)) {
2542 ath_drain_all_txq(sc, false);
2543 ath_stoprecv(sc);
2544 ath9k_hw_phy_disable(ah);
2545 } else
2546 sc->rx.rxlink = NULL;
2547
2548 /* disable HAL and put h/w to sleep */
2549 ath9k_hw_disable(ah);
2550 ath9k_hw_configpcipowersave(ah, 1, 1);
2551 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2552
2553 sc->sc_flags |= SC_OP_INVALID;
2554
2555 mutex_unlock(&sc->mutex);
2556
2557 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2558 }
2559
2560 static int ath9k_add_interface(struct ieee80211_hw *hw,
2561 struct ieee80211_if_init_conf *conf)
2562 {
2563 struct ath_wiphy *aphy = hw->priv;
2564 struct ath_softc *sc = aphy->sc;
2565 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2566 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2567 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2568 int ret = 0;
2569
2570 mutex_lock(&sc->mutex);
2571
2572 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2573 sc->nvifs > 0) {
2574 ret = -ENOBUFS;
2575 goto out;
2576 }
2577
2578 switch (conf->type) {
2579 case NL80211_IFTYPE_STATION:
2580 ic_opmode = NL80211_IFTYPE_STATION;
2581 break;
2582 case NL80211_IFTYPE_ADHOC:
2583 case NL80211_IFTYPE_AP:
2584 case NL80211_IFTYPE_MESH_POINT:
2585 if (sc->nbcnvifs >= ATH_BCBUF) {
2586 ret = -ENOBUFS;
2587 goto out;
2588 }
2589 ic_opmode = conf->type;
2590 break;
2591 default:
2592 ath_print(common, ATH_DBG_FATAL,
2593 "Interface type %d not yet supported\n", conf->type);
2594 ret = -EOPNOTSUPP;
2595 goto out;
2596 }
2597
2598 ath_print(common, ATH_DBG_CONFIG,
2599 "Attach a VIF of type: %d\n", ic_opmode);
2600
2601 /* Set the VIF opmode */
2602 avp->av_opmode = ic_opmode;
2603 avp->av_bslot = -1;
2604
2605 sc->nvifs++;
2606
2607 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2608 ath9k_set_bssid_mask(hw);
2609
2610 if (sc->nvifs > 1)
2611 goto out; /* skip global settings for secondary vif */
2612
2613 if (ic_opmode == NL80211_IFTYPE_AP) {
2614 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2615 sc->sc_flags |= SC_OP_TSF_RESET;
2616 }
2617
2618 /* Set the device opmode */
2619 sc->sc_ah->opmode = ic_opmode;
2620
2621 /*
2622 * Enable MIB interrupts when there are hardware phy counters.
2623 * Note we only do this (at the moment) for station mode.
2624 */
2625 if ((conf->type == NL80211_IFTYPE_STATION) ||
2626 (conf->type == NL80211_IFTYPE_ADHOC) ||
2627 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2628 sc->imask |= ATH9K_INT_MIB;
2629 sc->imask |= ATH9K_INT_TSFOOR;
2630 }
2631
2632 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2633
2634 if (conf->type == NL80211_IFTYPE_AP ||
2635 conf->type == NL80211_IFTYPE_ADHOC ||
2636 conf->type == NL80211_IFTYPE_MONITOR)
2637 ath_start_ani(sc);
2638
2639 out:
2640 mutex_unlock(&sc->mutex);
2641 return ret;
2642 }
2643
2644 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2645 struct ieee80211_if_init_conf *conf)
2646 {
2647 struct ath_wiphy *aphy = hw->priv;
2648 struct ath_softc *sc = aphy->sc;
2649 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2650 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2651 int i;
2652
2653 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2654
2655 mutex_lock(&sc->mutex);
2656
2657 /* Stop ANI */
2658 del_timer_sync(&sc->ani.timer);
2659
2660 /* Reclaim beacon resources */
2661 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2662 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2663 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2664 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2665 ath_beacon_return(sc, avp);
2666 }
2667
2668 sc->sc_flags &= ~SC_OP_BEACONS;
2669
2670 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2671 if (sc->beacon.bslot[i] == conf->vif) {
2672 printk(KERN_DEBUG "%s: vif had allocated beacon "
2673 "slot\n", __func__);
2674 sc->beacon.bslot[i] = NULL;
2675 sc->beacon.bslot_aphy[i] = NULL;
2676 }
2677 }
2678
2679 sc->nvifs--;
2680
2681 mutex_unlock(&sc->mutex);
2682 }
2683
2684 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2685 {
2686 struct ath_wiphy *aphy = hw->priv;
2687 struct ath_softc *sc = aphy->sc;
2688 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2689 struct ieee80211_conf *conf = &hw->conf;
2690 struct ath_hw *ah = sc->sc_ah;
2691 bool all_wiphys_idle = false, disable_radio = false;
2692
2693 mutex_lock(&sc->mutex);
2694
2695 /* Leave this as the first check */
2696 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2697
2698 spin_lock_bh(&sc->wiphy_lock);
2699 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2700 spin_unlock_bh(&sc->wiphy_lock);
2701
2702 if (conf->flags & IEEE80211_CONF_IDLE){
2703 if (all_wiphys_idle)
2704 disable_radio = true;
2705 }
2706 else if (all_wiphys_idle) {
2707 ath_radio_enable(sc);
2708 ath_print(common, ATH_DBG_CONFIG,
2709 "not-idle: enabling radio\n");
2710 }
2711 }
2712
2713 if (changed & IEEE80211_CONF_CHANGE_PS) {
2714 if (conf->flags & IEEE80211_CONF_PS) {
2715 if (!(ah->caps.hw_caps &
2716 ATH9K_HW_CAP_AUTOSLEEP)) {
2717 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2718 sc->imask |= ATH9K_INT_TIM_TIMER;
2719 ath9k_hw_set_interrupts(sc->sc_ah,
2720 sc->imask);
2721 }
2722 ath9k_hw_setrxabort(sc->sc_ah, 1);
2723 }
2724 sc->ps_enabled = true;
2725 } else {
2726 sc->ps_enabled = false;
2727 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2728 if (!(ah->caps.hw_caps &
2729 ATH9K_HW_CAP_AUTOSLEEP)) {
2730 ath9k_hw_setrxabort(sc->sc_ah, 0);
2731 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2732 SC_OP_WAIT_FOR_CAB |
2733 SC_OP_WAIT_FOR_PSPOLL_DATA |
2734 SC_OP_WAIT_FOR_TX_ACK);
2735 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2736 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2737 ath9k_hw_set_interrupts(sc->sc_ah,
2738 sc->imask);
2739 }
2740 }
2741 }
2742 }
2743
2744 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2745 struct ieee80211_channel *curchan = hw->conf.channel;
2746 int pos = curchan->hw_value;
2747
2748 aphy->chan_idx = pos;
2749 aphy->chan_is_ht = conf_is_ht(conf);
2750
2751 if (aphy->state == ATH_WIPHY_SCAN ||
2752 aphy->state == ATH_WIPHY_ACTIVE)
2753 ath9k_wiphy_pause_all_forced(sc, aphy);
2754 else {
2755 /*
2756 * Do not change operational channel based on a paused
2757 * wiphy changes.
2758 */
2759 goto skip_chan_change;
2760 }
2761
2762 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2763 curchan->center_freq);
2764
2765 /* XXX: remove me eventualy */
2766 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2767
2768 ath_update_chainmask(sc, conf_is_ht(conf));
2769
2770 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2771 ath_print(common, ATH_DBG_FATAL,
2772 "Unable to set channel\n");
2773 mutex_unlock(&sc->mutex);
2774 return -EINVAL;
2775 }
2776 }
2777
2778 skip_chan_change:
2779 if (changed & IEEE80211_CONF_CHANGE_POWER)
2780 sc->config.txpowlimit = 2 * conf->power_level;
2781
2782 if (disable_radio) {
2783 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2784 ath_radio_disable(sc);
2785 }
2786
2787 mutex_unlock(&sc->mutex);
2788
2789 return 0;
2790 }
2791
2792 #define SUPPORTED_FILTERS \
2793 (FIF_PROMISC_IN_BSS | \
2794 FIF_ALLMULTI | \
2795 FIF_CONTROL | \
2796 FIF_PSPOLL | \
2797 FIF_OTHER_BSS | \
2798 FIF_BCN_PRBRESP_PROMISC | \
2799 FIF_FCSFAIL)
2800
2801 /* FIXME: sc->sc_full_reset ? */
2802 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2803 unsigned int changed_flags,
2804 unsigned int *total_flags,
2805 u64 multicast)
2806 {
2807 struct ath_wiphy *aphy = hw->priv;
2808 struct ath_softc *sc = aphy->sc;
2809 u32 rfilt;
2810
2811 changed_flags &= SUPPORTED_FILTERS;
2812 *total_flags &= SUPPORTED_FILTERS;
2813
2814 sc->rx.rxfilter = *total_flags;
2815 ath9k_ps_wakeup(sc);
2816 rfilt = ath_calcrxfilter(sc);
2817 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2818 ath9k_ps_restore(sc);
2819
2820 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2821 "Set HW RX filter: 0x%x\n", rfilt);
2822 }
2823
2824 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2825 struct ieee80211_vif *vif,
2826 enum sta_notify_cmd cmd,
2827 struct ieee80211_sta *sta)
2828 {
2829 struct ath_wiphy *aphy = hw->priv;
2830 struct ath_softc *sc = aphy->sc;
2831
2832 switch (cmd) {
2833 case STA_NOTIFY_ADD:
2834 ath_node_attach(sc, sta);
2835 break;
2836 case STA_NOTIFY_REMOVE:
2837 ath_node_detach(sc, sta);
2838 break;
2839 default:
2840 break;
2841 }
2842 }
2843
2844 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2845 const struct ieee80211_tx_queue_params *params)
2846 {
2847 struct ath_wiphy *aphy = hw->priv;
2848 struct ath_softc *sc = aphy->sc;
2849 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2850 struct ath9k_tx_queue_info qi;
2851 int ret = 0, qnum;
2852
2853 if (queue >= WME_NUM_AC)
2854 return 0;
2855
2856 mutex_lock(&sc->mutex);
2857
2858 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2859
2860 qi.tqi_aifs = params->aifs;
2861 qi.tqi_cwmin = params->cw_min;
2862 qi.tqi_cwmax = params->cw_max;
2863 qi.tqi_burstTime = params->txop;
2864 qnum = ath_get_hal_qnum(queue, sc);
2865
2866 ath_print(common, ATH_DBG_CONFIG,
2867 "Configure tx [queue/halq] [%d/%d], "
2868 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2869 queue, qnum, params->aifs, params->cw_min,
2870 params->cw_max, params->txop);
2871
2872 ret = ath_txq_update(sc, qnum, &qi);
2873 if (ret)
2874 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2875
2876 mutex_unlock(&sc->mutex);
2877
2878 return ret;
2879 }
2880
2881 static int ath9k_set_key(struct ieee80211_hw *hw,
2882 enum set_key_cmd cmd,
2883 struct ieee80211_vif *vif,
2884 struct ieee80211_sta *sta,
2885 struct ieee80211_key_conf *key)
2886 {
2887 struct ath_wiphy *aphy = hw->priv;
2888 struct ath_softc *sc = aphy->sc;
2889 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2890 int ret = 0;
2891
2892 if (modparam_nohwcrypt)
2893 return -ENOSPC;
2894
2895 mutex_lock(&sc->mutex);
2896 ath9k_ps_wakeup(sc);
2897 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2898
2899 switch (cmd) {
2900 case SET_KEY:
2901 ret = ath_key_config(sc, vif, sta, key);
2902 if (ret >= 0) {
2903 key->hw_key_idx = ret;
2904 /* push IV and Michael MIC generation to stack */
2905 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2906 if (key->alg == ALG_TKIP)
2907 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2908 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2909 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2910 ret = 0;
2911 }
2912 break;
2913 case DISABLE_KEY:
2914 ath_key_delete(sc, key);
2915 break;
2916 default:
2917 ret = -EINVAL;
2918 }
2919
2920 ath9k_ps_restore(sc);
2921 mutex_unlock(&sc->mutex);
2922
2923 return ret;
2924 }
2925
2926 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2927 struct ieee80211_vif *vif,
2928 struct ieee80211_bss_conf *bss_conf,
2929 u32 changed)
2930 {
2931 struct ath_wiphy *aphy = hw->priv;
2932 struct ath_softc *sc = aphy->sc;
2933 struct ath_hw *ah = sc->sc_ah;
2934 struct ath_common *common = ath9k_hw_common(ah);
2935 struct ath_vif *avp = (void *)vif->drv_priv;
2936 u32 rfilt = 0;
2937 int error, i;
2938
2939 mutex_lock(&sc->mutex);
2940
2941 /*
2942 * TODO: Need to decide which hw opmode to use for
2943 * multi-interface cases
2944 * XXX: This belongs into add_interface!
2945 */
2946 if (vif->type == NL80211_IFTYPE_AP &&
2947 ah->opmode != NL80211_IFTYPE_AP) {
2948 ah->opmode = NL80211_IFTYPE_STATION;
2949 ath9k_hw_setopmode(ah);
2950 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2951 common->curaid = 0;
2952 ath9k_hw_write_associd(ah);
2953 /* Request full reset to get hw opmode changed properly */
2954 sc->sc_flags |= SC_OP_FULL_RESET;
2955 }
2956
2957 if ((changed & BSS_CHANGED_BSSID) &&
2958 !is_zero_ether_addr(bss_conf->bssid)) {
2959 switch (vif->type) {
2960 case NL80211_IFTYPE_STATION:
2961 case NL80211_IFTYPE_ADHOC:
2962 case NL80211_IFTYPE_MESH_POINT:
2963 /* Set BSSID */
2964 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2965 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2966 common->curaid = 0;
2967 ath9k_hw_write_associd(ah);
2968
2969 /* Set aggregation protection mode parameters */
2970 sc->config.ath_aggr_prot = 0;
2971
2972 ath_print(common, ATH_DBG_CONFIG,
2973 "RX filter 0x%x bssid %pM aid 0x%x\n",
2974 rfilt, common->curbssid, common->curaid);
2975
2976 /* need to reconfigure the beacon */
2977 sc->sc_flags &= ~SC_OP_BEACONS ;
2978
2979 break;
2980 default:
2981 break;
2982 }
2983 }
2984
2985 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2986 (vif->type == NL80211_IFTYPE_AP) ||
2987 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2988 if ((changed & BSS_CHANGED_BEACON) ||
2989 (changed & BSS_CHANGED_BEACON_ENABLED &&
2990 bss_conf->enable_beacon)) {
2991 /*
2992 * Allocate and setup the beacon frame.
2993 *
2994 * Stop any previous beacon DMA. This may be
2995 * necessary, for example, when an ibss merge
2996 * causes reconfiguration; we may be called
2997 * with beacon transmission active.
2998 */
2999 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
3000
3001 error = ath_beacon_alloc(aphy, vif);
3002 if (!error)
3003 ath_beacon_config(sc, vif);
3004 }
3005 }
3006
3007 /* Check for WLAN_CAPABILITY_PRIVACY ? */
3008 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
3009 for (i = 0; i < IEEE80211_WEP_NKID; i++)
3010 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
3011 ath9k_hw_keysetmac(sc->sc_ah,
3012 (u16)i,
3013 common->curbssid);
3014 }
3015
3016 /* Only legacy IBSS for now */
3017 if (vif->type == NL80211_IFTYPE_ADHOC)
3018 ath_update_chainmask(sc, 0);
3019
3020 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3021 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3022 bss_conf->use_short_preamble);
3023 if (bss_conf->use_short_preamble)
3024 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3025 else
3026 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3027 }
3028
3029 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
3030 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3031 bss_conf->use_cts_prot);
3032 if (bss_conf->use_cts_prot &&
3033 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3034 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3035 else
3036 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3037 }
3038
3039 if (changed & BSS_CHANGED_ASSOC) {
3040 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3041 bss_conf->assoc);
3042 ath9k_bss_assoc_info(sc, vif, bss_conf);
3043 }
3044
3045 /*
3046 * The HW TSF has to be reset when the beacon interval changes.
3047 * We set the flag here, and ath_beacon_config_ap() would take this
3048 * into account when it gets called through the subsequent
3049 * config_interface() call - with IFCC_BEACON in the changed field.
3050 */
3051
3052 if (changed & BSS_CHANGED_BEACON_INT) {
3053 sc->sc_flags |= SC_OP_TSF_RESET;
3054 sc->beacon_interval = bss_conf->beacon_int;
3055 }
3056
3057 mutex_unlock(&sc->mutex);
3058 }
3059
3060 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3061 {
3062 u64 tsf;
3063 struct ath_wiphy *aphy = hw->priv;
3064 struct ath_softc *sc = aphy->sc;
3065
3066 mutex_lock(&sc->mutex);
3067 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3068 mutex_unlock(&sc->mutex);
3069
3070 return tsf;
3071 }
3072
3073 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3074 {
3075 struct ath_wiphy *aphy = hw->priv;
3076 struct ath_softc *sc = aphy->sc;
3077
3078 mutex_lock(&sc->mutex);
3079 ath9k_hw_settsf64(sc->sc_ah, tsf);
3080 mutex_unlock(&sc->mutex);
3081 }
3082
3083 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3084 {
3085 struct ath_wiphy *aphy = hw->priv;
3086 struct ath_softc *sc = aphy->sc;
3087
3088 mutex_lock(&sc->mutex);
3089
3090 ath9k_ps_wakeup(sc);
3091 ath9k_hw_reset_tsf(sc->sc_ah);
3092 ath9k_ps_restore(sc);
3093
3094 mutex_unlock(&sc->mutex);
3095 }
3096
3097 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3098 enum ieee80211_ampdu_mlme_action action,
3099 struct ieee80211_sta *sta,
3100 u16 tid, u16 *ssn)
3101 {
3102 struct ath_wiphy *aphy = hw->priv;
3103 struct ath_softc *sc = aphy->sc;
3104 int ret = 0;
3105
3106 switch (action) {
3107 case IEEE80211_AMPDU_RX_START:
3108 if (!(sc->sc_flags & SC_OP_RXAGGR))
3109 ret = -ENOTSUPP;
3110 break;
3111 case IEEE80211_AMPDU_RX_STOP:
3112 break;
3113 case IEEE80211_AMPDU_TX_START:
3114 ath_tx_aggr_start(sc, sta, tid, ssn);
3115 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3116 break;
3117 case IEEE80211_AMPDU_TX_STOP:
3118 ath_tx_aggr_stop(sc, sta, tid);
3119 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3120 break;
3121 case IEEE80211_AMPDU_TX_OPERATIONAL:
3122 ath_tx_aggr_resume(sc, sta, tid);
3123 break;
3124 default:
3125 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3126 "Unknown AMPDU action\n");
3127 }
3128
3129 return ret;
3130 }
3131
3132 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3133 {
3134 struct ath_wiphy *aphy = hw->priv;
3135 struct ath_softc *sc = aphy->sc;
3136
3137 mutex_lock(&sc->mutex);
3138 if (ath9k_wiphy_scanning(sc)) {
3139 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3140 "same time\n");
3141 /*
3142 * Do not allow the concurrent scanning state for now. This
3143 * could be improved with scanning control moved into ath9k.
3144 */
3145 mutex_unlock(&sc->mutex);
3146 return;
3147 }
3148
3149 aphy->state = ATH_WIPHY_SCAN;
3150 ath9k_wiphy_pause_all_forced(sc, aphy);
3151
3152 spin_lock_bh(&sc->ani_lock);
3153 sc->sc_flags |= SC_OP_SCANNING;
3154 spin_unlock_bh(&sc->ani_lock);
3155 mutex_unlock(&sc->mutex);
3156 }
3157
3158 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3159 {
3160 struct ath_wiphy *aphy = hw->priv;
3161 struct ath_softc *sc = aphy->sc;
3162
3163 mutex_lock(&sc->mutex);
3164 spin_lock_bh(&sc->ani_lock);
3165 aphy->state = ATH_WIPHY_ACTIVE;
3166 sc->sc_flags &= ~SC_OP_SCANNING;
3167 sc->sc_flags |= SC_OP_FULL_RESET;
3168 spin_unlock_bh(&sc->ani_lock);
3169 ath_beacon_config(sc, NULL);
3170 mutex_unlock(&sc->mutex);
3171 }
3172
3173 struct ieee80211_ops ath9k_ops = {
3174 .tx = ath9k_tx,
3175 .start = ath9k_start,
3176 .stop = ath9k_stop,
3177 .add_interface = ath9k_add_interface,
3178 .remove_interface = ath9k_remove_interface,
3179 .config = ath9k_config,
3180 .configure_filter = ath9k_configure_filter,
3181 .sta_notify = ath9k_sta_notify,
3182 .conf_tx = ath9k_conf_tx,
3183 .bss_info_changed = ath9k_bss_info_changed,
3184 .set_key = ath9k_set_key,
3185 .get_tsf = ath9k_get_tsf,
3186 .set_tsf = ath9k_set_tsf,
3187 .reset_tsf = ath9k_reset_tsf,
3188 .ampdu_action = ath9k_ampdu_action,
3189 .sw_scan_start = ath9k_sw_scan_start,
3190 .sw_scan_complete = ath9k_sw_scan_complete,
3191 .rfkill_poll = ath9k_rfkill_poll_state,
3192 };
3193
3194 static struct {
3195 u32 version;
3196 const char * name;
3197 } ath_mac_bb_names[] = {
3198 { AR_SREV_VERSION_5416_PCI, "5416" },
3199 { AR_SREV_VERSION_5416_PCIE, "5418" },
3200 { AR_SREV_VERSION_9100, "9100" },
3201 { AR_SREV_VERSION_9160, "9160" },
3202 { AR_SREV_VERSION_9280, "9280" },
3203 { AR_SREV_VERSION_9285, "9285" },
3204 { AR_SREV_VERSION_9287, "9287" }
3205 };
3206
3207 static struct {
3208 u16 version;
3209 const char * name;
3210 } ath_rf_names[] = {
3211 { 0, "5133" },
3212 { AR_RAD5133_SREV_MAJOR, "5133" },
3213 { AR_RAD5122_SREV_MAJOR, "5122" },
3214 { AR_RAD2133_SREV_MAJOR, "2133" },
3215 { AR_RAD2122_SREV_MAJOR, "2122" }
3216 };
3217
3218 /*
3219 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3220 */
3221 const char *
3222 ath_mac_bb_name(u32 mac_bb_version)
3223 {
3224 int i;
3225
3226 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3227 if (ath_mac_bb_names[i].version == mac_bb_version) {
3228 return ath_mac_bb_names[i].name;
3229 }
3230 }
3231
3232 return "????";
3233 }
3234
3235 /*
3236 * Return the RF name. "????" is returned if the RF is unknown.
3237 */
3238 const char *
3239 ath_rf_name(u16 rf_version)
3240 {
3241 int i;
3242
3243 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3244 if (ath_rf_names[i].version == rf_version) {
3245 return ath_rf_names[i].name;
3246 }
3247 }
3248
3249 return "????";
3250 }
3251
3252 static int __init ath9k_init(void)
3253 {
3254 int error;
3255
3256 /* Register rate control algorithm */
3257 error = ath_rate_control_register();
3258 if (error != 0) {
3259 printk(KERN_ERR
3260 "ath9k: Unable to register rate control "
3261 "algorithm: %d\n",
3262 error);
3263 goto err_out;
3264 }
3265
3266 error = ath9k_debug_create_root();
3267 if (error) {
3268 printk(KERN_ERR
3269 "ath9k: Unable to create debugfs root: %d\n",
3270 error);
3271 goto err_rate_unregister;
3272 }
3273
3274 error = ath_pci_init();
3275 if (error < 0) {
3276 printk(KERN_ERR
3277 "ath9k: No PCI devices found, driver not installed.\n");
3278 error = -ENODEV;
3279 goto err_remove_root;
3280 }
3281
3282 error = ath_ahb_init();
3283 if (error < 0) {
3284 error = -ENODEV;
3285 goto err_pci_exit;
3286 }
3287
3288 return 0;
3289
3290 err_pci_exit:
3291 ath_pci_exit();
3292
3293 err_remove_root:
3294 ath9k_debug_remove_root();
3295 err_rate_unregister:
3296 ath_rate_control_unregister();
3297 err_out:
3298 return error;
3299 }
3300 module_init(ath9k_init);
3301
3302 static void __exit ath9k_exit(void)
3303 {
3304 ath_ahb_exit();
3305 ath_pci_exit();
3306 ath9k_debug_remove_root();
3307 ath_rate_control_unregister();
3308 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3309 }
3310 module_exit(ath9k_exit);
mm of the moment repository