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mm-only debug patch...
[mmotm.git] / drivers / pci / probe.c
blob6d90246a4ed0fe0d6d296ca0ac1fe023fa94967c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
21
22
23 static int find_anything(struct device *dev, void *data)
24 {
25 return 1;
26 }
27
28 /*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33 int no_pci_devices(void)
34 {
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42 }
43 EXPORT_SYMBOL(no_pci_devices);
44
45 /*
46 * PCI Bus Class Devices
47 */
48 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
49 int type,
50 struct device_attribute *attr,
51 char *buf)
52 {
53 int ret;
54 const struct cpumask *cpumask;
55
56 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
57 ret = type?
58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
60 buf[ret++] = '\n';
61 buf[ret] = '\0';
62 return ret;
63 }
64
65 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
67 char *buf)
68 {
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
70 }
71
72 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
74 char *buf)
75 {
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
77 }
78
79 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
81
82 /*
83 * PCI Bus Class
84 */
85 static void release_pcibus_dev(struct device *dev)
86 {
87 struct pci_bus *pci_bus = to_pci_bus(dev);
88
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
91 kfree(pci_bus);
92 }
93
94 static struct class pcibus_class = {
95 .name = "pci_bus",
96 .dev_release = &release_pcibus_dev,
97 };
98
99 static int __init pcibus_class_init(void)
100 {
101 return class_register(&pcibus_class);
102 }
103 postcore_initcall(pcibus_class_init);
104
105 /*
106 * Translate the low bits of the PCI base
107 * to the resource type
108 */
109 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
110 {
111 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
112 return IORESOURCE_IO;
113
114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
115 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
116
117 return IORESOURCE_MEM;
118 }
119
120 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
121 {
122 u64 size = mask & maxbase; /* Find the significant bits */
123 if (!size)
124 return 0;
125
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size = (size & ~(size-1)) - 1;
129
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base == maxbase && ((base | size) & mask) != mask)
133 return 0;
134
135 return size;
136 }
137
138 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
139 {
140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
141 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
142 return pci_bar_io;
143 }
144
145 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
146
147 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
148 return pci_bar_mem64;
149 return pci_bar_mem32;
150 }
151
152 /**
153 * pci_read_base - read a PCI BAR
154 * @dev: the PCI device
155 * @type: type of the BAR
156 * @res: resource buffer to be filled in
157 * @pos: BAR position in the config space
158 *
159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
160 */
161 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
162 struct resource *res, unsigned int pos)
163 {
164 u32 l, sz, mask;
165
166 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
167
168 res->name = pci_name(dev);
169
170 pci_read_config_dword(dev, pos, &l);
171 pci_write_config_dword(dev, pos, mask);
172 pci_read_config_dword(dev, pos, &sz);
173 pci_write_config_dword(dev, pos, l);
174
175 /*
176 * All bits set in sz means the device isn't working properly.
177 * If the BAR isn't implemented, all bits must be 0. If it's a
178 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
179 * 1 must be clear.
180 */
181 if (!sz || sz == 0xffffffff)
182 goto fail;
183
184 /*
185 * I don't know how l can have all bits set. Copied from old code.
186 * Maybe it fixes a bug on some ancient platform.
187 */
188 if (l == 0xffffffff)
189 l = 0;
190
191 if (type == pci_bar_unknown) {
192 type = decode_bar(res, l);
193 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
194 if (type == pci_bar_io) {
195 l &= PCI_BASE_ADDRESS_IO_MASK;
196 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
197 } else {
198 l &= PCI_BASE_ADDRESS_MEM_MASK;
199 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
200 }
201 } else {
202 res->flags |= (l & IORESOURCE_ROM_ENABLE);
203 l &= PCI_ROM_ADDRESS_MASK;
204 mask = (u32)PCI_ROM_ADDRESS_MASK;
205 }
206
207 if (type == pci_bar_mem64) {
208 u64 l64 = l;
209 u64 sz64 = sz;
210 u64 mask64 = mask | (u64)~0 << 32;
211
212 pci_read_config_dword(dev, pos + 4, &l);
213 pci_write_config_dword(dev, pos + 4, ~0);
214 pci_read_config_dword(dev, pos + 4, &sz);
215 pci_write_config_dword(dev, pos + 4, l);
216
217 l64 |= ((u64)l << 32);
218 sz64 |= ((u64)sz << 32);
219
220 sz64 = pci_size(l64, sz64, mask64);
221
222 if (!sz64)
223 goto fail;
224
225 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
226 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
227 goto fail;
228 } else if ((sizeof(resource_size_t) < 8) && l) {
229 /* Address above 32-bit boundary; disable the BAR */
230 pci_write_config_dword(dev, pos, 0);
231 pci_write_config_dword(dev, pos + 4, 0);
232 res->start = 0;
233 res->end = sz64;
234 } else {
235 res->start = l64;
236 res->end = l64 + sz64;
237 dev_printk(KERN_DEBUG, &dev->dev,
238 "reg %x %s: %pR\n", pos,
239 (res->flags & IORESOURCE_PREFETCH) ?
240 "64bit mmio pref" : "64bit mmio",
241 res);
242 }
243
244 res->flags |= IORESOURCE_MEM_64;
245 } else {
246 sz = pci_size(l, sz, mask);
247
248 if (!sz)
249 goto fail;
250
251 res->start = l;
252 res->end = l + sz;
253
254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos,
255 (res->flags & IORESOURCE_IO) ? "io port" :
256 ((res->flags & IORESOURCE_PREFETCH) ?
257 "32bit mmio pref" : "32bit mmio"),
258 res);
259 }
260
261 out:
262 return (type == pci_bar_mem64) ? 1 : 0;
263 fail:
264 res->flags = 0;
265 goto out;
266 }
267
268 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
269 {
270 unsigned int pos, reg;
271
272 for (pos = 0; pos < howmany; pos++) {
273 struct resource *res = &dev->resource[pos];
274 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
275 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
276 }
277
278 if (rom) {
279 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
280 dev->rom_base_reg = rom;
281 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
282 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
283 IORESOURCE_SIZEALIGN;
284 __pci_read_base(dev, pci_bar_mem32, res, rom);
285 }
286 }
287
288 void __devinit pci_read_bridge_bases(struct pci_bus *child)
289 {
290 struct pci_dev *dev = child->self;
291 u8 io_base_lo, io_limit_lo;
292 u16 mem_base_lo, mem_limit_lo;
293 unsigned long base, limit;
294 struct resource *res;
295 int i;
296
297 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
298 return;
299
300 if (dev->transparent) {
301 dev_info(&dev->dev, "transparent bridge\n");
302 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
303 child->resource[i] = child->parent->resource[i - 3];
304 }
305
306 res = child->resource[0];
307 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
308 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
309 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
310 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
311
312 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
313 u16 io_base_hi, io_limit_hi;
314 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
315 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
316 base |= (io_base_hi << 16);
317 limit |= (io_limit_hi << 16);
318 }
319
320 if (base <= limit) {
321 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
322 if (!res->start)
323 res->start = base;
324 if (!res->end)
325 res->end = limit + 0xfff;
326 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
327 }
328
329 res = child->resource[1];
330 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
331 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
332 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
333 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
334 if (base <= limit) {
335 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
336 res->start = base;
337 res->end = limit + 0xfffff;
338 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n",
339 res);
340 }
341
342 res = child->resource[2];
343 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
344 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
345 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
346 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
347
348 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
349 u32 mem_base_hi, mem_limit_hi;
350 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
351 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
352
353 /*
354 * Some bridges set the base > limit by default, and some
355 * (broken) BIOSes do not initialize them. If we find
356 * this, just assume they are not being used.
357 */
358 if (mem_base_hi <= mem_limit_hi) {
359 #if BITS_PER_LONG == 64
360 base |= ((long) mem_base_hi) << 32;
361 limit |= ((long) mem_limit_hi) << 32;
362 #else
363 if (mem_base_hi || mem_limit_hi) {
364 dev_err(&dev->dev, "can't handle 64-bit "
365 "address space for bridge\n");
366 return;
367 }
368 #endif
369 }
370 }
371 if (base <= limit) {
372 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
373 IORESOURCE_MEM | IORESOURCE_PREFETCH;
374 if (res->flags & PCI_PREF_RANGE_TYPE_64)
375 res->flags |= IORESOURCE_MEM_64;
376 res->start = base;
377 res->end = limit + 0xfffff;
378 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
379 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
380 res);
381 }
382 }
383
384 static struct pci_bus * pci_alloc_bus(void)
385 {
386 struct pci_bus *b;
387
388 b = kzalloc(sizeof(*b), GFP_KERNEL);
389 if (b) {
390 INIT_LIST_HEAD(&b->node);
391 INIT_LIST_HEAD(&b->children);
392 INIT_LIST_HEAD(&b->devices);
393 INIT_LIST_HEAD(&b->slots);
394 }
395 return b;
396 }
397
398 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
399 struct pci_dev *bridge, int busnr)
400 {
401 struct pci_bus *child;
402 int i;
403
404 /*
405 * Allocate a new bus, and inherit stuff from the parent..
406 */
407 child = pci_alloc_bus();
408 if (!child)
409 return NULL;
410
411 child->parent = parent;
412 child->ops = parent->ops;
413 child->sysdata = parent->sysdata;
414 child->bus_flags = parent->bus_flags;
415
416 /* initialize some portions of the bus device, but don't register it
417 * now as the parent is not properly set up yet. This device will get
418 * registered later in pci_bus_add_devices()
419 */
420 child->dev.class = &pcibus_class;
421 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
422
423 /*
424 * Set up the primary, secondary and subordinate
425 * bus numbers.
426 */
427 child->number = child->secondary = busnr;
428 child->primary = parent->secondary;
429 child->subordinate = 0xff;
430
431 if (!bridge)
432 return child;
433
434 child->self = bridge;
435 child->bridge = get_device(&bridge->dev);
436
437 /* Set up default resource pointers and names.. */
438 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
439 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
440 child->resource[i]->name = child->name;
441 }
442 bridge->subordinate = child;
443
444 return child;
445 }
446
447 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
448 {
449 struct pci_bus *child;
450
451 child = pci_alloc_child_bus(parent, dev, busnr);
452 if (child) {
453 down_write(&pci_bus_sem);
454 list_add_tail(&child->node, &parent->children);
455 up_write(&pci_bus_sem);
456 }
457 return child;
458 }
459
460 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
461 {
462 struct pci_bus *parent = child->parent;
463
464 /* Attempts to fix that up are really dangerous unless
465 we're going to re-assign all bus numbers. */
466 if (!pcibios_assign_all_busses())
467 return;
468
469 while (parent->parent && parent->subordinate < max) {
470 parent->subordinate = max;
471 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
472 parent = parent->parent;
473 }
474 }
475
476 /*
477 * If it's a bridge, configure it and scan the bus behind it.
478 * For CardBus bridges, we don't scan behind as the devices will
479 * be handled by the bridge driver itself.
480 *
481 * We need to process bridges in two passes -- first we scan those
482 * already configured by the BIOS and after we are done with all of
483 * them, we proceed to assigning numbers to the remaining buses in
484 * order to avoid overlaps between old and new bus numbers.
485 */
486 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
487 {
488 struct pci_bus *child;
489 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
490 u32 buses, i, j = 0;
491 u16 bctl;
492 int broken = 0;
493
494 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
495
496 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
497 buses & 0xffffff, pass);
498
499 /* Check if setup is sensible at all */
500 if (!pass &&
501 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
502 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
503 broken = 1;
504 }
505
506 /* Disable MasterAbortMode during probing to avoid reporting
507 of bus errors (in some architectures) */
508 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
509 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
510 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
511
512 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
513 unsigned int cmax, busnr;
514 /*
515 * Bus already configured by firmware, process it in the first
516 * pass and just note the configuration.
517 */
518 if (pass)
519 goto out;
520 busnr = (buses >> 8) & 0xFF;
521
522 /*
523 * If we already got to this bus through a different bridge,
524 * don't re-add it. This can happen with the i450NX chipset.
525 *
526 * However, we continue to descend down the hierarchy and
527 * scan remaining child buses.
528 */
529 child = pci_find_bus(pci_domain_nr(bus), busnr);
530 if (!child) {
531 child = pci_add_new_bus(bus, dev, busnr);
532 if (!child)
533 goto out;
534 child->primary = buses & 0xFF;
535 child->subordinate = (buses >> 16) & 0xFF;
536 child->bridge_ctl = bctl;
537 }
538
539 cmax = pci_scan_child_bus(child);
540 if (cmax > max)
541 max = cmax;
542 if (child->subordinate > max)
543 max = child->subordinate;
544 } else {
545 /*
546 * We need to assign a number to this bus which we always
547 * do in the second pass.
548 */
549 if (!pass) {
550 if (pcibios_assign_all_busses() || broken)
551 /* Temporarily disable forwarding of the
552 configuration cycles on all bridges in
553 this bus segment to avoid possible
554 conflicts in the second pass between two
555 bridges programmed with overlapping
556 bus ranges. */
557 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
558 buses & ~0xffffff);
559 goto out;
560 }
561
562 /* Clear errors */
563 pci_write_config_word(dev, PCI_STATUS, 0xffff);
564
565 /* Prevent assigning a bus number that already exists.
566 * This can happen when a bridge is hot-plugged */
567 if (pci_find_bus(pci_domain_nr(bus), max+1))
568 goto out;
569 child = pci_add_new_bus(bus, dev, ++max);
570 buses = (buses & 0xff000000)
571 | ((unsigned int)(child->primary) << 0)
572 | ((unsigned int)(child->secondary) << 8)
573 | ((unsigned int)(child->subordinate) << 16);
574
575 /*
576 * yenta.c forces a secondary latency timer of 176.
577 * Copy that behaviour here.
578 */
579 if (is_cardbus) {
580 buses &= ~0xff000000;
581 buses |= CARDBUS_LATENCY_TIMER << 24;
582 }
583
584 /*
585 * We need to blast all three values with a single write.
586 */
587 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
588
589 if (!is_cardbus) {
590 child->bridge_ctl = bctl;
591 /*
592 * Adjust subordinate busnr in parent buses.
593 * We do this before scanning for children because
594 * some devices may not be detected if the bios
595 * was lazy.
596 */
597 pci_fixup_parent_subordinate_busnr(child, max);
598 /* Now we can scan all subordinate buses... */
599 max = pci_scan_child_bus(child);
600 /*
601 * now fix it up again since we have found
602 * the real value of max.
603 */
604 pci_fixup_parent_subordinate_busnr(child, max);
605 } else {
606 /*
607 * For CardBus bridges, we leave 4 bus numbers
608 * as cards with a PCI-to-PCI bridge can be
609 * inserted later.
610 */
611 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
612 struct pci_bus *parent = bus;
613 if (pci_find_bus(pci_domain_nr(bus),
614 max+i+1))
615 break;
616 while (parent->parent) {
617 if ((!pcibios_assign_all_busses()) &&
618 (parent->subordinate > max) &&
619 (parent->subordinate <= max+i)) {
620 j = 1;
621 }
622 parent = parent->parent;
623 }
624 if (j) {
625 /*
626 * Often, there are two cardbus bridges
627 * -- try to leave one valid bus number
628 * for each one.
629 */
630 i /= 2;
631 break;
632 }
633 }
634 max += i;
635 pci_fixup_parent_subordinate_busnr(child, max);
636 }
637 /*
638 * Set the subordinate bus number to its real value.
639 */
640 child->subordinate = max;
641 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
642 }
643
644 sprintf(child->name,
645 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
646 pci_domain_nr(bus), child->number);
647
648 /* Has only triggered on CardBus, fixup is in yenta_socket */
649 while (bus->parent) {
650 if ((child->subordinate > bus->subordinate) ||
651 (child->number > bus->subordinate) ||
652 (child->number < bus->number) ||
653 (child->subordinate < bus->number)) {
654 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
655 "hidden behind%s bridge #%02x (-#%02x)\n",
656 child->number, child->subordinate,
657 (bus->number > child->subordinate &&
658 bus->subordinate < child->number) ?
659 "wholly" : "partially",
660 bus->self->transparent ? " transparent" : "",
661 bus->number, bus->subordinate);
662 }
663 bus = bus->parent;
664 }
665
666 out:
667 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
668
669 return max;
670 }
671
672 /*
673 * Read interrupt line and base address registers.
674 * The architecture-dependent code can tweak these, of course.
675 */
676 static void pci_read_irq(struct pci_dev *dev)
677 {
678 unsigned char irq;
679
680 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
681 dev->pin = irq;
682 if (irq)
683 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
684 dev->irq = irq;
685 }
686
687 static void set_pcie_port_type(struct pci_dev *pdev)
688 {
689 int pos;
690 u16 reg16;
691
692 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
693 if (!pos)
694 return;
695 pdev->is_pcie = 1;
696 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
697 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
698 }
699
700 static void set_pcie_hotplug_bridge(struct pci_dev *pdev)
701 {
702 int pos;
703 u16 reg16;
704 u32 reg32;
705
706 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
707 if (!pos)
708 return;
709 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
710 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
711 return;
712 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
713 if (reg32 & PCI_EXP_SLTCAP_HPC)
714 pdev->is_hotplug_bridge = 1;
715 }
716
717 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
718
719 /**
720 * pci_setup_device - fill in class and map information of a device
721 * @dev: the device structure to fill
722 *
723 * Initialize the device structure with information about the device's
724 * vendor,class,memory and IO-space addresses,IRQ lines etc.
725 * Called at initialisation of the PCI subsystem and by CardBus services.
726 * Returns 0 on success and negative if unknown type of device (not normal,
727 * bridge or CardBus).
728 */
729 int pci_setup_device(struct pci_dev *dev)
730 {
731 u32 class;
732 u8 hdr_type;
733 struct pci_slot *slot;
734 int pos = 0;
735
736 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
737 return -EIO;
738
739 dev->sysdata = dev->bus->sysdata;
740 dev->dev.parent = dev->bus->bridge;
741 dev->dev.bus = &pci_bus_type;
742 dev->hdr_type = hdr_type & 0x7f;
743 dev->multifunction = !!(hdr_type & 0x80);
744 dev->error_state = pci_channel_io_normal;
745 set_pcie_port_type(dev);
746
747 list_for_each_entry(slot, &dev->bus->slots, list)
748 if (PCI_SLOT(dev->devfn) == slot->number)
749 dev->slot = slot;
750
751 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
752 set this higher, assuming the system even supports it. */
753 dev->dma_mask = 0xffffffff;
754
755 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
756 dev->bus->number, PCI_SLOT(dev->devfn),
757 PCI_FUNC(dev->devfn));
758
759 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
760 dev->revision = class & 0xff;
761 class >>= 8; /* upper 3 bytes */
762 dev->class = class;
763 class >>= 8;
764
765 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
766 dev->vendor, dev->device, class, dev->hdr_type);
767
768 /* need to have dev->class ready */
769 dev->cfg_size = pci_cfg_space_size(dev);
770
771 /* "Unknown power state" */
772 dev->current_state = PCI_UNKNOWN;
773
774 /* Early fixups, before probing the BARs */
775 pci_fixup_device(pci_fixup_early, dev);
776 /* device class may be changed after fixup */
777 class = dev->class >> 8;
778
779 switch (dev->hdr_type) { /* header type */
780 case PCI_HEADER_TYPE_NORMAL: /* standard header */
781 if (class == PCI_CLASS_BRIDGE_PCI)
782 goto bad;
783 pci_read_irq(dev);
784 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
785 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
786 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
787
788 /*
789 * Do the ugly legacy mode stuff here rather than broken chip
790 * quirk code. Legacy mode ATA controllers have fixed
791 * addresses. These are not always echoed in BAR0-3, and
792 * BAR0-3 in a few cases contain junk!
793 */
794 if (class == PCI_CLASS_STORAGE_IDE) {
795 u8 progif;
796 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
797 if ((progif & 1) == 0) {
798 dev->resource[0].start = 0x1F0;
799 dev->resource[0].end = 0x1F7;
800 dev->resource[0].flags = LEGACY_IO_RESOURCE;
801 dev->resource[1].start = 0x3F6;
802 dev->resource[1].end = 0x3F6;
803 dev->resource[1].flags = LEGACY_IO_RESOURCE;
804 }
805 if ((progif & 4) == 0) {
806 dev->resource[2].start = 0x170;
807 dev->resource[2].end = 0x177;
808 dev->resource[2].flags = LEGACY_IO_RESOURCE;
809 dev->resource[3].start = 0x376;
810 dev->resource[3].end = 0x376;
811 dev->resource[3].flags = LEGACY_IO_RESOURCE;
812 }
813 }
814 break;
815
816 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
817 if (class != PCI_CLASS_BRIDGE_PCI)
818 goto bad;
819 /* The PCI-to-PCI bridge spec requires that subtractive
820 decoding (i.e. transparent) bridge must have programming
821 interface code of 0x01. */
822 pci_read_irq(dev);
823 dev->transparent = ((dev->class & 0xff) == 1);
824 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
825 set_pcie_hotplug_bridge(dev);
826 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
827 if (pos) {
828 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
829 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
830 }
831 break;
832
833 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
834 if (class != PCI_CLASS_BRIDGE_CARDBUS)
835 goto bad;
836 pci_read_irq(dev);
837 pci_read_bases(dev, 1, 0);
838 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
839 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
840 break;
841
842 default: /* unknown header */
843 dev_err(&dev->dev, "unknown header type %02x, "
844 "ignoring device\n", dev->hdr_type);
845 return -EIO;
846
847 bad:
848 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
849 "type %02x)\n", class, dev->hdr_type);
850 dev->class = PCI_CLASS_NOT_DEFINED;
851 }
852
853 /* We found a fine healthy device, go go go... */
854 return 0;
855 }
856
857 static void pci_release_capabilities(struct pci_dev *dev)
858 {
859 pci_vpd_release(dev);
860 pci_iov_release(dev);
861 }
862
863 /**
864 * pci_release_dev - free a pci device structure when all users of it are finished.
865 * @dev: device that's been disconnected
866 *
867 * Will be called only by the device core when all users of this pci device are
868 * done.
869 */
870 static void pci_release_dev(struct device *dev)
871 {
872 struct pci_dev *pci_dev;
873
874 pci_dev = to_pci_dev(dev);
875 pci_release_capabilities(pci_dev);
876 kfree(pci_dev);
877 }
878
879 /**
880 * pci_cfg_space_size - get the configuration space size of the PCI device.
881 * @dev: PCI device
882 *
883 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
884 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
885 * access it. Maybe we don't have a way to generate extended config space
886 * accesses, or the device is behind a reverse Express bridge. So we try
887 * reading the dword at 0x100 which must either be 0 or a valid extended
888 * capability header.
889 */
890 int pci_cfg_space_size_ext(struct pci_dev *dev)
891 {
892 u32 status;
893 int pos = PCI_CFG_SPACE_SIZE;
894
895 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
896 goto fail;
897 if (status == 0xffffffff)
898 goto fail;
899
900 return PCI_CFG_SPACE_EXP_SIZE;
901
902 fail:
903 return PCI_CFG_SPACE_SIZE;
904 }
905
906 int pci_cfg_space_size(struct pci_dev *dev)
907 {
908 int pos;
909 u32 status;
910 u16 class;
911
912 class = dev->class >> 8;
913 if (class == PCI_CLASS_BRIDGE_HOST)
914 return pci_cfg_space_size_ext(dev);
915
916 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
917 if (!pos) {
918 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
919 if (!pos)
920 goto fail;
921
922 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
923 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
924 goto fail;
925 }
926
927 return pci_cfg_space_size_ext(dev);
928
929 fail:
930 return PCI_CFG_SPACE_SIZE;
931 }
932
933 static void pci_release_bus_bridge_dev(struct device *dev)
934 {
935 kfree(dev);
936 }
937
938 struct pci_dev *alloc_pci_dev(void)
939 {
940 struct pci_dev *dev;
941
942 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
943 if (!dev)
944 return NULL;
945
946 INIT_LIST_HEAD(&dev->bus_list);
947
948 return dev;
949 }
950 EXPORT_SYMBOL(alloc_pci_dev);
951
952 /*
953 * Read the config data for a PCI device, sanity-check it
954 * and fill in the dev structure...
955 */
956 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
957 {
958 struct pci_dev *dev;
959 u32 l;
960 int delay = 1;
961
962 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
963 return NULL;
964
965 /* some broken boards return 0 or ~0 if a slot is empty: */
966 if (l == 0xffffffff || l == 0x00000000 ||
967 l == 0x0000ffff || l == 0xffff0000)
968 return NULL;
969
970 /* Configuration request Retry Status */
971 while (l == 0xffff0001) {
972 msleep(delay);
973 delay *= 2;
974 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
975 return NULL;
976 /* Card hasn't responded in 60 seconds? Must be stuck. */
977 if (delay > 60 * 1000) {
978 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
979 "responding\n", pci_domain_nr(bus),
980 bus->number, PCI_SLOT(devfn),
981 PCI_FUNC(devfn));
982 return NULL;
983 }
984 }
985
986 dev = alloc_pci_dev();
987 if (!dev)
988 return NULL;
989
990 dev->bus = bus;
991 dev->devfn = devfn;
992 dev->vendor = l & 0xffff;
993 dev->device = (l >> 16) & 0xffff;
994
995 if (pci_setup_device(dev)) {
996 kfree(dev);
997 return NULL;
998 }
999
1000 return dev;
1001 }
1002
1003 static void pci_init_capabilities(struct pci_dev *dev)
1004 {
1005 /* MSI/MSI-X list */
1006 pci_msi_init_pci_dev(dev);
1007
1008 /* Buffers for saving PCIe and PCI-X capabilities */
1009 pci_allocate_cap_save_buffers(dev);
1010
1011 /* Power Management */
1012 pci_pm_init(dev);
1013 platform_pci_wakeup_init(dev);
1014
1015 /* Vital Product Data */
1016 pci_vpd_pci22_init(dev);
1017
1018 /* Alternative Routing-ID Forwarding */
1019 pci_enable_ari(dev);
1020
1021 /* Single Root I/O Virtualization */
1022 pci_iov_init(dev);
1023 }
1024
1025 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1026 {
1027 device_initialize(&dev->dev);
1028 dev->dev.release = pci_release_dev;
1029 pci_dev_get(dev);
1030
1031 dev->dev.dma_mask = &dev->dma_mask;
1032 dev->dev.dma_parms = &dev->dma_parms;
1033 dev->dev.coherent_dma_mask = 0xffffffffull;
1034
1035 pci_set_dma_max_seg_size(dev, 65536);
1036 pci_set_dma_seg_boundary(dev, 0xffffffff);
1037
1038 /* Fix up broken headers */
1039 pci_fixup_device(pci_fixup_header, dev);
1040
1041 /* Clear the state_saved flag. */
1042 dev->state_saved = false;
1043
1044 /* Initialize various capabilities */
1045 pci_init_capabilities(dev);
1046
1047 /*
1048 * Add the device to our list of discovered devices
1049 * and the bus list for fixup functions, etc.
1050 */
1051 down_write(&pci_bus_sem);
1052 list_add_tail(&dev->bus_list, &bus->devices);
1053 up_write(&pci_bus_sem);
1054 }
1055
1056 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1057 {
1058 struct pci_dev *dev;
1059
1060 dev = pci_get_slot(bus, devfn);
1061 if (dev) {
1062 pci_dev_put(dev);
1063 return dev;
1064 }
1065
1066 dev = pci_scan_device(bus, devfn);
1067 if (!dev)
1068 return NULL;
1069
1070 pci_device_add(dev, bus);
1071
1072 return dev;
1073 }
1074 EXPORT_SYMBOL(pci_scan_single_device);
1075
1076 /**
1077 * pci_scan_slot - scan a PCI slot on a bus for devices.
1078 * @bus: PCI bus to scan
1079 * @devfn: slot number to scan (must have zero function.)
1080 *
1081 * Scan a PCI slot on the specified PCI bus for devices, adding
1082 * discovered devices to the @bus->devices list. New devices
1083 * will not have is_added set.
1084 *
1085 * Returns the number of new devices found.
1086 */
1087 int pci_scan_slot(struct pci_bus *bus, int devfn)
1088 {
1089 int fn, nr = 0;
1090 struct pci_dev *dev;
1091
1092 dev = pci_scan_single_device(bus, devfn);
1093 if (dev && !dev->is_added) /* new device? */
1094 nr++;
1095
1096 if (dev && dev->multifunction) {
1097 for (fn = 1; fn < 8; fn++) {
1098 dev = pci_scan_single_device(bus, devfn + fn);
1099 if (dev) {
1100 if (!dev->is_added)
1101 nr++;
1102 dev->multifunction = 1;
1103 }
1104 }
1105 }
1106
1107 /* only one slot has pcie device */
1108 if (bus->self && nr)
1109 pcie_aspm_init_link_state(bus->self);
1110
1111 return nr;
1112 }
1113
1114 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1115 {
1116 unsigned int devfn, pass, max = bus->secondary;
1117 struct pci_dev *dev;
1118
1119 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1120
1121 /* Go find them, Rover! */
1122 for (devfn = 0; devfn < 0x100; devfn += 8)
1123 pci_scan_slot(bus, devfn);
1124
1125 /* Reserve buses for SR-IOV capability. */
1126 max += pci_iov_bus_range(bus);
1127
1128 /*
1129 * After performing arch-dependent fixup of the bus, look behind
1130 * all PCI-to-PCI bridges on this bus.
1131 */
1132 if (!bus->is_added) {
1133 pr_debug("PCI: Fixups for bus %04x:%02x\n",
1134 pci_domain_nr(bus), bus->number);
1135 pcibios_fixup_bus(bus);
1136 if (pci_is_root_bus(bus))
1137 bus->is_added = 1;
1138 }
1139
1140 for (pass=0; pass < 2; pass++)
1141 list_for_each_entry(dev, &bus->devices, bus_list) {
1142 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1143 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1144 max = pci_scan_bridge(bus, dev, max, pass);
1145 }
1146
1147 /*
1148 * We've scanned the bus and so we know all about what's on
1149 * the other side of any bridges that may be on this bus plus
1150 * any devices.
1151 *
1152 * Return how far we've got finding sub-buses.
1153 */
1154 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1155 pci_domain_nr(bus), bus->number, max);
1156 return max;
1157 }
1158
1159 struct pci_bus * pci_create_bus(struct device *parent,
1160 int bus, struct pci_ops *ops, void *sysdata)
1161 {
1162 int error;
1163 struct pci_bus *b;
1164 struct device *dev;
1165
1166 b = pci_alloc_bus();
1167 if (!b)
1168 return NULL;
1169
1170 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1171 if (!dev){
1172 kfree(b);
1173 return NULL;
1174 }
1175
1176 b->sysdata = sysdata;
1177 b->ops = ops;
1178
1179 if (pci_find_bus(pci_domain_nr(b), bus)) {
1180 /* If we already got to this bus through a different bridge, ignore it */
1181 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1182 goto err_out;
1183 }
1184
1185 down_write(&pci_bus_sem);
1186 list_add_tail(&b->node, &pci_root_buses);
1187 up_write(&pci_bus_sem);
1188
1189 dev->parent = parent;
1190 dev->release = pci_release_bus_bridge_dev;
1191 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1192 error = device_register(dev);
1193 if (error)
1194 goto dev_reg_err;
1195 b->bridge = get_device(dev);
1196
1197 if (!parent)
1198 set_dev_node(b->bridge, pcibus_to_node(b));
1199
1200 b->dev.class = &pcibus_class;
1201 b->dev.parent = b->bridge;
1202 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1203 error = device_register(&b->dev);
1204 if (error)
1205 goto class_dev_reg_err;
1206 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1207 if (error)
1208 goto dev_create_file_err;
1209
1210 /* Create legacy_io and legacy_mem files for this bus */
1211 pci_create_legacy_files(b);
1212
1213 b->number = b->secondary = bus;
1214 b->resource[0] = &ioport_resource;
1215 b->resource[1] = &iomem_resource;
1216
1217 return b;
1218
1219 dev_create_file_err:
1220 device_unregister(&b->dev);
1221 class_dev_reg_err:
1222 device_unregister(dev);
1223 dev_reg_err:
1224 down_write(&pci_bus_sem);
1225 list_del(&b->node);
1226 up_write(&pci_bus_sem);
1227 err_out:
1228 kfree(dev);
1229 kfree(b);
1230 return NULL;
1231 }
1232
1233 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1234 int bus, struct pci_ops *ops, void *sysdata)
1235 {
1236 struct pci_bus *b;
1237
1238 b = pci_create_bus(parent, bus, ops, sysdata);
1239 if (b)
1240 b->subordinate = pci_scan_child_bus(b);
1241 return b;
1242 }
1243 EXPORT_SYMBOL(pci_scan_bus_parented);
1244
1245 #ifdef CONFIG_HOTPLUG
1246 /**
1247 * pci_rescan_bus - scan a PCI bus for devices.
1248 * @bus: PCI bus to scan
1249 *
1250 * Scan a PCI bus and child buses for new devices, adds them,
1251 * and enables them.
1252 *
1253 * Returns the max number of subordinate bus discovered.
1254 */
1255 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1256 {
1257 unsigned int max;
1258 struct pci_dev *dev;
1259
1260 max = pci_scan_child_bus(bus);
1261
1262 down_read(&pci_bus_sem);
1263 list_for_each_entry(dev, &bus->devices, bus_list)
1264 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1265 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1266 if (dev->subordinate)
1267 pci_bus_size_bridges(dev->subordinate);
1268 up_read(&pci_bus_sem);
1269
1270 pci_bus_assign_resources(bus);
1271 pci_enable_bridges(bus);
1272 pci_bus_add_devices(bus);
1273
1274 return max;
1275 }
1276 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1277
1278 EXPORT_SYMBOL(pci_add_new_bus);
1279 EXPORT_SYMBOL(pci_scan_slot);
1280 EXPORT_SYMBOL(pci_scan_bridge);
1281 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1282 #endif
1283
1284 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1285 {
1286 const struct pci_dev *a = to_pci_dev(d_a);
1287 const struct pci_dev *b = to_pci_dev(d_b);
1288
1289 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1290 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1291
1292 if (a->bus->number < b->bus->number) return -1;
1293 else if (a->bus->number > b->bus->number) return 1;
1294
1295 if (a->devfn < b->devfn) return -1;
1296 else if (a->devfn > b->devfn) return 1;
1297
1298 return 0;
1299 }
1300
1301 void __init pci_sort_breadthfirst(void)
1302 {
1303 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1304 }
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