mm-only debug patch...
[mmotm.git] / drivers / staging / rtl8192e / r819xE_phyreg.h
blobd4a439275effa999d2862d41521a8d8532793fbc
1 #ifndef _R819XU_PHYREG_H
2 #define _R819XU_PHYREG_H
5 #define RF_DATA 0x1d4 // FW will write RF data in the register.
7 //Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
8 //page 1
9 #define rPMAC_Reset 0x100
10 #define rPMAC_TxStart 0x104
11 #define rPMAC_TxLegacySIG 0x108
12 #define rPMAC_TxHTSIG1 0x10c
13 #define rPMAC_TxHTSIG2 0x110
14 #define rPMAC_PHYDebug 0x114
15 #define rPMAC_TxPacketNum 0x118
16 #define rPMAC_TxIdle 0x11c
17 #define rPMAC_TxMACHeader0 0x120
18 #define rPMAC_TxMACHeader1 0x124
19 #define rPMAC_TxMACHeader2 0x128
20 #define rPMAC_TxMACHeader3 0x12c
21 #define rPMAC_TxMACHeader4 0x130
22 #define rPMAC_TxMACHeader5 0x134
23 #define rPMAC_TxDataType 0x138
24 #define rPMAC_TxRandomSeed 0x13c
25 #define rPMAC_CCKPLCPPreamble 0x140
26 #define rPMAC_CCKPLCPHeader 0x144
27 #define rPMAC_CCKCRC16 0x148
28 #define rPMAC_OFDMRxCRC32OK 0x170
29 #define rPMAC_OFDMRxCRC32Er 0x174
30 #define rPMAC_OFDMRxParityEr 0x178
31 #define rPMAC_OFDMRxCRC8Er 0x17c
32 #define rPMAC_CCKCRxRC16Er 0x180
33 #define rPMAC_CCKCRxRC32Er 0x184
34 #define rPMAC_CCKCRxRC32OK 0x188
35 #define rPMAC_TxStatus 0x18c
37 //90P
38 #define MCS_TXAGC 0x340 // MCS AGC
39 #define CCK_TXAGC 0x348 // CCK AGC
41 //page8
42 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC
43 #define rFPGA0_TxInfo 0x804
44 #define rFPGA0_PSDFunction 0x808
45 #define rFPGA0_TxGainStage 0x80c
46 #define rFPGA0_RFTiming1 0x810
47 #define rFPGA0_RFTiming2 0x814
48 //#define rFPGA0_XC_RFTiming 0x818
49 //#define rFPGA0_XD_RFTiming 0x81c
50 #define rFPGA0_XA_HSSIParameter1 0x820
51 #define rFPGA0_XA_HSSIParameter2 0x824
52 #define rFPGA0_XB_HSSIParameter1 0x828
53 #define rFPGA0_XB_HSSIParameter2 0x82c
54 #define rFPGA0_XC_HSSIParameter1 0x830
55 #define rFPGA0_XC_HSSIParameter2 0x834
56 #define rFPGA0_XD_HSSIParameter1 0x838
57 #define rFPGA0_XD_HSSIParameter2 0x83c
58 #define rFPGA0_XA_LSSIParameter 0x840
59 #define rFPGA0_XB_LSSIParameter 0x844
60 #define rFPGA0_XC_LSSIParameter 0x848
61 #define rFPGA0_XD_LSSIParameter 0x84c
62 #define rFPGA0_RFWakeUpParameter 0x850
63 #define rFPGA0_RFSleepUpParameter 0x854
64 #define rFPGA0_XAB_SwitchControl 0x858
65 #define rFPGA0_XCD_SwitchControl 0x85c
66 #define rFPGA0_XA_RFInterfaceOE 0x860
67 #define rFPGA0_XB_RFInterfaceOE 0x864
68 #define rFPGA0_XC_RFInterfaceOE 0x868
69 #define rFPGA0_XD_RFInterfaceOE 0x86c
70 #define rFPGA0_XAB_RFInterfaceSW 0x870
71 #define rFPGA0_XCD_RFInterfaceSW 0x874
72 #define rFPGA0_XAB_RFParameter 0x878
73 #define rFPGA0_XCD_RFParameter 0x87c
74 #define rFPGA0_AnalogParameter1 0x880
75 #define rFPGA0_AnalogParameter2 0x884
76 #define rFPGA0_AnalogParameter3 0x888
77 #define rFPGA0_AnalogParameter4 0x88c
78 #define rFPGA0_XA_LSSIReadBack 0x8a0
79 #define rFPGA0_XB_LSSIReadBack 0x8a4
80 #define rFPGA0_XC_LSSIReadBack 0x8a8
81 #define rFPGA0_XD_LSSIReadBack 0x8ac
82 #define rFPGA0_PSDReport 0x8b4
83 #define rFPGA0_XAB_RFInterfaceRB 0x8e0
84 #define rFPGA0_XCD_RFInterfaceRB 0x8e4
86 //page 9
87 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC
88 #define rFPGA1_TxBlock 0x904
89 #define rFPGA1_DebugSelect 0x908
90 #define rFPGA1_TxInfo 0x90c
92 //page a
93 #define rCCK0_System 0xa00
94 #define rCCK0_AFESetting 0xa04
95 #define rCCK0_CCA 0xa08
96 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level
97 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC
98 #define rCCK0_RxHP 0xa14
99 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
100 #define rCCK0_DSPParameter2 0xa1c //SQ threshold
101 #define rCCK0_TxFilter1 0xa20
102 #define rCCK0_TxFilter2 0xa24
103 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
104 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d
105 #define rCCK0_TRSSIReport 0xa50
106 #define rCCK0_RxReport 0xa54 //0xa57
107 #define rCCK0_FACounterLower 0xa5c //0xa5b
108 #define rCCK0_FACounterUpper 0xa58 //0xa5c
110 //page c
111 #define rOFDM0_LSTF 0xc00
112 #define rOFDM0_TRxPathEnable 0xc04
113 #define rOFDM0_TRMuxPar 0xc08
114 #define rOFDM0_TRSWIsolation 0xc0c
115 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
116 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
117 #define rOFDM0_XBRxAFE 0xc18
118 #define rOFDM0_XBRxIQImbalance 0xc1c
119 #define rOFDM0_XCRxAFE 0xc20
120 #define rOFDM0_XCRxIQImbalance 0xc24
121 #define rOFDM0_XDRxAFE 0xc28
122 #define rOFDM0_XDRxIQImbalance 0xc2c
123 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD
124 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
125 #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
126 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
127 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
128 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
129 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
130 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
131 #define rOFDM0_XAAGCCore1 0xc50
132 #define rOFDM0_XAAGCCore2 0xc54
133 #define rOFDM0_XBAGCCore1 0xc58
134 #define rOFDM0_XBAGCCore2 0xc5c
135 #define rOFDM0_XCAGCCore1 0xc60
136 #define rOFDM0_XCAGCCore2 0xc64
137 #define rOFDM0_XDAGCCore1 0xc68
138 #define rOFDM0_XDAGCCore2 0xc6c
139 #define rOFDM0_AGCParameter1 0xc70
140 #define rOFDM0_AGCParameter2 0xc74
141 #define rOFDM0_AGCRSSITable 0xc78
142 #define rOFDM0_HTSTFAGC 0xc7c
143 #define rOFDM0_XATxIQImbalance 0xc80
144 #define rOFDM0_XATxAFE 0xc84
145 #define rOFDM0_XBTxIQImbalance 0xc88
146 #define rOFDM0_XBTxAFE 0xc8c
147 #define rOFDM0_XCTxIQImbalance 0xc90
148 #define rOFDM0_XCTxAFE 0xc94
149 #define rOFDM0_XDTxIQImbalance 0xc98
150 #define rOFDM0_XDTxAFE 0xc9c
151 #define rOFDM0_RxHPParameter 0xce0
152 #define rOFDM0_TxPseudoNoiseWgt 0xce4
153 #define rOFDM0_FrameSync 0xcf0
154 #define rOFDM0_DFSReport 0xcf4
155 #define rOFDM0_TxCoeff1 0xca4
156 #define rOFDM0_TxCoeff2 0xca8
157 #define rOFDM0_TxCoeff3 0xcac
158 #define rOFDM0_TxCoeff4 0xcb0
159 #define rOFDM0_TxCoeff5 0xcb4
160 #define rOFDM0_TxCoeff6 0xcb8
163 //page d
164 #define rOFDM1_LSTF 0xd00
165 #define rOFDM1_TRxPathEnable 0xd04
166 #define rOFDM1_CFO 0xd08
167 #define rOFDM1_CSI1 0xd10
168 #define rOFDM1_SBD 0xd14
169 #define rOFDM1_CSI2 0xd18
170 #define rOFDM1_CFOTracking 0xd2c
171 #define rOFDM1_TRxMesaure1 0xd34
172 #define rOFDM1_IntfDet 0xd3c
173 #define rOFDM1_PseudoNoiseStateAB 0xd50
174 #define rOFDM1_PseudoNoiseStateCD 0xd54
175 #define rOFDM1_RxPseudoNoiseWgt 0xd58
176 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail
177 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
178 #define rOFDM_PHYCounter3 0xda8 //MCS not support
179 #define rOFDM_ShortCFOAB 0xdac
180 #define rOFDM_ShortCFOCD 0xdb0
181 #define rOFDM_LongCFOAB 0xdb4
182 #define rOFDM_LongCFOCD 0xdb8
183 #define rOFDM_TailCFOAB 0xdbc
184 #define rOFDM_TailCFOCD 0xdc0
185 #define rOFDM_PWMeasure1 0xdc4
186 #define rOFDM_PWMeasure2 0xdc8
187 #define rOFDM_BWReport 0xdcc
188 #define rOFDM_AGCReport 0xdd0
189 #define rOFDM_RxSNR 0xdd4
190 #define rOFDM_RxEVMCSI 0xdd8
191 #define rOFDM_SIGReport 0xddc
193 //page e
194 #define rTxAGC_Rate18_06 0xe00
195 #define rTxAGC_Rate54_24 0xe04
196 #define rTxAGC_CCK_Mcs32 0xe08
197 #define rTxAGC_Mcs03_Mcs00 0xe10
198 #define rTxAGC_Mcs07_Mcs04 0xe14
199 #define rTxAGC_Mcs11_Mcs08 0xe18
200 #define rTxAGC_Mcs15_Mcs12 0xe1c
203 //RF
204 //Zebra1
205 #define rZebra1_HSSIEnable 0x0
206 #define rZebra1_TRxEnable1 0x1
207 #define rZebra1_TRxEnable2 0x2
208 #define rZebra1_AGC 0x4
209 #define rZebra1_ChargePump 0x5
210 #define rZebra1_Channel 0x7
211 #define rZebra1_TxGain 0x8
212 #define rZebra1_TxLPF 0x9
213 #define rZebra1_RxLPF 0xb
214 #define rZebra1_RxHPFCorner 0xc
216 //Zebra4
217 #define rGlobalCtrl 0
218 #define rRTL8256_TxLPF 19
219 #define rRTL8256_RxLPF 11
221 //RTL8258
222 #define rRTL8258_TxLPF 0x11
223 #define rRTL8258_RxLPF 0x13
224 #define rRTL8258_RSSILPF 0xa
226 //Bit Mask
227 //page-1
228 #define bBBResetB 0x100
229 #define bGlobalResetB 0x200
230 #define bOFDMTxStart 0x4
231 #define bCCKTxStart 0x8
232 #define bCRC32Debug 0x100
233 #define bPMACLoopback 0x10
234 #define bTxLSIG 0xffffff
235 #define bOFDMTxRate 0xf
236 #define bOFDMTxReserved 0x10
237 #define bOFDMTxLength 0x1ffe0
238 #define bOFDMTxParity 0x20000
239 #define bTxHTSIG1 0xffffff
240 #define bTxHTMCSRate 0x7f
241 #define bTxHTBW 0x80
242 #define bTxHTLength 0xffff00
243 #define bTxHTSIG2 0xffffff
244 #define bTxHTSmoothing 0x1
245 #define bTxHTSounding 0x2
246 #define bTxHTReserved 0x4
247 #define bTxHTAggreation 0x8
248 #define bTxHTSTBC 0x30
249 #define bTxHTAdvanceCoding 0x40
250 #define bTxHTShortGI 0x80
251 #define bTxHTNumberHT_LTF 0x300
252 #define bTxHTCRC8 0x3fc00
253 #define bCounterReset 0x10000
254 #define bNumOfOFDMTx 0xffff
255 #define bNumOfCCKTx 0xffff0000
256 #define bTxIdleInterval 0xffff
257 #define bOFDMService 0xffff0000
258 #define bTxMACHeader 0xffffffff
259 #define bTxDataInit 0xff
260 #define bTxHTMode 0x100
261 #define bTxDataType 0x30000
262 #define bTxRandomSeed 0xffffffff
263 #define bCCKTxPreamble 0x1
264 #define bCCKTxSFD 0xffff0000
265 #define bCCKTxSIG 0xff
266 #define bCCKTxService 0xff00
267 #define bCCKLengthExt 0x8000
268 #define bCCKTxLength 0xffff0000
269 #define bCCKTxCRC16 0xffff
270 #define bCCKTxStatus 0x1
271 #define bOFDMTxStatus 0x2
273 //page-8
274 #define bRFMOD 0x1
275 #define bJapanMode 0x2
276 #define bCCKTxSC 0x30
277 #define bCCKEn 0x1000000
278 #define bOFDMEn 0x2000000
279 #define bOFDMRxADCPhase 0x10000
280 #define bOFDMTxDACPhase 0x40000
281 #define bXATxAGC 0x3f
282 #define bXBTxAGC 0xf00
283 #define bXCTxAGC 0xf000
284 #define bXDTxAGC 0xf0000
285 #define bPAStart 0xf0000000
286 #define bTRStart 0x00f00000
287 #define bRFStart 0x0000f000
288 #define bBBStart 0x000000f0
289 #define bBBCCKStart 0x0000000f
290 #define bPAEnd 0xf //Reg0x814
291 #define bTREnd 0x0f000000
292 #define bRFEnd 0x000f0000
293 #define bCCAMask 0x000000f0 //T2R
294 #define bR2RCCAMask 0x00000f00
295 #define bHSSI_R2TDelay 0xf8000000
296 #define bHSSI_T2RDelay 0xf80000
297 #define bContTxHSSI 0x400 //chane gain at continue Tx
298 #define bIGFromCCK 0x200
299 #define bAGCAddress 0x3f
300 #define bRxHPTx 0x7000
301 #define bRxHPT2R 0x38000
302 #define bRxHPCCKIni 0xc0000
303 #define bAGCTxCode 0xc00000
304 #define bAGCRxCode 0x300000
305 #define b3WireDataLength 0x800
306 #define b3WireAddressLength 0x400
307 #define b3WireRFPowerDown 0x1
308 //#define bHWSISelect 0x8
309 #define b5GPAPEPolarity 0x40000000
310 #define b2GPAPEPolarity 0x80000000
311 #define bRFSW_TxDefaultAnt 0x3
312 #define bRFSW_TxOptionAnt 0x30
313 #define bRFSW_RxDefaultAnt 0x300
314 #define bRFSW_RxOptionAnt 0x3000
315 #define bRFSI_3WireData 0x1
316 #define bRFSI_3WireClock 0x2
317 #define bRFSI_3WireLoad 0x4
318 #define bRFSI_3WireRW 0x8
319 #define bRFSI_3Wire 0xf //3-wire total control
320 #define bRFSI_RFENV 0x10
321 #define bRFSI_TRSW 0x20
322 #define bRFSI_TRSWB 0x40
323 #define bRFSI_ANTSW 0x100
324 #define bRFSI_ANTSWB 0x200
325 #define bRFSI_PAPE 0x400
326 #define bRFSI_PAPE5G 0x800
327 #define bBandSelect 0x1
328 #define bHTSIG2_GI 0x80
329 #define bHTSIG2_Smoothing 0x01
330 #define bHTSIG2_Sounding 0x02
331 #define bHTSIG2_Aggreaton 0x08
332 #define bHTSIG2_STBC 0x30
333 #define bHTSIG2_AdvCoding 0x40
334 #define bHTSIG2_NumOfHTLTF 0x300
335 #define bHTSIG2_CRC8 0x3fc
336 #define bHTSIG1_MCS 0x7f
337 #define bHTSIG1_BandWidth 0x80
338 #define bHTSIG1_HTLength 0xffff
339 #define bLSIG_Rate 0xf
340 #define bLSIG_Reserved 0x10
341 #define bLSIG_Length 0x1fffe
342 #define bLSIG_Parity 0x20
343 #define bCCKRxPhase 0x4
344 #define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address
345 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
346 #define bLSSIReadBackData 0xfff
347 #define bLSSIReadOKFlag 0x1000
348 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
350 #define bRegulator0Standby 0x1
351 #define bRegulatorPLLStandby 0x2
352 #define bRegulator1Standby 0x4
353 #define bPLLPowerUp 0x8
354 #define bDPLLPowerUp 0x10
355 #define bDA10PowerUp 0x20
356 #define bAD7PowerUp 0x200
357 #define bDA6PowerUp 0x2000
358 #define bXtalPowerUp 0x4000
359 #define b40MDClkPowerUP 0x8000
360 #define bDA6DebugMode 0x20000
361 #define bDA6Swing 0x380000
362 #define bADClkPhase 0x4000000
363 #define b80MClkDelay 0x18000000
364 #define bAFEWatchDogEnable 0x20000000
365 #define bXtalCap 0x0f000000
366 #define bXtalCap01 0xc0000000
367 #define bXtalCap23 0x3
368 #define bXtalCap92x 0x0f000000
369 #define bIntDifClkEnable 0x400
370 #define bExtSigClkEnable 0x800
371 #define bBandgapMbiasPowerUp 0x10000
372 #define bAD11SHGain 0xc0000
373 #define bAD11InputRange 0x700000
374 #define bAD11OPCurrent 0x3800000
375 #define bIPathLoopback 0x4000000
376 #define bQPathLoopback 0x8000000
377 #define bAFELoopback 0x10000000
378 #define bDA10Swing 0x7e0
379 #define bDA10Reverse 0x800
380 #define bDAClkSource 0x1000
381 #define bAD7InputRange 0x6000
382 #define bAD7Gain 0x38000
383 #define bAD7OutputCMMode 0x40000
384 #define bAD7InputCMMode 0x380000
385 #define bAD7Current 0xc00000
386 #define bRegulatorAdjust 0x7000000
387 #define bAD11PowerUpAtTx 0x1
388 #define bDA10PSAtTx 0x10
389 #define bAD11PowerUpAtRx 0x100
390 #define bDA10PSAtRx 0x1000
392 #define bCCKRxAGCFormat 0x200
394 #define bPSDFFTSamplepPoint 0xc000
395 #define bPSDAverageNum 0x3000
396 #define bIQPathControl 0xc00
397 #define bPSDFreq 0x3ff
398 #define bPSDAntennaPath 0x30
399 #define bPSDIQSwitch 0x40
400 #define bPSDRxTrigger 0x400000
401 #define bPSDTxTrigger 0x80000000
402 #define bPSDSineToneScale 0x7f000000
403 #define bPSDReport 0xffff
405 //page-9
406 #define bOFDMTxSC 0x30000000
407 #define bCCKTxOn 0x1
408 #define bOFDMTxOn 0x2
409 #define bDebugPage 0xfff //reset debug page and also HWord, LWord
410 #define bDebugItem 0xff //reset debug page and LWord
411 #define bAntL 0x10
412 #define bAntNonHT 0x100
413 #define bAntHT1 0x1000
414 #define bAntHT2 0x10000
415 #define bAntHT1S1 0x100000
416 #define bAntNonHTS1 0x1000000
418 //page-a
419 #define bCCKBBMode 0x3
420 #define bCCKTxPowerSaving 0x80
421 #define bCCKRxPowerSaving 0x40
422 #define bCCKSideBand 0x10
423 #define bCCKScramble 0x8
424 #define bCCKAntDiversity 0x8000
425 #define bCCKCarrierRecovery 0x4000
426 #define bCCKTxRate 0x3000
427 #define bCCKDCCancel 0x0800
428 #define bCCKISICancel 0x0400
429 #define bCCKMatchFilter 0x0200
430 #define bCCKEqualizer 0x0100
431 #define bCCKPreambleDetect 0x800000
432 #define bCCKFastFalseCCA 0x400000
433 #define bCCKChEstStart 0x300000
434 #define bCCKCCACount 0x080000
435 #define bCCKcs_lim 0x070000
436 #define bCCKBistMode 0x80000000
437 #define bCCKCCAMask 0x40000000
438 #define bCCKTxDACPhase 0x4
439 #define bCCKRxADCPhase 0x20000000 //r_rx_clk
440 #define bCCKr_cp_mode0 0x0100
441 #define bCCKTxDCOffset 0xf0
442 #define bCCKRxDCOffset 0xf
443 #define bCCKCCAMode 0xc000
444 #define bCCKFalseCS_lim 0x3f00
445 #define bCCKCS_ratio 0xc00000
446 #define bCCKCorgBit_sel 0x300000
447 #define bCCKPD_lim 0x0f0000
448 #define bCCKNewCCA 0x80000000
449 #define bCCKRxHPofIG 0x8000
450 #define bCCKRxIG 0x7f00
451 #define bCCKLNAPolarity 0x800000
452 #define bCCKRx1stGain 0x7f0000
453 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
454 #define bCCKRxAGCSatLevel 0x1f000000
455 #define bCCKRxAGCSatCount 0xe0
456 #define bCCKRxRFSettle 0x1f //AGCsamp_dly
457 #define bCCKFixedRxAGC 0x8000
458 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
459 #define bCCKAntennaPolarity 0x2000
460 #define bCCKTxFilterType 0x0c00
461 #define bCCKRxAGCReportType 0x0300
462 #define bCCKRxDAGCEn 0x80000000
463 #define bCCKRxDAGCPeriod 0x20000000
464 #define bCCKRxDAGCSatLevel 0x1f000000
465 #define bCCKTimingRecovery 0x800000
466 #define bCCKTxC0 0x3f0000
467 #define bCCKTxC1 0x3f000000
468 #define bCCKTxC2 0x3f
469 #define bCCKTxC3 0x3f00
470 #define bCCKTxC4 0x3f0000
471 #define bCCKTxC5 0x3f000000
472 #define bCCKTxC6 0x3f
473 #define bCCKTxC7 0x3f00
474 #define bCCKDebugPort 0xff0000
475 #define bCCKDACDebug 0x0f000000
476 #define bCCKFalseAlarmEnable 0x8000
477 #define bCCKFalseAlarmRead 0x4000
478 #define bCCKTRSSI 0x7f
479 #define bCCKRxAGCReport 0xfe
480 #define bCCKRxReport_AntSel 0x80000000
481 #define bCCKRxReport_MFOff 0x40000000
482 #define bCCKRxRxReport_SQLoss 0x20000000
483 #define bCCKRxReport_Pktloss 0x10000000
484 #define bCCKRxReport_Lockedbit 0x08000000
485 #define bCCKRxReport_RateError 0x04000000
486 #define bCCKRxReport_RxRate 0x03000000
487 #define bCCKRxFACounterLower 0xff
488 #define bCCKRxFACounterUpper 0xff000000
489 #define bCCKRxHPAGCStart 0xe000
490 #define bCCKRxHPAGCFinal 0x1c00
492 #define bCCKRxFalseAlarmEnable 0x8000
493 #define bCCKFACounterFreeze 0x4000
495 #define bCCKTxPathSel 0x10000000
496 #define bCCKDefaultRxPath 0xc000000
497 #define bCCKOptionRxPath 0x3000000
499 //page c
500 #define bNumOfSTF 0x3
501 #define bShift_L 0xc0
502 #define bGI_TH 0xc
503 #define bRxPathA 0x1
504 #define bRxPathB 0x2
505 #define bRxPathC 0x4
506 #define bRxPathD 0x8
507 #define bTxPathA 0x1
508 #define bTxPathB 0x2
509 #define bTxPathC 0x4
510 #define bTxPathD 0x8
511 #define bTRSSIFreq 0x200
512 #define bADCBackoff 0x3000
513 #define bDFIRBackoff 0xc000
514 #define bTRSSILatchPhase 0x10000
515 #define bRxIDCOffset 0xff
516 #define bRxQDCOffset 0xff00
517 #define bRxDFIRMode 0x1800000
518 #define bRxDCNFType 0xe000000
519 #define bRXIQImb_A 0x3ff
520 #define bRXIQImb_B 0xfc00
521 #define bRXIQImb_C 0x3f0000
522 #define bRXIQImb_D 0xffc00000
523 #define bDC_dc_Notch 0x60000
524 #define bRxNBINotch 0x1f000000
525 #define bPD_TH 0xf
526 #define bPD_TH_Opt2 0xc000
527 #define bPWED_TH 0x700
528 #define bIfMF_Win_L 0x800
529 #define bPD_Option 0x1000
530 #define bMF_Win_L 0xe000
531 #define bBW_Search_L 0x30000
532 #define bwin_enh_L 0xc0000
533 #define bBW_TH 0x700000
534 #define bED_TH2 0x3800000
535 #define bBW_option 0x4000000
536 #define bRatio_TH 0x18000000
537 #define bWindow_L 0xe0000000
538 #define bSBD_Option 0x1
539 #define bFrame_TH 0x1c
540 #define bFS_Option 0x60
541 #define bDC_Slope_check 0x80
542 #define bFGuard_Counter_DC_L 0xe00
543 #define bFrame_Weight_Short 0x7000
544 #define bSub_Tune 0xe00000
545 #define bFrame_DC_Length 0xe000000
546 #define bSBD_start_offset 0x30000000
547 #define bFrame_TH_2 0x7
548 #define bFrame_GI2_TH 0x38
549 #define bGI2_Sync_en 0x40
550 #define bSarch_Short_Early 0x300
551 #define bSarch_Short_Late 0xc00
552 #define bSarch_GI2_Late 0x70000
553 #define bCFOAntSum 0x1
554 #define bCFOAcc 0x2
555 #define bCFOStartOffset 0xc
556 #define bCFOLookBack 0x70
557 #define bCFOSumWeight 0x80
558 #define bDAGCEnable 0x10000
559 #define bTXIQImb_A 0x3ff
560 #define bTXIQImb_B 0xfc00
561 #define bTXIQImb_C 0x3f0000
562 #define bTXIQImb_D 0xffc00000
563 #define bTxIDCOffset 0xff
564 #define bTxQDCOffset 0xff00
565 #define bTxDFIRMode 0x10000
566 #define bTxPesudoNoiseOn 0x4000000
567 #define bTxPesudoNoise_A 0xff
568 #define bTxPesudoNoise_B 0xff00
569 #define bTxPesudoNoise_C 0xff0000
570 #define bTxPesudoNoise_D 0xff000000
571 #define bCCADropOption 0x20000
572 #define bCCADropThres 0xfff00000
573 #define bEDCCA_H 0xf
574 #define bEDCCA_L 0xf0
575 #define bLambda_ED 0x300
576 #define bRxInitialGain 0x7f
577 #define bRxAntDivEn 0x80
578 #define bRxAGCAddressForLNA 0x7f00
579 #define bRxHighPowerFlow 0x8000
580 #define bRxAGCFreezeThres 0xc0000
581 #define bRxFreezeStep_AGC1 0x300000
582 #define bRxFreezeStep_AGC2 0xc00000
583 #define bRxFreezeStep_AGC3 0x3000000
584 #define bRxFreezeStep_AGC0 0xc000000
585 #define bRxRssi_Cmp_En 0x10000000
586 #define bRxQuickAGCEn 0x20000000
587 #define bRxAGCFreezeThresMode 0x40000000
588 #define bRxOverFlowCheckType 0x80000000
589 #define bRxAGCShift 0x7f
590 #define bTRSW_Tri_Only 0x80
591 #define bPowerThres 0x300
592 #define bRxAGCEn 0x1
593 #define bRxAGCTogetherEn 0x2
594 #define bRxAGCMin 0x4
595 #define bRxHP_Ini 0x7
596 #define bRxHP_TRLNA 0x70
597 #define bRxHP_RSSI 0x700
598 #define bRxHP_BBP1 0x7000
599 #define bRxHP_BBP2 0x70000
600 #define bRxHP_BBP3 0x700000
601 #define bRSSI_H 0x7f0000 //the threshold for high power
602 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
603 #define bRxSettle_TRSW 0x7
604 #define bRxSettle_LNA 0x38
605 #define bRxSettle_RSSI 0x1c0
606 #define bRxSettle_BBP 0xe00
607 #define bRxSettle_RxHP 0x7000
608 #define bRxSettle_AntSW_RSSI 0x38000
609 #define bRxSettle_AntSW 0xc0000
610 #define bRxProcessTime_DAGC 0x300000
611 #define bRxSettle_HSSI 0x400000
612 #define bRxProcessTime_BBPPW 0x800000
613 #define bRxAntennaPowerShift 0x3000000
614 #define bRSSITableSelect 0xc000000
615 #define bRxHP_Final 0x7000000
616 #define bRxHTSettle_BBP 0x7
617 #define bRxHTSettle_HSSI 0x8
618 #define bRxHTSettle_RxHP 0x70
619 #define bRxHTSettle_BBPPW 0x80
620 #define bRxHTSettle_Idle 0x300
621 #define bRxHTSettle_Reserved 0x1c00
622 #define bRxHTRxHPEn 0x8000
623 #define bRxHTAGCFreezeThres 0x30000
624 #define bRxHTAGCTogetherEn 0x40000
625 #define bRxHTAGCMin 0x80000
626 #define bRxHTAGCEn 0x100000
627 #define bRxHTDAGCEn 0x200000
628 #define bRxHTRxHP_BBP 0x1c00000
629 #define bRxHTRxHP_Final 0xe0000000
630 #define bRxPWRatioTH 0x3
631 #define bRxPWRatioEn 0x4
632 #define bRxMFHold 0x3800
633 #define bRxPD_Delay_TH1 0x38
634 #define bRxPD_Delay_TH2 0x1c0
635 #define bRxPD_DC_COUNT_MAX 0x600
636 //#define bRxMF_Hold 0x3800
637 #define bRxPD_Delay_TH 0x8000
638 #define bRxProcess_Delay 0xf0000
639 #define bRxSearchrange_GI2_Early 0x700000
640 #define bRxFrame_Guard_Counter_L 0x3800000
641 #define bRxSGI_Guard_L 0xc000000
642 #define bRxSGI_Search_L 0x30000000
643 #define bRxSGI_TH 0xc0000000
644 #define bDFSCnt0 0xff
645 #define bDFSCnt1 0xff00
646 #define bDFSFlag 0xf0000
648 #define bMFWeightSum 0x300000
649 #define bMinIdxTH 0x7f000000
651 #define bDAFormat 0x40000
653 #define bTxChEmuEnable 0x01000000
655 #define bTRSWIsolation_A 0x7f
656 #define bTRSWIsolation_B 0x7f00
657 #define bTRSWIsolation_C 0x7f0000
658 #define bTRSWIsolation_D 0x7f000000
660 #define bExtLNAGain 0x7c00
662 //page d
663 #define bSTBCEn 0x4
664 #define bAntennaMapping 0x10
665 #define bNss 0x20
666 #define bCFOAntSumD 0x200
667 #define bPHYCounterReset 0x8000000
668 #define bCFOReportGet 0x4000000
669 #define bOFDMContinueTx 0x10000000
670 #define bOFDMSingleCarrier 0x20000000
671 #define bOFDMSingleTone 0x40000000
672 //#define bRxPath1 0x01
673 //#define bRxPath2 0x02
674 //#define bRxPath3 0x04
675 //#define bRxPath4 0x08
676 //#define bTxPath1 0x10
677 //#define bTxPath2 0x20
678 #define bHTDetect 0x100
679 #define bCFOEn 0x10000
680 #define bCFOValue 0xfff00000
681 #define bSigTone_Re 0x3f
682 #define bSigTone_Im 0x7f00
683 #define bCounter_CCA 0xffff
684 #define bCounter_ParityFail 0xffff0000
685 #define bCounter_RateIllegal 0xffff
686 #define bCounter_CRC8Fail 0xffff0000
687 #define bCounter_MCSNoSupport 0xffff
688 #define bCounter_FastSync 0xffff
689 #define bShortCFO 0xfff
690 #define bShortCFOTLength 12 //total
691 #define bShortCFOFLength 11 //fraction
692 #define bLongCFO 0x7ff
693 #define bLongCFOTLength 11
694 #define bLongCFOFLength 11
695 #define bTailCFO 0x1fff
696 #define bTailCFOTLength 13
697 #define bTailCFOFLength 12
699 #define bmax_en_pwdB 0xffff
700 #define bCC_power_dB 0xffff0000
701 #define bnoise_pwdB 0xffff
702 #define bPowerMeasTLength 10
703 #define bPowerMeasFLength 3
704 #define bRx_HT_BW 0x1
705 #define bRxSC 0x6
706 #define bRx_HT 0x8
708 #define bNB_intf_det_on 0x1
709 #define bIntf_win_len_cfg 0x30
710 #define bNB_Intf_TH_cfg 0x1c0
712 #define bRFGain 0x3f
713 #define bTableSel 0x40
714 #define bTRSW 0x80
716 #define bRxSNR_A 0xff
717 #define bRxSNR_B 0xff00
718 #define bRxSNR_C 0xff0000
719 #define bRxSNR_D 0xff000000
720 #define bSNREVMTLength 8
721 #define bSNREVMFLength 1
723 #define bCSI1st 0xff
724 #define bCSI2nd 0xff00
725 #define bRxEVM1st 0xff0000
726 #define bRxEVM2nd 0xff000000
728 #define bSIGEVM 0xff
729 #define bPWDB 0xff00
730 #define bSGIEN 0x10000
732 #define bSFactorQAM1 0xf
733 #define bSFactorQAM2 0xf0
734 #define bSFactorQAM3 0xf00
735 #define bSFactorQAM4 0xf000
736 #define bSFactorQAM5 0xf0000
737 #define bSFactorQAM6 0xf0000
738 #define bSFactorQAM7 0xf00000
739 #define bSFactorQAM8 0xf000000
740 #define bSFactorQAM9 0xf0000000
741 #define bCSIScheme 0x100000
743 #define bNoiseLvlTopSet 0x3
744 #define bChSmooth 0x4
745 #define bChSmoothCfg1 0x38
746 #define bChSmoothCfg2 0x1c0
747 #define bChSmoothCfg3 0xe00
748 #define bChSmoothCfg4 0x7000
749 #define bMRCMode 0x800000
750 #define bTHEVMCfg 0x7000000
752 #define bLoopFitType 0x1
753 #define bUpdCFO 0x40
754 #define bUpdCFOOffData 0x80
755 #define bAdvUpdCFO 0x100
756 #define bAdvTimeCtrl 0x800
757 #define bUpdClko 0x1000
758 #define bFC 0x6000
759 #define bTrackingMode 0x8000
760 #define bPhCmpEnable 0x10000
761 #define bUpdClkoLTF 0x20000
762 #define bComChCFO 0x40000
763 #define bCSIEstiMode 0x80000
764 #define bAdvUpdEqz 0x100000
765 #define bUChCfg 0x7000000
766 #define bUpdEqz 0x8000000
768 //page e
769 #define bTxAGCRate18_06 0x7f7f7f7f
770 #define bTxAGCRate54_24 0x7f7f7f7f
771 #define bTxAGCRateMCS32 0x7f
772 #define bTxAGCRateCCK 0x7f00
773 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
774 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
775 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
776 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
779 //Rx Pseduo noise
780 #define bRxPesudoNoiseOn 0x20000000
781 #define bRxPesudoNoise_A 0xff
782 #define bRxPesudoNoise_B 0xff00
783 #define bRxPesudoNoise_C 0xff0000
784 #define bRxPesudoNoise_D 0xff000000
785 #define bPesudoNoiseState_A 0xffff
786 #define bPesudoNoiseState_B 0xffff0000
787 #define bPesudoNoiseState_C 0xffff
788 #define bPesudoNoiseState_D 0xffff0000
790 //RF
791 //Zebra1
792 #define bZebra1_HSSIEnable 0x8
793 #define bZebra1_TRxControl 0xc00
794 #define bZebra1_TRxGainSetting 0x07f
795 #define bZebra1_RxCorner 0xc00
796 #define bZebra1_TxChargePump 0x38
797 #define bZebra1_RxChargePump 0x7
798 #define bZebra1_ChannelNum 0xf80
799 #define bZebra1_TxLPFBW 0x400
800 #define bZebra1_RxLPFBW 0x600
802 //Zebra4
803 #define bRTL8256RegModeCtrl1 0x100
804 #define bRTL8256RegModeCtrl0 0x40
805 #define bRTL8256_TxLPFBW 0x18
806 #define bRTL8256_RxLPFBW 0x600
808 //RTL8258
809 #define bRTL8258_TxLPFBW 0xc
810 #define bRTL8258_RxLPFBW 0xc00
811 #define bRTL8258_RSSILPFBW 0xc0
813 //byte endable for sb_write
814 #define bByte0 0x1
815 #define bByte1 0x2
816 #define bByte2 0x4
817 #define bByte3 0x8
818 #define bWord0 0x3
819 #define bWord1 0xc
820 #define bDWord 0xf
822 //for PutRegsetting & GetRegSetting BitMask
823 #define bMaskByte0 0xff
824 #define bMaskByte1 0xff00
825 #define bMaskByte2 0xff0000
826 #define bMaskByte3 0xff000000
827 #define bMaskHWord 0xffff0000
828 #define bMaskLWord 0x0000ffff
829 #define bMaskDWord 0xffffffff
831 //for PutRFRegsetting & GetRFRegSetting BitMask
832 #define bMask12Bits 0xfff
834 #define bEnable 0x1
835 #define bDisable 0x0
837 #define LeftAntenna 0x0
838 #define RightAntenna 0x1
840 #define tCheckTxStatus 500 //500ms
841 #define tUpdateRxCounter 100 //100ms
843 #define rateCCK 0
844 #define rateOFDM 1
845 #define rateHT 2
847 //define Register-End
848 #define bPMAC_End 0x1ff
849 #define bFPGAPHY0_End 0x8ff
850 #define bFPGAPHY1_End 0x9ff
851 #define bCCKPHY0_End 0xaff
852 #define bOFDMPHY0_End 0xcff
853 #define bOFDMPHY1_End 0xdff
855 //define max debug item in each debug page
856 //#define bMaxItem_FPGA_PHY0 0x9
857 //#define bMaxItem_FPGA_PHY1 0x3
858 //#define bMaxItem_PHY_11B 0x16
859 //#define bMaxItem_OFDM_PHY0 0x29
860 //#define bMaxItem_OFDM_PHY1 0x0
862 #define bPMACControl 0x0
863 #define bWMACControl 0x1
864 #define bWNICControl 0x2
866 #define PathA 0x0
867 #define PathB 0x1
868 #define PathC 0x2
869 #define PathD 0x3
871 #define rRTL8256RxMixerPole 0xb
872 #define bZebraRxMixerPole 0x6
873 #define rRTL8256TxBBOPBias 0x9
874 #define bRTL8256TxBBOPBias 0x400
875 #define rRTL8256TxBBBW 19
876 #define bRTL8256TxBBBW 0x18
878 #endif //__INC_HAL8190PCIPHYREG_H