drivers/staging/winbond/wb35rx_s.h

   1 //============================================================================
   2 // wb35rx.h --
   3 //============================================================================
   4
   5 // Definition for this module used
   6 #define MAX_USB_RX_BUFFER       4096    // This parameter must be 4096 931130.4.f
   7
   8 #define MAX_USB_RX_BUFFER_NUMBER        ETHERNET_RX_DESCRIPTORS         // Maximum 254, 255 is RESERVED ID
   9 #define RX_INTERFACE                            0       // Interface 1
  10 #define RX_PIPE                                         2       // Pipe 3
  11 #define MAX_PACKET_SIZE                         1600 //1568     // 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g
  12 #define RX_END_TAG                                      0x0badbeef
  13
  14
  15 //====================================
  16 // Internal variable for module
  17 //====================================
  18 struct wb35_rx {
  19         u32                     ByteReceived;// For calculating throughput of BulkIn
  20         atomic_t                RxFireCounter;// Does Wb35Rx module fire?
  21
  22         u8      RxBuffer[ MAX_USB_RX_BUFFER_NUMBER ][ ((MAX_USB_RX_BUFFER+3) & ~0x03 ) ];
  23         u16     RxBufferSize[ ((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01) ];
  24         u8      RxOwner[ ((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03 ) ];//Ownership of buffer  0: SW 1:HW
  25
  26         u32     RxProcessIndex;//The next index to process
  27         u32     RxBufferId;
  28         u32     EP3vm_state;
  29
  30         u32     rx_halt; // For VM stopping
  31
  32         u16     MoreDataSize;
  33         u16     PacketSize;
  34
  35         u32     CurrentRxBufferId; // For complete routine usage
  36         u32     Rx3UrbCancel;
  37
  38         u32     LastR1; // For RSSI reporting
  39         struct urb *                            RxUrb;
  40         u32             Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count
  41
  42         int             EP3VM_status;
  43         u8 *    pDRx;
  44 };