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mm-only debug patch...
[mmotm.git] / drivers / staging / winbond / wbhal_s.h
blob372a05e3021accca3ced9a364d8ee505c8766ff4
1 #ifndef __WINBOND_WBHAL_S_H
2 #define __WINBOND_WBHAL_S_H
3
4 #include <linux/types.h>
5 #include <linux/if_ether.h> /* for ETH_ALEN */
6
7 //[20040722 WK]
8 #define HAL_LED_SET_MASK 0x001c //20060901 Extend
9 #define HAL_LED_SET_SHIFT 2
10
11 //supported RF type
12 #define RF_MAXIM_2825 0
13 #define RF_MAXIM_2827 1
14 #define RF_MAXIM_2828 2
15 #define RF_MAXIM_2829 3
16 #define RF_MAXIM_V1 15
17 #define RF_AIROHA_2230 16
18 #define RF_AIROHA_7230 17
19 #define RF_AIROHA_2230S 18 // 20060420 Add this
20 // #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD
21 #define RF_WB_242 33
22 #define RF_WB_242_1 34 // 20060619.5 Add
23 #define RF_DECIDE_BY_INF 255
24
25 //----------------------------------------------------------------
26 // The follow define connect to upper layer
27 // User must modify for connection between HAL and upper layer
28 //----------------------------------------------------------------
29
30
31
32
33 /////////////////////////////////////////////////////////////////////////////////////////////////////
34 //================================================================================================
35 // Common define
36 //================================================================================================
37 #define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
38
39 // Scan interval
40 #define SCAN_MAX_CHNL_TIME (50)
41
42 // For TxL2 Frame typr recognise
43 #define FRAME_TYPE_802_3_DATA 0
44 #define FRAME_TYPE_802_11_MANAGEMENT 1
45 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
46 #define FRAME_TYPE_802_11_CONTROL 3
47 #define FRAME_TYPE_802_11_DATA 4
48 #define FRAME_TYPE_PROMISCUOUS 5
49
50 // The follow definition is used for convert the frame--------------------
51 #define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
52 #define DOT_3_TYPE_OFFSET 12
53 #define DOT_11_MAC_HEADER_SIZE 24
54 #define DOT_11_SNAP_SIZE 6
55 #define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin.
56 #define DEFAULT_SIFSTIME 10
57 #define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
58 #define DEFAULT_MSDU_LIFE_TIME 0xffff
59
60 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48)
61 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24)
62 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6)
63 #define Tsym 4
64
65 // Frame Type of Bits (2, 3)---------------------------------------------
66 #define MAC_TYPE_MANAGEMENT 0x00
67 #define MAC_TYPE_CONTROL 0x04
68 #define MAC_TYPE_DATA 0x08
69 #define MASK_FRAGMENT_NUMBER 0x000F
70 #define SEQUENCE_NUMBER_SHIFT 4
71
72 #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
73 #define HAL_WOL_TYPE_MAGIC_PACKET 0x02
74
75 // 20040106 ADDED
76 #define HAL_KEYTYPE_WEP40 0
77 #define HAL_KEYTYPE_WEP104 1
78 #define HAL_KEYTYPE_TKIP 2 // 128 bit key
79 #define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key
80
81 // For VM state
82 enum {
83 VM_STOP = 0,
84 VM_RUNNING,
85 VM_COMPLETED
86 };
87
88 //-----------------------------------------------------
89 // Normal Key table format
90 //-----------------------------------------------------
91 // The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
92 #define MAX_KEY_TABLE 24 // 24 entry for storing key data
93 #define GROUP_KEY_START_INDEX 4
94 #define MAPPING_KEY_START_INDEX 8
95
96 //--------------------------------------------------------
97 // Descriptor
98 //--------------------------------------------------------
99 #define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2
100 //#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
101 #define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian
102 //#define FLAG_ERROR_RX_MASK 0x00000c3f
103 //#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
104 //Don't care replay error,
105 //it is handled by S/W
106 #define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian
107
108 #define FLAG_BAND_RX_MASK 0x10000000 //Bit 28
109
110 typedef struct _R00_DESCRIPTOR
111 {
112 union
113 {
114 u32 value;
115 #ifdef _BIG_ENDIAN_ //20060926 anson's endian
116 struct
117 {
118 u32 R00_packet_or_buffer_status:1;
119 u32 R00_packet_in_fifo:1;
120 u32 R00_RESERVED:2;
121 u32 R00_receive_byte_count:12;
122 u32 R00_receive_time_index:16;
123 };
124 #else
125 struct
126 {
127 u32 R00_receive_time_index:16;
128 u32 R00_receive_byte_count:12;
129 u32 R00_RESERVED:2;
130 u32 R00_packet_in_fifo:1;
131 u32 R00_packet_or_buffer_status:1;
132 };
133 #endif
134 };
135 } R00_DESCRIPTOR, *PR00_DESCRIPTOR;
136
137 typedef struct _T00_DESCRIPTOR
138 {
139 union
140 {
141 u32 value;
142 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
143 struct
144 {
145 u32 T00_first_mpdu:1; // for hardware use
146 u32 T00_last_mpdu:1; // for hardware use
147 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
148 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
149 u32 T00_RESERVED_ID:2;//3 bit ID reserved
150 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
151 u32 T00_RESERVED:4;
152 u32 T00_header_length:6;
153 u32 T00_frame_length:12;
154 };
155 #else
156 struct
157 {
158 u32 T00_frame_length:12;
159 u32 T00_header_length:6;
160 u32 T00_RESERVED:4;
161 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
162 u32 T00_RESERVED_ID:2;//3 bit ID reserved
163 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
164 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
165 u32 T00_last_mpdu:1; // for hardware use
166 u32 T00_first_mpdu:1; // for hardware use
167 };
168 #endif
169 };
170 } T00_DESCRIPTOR, *PT00_DESCRIPTOR;
171
172 typedef struct _R01_DESCRIPTOR
173 {
174 union
175 {
176 u32 value;
177 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
178 struct
179 {
180 u32 R01_RESERVED:3;
181 u32 R01_mod_type:1;
182 u32 R01_pre_type:1;
183 u32 R01_data_rate:3;
184 u32 R01_AGC_state:8;
185 u32 R01_LNA_state:2;
186 u32 R01_decryption_method:2;
187 u32 R01_mic_error:1;
188 u32 R01_replay:1;
189 u32 R01_broadcast_frame:1;
190 u32 R01_multicast_frame:1;
191 u32 R01_directed_frame:1;
192 u32 R01_receive_frame_antenna_selection:1;
193 u32 R01_frame_receive_during_atim_window:1;
194 u32 R01_protocol_version_error:1;
195 u32 R01_authentication_frame_icv_error:1;
196 u32 R01_null_key_to_authentication_frame:1;
197 u32 R01_icv_error:1;
198 u32 R01_crc_error:1;
199 };
200 #else
201 struct
202 {
203 u32 R01_crc_error:1;
204 u32 R01_icv_error:1;
205 u32 R01_null_key_to_authentication_frame:1;
206 u32 R01_authentication_frame_icv_error:1;
207 u32 R01_protocol_version_error:1;
208 u32 R01_frame_receive_during_atim_window:1;
209 u32 R01_receive_frame_antenna_selection:1;
210 u32 R01_directed_frame:1;
211 u32 R01_multicast_frame:1;
212 u32 R01_broadcast_frame:1;
213 u32 R01_replay:1;
214 u32 R01_mic_error:1;
215 u32 R01_decryption_method:2;
216 u32 R01_LNA_state:2;
217 u32 R01_AGC_state:8;
218 u32 R01_data_rate:3;
219 u32 R01_pre_type:1;
220 u32 R01_mod_type:1;
221 u32 R01_RESERVED:3;
222 };
223 #endif
224 };
225 } R01_DESCRIPTOR, *PR01_DESCRIPTOR;
226
227 typedef struct _T01_DESCRIPTOR
228 {
229 union
230 {
231 u32 value;
232 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
233 struct
234 {
235 u32 T01_rts_cts_duration:16;
236 u32 T01_fall_back_rate:3;
237 u32 T01_add_rts:1;
238 u32 T01_add_cts:1;
239 u32 T01_modulation_type:1;
240 u32 T01_plcp_header_length:1;
241 u32 T01_transmit_rate:3;
242 u32 T01_wep_id:2;
243 u32 T01_add_challenge_text:1;
244 u32 T01_inhibit_crc:1;
245 u32 T01_loop_back_wep_mode:1;
246 u32 T01_retry_abort_ebable:1;
247 };
248 #else
249 struct
250 {
251 u32 T01_retry_abort_ebable:1;
252 u32 T01_loop_back_wep_mode:1;
253 u32 T01_inhibit_crc:1;
254 u32 T01_add_challenge_text:1;
255 u32 T01_wep_id:2;
256 u32 T01_transmit_rate:3;
257 u32 T01_plcp_header_length:1;
258 u32 T01_modulation_type:1;
259 u32 T01_add_cts:1;
260 u32 T01_add_rts:1;
261 u32 T01_fall_back_rate:3;
262 u32 T01_rts_cts_duration:16;
263 };
264 #endif
265 };
266 } T01_DESCRIPTOR, *PT01_DESCRIPTOR;
267
268 typedef struct _T02_DESCRIPTOR
269 {
270 union
271 {
272 u32 value;
273 #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian
274 struct
275 {
276 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
277 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
278 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
279 u32 T02_Tx_PktID:4;
280 u32 T02_MPDU_Cnt:4;
281 u32 T02_RTS_Cnt:4;
282 u32 T02_RESERVED:7;
283 u32 T02_transmit_complete:1;
284 u32 T02_transmit_abort_due_to_TBTT:1;
285 u32 T02_effective_transmission_rate:1;
286 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
287 u32 T02_discard_due_to_null_wep_key:1;
288 u32 T02_RESERVED_1:1;
289 u32 T02_out_of_MaxTxMSDULiftTime:1;
290 u32 T02_transmit_abort:1;
291 u32 T02_transmit_fail:1;
292 };
293 #else
294 struct
295 {
296 u32 T02_transmit_fail:1;
297 u32 T02_transmit_abort:1;
298 u32 T02_out_of_MaxTxMSDULiftTime:1;
299 u32 T02_RESERVED_1:1;
300 u32 T02_discard_due_to_null_wep_key:1;
301 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
302 u32 T02_effective_transmission_rate:1;
303 u32 T02_transmit_abort_due_to_TBTT:1;
304 u32 T02_transmit_complete:1;
305 u32 T02_RESERVED:7;
306 u32 T02_RTS_Cnt:4;
307 u32 T02_MPDU_Cnt:4;
308 u32 T02_Tx_PktID:4;
309 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
310 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
311 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
312 };
313 #endif
314 };
315 } T02_DESCRIPTOR, *PT02_DESCRIPTOR;
316
317 struct wb35_descriptor { // Skip length = 8 DWORD
318 // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
319 u8 Descriptor_ID;
320 //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
321 u8 RESERVED[3];
322
323 u16 FragmentThreshold;
324 u8 InternalUsed;//Only can be used by operation of descriptor definition
325 u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame
326
327 u8 PreambleMode;// 0: short 1:long
328 u8 TxRate;
329 u8 FragmentCount;
330 u8 EapFix; // For speed up key install
331
332 // For R00 and T00 ----------------------------------------------
333 union
334 {
335 R00_DESCRIPTOR R00;
336 T00_DESCRIPTOR T00;
337 };
338
339 // For R01 and T01 ----------------------------------------------
340 union
341 {
342 R01_DESCRIPTOR R01;
343 T01_DESCRIPTOR T01;
344 };
345
346 // For R02 and T02 ----------------------------------------------
347 union
348 {
349 u32 R02;
350 T02_DESCRIPTOR T02;
351 };
352
353 // For R03 and T03 ----------------------------------------------
354 // For software used
355 union
356 {
357 u32 R03;
358 u32 T03;
359 struct
360 {
361 u8 buffer_number;
362 u8 buffer_start_index;
363 u16 buffer_total_size;
364 };
365 };
366
367 // For storing the buffer
368 u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
369 void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
370
371 };
372
373
374 #define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds
375
376 #define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA
377 #define MAX_RF_PARAMETER 32
378
379 typedef struct _TXVGA_FOR_50 {
380 u8 ChanNo;
381 u8 TxVgaValue;
382 } TXVGA_FOR_50;
383
384
385 //=====================================================================
386 // Device related include
387 //=====================================================================
388
389 #include "wbusb_s.h"
390 #include "wb35reg_s.h"
391 #include "wb35tx_s.h"
392 #include "wb35rx_s.h"
393
394 // For Hal using ==================================================================
395 struct hw_data {
396 // For compatible with 33
397 u32 revision;
398 u32 BB3c_cal; // The value for Tx calibration comes from EEPROM
399 u32 BB54_cal; // The value for Rx calibration comes from EEPROM
400
401
402 // For surprise remove
403 u32 SurpriseRemove; // 0: Normal 1: Surprise remove
404 u8 IsKeyPreSet;
405 u8 CalOneTime; // 20060630.1
406
407 u8 VCO_trim;
408
409 // For Fix 1'st DMA bug
410 u32 FragCount;
411 u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
412
413 //===============================================
414 // Definition for MAC address
415 //===============================================
416 u8 PermanentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment
417 u8 CurrentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment
418
419 //=====================================================================
420 // Definition for 802.11
421 //=====================================================================
422 u8 *bssid_pointer; // Used by hal_get_bssid for return value
423 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
424 u8 ssid[32];// maximum ssid length is 32 byte
425
426 u16 AID;
427 u8 ssid_length;
428 u8 Channel;
429
430 u16 ListenInterval;
431 u16 CapabilityInformation;
432
433 u16 BeaconPeriod;
434 u16 ProbeDelay;
435
436 u8 bss_type;// 0: IBSS_NET or 1:ESS_NET
437 u8 preamble;// 0: short preamble, 1: long preamble
438 u8 slot_time_select;// 9 or 20 value
439 u8 phy_type;// Phy select
440
441 u32 phy_para[MAX_RF_PARAMETER];
442 u32 phy_number;
443
444 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
445 u32 CurrentRadioHw; // 20060825 0:On 1:Off
446
447 u8 *power_save_point; // Used by hal_get_power_save_mode for return value
448 u8 cwmin;
449 u8 desired_power_save;
450 u8 dtim;// Is running dtim
451 u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
452
453 u16 MaxReceiveLifeTime;
454 u16 FragmentThreshold;
455 u16 FragmentThreshold_tmp;
456 u16 cwmax;
457
458 u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
459 u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
460 u8 CurrentDefaultKeyIndex;
461 u32 CurrentDefaultKeyLength;
462
463 //========================================================================
464 // Variable for each module
465 //========================================================================
466 struct wb_usb WbUsb; // Need WbUsb.h
467 struct wb35_reg reg; // Need Wb35Reg.h
468 struct wb35_tx Wb35Tx; // Need Wb35Tx.h
469 struct wb35_rx Wb35Rx; // Need Wb35Rx.h
470
471 struct timer_list LEDTimer;// For LED
472
473 u32 LEDpoint;// For LED
474
475 u32 dto_tx_retry_count; // LA20040210_DTO kevin
476 u32 dto_tx_frag_count; // LA20040210_DTO kevin
477 u32 rx_ok_count[13]; // index=0: total rx ok
478 //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes
479 u32 rx_err_count[13]; // index=0: total rx err
480
481 //for Tx debug
482 u32 tx_TBTT_start_count;
483 u32 tx_ETR_count;
484 u32 tx_WepOn_false_count;
485 u32 tx_Null_key_count;
486 u32 tx_retry_count[8];
487
488 u8 PowerIndexFromEEPROM; // For 2412MHz
489 u8 power_index;
490 u8 IsWaitJoinComplete; // TRUE: set join request
491 u8 band;
492
493 u16 SoftwareSet;
494 u16 Reserved_s;
495
496 u32 IsInitOK; // 0: Driver starting 1: Driver init OK
497
498 // For Phy calibration
499 s32 iq_rsdl_gain_tx_d2;
500 s32 iq_rsdl_phase_tx_d2;
501 u32 txvga_setting_for_cal; // 20060703.1 Add
502
503 u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
504 u8 TxVgaFor24[16]; // Max is 14, 2 for alignment
505 TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
506
507 u16 Scan_Interval;
508 u16 RESERVED6;
509
510 // LED control
511 u32 LED_control;
512 // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
513 // Gray_Led
514 // For Led gray setting
515 // Led
516 // 0: normal control, LED behavior will decide by EEPROM setting
517 // 1: Turn off specific LED
518 // 2: Always on specific LED
519 // 3: slow blinking specific LED
520 // 4: fast blinking specific LED
521 // 5: WPS led control is set. Led0 is Red, Led1 id Green
522 // Led[1] is parameter for WPS LED mode
523 // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control
524
525 u32 LED_LinkOn; //Turn LED on control
526 u32 LED_Scanning; // Let LED in scan process control
527 u32 LED_Blinking; // Temp variable for shining
528 u32 RxByteCountLast;
529 u32 TxByteCountLast;
530
531 atomic_t SurpriseRemoveCount;
532
533 // For global timer
534 u32 time_count;//TICK_TIME_100ms 1 = 100ms
535
536 // For error recover
537 u32 HwStop;
538
539 // 20060828.1 for avoid AP disconnect
540 u32 NullPacketCount;
541
542 };
543
544 #endif
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