2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
119 module_param_named(debug
, musb_debug
, uint
, S_IRUGO
| S_IWUSR
);
120 MODULE_PARM_DESC(debug
, "Debug message level. Default = 0");
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
125 #define MUSB_VERSION "6.0"
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name
[] = MUSB_DRIVER_NAME
;
132 MODULE_DESCRIPTION(DRIVER_INFO
);
133 MODULE_AUTHOR(DRIVER_AUTHOR
);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME
);
138 /*-------------------------------------------------------------------------*/
140 static inline struct musb
*dev_to_musb(struct device
*dev
)
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev
));
146 return dev_get_drvdata(dev
);
150 /*-------------------------------------------------------------------------*/
152 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
155 * Load an endpoint's FIFO
157 void musb_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, const u8
*src
)
159 void __iomem
*fifo
= hw_ep
->fifo
;
163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
164 'T', hw_ep
->epnum
, fifo
, len
, src
);
166 /* we can't assume unaligned reads work */
167 if (likely((0x01 & (unsigned long) src
) == 0)) {
170 /* best case is 32bit-aligned source address */
171 if ((0x02 & (unsigned long) src
) == 0) {
173 writesl(fifo
, src
+ index
, len
>> 2);
174 index
+= len
& ~0x03;
177 musb_writew(fifo
, 0, *(u16
*)&src
[index
]);
182 writesw(fifo
, src
+ index
, len
>> 1);
183 index
+= len
& ~0x01;
187 musb_writeb(fifo
, 0, src
[index
]);
190 writesb(fifo
, src
, len
);
195 * Unload an endpoint's FIFO
197 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
199 void __iomem
*fifo
= hw_ep
->fifo
;
201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
202 'R', hw_ep
->epnum
, fifo
, len
, dst
);
204 /* we can't assume unaligned writes work */
205 if (likely((0x01 & (unsigned long) dst
) == 0)) {
208 /* best case is 32bit-aligned destination address */
209 if ((0x02 & (unsigned long) dst
) == 0) {
211 readsl(fifo
, dst
, len
>> 2);
215 *(u16
*)&dst
[index
] = musb_readw(fifo
, 0);
220 readsw(fifo
, dst
, len
>> 1);
225 dst
[index
] = musb_readb(fifo
, 0);
228 readsb(fifo
, dst
, len
);
232 #endif /* normal PIO */
235 /*-------------------------------------------------------------------------*/
237 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
238 static const u8 musb_test_packet
[53] = {
239 /* implicit SYNC then DATA0 to start */
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
247 /* JJJJJJJKKKKKKK x8 */
248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
251 /* JKKKKKKK x10, JK */
252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
254 /* implicit CRC16 then EOP to end */
257 void musb_load_testpacket(struct musb
*musb
)
259 void __iomem
*regs
= musb
->endpoints
[0].regs
;
261 musb_ep_select(musb
->mregs
, 0);
262 musb_write_fifo(musb
->control_ep
,
263 sizeof(musb_test_packet
), musb_test_packet
);
264 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_TXPKTRDY
);
267 /*-------------------------------------------------------------------------*/
269 const char *otg_state_string(struct musb
*musb
)
271 switch (musb
->xceiv
->state
) {
272 case OTG_STATE_A_IDLE
: return "a_idle";
273 case OTG_STATE_A_WAIT_VRISE
: return "a_wait_vrise";
274 case OTG_STATE_A_WAIT_BCON
: return "a_wait_bcon";
275 case OTG_STATE_A_HOST
: return "a_host";
276 case OTG_STATE_A_SUSPEND
: return "a_suspend";
277 case OTG_STATE_A_PERIPHERAL
: return "a_peripheral";
278 case OTG_STATE_A_WAIT_VFALL
: return "a_wait_vfall";
279 case OTG_STATE_A_VBUS_ERR
: return "a_vbus_err";
280 case OTG_STATE_B_IDLE
: return "b_idle";
281 case OTG_STATE_B_SRP_INIT
: return "b_srp_init";
282 case OTG_STATE_B_PERIPHERAL
: return "b_peripheral";
283 case OTG_STATE_B_WAIT_ACON
: return "b_wait_acon";
284 case OTG_STATE_B_HOST
: return "b_host";
285 default: return "UNDEFINED";
289 #ifdef CONFIG_USB_MUSB_OTG
292 * Handles OTG hnp timeouts, such as b_ase0_brst
294 void musb_otg_timer_func(unsigned long data
)
296 struct musb
*musb
= (struct musb
*)data
;
299 spin_lock_irqsave(&musb
->lock
, flags
);
300 switch (musb
->xceiv
->state
) {
301 case OTG_STATE_B_WAIT_ACON
:
302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
303 musb_g_disconnect(musb
);
304 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
307 case OTG_STATE_A_SUSPEND
:
308 case OTG_STATE_A_WAIT_BCON
:
309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb
));
310 musb_set_vbus(musb
, 0);
311 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VFALL
;
314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb
));
316 musb
->ignore_disconnect
= 0;
317 spin_unlock_irqrestore(&musb
->lock
, flags
);
321 * Stops the HNP transition. Caller must take care of locking.
323 void musb_hnp_stop(struct musb
*musb
)
325 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
326 void __iomem
*mbase
= musb
->mregs
;
329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb
));
331 switch (musb
->xceiv
->state
) {
332 case OTG_STATE_A_PERIPHERAL
:
333 musb_g_disconnect(musb
);
334 DBG(1, "HNP: back to %s\n", otg_state_string(musb
));
336 case OTG_STATE_B_HOST
:
337 DBG(1, "HNP: Disabling HR\n");
338 hcd
->self
.is_b_host
= 0;
339 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
341 reg
= musb_readb(mbase
, MUSB_POWER
);
342 reg
|= MUSB_POWER_SUSPENDM
;
343 musb_writeb(mbase
, MUSB_POWER
, reg
);
344 /* REVISIT: Start SESSION_REQUEST here? */
347 DBG(1, "HNP: Stopping in unknown state %s\n",
348 otg_state_string(musb
));
352 * When returning to A state after HNP, avoid hub_port_rebounce(),
353 * which cause occasional OPT A "Did not receive reset after connect"
356 musb
->port1_status
&=
357 ~(1 << USB_PORT_FEAT_C_CONNECTION
);
363 * Interrupt Service Routine to record USB "global" interrupts.
364 * Since these do not happen often and signify things of
365 * paramount importance, it seems OK to check them individually;
366 * the order of the tests is specified in the manual
368 * @param musb instance pointer
369 * @param int_usb register contents
374 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
378 static irqreturn_t
musb_stage0_irq(struct musb
*musb
, u8 int_usb
,
381 irqreturn_t handled
= IRQ_NONE
;
382 void __iomem
*mbase
= musb
->mregs
;
384 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power
, devctl
,
387 /* in host mode, the peripheral may issue remote wakeup.
388 * in peripheral mode, the host may resume the link.
389 * spurious RESUME irqs happen too, paired with SUSPEND.
391 if (int_usb
& MUSB_INTR_RESUME
) {
392 handled
= IRQ_HANDLED
;
393 DBG(3, "RESUME (%s)\n", otg_state_string(musb
));
395 if (devctl
& MUSB_DEVCTL_HM
) {
396 #ifdef CONFIG_USB_MUSB_HDRC_HCD
397 switch (musb
->xceiv
->state
) {
398 case OTG_STATE_A_SUSPEND
:
399 /* remote wakeup? later, GetPortStatus
400 * will stop RESUME signaling
403 if (power
& MUSB_POWER_SUSPENDM
) {
405 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
406 DBG(2, "Spurious SUSPENDM\n");
410 power
&= ~MUSB_POWER_SUSPENDM
;
411 musb_writeb(mbase
, MUSB_POWER
,
412 power
| MUSB_POWER_RESUME
);
414 musb
->port1_status
|=
415 (USB_PORT_STAT_C_SUSPEND
<< 16)
416 | MUSB_PORT_STAT_RESUME
;
417 musb
->rh_timer
= jiffies
418 + msecs_to_jiffies(20);
420 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
422 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
424 case OTG_STATE_B_WAIT_ACON
:
425 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
430 WARNING("bogus %s RESUME (%s)\n",
432 otg_state_string(musb
));
436 switch (musb
->xceiv
->state
) {
437 #ifdef CONFIG_USB_MUSB_HDRC_HCD
438 case OTG_STATE_A_SUSPEND
:
439 /* possibly DISCONNECT is upcoming */
440 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
441 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
444 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
445 case OTG_STATE_B_WAIT_ACON
:
446 case OTG_STATE_B_PERIPHERAL
:
447 /* disconnect while suspended? we may
448 * not get a disconnect irq...
450 if ((devctl
& MUSB_DEVCTL_VBUS
)
451 != (3 << MUSB_DEVCTL_VBUS_SHIFT
)
453 musb
->int_usb
|= MUSB_INTR_DISCONNECT
;
454 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
459 case OTG_STATE_B_IDLE
:
460 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
464 WARNING("bogus %s RESUME (%s)\n",
466 otg_state_string(musb
));
471 #ifdef CONFIG_USB_MUSB_HDRC_HCD
472 /* see manual for the order of the tests */
473 if (int_usb
& MUSB_INTR_SESSREQ
) {
474 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb
));
476 /* IRQ arrives from ID pin sense or (later, if VBUS power
477 * is removed) SRP. responses are time critical:
478 * - turn on VBUS (with silicon-specific mechanism)
479 * - go through A_WAIT_VRISE
480 * - ... to A_WAIT_BCON.
481 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
483 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
484 musb
->ep0_stage
= MUSB_EP0_START
;
485 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
487 musb_set_vbus(musb
, 1);
489 handled
= IRQ_HANDLED
;
492 if (int_usb
& MUSB_INTR_VBUSERROR
) {
495 /* During connection as an A-Device, we may see a short
496 * current spikes causing voltage drop, because of cable
497 * and peripheral capacitance combined with vbus draw.
498 * (So: less common with truly self-powered devices, where
499 * vbus doesn't act like a power supply.)
501 * Such spikes are short; usually less than ~500 usec, max
502 * of ~2 msec. That is, they're not sustained overcurrent
503 * errors, though they're reported using VBUSERROR irqs.
505 * Workarounds: (a) hardware: use self powered devices.
506 * (b) software: ignore non-repeated VBUS errors.
508 * REVISIT: do delays from lots of DEBUG_KERNEL checks
509 * make trouble here, keeping VBUS < 4.4V ?
511 switch (musb
->xceiv
->state
) {
512 case OTG_STATE_A_HOST
:
513 /* recovery is dicey once we've gotten past the
514 * initial stages of enumeration, but if VBUS
515 * stayed ok at the other end of the link, and
516 * another reset is due (at least for high speed,
517 * to redo the chirp etc), it might work OK...
519 case OTG_STATE_A_WAIT_BCON
:
520 case OTG_STATE_A_WAIT_VRISE
:
521 if (musb
->vbuserr_retry
) {
522 musb
->vbuserr_retry
--;
524 devctl
|= MUSB_DEVCTL_SESSION
;
525 musb_writeb(mbase
, MUSB_DEVCTL
, devctl
);
527 musb
->port1_status
|=
528 (1 << USB_PORT_FEAT_OVER_CURRENT
)
529 | (1 << USB_PORT_FEAT_C_OVER_CURRENT
);
536 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
537 otg_state_string(musb
),
540 switch (devctl
& MUSB_DEVCTL_VBUS
) {
541 case 0 << MUSB_DEVCTL_VBUS_SHIFT
:
542 s
= "<SessEnd"; break;
543 case 1 << MUSB_DEVCTL_VBUS_SHIFT
:
544 s
= "<AValid"; break;
545 case 2 << MUSB_DEVCTL_VBUS_SHIFT
:
546 s
= "<VBusValid"; break;
547 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
551 VBUSERR_RETRY_COUNT
- musb
->vbuserr_retry
,
554 /* go through A_WAIT_VFALL then start a new session */
556 musb_set_vbus(musb
, 0);
557 handled
= IRQ_HANDLED
;
560 if (int_usb
& MUSB_INTR_CONNECT
) {
561 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
563 handled
= IRQ_HANDLED
;
565 set_bit(HCD_FLAG_SAW_IRQ
, &hcd
->flags
);
567 musb
->ep0_stage
= MUSB_EP0_START
;
569 #ifdef CONFIG_USB_MUSB_OTG
570 /* flush endpoints when transitioning from Device Mode */
571 if (is_peripheral_active(musb
)) {
572 /* REVISIT HNP; just force disconnect */
574 musb_writew(mbase
, MUSB_INTRTXE
, musb
->epmask
);
575 musb_writew(mbase
, MUSB_INTRRXE
, musb
->epmask
& 0xfffe);
576 musb_writeb(mbase
, MUSB_INTRUSBE
, 0xf7);
578 musb
->port1_status
&= ~(USB_PORT_STAT_LOW_SPEED
579 |USB_PORT_STAT_HIGH_SPEED
580 |USB_PORT_STAT_ENABLE
582 musb
->port1_status
|= USB_PORT_STAT_CONNECTION
583 |(USB_PORT_STAT_C_CONNECTION
<< 16);
585 /* high vs full speed is just a guess until after reset */
586 if (devctl
& MUSB_DEVCTL_LSDEV
)
587 musb
->port1_status
|= USB_PORT_STAT_LOW_SPEED
;
589 /* indicate new connection to OTG machine */
590 switch (musb
->xceiv
->state
) {
591 case OTG_STATE_B_PERIPHERAL
:
592 if (int_usb
& MUSB_INTR_SUSPEND
) {
593 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
594 int_usb
&= ~MUSB_INTR_SUSPEND
;
597 DBG(1, "CONNECT as b_peripheral???\n");
599 case OTG_STATE_B_WAIT_ACON
:
600 DBG(1, "HNP: CONNECT, now b_host\n");
602 musb
->xceiv
->state
= OTG_STATE_B_HOST
;
603 hcd
->self
.is_b_host
= 1;
604 musb
->ignore_disconnect
= 0;
605 del_timer(&musb
->otg_timer
);
608 if ((devctl
& MUSB_DEVCTL_VBUS
)
609 == (3 << MUSB_DEVCTL_VBUS_SHIFT
)) {
610 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
611 hcd
->self
.is_b_host
= 0;
616 /* poke the root hub */
619 usb_hcd_poll_rh_status(hcd
);
621 usb_hcd_resume_root_hub(hcd
);
623 DBG(1, "CONNECT (%s) devctl %02x\n",
624 otg_state_string(musb
), devctl
);
626 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
628 /* mentor saves a bit: bus reset and babble share the same irq.
629 * only host sees babble; only peripheral sees bus reset.
631 if (int_usb
& MUSB_INTR_RESET
) {
632 if (is_host_capable() && (devctl
& MUSB_DEVCTL_HM
) != 0) {
634 * Looks like non-HS BABBLE can be ignored, but
635 * HS BABBLE is an error condition. For HS the solution
636 * is to avoid babble in the first place and fix what
637 * caused BABBLE. When HS BABBLE happens we can only
640 if (devctl
& (MUSB_DEVCTL_FSDEV
| MUSB_DEVCTL_LSDEV
))
641 DBG(1, "BABBLE devctl: %02x\n", devctl
);
643 ERR("Stopping host session -- babble\n");
644 musb_writeb(mbase
, MUSB_DEVCTL
, 0);
646 } else if (is_peripheral_capable()) {
647 DBG(1, "BUS RESET as %s\n", otg_state_string(musb
));
648 switch (musb
->xceiv
->state
) {
649 #ifdef CONFIG_USB_OTG
650 case OTG_STATE_A_SUSPEND
:
651 /* We need to ignore disconnect on suspend
652 * otherwise tusb 2.0 won't reconnect after a
653 * power cycle, which breaks otg compliance.
655 musb
->ignore_disconnect
= 1;
658 case OTG_STATE_A_WAIT_BCON
: /* OPT TD.4.7-900ms */
659 /* never use invalid T(a_wait_bcon) */
660 DBG(1, "HNP: in %s, %d msec timeout\n",
661 otg_state_string(musb
),
663 mod_timer(&musb
->otg_timer
, jiffies
664 + msecs_to_jiffies(TA_WAIT_BCON(musb
)));
666 case OTG_STATE_A_PERIPHERAL
:
667 musb
->ignore_disconnect
= 0;
668 del_timer(&musb
->otg_timer
);
671 case OTG_STATE_B_WAIT_ACON
:
672 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
673 otg_state_string(musb
));
674 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
678 case OTG_STATE_B_IDLE
:
679 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
681 case OTG_STATE_B_PERIPHERAL
:
685 DBG(1, "Unhandled BUS RESET as %s\n",
686 otg_state_string(musb
));
690 handled
= IRQ_HANDLED
;
692 schedule_work(&musb
->irq_work
);
698 * Interrupt Service Routine to record USB "global" interrupts.
699 * Since these do not happen often and signify things of
700 * paramount importance, it seems OK to check them individually;
701 * the order of the tests is specified in the manual
703 * @param musb instance pointer
704 * @param int_usb register contents
708 static irqreturn_t
musb_stage2_irq(struct musb
*musb
, u8 int_usb
,
711 irqreturn_t handled
= IRQ_NONE
;
714 /* REVISIT ... this would be for multiplexing periodic endpoints, or
715 * supporting transfer phasing to prevent exceeding ISO bandwidth
716 * limits of a given frame or microframe.
718 * It's not needed for peripheral side, which dedicates endpoints;
719 * though it _might_ use SOF irqs for other purposes.
721 * And it's not currently needed for host side, which also dedicates
722 * endpoints, relies on TX/RX interval registers, and isn't claimed
723 * to support ISO transfers yet.
725 if (int_usb
& MUSB_INTR_SOF
) {
726 void __iomem
*mbase
= musb
->mregs
;
727 struct musb_hw_ep
*ep
;
731 DBG(6, "START_OF_FRAME\n");
732 handled
= IRQ_HANDLED
;
734 /* start any periodic Tx transfers waiting for current frame */
735 frame
= musb_readw(mbase
, MUSB_FRAME
);
736 ep
= musb
->endpoints
;
737 for (epnum
= 1; (epnum
< musb
->nr_endpoints
)
738 && (musb
->epmask
>= (1 << epnum
));
741 * FIXME handle framecounter wraps (12 bits)
742 * eliminate duplicated StartUrb logic
744 if (ep
->dwWaitFrame
>= frame
) {
746 pr_debug("SOF --> periodic TX%s on %d\n",
747 ep
->tx_channel
? " DMA" : "",
750 musb_h_tx_start(musb
, epnum
);
752 cppi_hostdma_start(musb
, epnum
);
754 } /* end of for loop */
758 if ((int_usb
& MUSB_INTR_DISCONNECT
) && !musb
->ignore_disconnect
) {
759 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
760 otg_state_string(musb
),
761 MUSB_MODE(musb
), devctl
);
762 handled
= IRQ_HANDLED
;
764 switch (musb
->xceiv
->state
) {
765 #ifdef CONFIG_USB_MUSB_HDRC_HCD
766 case OTG_STATE_A_HOST
:
767 case OTG_STATE_A_SUSPEND
:
768 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
769 musb_root_disconnect(musb
);
770 if (musb
->a_wait_bcon
!= 0 && is_otg_enabled(musb
))
771 musb_platform_try_idle(musb
, jiffies
772 + msecs_to_jiffies(musb
->a_wait_bcon
));
775 #ifdef CONFIG_USB_MUSB_OTG
776 case OTG_STATE_B_HOST
:
777 /* REVISIT this behaves for "real disconnect"
778 * cases; make sure the other transitions from
779 * from B_HOST act right too. The B_HOST code
780 * in hnp_stop() is currently not used...
782 musb_root_disconnect(musb
);
783 musb_to_hcd(musb
)->self
.is_b_host
= 0;
784 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
786 musb_g_disconnect(musb
);
788 case OTG_STATE_A_PERIPHERAL
:
790 musb_root_disconnect(musb
);
792 case OTG_STATE_B_WAIT_ACON
:
795 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
796 case OTG_STATE_B_PERIPHERAL
:
797 case OTG_STATE_B_IDLE
:
798 musb_g_disconnect(musb
);
802 WARNING("unhandled DISCONNECT transition (%s)\n",
803 otg_state_string(musb
));
807 schedule_work(&musb
->irq_work
);
810 if (int_usb
& MUSB_INTR_SUSPEND
) {
811 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
812 otg_state_string(musb
), devctl
, power
);
813 handled
= IRQ_HANDLED
;
815 switch (musb
->xceiv
->state
) {
816 #ifdef CONFIG_USB_MUSB_OTG
817 case OTG_STATE_A_PERIPHERAL
:
818 /* We also come here if the cable is removed, since
819 * this silicon doesn't report ID-no-longer-grounded.
821 * We depend on T(a_wait_bcon) to shut us down, and
822 * hope users don't do anything dicey during this
823 * undesired detour through A_WAIT_BCON.
826 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
827 musb_root_disconnect(musb
);
828 musb_platform_try_idle(musb
, jiffies
829 + msecs_to_jiffies(musb
->a_wait_bcon
830 ? : OTG_TIME_A_WAIT_BCON
));
833 case OTG_STATE_B_PERIPHERAL
:
834 musb_g_suspend(musb
);
835 musb
->is_active
= is_otg_enabled(musb
)
836 && musb
->xceiv
->gadget
->b_hnp_enable
;
837 if (musb
->is_active
) {
838 #ifdef CONFIG_USB_MUSB_OTG
839 musb
->xceiv
->state
= OTG_STATE_B_WAIT_ACON
;
840 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
841 mod_timer(&musb
->otg_timer
, jiffies
843 OTG_TIME_B_ASE0_BRST
));
847 case OTG_STATE_A_WAIT_BCON
:
848 if (musb
->a_wait_bcon
!= 0)
849 musb_platform_try_idle(musb
, jiffies
850 + msecs_to_jiffies(musb
->a_wait_bcon
));
852 case OTG_STATE_A_HOST
:
853 musb
->xceiv
->state
= OTG_STATE_A_SUSPEND
;
854 musb
->is_active
= is_otg_enabled(musb
)
855 && musb
->xceiv
->host
->b_hnp_enable
;
857 case OTG_STATE_B_HOST
:
858 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
859 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
862 /* "should not happen" */
866 schedule_work(&musb
->irq_work
);
873 /*-------------------------------------------------------------------------*/
876 * Program the HDRC to start (enable interrupts, dma, etc.).
878 void musb_start(struct musb
*musb
)
880 void __iomem
*regs
= musb
->mregs
;
881 u8 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
883 DBG(2, "<== devctl %02x\n", devctl
);
885 /* Set INT enable registers, enable interrupts */
886 musb_writew(regs
, MUSB_INTRTXE
, musb
->epmask
);
887 musb_writew(regs
, MUSB_INTRRXE
, musb
->epmask
& 0xfffe);
888 musb_writeb(regs
, MUSB_INTRUSBE
, 0xf7);
890 musb_writeb(regs
, MUSB_TESTMODE
, 0);
892 /* put into basic highspeed mode and start session */
893 musb_writeb(regs
, MUSB_POWER
, MUSB_POWER_ISOUPDATE
894 | MUSB_POWER_SOFTCONN
896 /* ENSUSPEND wedges tusb */
897 /* | MUSB_POWER_ENSUSPEND */
901 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
902 devctl
&= ~MUSB_DEVCTL_SESSION
;
904 if (is_otg_enabled(musb
)) {
905 /* session started after:
906 * (a) ID-grounded irq, host mode;
907 * (b) vbus present/connect IRQ, peripheral mode;
908 * (c) peripheral initiates, using SRP
910 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
913 devctl
|= MUSB_DEVCTL_SESSION
;
915 } else if (is_host_enabled(musb
)) {
916 /* assume ID pin is hard-wired to ground */
917 devctl
|= MUSB_DEVCTL_SESSION
;
919 } else /* peripheral is enabled */ {
920 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
923 musb_platform_enable(musb
);
924 musb_writeb(regs
, MUSB_DEVCTL
, devctl
);
928 static void musb_generic_disable(struct musb
*musb
)
930 void __iomem
*mbase
= musb
->mregs
;
933 /* disable interrupts */
934 musb_writeb(mbase
, MUSB_INTRUSBE
, 0);
935 musb_writew(mbase
, MUSB_INTRTXE
, 0);
936 musb_writew(mbase
, MUSB_INTRRXE
, 0);
939 musb_writeb(mbase
, MUSB_DEVCTL
, 0);
941 /* flush pending interrupts */
942 temp
= musb_readb(mbase
, MUSB_INTRUSB
);
943 temp
= musb_readw(mbase
, MUSB_INTRTX
);
944 temp
= musb_readw(mbase
, MUSB_INTRRX
);
949 * Make the HDRC stop (disable interrupts, etc.);
950 * reversible by musb_start
951 * called on gadget driver unregister
952 * with controller locked, irqs blocked
953 * acts as a NOP unless some role activated the hardware
955 void musb_stop(struct musb
*musb
)
957 /* stop IRQs, timers, ... */
958 musb_platform_disable(musb
);
959 musb_generic_disable(musb
);
960 DBG(3, "HDRC disabled\n");
963 * - mark host and/or peripheral drivers unusable/inactive
964 * - disable DMA (and enable it in HdrcStart)
965 * - make sure we can musb_start() after musb_stop(); with
966 * OTG mode, gadget driver module rmmod/modprobe cycles that
969 musb_platform_try_idle(musb
, 0);
972 static void musb_shutdown(struct platform_device
*pdev
)
974 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
977 spin_lock_irqsave(&musb
->lock
, flags
);
978 musb_platform_disable(musb
);
979 musb_generic_disable(musb
);
981 clk_put(musb
->clock
);
984 spin_unlock_irqrestore(&musb
->lock
, flags
);
986 /* FIXME power down */
990 /*-------------------------------------------------------------------------*/
993 * The silicon either has hard-wired endpoint configurations, or else
994 * "dynamic fifo" sizing. The driver has support for both, though at this
995 * writing only the dynamic sizing is very well tested. Since we switched
996 * away from compile-time hardware parameters, we can no longer rely on
997 * dead code elimination to leave only the relevant one in the object file.
999 * We don't currently use dynamic fifo setup capability to do anything
1000 * more than selecting one of a bunch of predefined configurations.
1002 #if defined(CONFIG_USB_TUSB6010) || \
1003 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1004 static ushort __initdata fifo_mode
= 4;
1006 static ushort __initdata fifo_mode
= 2;
1009 /* "modprobe ... fifo_mode=1" etc */
1010 module_param(fifo_mode
, ushort
, 0);
1011 MODULE_PARM_DESC(fifo_mode
, "initial endpoint configuration");
1014 enum fifo_style
{ FIFO_RXTX
, FIFO_TX
, FIFO_RX
} __attribute__ ((packed
));
1015 enum buf_mode
{ BUF_SINGLE
, BUF_DOUBLE
} __attribute__ ((packed
));
1019 enum fifo_style style
;
1025 * tables defining fifo_mode values. define more if you like.
1026 * for host side, make sure both halves of ep1 are set up.
1029 /* mode 0 - fits in 2KB */
1030 static struct fifo_cfg __initdata mode_0_cfg
[] = {
1031 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1032 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1033 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1034 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1035 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1038 /* mode 1 - fits in 4KB */
1039 static struct fifo_cfg __initdata mode_1_cfg
[] = {
1040 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1041 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1042 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1043 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1044 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1047 /* mode 2 - fits in 4KB */
1048 static struct fifo_cfg __initdata mode_2_cfg
[] = {
1049 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1050 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1051 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1052 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1053 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1054 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1057 /* mode 3 - fits in 4KB */
1058 static struct fifo_cfg __initdata mode_3_cfg
[] = {
1059 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1060 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1061 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1062 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1063 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1064 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1067 /* mode 4 - fits in 16KB */
1068 static struct fifo_cfg __initdata mode_4_cfg
[] = {
1069 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1070 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1071 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1072 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1073 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1074 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1075 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1076 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1077 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1078 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1079 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 512, },
1080 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 512, },
1081 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 512, },
1082 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 512, },
1083 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 512, },
1084 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 512, },
1085 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 512, },
1086 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 512, },
1087 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 256, },
1088 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 64, },
1089 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 256, },
1090 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 64, },
1091 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 256, },
1092 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 64, },
1093 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 4096, },
1094 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1095 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1100 * configure a fifo; for non-shared endpoints, this may be called
1101 * once for a tx fifo and once for an rx fifo.
1103 * returns negative errno or offset for next fifo.
1106 fifo_setup(struct musb
*musb
, struct musb_hw_ep
*hw_ep
,
1107 const struct fifo_cfg
*cfg
, u16 offset
)
1109 void __iomem
*mbase
= musb
->mregs
;
1111 u16 maxpacket
= cfg
->maxpacket
;
1112 u16 c_off
= offset
>> 3;
1115 /* expect hw_ep has already been zero-initialized */
1117 size
= ffs(max(maxpacket
, (u16
) 8)) - 1;
1118 maxpacket
= 1 << size
;
1121 if (cfg
->mode
== BUF_DOUBLE
) {
1122 if ((offset
+ (maxpacket
<< 1)) >
1123 (1 << (musb
->config
->ram_bits
+ 2)))
1125 c_size
|= MUSB_FIFOSZ_DPB
;
1127 if ((offset
+ maxpacket
) > (1 << (musb
->config
->ram_bits
+ 2)))
1131 /* configure the FIFO */
1132 musb_writeb(mbase
, MUSB_INDEX
, hw_ep
->epnum
);
1134 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1135 /* EP0 reserved endpoint for control, bidirectional;
1136 * EP1 reserved for bulk, two unidirection halves.
1138 if (hw_ep
->epnum
== 1)
1139 musb
->bulk_ep
= hw_ep
;
1140 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1142 switch (cfg
->style
) {
1144 musb_write_txfifosz(mbase
, c_size
);
1145 musb_write_txfifoadd(mbase
, c_off
);
1146 hw_ep
->tx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1147 hw_ep
->max_packet_sz_tx
= maxpacket
;
1150 musb_write_rxfifosz(mbase
, c_size
);
1151 musb_write_rxfifoadd(mbase
, c_off
);
1152 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1153 hw_ep
->max_packet_sz_rx
= maxpacket
;
1156 musb_write_txfifosz(mbase
, c_size
);
1157 musb_write_txfifoadd(mbase
, c_off
);
1158 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1159 hw_ep
->max_packet_sz_rx
= maxpacket
;
1161 musb_write_rxfifosz(mbase
, c_size
);
1162 musb_write_rxfifoadd(mbase
, c_off
);
1163 hw_ep
->tx_double_buffered
= hw_ep
->rx_double_buffered
;
1164 hw_ep
->max_packet_sz_tx
= maxpacket
;
1166 hw_ep
->is_shared_fifo
= true;
1170 /* NOTE rx and tx endpoint irqs aren't managed separately,
1171 * which happens to be ok
1173 musb
->epmask
|= (1 << hw_ep
->epnum
);
1175 return offset
+ (maxpacket
<< ((c_size
& MUSB_FIFOSZ_DPB
) ? 1 : 0));
1178 static struct fifo_cfg __initdata ep0_cfg
= {
1179 .style
= FIFO_RXTX
, .maxpacket
= 64,
1182 static int __init
ep_config_from_table(struct musb
*musb
)
1184 const struct fifo_cfg
*cfg
;
1187 struct musb_hw_ep
*hw_ep
= musb
->endpoints
;
1189 switch (fifo_mode
) {
1195 n
= ARRAY_SIZE(mode_0_cfg
);
1199 n
= ARRAY_SIZE(mode_1_cfg
);
1203 n
= ARRAY_SIZE(mode_2_cfg
);
1207 n
= ARRAY_SIZE(mode_3_cfg
);
1211 n
= ARRAY_SIZE(mode_4_cfg
);
1215 printk(KERN_DEBUG
"%s: setup fifo_mode %d\n",
1216 musb_driver_name
, fifo_mode
);
1219 offset
= fifo_setup(musb
, hw_ep
, &ep0_cfg
, 0);
1220 /* assert(offset > 0) */
1222 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1223 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1226 for (i
= 0; i
< n
; i
++) {
1227 u8 epn
= cfg
->hw_ep_num
;
1229 if (epn
>= musb
->config
->num_eps
) {
1230 pr_debug("%s: invalid ep %d\n",
1231 musb_driver_name
, epn
);
1234 offset
= fifo_setup(musb
, hw_ep
+ epn
, cfg
++, offset
);
1236 pr_debug("%s: mem overrun, ep %d\n",
1237 musb_driver_name
, epn
);
1241 musb
->nr_endpoints
= max(epn
, musb
->nr_endpoints
);
1244 printk(KERN_DEBUG
"%s: %d/%d max ep, %d/%d memory\n",
1246 n
+ 1, musb
->config
->num_eps
* 2 - 1,
1247 offset
, (1 << (musb
->config
->ram_bits
+ 2)));
1249 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1250 if (!musb
->bulk_ep
) {
1251 pr_debug("%s: missing bulk\n", musb_driver_name
);
1261 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1262 * @param musb the controller
1264 static int __init
ep_config_from_hw(struct musb
*musb
)
1267 struct musb_hw_ep
*hw_ep
;
1268 void *mbase
= musb
->mregs
;
1271 DBG(2, "<== static silicon ep config\n");
1273 /* FIXME pick up ep0 maxpacket size */
1275 for (epnum
= 1; epnum
< musb
->config
->num_eps
; epnum
++) {
1276 musb_ep_select(mbase
, epnum
);
1277 hw_ep
= musb
->endpoints
+ epnum
;
1279 ret
= musb_read_fifosize(musb
, hw_ep
, epnum
);
1283 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1285 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1286 /* pick an RX/TX endpoint for bulk */
1287 if (hw_ep
->max_packet_sz_tx
< 512
1288 || hw_ep
->max_packet_sz_rx
< 512)
1291 /* REVISIT: this algorithm is lazy, we should at least
1292 * try to pick a double buffered endpoint.
1296 musb
->bulk_ep
= hw_ep
;
1300 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1301 if (!musb
->bulk_ep
) {
1302 pr_debug("%s: missing bulk\n", musb_driver_name
);
1310 enum { MUSB_CONTROLLER_MHDRC
, MUSB_CONTROLLER_HDRC
, };
1312 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1313 * configure endpoints, or take their config from silicon
1315 static int __init
musb_core_init(u16 musb_type
, struct musb
*musb
)
1322 u16 hwvers
, rev_major
, rev_minor
;
1323 char aInfo
[78], aRevision
[32], aDate
[12];
1324 void __iomem
*mbase
= musb
->mregs
;
1328 /* log core options (read using indexed model) */
1329 reg
= musb_read_configdata(mbase
);
1331 strcpy(aInfo
, (reg
& MUSB_CONFIGDATA_UTMIDW
) ? "UTMI-16" : "UTMI-8");
1332 if (reg
& MUSB_CONFIGDATA_DYNFIFO
)
1333 strcat(aInfo
, ", dyn FIFOs");
1334 if (reg
& MUSB_CONFIGDATA_MPRXE
) {
1335 strcat(aInfo
, ", bulk combine");
1337 musb
->bulk_combine
= true;
1339 strcat(aInfo
, " (X)"); /* no driver support */
1342 if (reg
& MUSB_CONFIGDATA_MPTXE
) {
1343 strcat(aInfo
, ", bulk split");
1345 musb
->bulk_split
= true;
1347 strcat(aInfo
, " (X)"); /* no driver support */
1350 if (reg
& MUSB_CONFIGDATA_HBRXE
) {
1351 strcat(aInfo
, ", HB-ISO Rx");
1352 musb
->hb_iso_rx
= true;
1354 if (reg
& MUSB_CONFIGDATA_HBTXE
) {
1355 strcat(aInfo
, ", HB-ISO Tx");
1356 musb
->hb_iso_tx
= true;
1358 if (reg
& MUSB_CONFIGDATA_SOFTCONE
)
1359 strcat(aInfo
, ", SoftConn");
1361 printk(KERN_DEBUG
"%s: ConfigData=0x%02x (%s)\n",
1362 musb_driver_name
, reg
, aInfo
);
1365 data
= musb_readl(mbase
, 0x404);
1366 sprintf(aDate
, "%04d-%02x-%02x", (data
& 0xffff),
1367 (data
>> 16) & 0xff, (data
>> 24) & 0xff);
1368 /* FIXME ID2 and ID3 are unused */
1369 data
= musb_readl(mbase
, 0x408);
1370 printk(KERN_DEBUG
"ID2=%lx\n", (long unsigned)data
);
1371 data
= musb_readl(mbase
, 0x40c);
1372 printk(KERN_DEBUG
"ID3=%lx\n", (long unsigned)data
);
1373 reg
= musb_readb(mbase
, 0x400);
1374 musb_type
= ('M' == reg
) ? MUSB_CONTROLLER_MHDRC
: MUSB_CONTROLLER_HDRC
;
1378 if (MUSB_CONTROLLER_MHDRC
== musb_type
) {
1379 musb
->is_multipoint
= 1;
1382 musb
->is_multipoint
= 0;
1384 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1385 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1387 "%s: kernel must blacklist external hubs\n",
1393 /* log release info */
1394 hwvers
= musb_read_hwvers(mbase
);
1395 rev_major
= (hwvers
>> 10) & 0x1f;
1396 rev_minor
= hwvers
& 0x3ff;
1397 snprintf(aRevision
, 32, "%d.%d%s", rev_major
,
1398 rev_minor
, (hwvers
& 0x8000) ? "RC" : "");
1399 printk(KERN_DEBUG
"%s: %sHDRC RTL version %s %s\n",
1400 musb_driver_name
, type
, aRevision
, aDate
);
1403 musb_configure_ep0(musb
);
1405 /* discover endpoint configuration */
1406 musb
->nr_endpoints
= 1;
1409 if (reg
& MUSB_CONFIGDATA_DYNFIFO
) {
1410 if (musb
->config
->dyn_fifo
)
1411 status
= ep_config_from_table(musb
);
1413 ERR("reconfigure software for Dynamic FIFOs\n");
1417 if (!musb
->config
->dyn_fifo
)
1418 status
= ep_config_from_hw(musb
);
1420 ERR("reconfigure software for static FIFOs\n");
1428 /* finish init, and print endpoint config */
1429 for (i
= 0; i
< musb
->nr_endpoints
; i
++) {
1430 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ i
;
1432 hw_ep
->fifo
= MUSB_FIFO_OFFSET(i
) + mbase
;
1433 #ifdef CONFIG_USB_TUSB6010
1434 hw_ep
->fifo_async
= musb
->async
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1435 hw_ep
->fifo_sync
= musb
->sync
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1436 hw_ep
->fifo_sync_va
=
1437 musb
->sync_va
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1440 hw_ep
->conf
= mbase
- 0x400 + TUSB_EP0_CONF
;
1442 hw_ep
->conf
= mbase
+ 0x400 + (((i
- 1) & 0xf) << 2);
1445 hw_ep
->regs
= MUSB_EP_OFFSET(i
, 0) + mbase
;
1446 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1447 hw_ep
->target_regs
= musb_read_target_reg_base(i
, mbase
);
1448 hw_ep
->rx_reinit
= 1;
1449 hw_ep
->tx_reinit
= 1;
1452 if (hw_ep
->max_packet_sz_tx
) {
1454 "%s: hw_ep %d%s, %smax %d\n",
1455 musb_driver_name
, i
,
1456 hw_ep
->is_shared_fifo
? "shared" : "tx",
1457 hw_ep
->tx_double_buffered
1458 ? "doublebuffer, " : "",
1459 hw_ep
->max_packet_sz_tx
);
1461 if (hw_ep
->max_packet_sz_rx
&& !hw_ep
->is_shared_fifo
) {
1463 "%s: hw_ep %d%s, %smax %d\n",
1464 musb_driver_name
, i
,
1466 hw_ep
->rx_double_buffered
1467 ? "doublebuffer, " : "",
1468 hw_ep
->max_packet_sz_rx
);
1470 if (!(hw_ep
->max_packet_sz_tx
|| hw_ep
->max_packet_sz_rx
))
1471 DBG(1, "hw_ep %d not configured\n", i
);
1477 /*-------------------------------------------------------------------------*/
1479 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1481 static irqreturn_t
generic_interrupt(int irq
, void *__hci
)
1483 unsigned long flags
;
1484 irqreturn_t retval
= IRQ_NONE
;
1485 struct musb
*musb
= __hci
;
1487 spin_lock_irqsave(&musb
->lock
, flags
);
1489 musb
->int_usb
= musb_readb(musb
->mregs
, MUSB_INTRUSB
);
1490 musb
->int_tx
= musb_readw(musb
->mregs
, MUSB_INTRTX
);
1491 musb
->int_rx
= musb_readw(musb
->mregs
, MUSB_INTRRX
);
1493 if (musb
->int_usb
|| musb
->int_tx
|| musb
->int_rx
)
1494 retval
= musb_interrupt(musb
);
1496 spin_unlock_irqrestore(&musb
->lock
, flags
);
1502 #define generic_interrupt NULL
1506 * handle all the irqs defined by the HDRC core. for now we expect: other
1507 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1508 * will be assigned, and the irq will already have been acked.
1510 * called in irq context with spinlock held, irqs blocked
1512 irqreturn_t
musb_interrupt(struct musb
*musb
)
1514 irqreturn_t retval
= IRQ_NONE
;
1519 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1520 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1522 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1523 (devctl
& MUSB_DEVCTL_HM
) ? "host" : "peripheral",
1524 musb
->int_usb
, musb
->int_tx
, musb
->int_rx
);
1526 /* the core can interrupt us for multiple reasons; docs have
1527 * a generic interrupt flowchart to follow
1529 if (musb
->int_usb
& STAGE0_MASK
)
1530 retval
|= musb_stage0_irq(musb
, musb
->int_usb
,
1533 /* "stage 1" is handling endpoint irqs */
1535 /* handle endpoint 0 first */
1536 if (musb
->int_tx
& 1) {
1537 if (devctl
& MUSB_DEVCTL_HM
)
1538 retval
|= musb_h_ep0_irq(musb
);
1540 retval
|= musb_g_ep0_irq(musb
);
1543 /* RX on endpoints 1-15 */
1544 reg
= musb
->int_rx
>> 1;
1548 /* musb_ep_select(musb->mregs, ep_num); */
1549 /* REVISIT just retval = ep->rx_irq(...) */
1550 retval
= IRQ_HANDLED
;
1551 if (devctl
& MUSB_DEVCTL_HM
) {
1552 if (is_host_capable())
1553 musb_host_rx(musb
, ep_num
);
1555 if (is_peripheral_capable())
1556 musb_g_rx(musb
, ep_num
);
1564 /* TX on endpoints 1-15 */
1565 reg
= musb
->int_tx
>> 1;
1569 /* musb_ep_select(musb->mregs, ep_num); */
1570 /* REVISIT just retval |= ep->tx_irq(...) */
1571 retval
= IRQ_HANDLED
;
1572 if (devctl
& MUSB_DEVCTL_HM
) {
1573 if (is_host_capable())
1574 musb_host_tx(musb
, ep_num
);
1576 if (is_peripheral_capable())
1577 musb_g_tx(musb
, ep_num
);
1584 /* finish handling "global" interrupts after handling fifos */
1586 retval
|= musb_stage2_irq(musb
,
1587 musb
->int_usb
, devctl
, power
);
1593 #ifndef CONFIG_MUSB_PIO_ONLY
1594 static int __initdata use_dma
= 1;
1596 /* "modprobe ... use_dma=0" etc */
1597 module_param(use_dma
, bool, 0);
1598 MODULE_PARM_DESC(use_dma
, "enable/disable use of DMA");
1600 void musb_dma_completion(struct musb
*musb
, u8 epnum
, u8 transmit
)
1602 u8 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1604 /* called with controller lock already held */
1607 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1608 if (!is_cppi_enabled()) {
1610 if (devctl
& MUSB_DEVCTL_HM
)
1611 musb_h_ep0_irq(musb
);
1613 musb_g_ep0_irq(musb
);
1617 /* endpoints 1..15 */
1619 if (devctl
& MUSB_DEVCTL_HM
) {
1620 if (is_host_capable())
1621 musb_host_tx(musb
, epnum
);
1623 if (is_peripheral_capable())
1624 musb_g_tx(musb
, epnum
);
1628 if (devctl
& MUSB_DEVCTL_HM
) {
1629 if (is_host_capable())
1630 musb_host_rx(musb
, epnum
);
1632 if (is_peripheral_capable())
1633 musb_g_rx(musb
, epnum
);
1643 /*-------------------------------------------------------------------------*/
1648 musb_mode_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1650 struct musb
*musb
= dev_to_musb(dev
);
1651 unsigned long flags
;
1654 spin_lock_irqsave(&musb
->lock
, flags
);
1655 ret
= sprintf(buf
, "%s\n", otg_state_string(musb
));
1656 spin_unlock_irqrestore(&musb
->lock
, flags
);
1662 musb_mode_store(struct device
*dev
, struct device_attribute
*attr
,
1663 const char *buf
, size_t n
)
1665 struct musb
*musb
= dev_to_musb(dev
);
1666 unsigned long flags
;
1669 spin_lock_irqsave(&musb
->lock
, flags
);
1670 if (sysfs_streq(buf
, "host"))
1671 status
= musb_platform_set_mode(musb
, MUSB_HOST
);
1672 else if (sysfs_streq(buf
, "peripheral"))
1673 status
= musb_platform_set_mode(musb
, MUSB_PERIPHERAL
);
1674 else if (sysfs_streq(buf
, "otg"))
1675 status
= musb_platform_set_mode(musb
, MUSB_OTG
);
1678 spin_unlock_irqrestore(&musb
->lock
, flags
);
1680 return (status
== 0) ? n
: status
;
1682 static DEVICE_ATTR(mode
, 0644, musb_mode_show
, musb_mode_store
);
1685 musb_vbus_store(struct device
*dev
, struct device_attribute
*attr
,
1686 const char *buf
, size_t n
)
1688 struct musb
*musb
= dev_to_musb(dev
);
1689 unsigned long flags
;
1692 if (sscanf(buf
, "%lu", &val
) < 1) {
1693 printk(KERN_ERR
"Invalid VBUS timeout ms value\n");
1697 spin_lock_irqsave(&musb
->lock
, flags
);
1698 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1699 musb
->a_wait_bcon
= val
? max_t(int, val
, OTG_TIME_A_WAIT_BCON
) : 0 ;
1700 if (musb
->xceiv
->state
== OTG_STATE_A_WAIT_BCON
)
1701 musb
->is_active
= 0;
1702 musb_platform_try_idle(musb
, jiffies
+ msecs_to_jiffies(val
));
1703 spin_unlock_irqrestore(&musb
->lock
, flags
);
1709 musb_vbus_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1711 struct musb
*musb
= dev_to_musb(dev
);
1712 unsigned long flags
;
1716 spin_lock_irqsave(&musb
->lock
, flags
);
1717 val
= musb
->a_wait_bcon
;
1718 /* FIXME get_vbus_status() is normally #defined as false...
1719 * and is effectively TUSB-specific.
1721 vbus
= musb_platform_get_vbus_status(musb
);
1722 spin_unlock_irqrestore(&musb
->lock
, flags
);
1724 return sprintf(buf
, "Vbus %s, timeout %lu msec\n",
1725 vbus
? "on" : "off", val
);
1727 static DEVICE_ATTR(vbus
, 0644, musb_vbus_show
, musb_vbus_store
);
1729 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1731 /* Gadget drivers can't know that a host is connected so they might want
1732 * to start SRP, but users can. This allows userspace to trigger SRP.
1735 musb_srp_store(struct device
*dev
, struct device_attribute
*attr
,
1736 const char *buf
, size_t n
)
1738 struct musb
*musb
= dev_to_musb(dev
);
1741 if (sscanf(buf
, "%hu", &srp
) != 1
1743 printk(KERN_ERR
"SRP: Value must be 1\n");
1748 musb_g_wakeup(musb
);
1752 static DEVICE_ATTR(srp
, 0644, NULL
, musb_srp_store
);
1754 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1758 /* Only used to provide driver mode change events */
1759 static void musb_irq_work(struct work_struct
*data
)
1761 struct musb
*musb
= container_of(data
, struct musb
, irq_work
);
1762 static int old_state
;
1764 if (musb
->xceiv
->state
!= old_state
) {
1765 old_state
= musb
->xceiv
->state
;
1766 sysfs_notify(&musb
->controller
->kobj
, NULL
, "mode");
1770 /* --------------------------------------------------------------------------
1774 static struct musb
*__init
1775 allocate_instance(struct device
*dev
,
1776 struct musb_hdrc_config
*config
, void __iomem
*mbase
)
1779 struct musb_hw_ep
*ep
;
1781 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1782 struct usb_hcd
*hcd
;
1784 hcd
= usb_create_hcd(&musb_hc_driver
, dev
, dev_name(dev
));
1787 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1789 musb
= hcd_to_musb(hcd
);
1790 INIT_LIST_HEAD(&musb
->control
);
1791 INIT_LIST_HEAD(&musb
->in_bulk
);
1792 INIT_LIST_HEAD(&musb
->out_bulk
);
1794 hcd
->uses_new_polling
= 1;
1796 musb
->vbuserr_retry
= VBUSERR_RETRY_COUNT
;
1797 musb
->a_wait_bcon
= OTG_TIME_A_WAIT_BCON
;
1799 musb
= kzalloc(sizeof *musb
, GFP_KERNEL
);
1802 dev_set_drvdata(dev
, musb
);
1806 musb
->mregs
= mbase
;
1807 musb
->ctrl_base
= mbase
;
1808 musb
->nIrq
= -ENODEV
;
1809 musb
->config
= config
;
1810 BUG_ON(musb
->config
->num_eps
> MUSB_C_NUM_EPS
);
1811 for (epnum
= 0, ep
= musb
->endpoints
;
1812 epnum
< musb
->config
->num_eps
;
1818 musb
->controller
= dev
;
1822 static void musb_free(struct musb
*musb
)
1824 /* this has multiple entry modes. it handles fault cleanup after
1825 * probe(), where things may be partially set up, as well as rmmod
1826 * cleanup after everything's been de-activated.
1830 device_remove_file(musb
->controller
, &dev_attr_mode
);
1831 device_remove_file(musb
->controller
, &dev_attr_vbus
);
1832 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1833 device_remove_file(musb
->controller
, &dev_attr_srp
);
1837 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1838 musb_gadget_cleanup(musb
);
1841 if (musb
->nIrq
>= 0) {
1843 disable_irq_wake(musb
->nIrq
);
1844 free_irq(musb
->nIrq
, musb
);
1846 if (is_dma_capable() && musb
->dma_controller
) {
1847 struct dma_controller
*c
= musb
->dma_controller
;
1850 dma_controller_destroy(c
);
1853 #ifdef CONFIG_USB_MUSB_OTG
1854 put_device(musb
->xceiv
->dev
);
1857 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
1858 musb_platform_exit(musb
);
1859 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
1862 clk_disable(musb
->clock
);
1863 clk_put(musb
->clock
);
1866 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1867 usb_put_hcd(musb_to_hcd(musb
));
1874 * Perform generic per-controller initialization.
1876 * @pDevice: the controller (already clocked, etc)
1878 * @mregs: virtual address of controller registers,
1879 * not yet corrected for platform-specific offsets
1882 musb_init_controller(struct device
*dev
, int nIrq
, void __iomem
*ctrl
)
1886 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
1888 /* The driver might handle more features than the board; OK.
1889 * Fail when the board needs a feature that's not enabled.
1892 dev_dbg(dev
, "no platform_data?\n");
1895 switch (plat
->mode
) {
1897 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1902 case MUSB_PERIPHERAL
:
1903 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1909 #ifdef CONFIG_USB_MUSB_OTG
1915 dev_err(dev
, "incompatible Kconfig role setting\n");
1920 musb
= allocate_instance(dev
, plat
->config
, ctrl
);
1924 spin_lock_init(&musb
->lock
);
1925 musb
->board_mode
= plat
->mode
;
1926 musb
->board_set_power
= plat
->set_power
;
1927 musb
->set_clock
= plat
->set_clock
;
1928 musb
->min_power
= plat
->min_power
;
1930 /* Clock usage is chip-specific ... functional clock (DaVinci,
1931 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1932 * code does is make sure a clock handle is available; platform
1933 * code manages it during start/stop and suspend/resume.
1936 musb
->clock
= clk_get(dev
, plat
->clock
);
1937 if (IS_ERR(musb
->clock
)) {
1938 status
= PTR_ERR(musb
->clock
);
1944 /* The musb_platform_init() call:
1945 * - adjusts musb->mregs and musb->isr if needed,
1946 * - may initialize an integrated tranceiver
1947 * - initializes musb->xceiv, usually by otg_get_transceiver()
1948 * - activates clocks.
1949 * - stops powering VBUS
1950 * - assigns musb->board_set_vbus if host mode is enabled
1952 * There are various transciever configurations. Blackfin,
1953 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1954 * external/discrete ones in various flavors (twl4030 family,
1955 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1957 musb
->isr
= generic_interrupt
;
1958 status
= musb_platform_init(musb
);
1967 #ifndef CONFIG_MUSB_PIO_ONLY
1968 if (use_dma
&& dev
->dma_mask
) {
1969 struct dma_controller
*c
;
1971 c
= dma_controller_create(musb
, musb
->mregs
);
1972 musb
->dma_controller
= c
;
1977 /* ideally this would be abstracted in platform setup */
1978 if (!is_dma_capable() || !musb
->dma_controller
)
1979 dev
->dma_mask
= NULL
;
1981 /* be sure interrupts are disabled before connecting ISR */
1982 musb_platform_disable(musb
);
1983 musb_generic_disable(musb
);
1985 /* setup musb parts of the core (especially endpoints) */
1986 status
= musb_core_init(plat
->config
->multipoint
1987 ? MUSB_CONTROLLER_MHDRC
1988 : MUSB_CONTROLLER_HDRC
, musb
);
1992 #ifdef CONFIG_USB_MUSB_OTG
1993 setup_timer(&musb
->otg_timer
, musb_otg_timer_func
, (unsigned long) musb
);
1996 /* Init IRQ workqueue before request_irq */
1997 INIT_WORK(&musb
->irq_work
, musb_irq_work
);
1999 /* attach to the IRQ */
2000 if (request_irq(nIrq
, musb
->isr
, 0, dev_name(dev
), musb
)) {
2001 dev_err(dev
, "request_irq %d failed!\n", nIrq
);
2006 /* FIXME this handles wakeup irqs wrong */
2007 if (enable_irq_wake(nIrq
) == 0) {
2009 device_init_wakeup(dev
, 1);
2014 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2017 switch (musb
->board_mode
) {
2018 case MUSB_HOST
: s
= "Host"; break;
2019 case MUSB_PERIPHERAL
: s
= "Peripheral"; break;
2020 default: s
= "OTG"; break;
2023 (is_dma_capable() && musb
->dma_controller
)
2027 /* host side needs more setup */
2028 if (is_host_enabled(musb
)) {
2029 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
2031 otg_set_host(musb
->xceiv
, &hcd
->self
);
2033 if (is_otg_enabled(musb
))
2034 hcd
->self
.otg_port
= 1;
2035 musb
->xceiv
->host
= &hcd
->self
;
2036 hcd
->power_budget
= 2 * (plat
->power
? : 250);
2039 /* For the host-only role, we can activate right away.
2040 * (We expect the ID pin to be forcibly grounded!!)
2041 * Otherwise, wait till the gadget driver hooks up.
2043 if (!is_otg_enabled(musb
) && is_host_enabled(musb
)) {
2044 MUSB_HST_MODE(musb
);
2045 musb
->xceiv
->default_a
= 1;
2046 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
2048 status
= usb_add_hcd(musb_to_hcd(musb
), -1, 0);
2052 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2054 musb_readb(musb
->mregs
, MUSB_DEVCTL
),
2055 (musb_readb(musb
->mregs
, MUSB_DEVCTL
)
2056 & MUSB_DEVCTL_BDEVICE
2059 } else /* peripheral is enabled */ {
2060 MUSB_DEV_MODE(musb
);
2061 musb
->xceiv
->default_a
= 0;
2062 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
2064 status
= musb_gadget_setup(musb
);
2068 DBG(1, "%s mode, status %d, dev%02x\n",
2069 is_otg_enabled(musb
) ? "OTG" : "PERIPHERAL",
2071 musb_readb(musb
->mregs
, MUSB_DEVCTL
));
2076 status
= device_create_file(dev
, &dev_attr_mode
);
2077 status
= device_create_file(dev
, &dev_attr_vbus
);
2078 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2079 status
= device_create_file(dev
, &dev_attr_srp
);
2080 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2090 device_remove_file(musb
->controller
, &dev_attr_mode
);
2091 device_remove_file(musb
->controller
, &dev_attr_vbus
);
2092 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2093 device_remove_file(musb
->controller
, &dev_attr_srp
);
2096 musb_platform_exit(musb
);
2098 dev_err(musb
->controller
,
2099 "musb_init_controller failed with status %d\n", status
);
2102 clk_put(musb
->clock
);
2103 device_init_wakeup(dev
, 0);
2110 /*-------------------------------------------------------------------------*/
2112 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2113 * bridge to a platform device; this driver then suffices.
2116 #ifndef CONFIG_MUSB_PIO_ONLY
2117 static u64
*orig_dma_mask
;
2120 static int __init
musb_probe(struct platform_device
*pdev
)
2122 struct device
*dev
= &pdev
->dev
;
2123 int irq
= platform_get_irq(pdev
, 0);
2124 struct resource
*iomem
;
2127 iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2128 if (!iomem
|| irq
== 0)
2131 base
= ioremap(iomem
->start
, iomem
->end
- iomem
->start
+ 1);
2133 dev_err(dev
, "ioremap failed\n");
2137 #ifndef CONFIG_MUSB_PIO_ONLY
2138 /* clobbered by use_dma=n */
2139 orig_dma_mask
= dev
->dma_mask
;
2141 return musb_init_controller(dev
, irq
, base
);
2144 static int __devexit
musb_remove(struct platform_device
*pdev
)
2146 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
2147 void __iomem
*ctrl_base
= musb
->ctrl_base
;
2149 /* this gets called on rmmod.
2150 * - Host mode: host may still be active
2151 * - Peripheral mode: peripheral is deactivated (or never-activated)
2152 * - OTG mode: both roles are deactivated (or never-activated)
2154 musb_shutdown(pdev
);
2155 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2156 if (musb
->board_mode
== MUSB_HOST
)
2157 usb_remove_hcd(musb_to_hcd(musb
));
2161 device_init_wakeup(&pdev
->dev
, 0);
2162 #ifndef CONFIG_MUSB_PIO_ONLY
2163 pdev
->dev
.dma_mask
= orig_dma_mask
;
2170 static int musb_suspend(struct device
*dev
)
2172 struct platform_device
*pdev
= to_platform_device(dev
);
2173 unsigned long flags
;
2174 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
2179 spin_lock_irqsave(&musb
->lock
, flags
);
2181 if (is_peripheral_active(musb
)) {
2182 /* FIXME force disconnect unless we know USB will wake
2183 * the system up quickly enough to respond ...
2185 } else if (is_host_active(musb
)) {
2186 /* we know all the children are suspended; sometimes
2187 * they will even be wakeup-enabled.
2191 if (musb
->set_clock
)
2192 musb
->set_clock(musb
->clock
, 0);
2194 clk_disable(musb
->clock
);
2195 spin_unlock_irqrestore(&musb
->lock
, flags
);
2199 static int musb_resume_noirq(struct device
*dev
)
2201 struct platform_device
*pdev
= to_platform_device(dev
);
2202 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
2207 if (musb
->set_clock
)
2208 musb
->set_clock(musb
->clock
, 1);
2210 clk_enable(musb
->clock
);
2212 /* for static cmos like DaVinci, register values were preserved
2213 * unless for some reason the whole soc powered down or the USB
2214 * module got reset through the PSC (vs just being disabled).
2219 static struct dev_pm_ops musb_dev_pm_ops
= {
2220 .suspend
= musb_suspend
,
2221 .resume_noirq
= musb_resume_noirq
,
2224 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2226 #define MUSB_DEV_PM_OPS NULL
2229 static struct platform_driver musb_driver
= {
2231 .name
= (char *)musb_driver_name
,
2232 .bus
= &platform_bus_type
,
2233 .owner
= THIS_MODULE
,
2234 .pm
= MUSB_DEV_PM_OPS
,
2236 .remove
= __devexit_p(musb_remove
),
2237 .shutdown
= musb_shutdown
,
2240 /*-------------------------------------------------------------------------*/
2242 static int __init
musb_init(void)
2244 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2249 pr_info("%s: version " MUSB_VERSION
", "
2250 #ifdef CONFIG_MUSB_PIO_ONLY
2252 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2254 #elif defined(CONFIG_USB_INVENTRA_DMA)
2256 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2262 #ifdef CONFIG_USB_MUSB_OTG
2263 "otg (peripheral+host)"
2264 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2266 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2270 musb_driver_name
, musb_debug
);
2271 return platform_driver_probe(&musb_driver
, musb_probe
);
2274 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2275 * and before usb gadget and host-side drivers start to register
2277 fs_initcall(musb_init
);
2279 static void __exit
musb_cleanup(void)
2281 platform_driver_unregister(&musb_driver
);
2283 module_exit(musb_cleanup
);