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fed up with those stupid warnings
[mmotm.git] / arch / arm / plat-omap / gpio.c
blobcdc2a589829f86b4bf09bea93d89533026367469
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000)
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400)
49 #define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00)
50 #define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400)
51 #define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00)
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP7XX specific GPIO registers
72 */
73 #define OMAP7XX_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
74 #define OMAP7XX_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
75 #define OMAP7XX_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
76 #define OMAP7XX_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
77 #define OMAP7XX_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
78 #define OMAP7XX_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
79 #define OMAP7XX_GPIO_DATA_INPUT 0x00
80 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
82 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
83 #define OMAP7XX_GPIO_INT_MASK 0x10
84 #define OMAP7XX_GPIO_INT_STATUS 0x14
85
86 #define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
87
88 /*
89 * omap24xx specific GPIO registers
90 */
91 #define OMAP242X_GPIO1_BASE OMAP2_L4_IO_ADDRESS(0x48018000)
92 #define OMAP242X_GPIO2_BASE OMAP2_L4_IO_ADDRESS(0x4801a000)
93 #define OMAP242X_GPIO3_BASE OMAP2_L4_IO_ADDRESS(0x4801c000)
94 #define OMAP242X_GPIO4_BASE OMAP2_L4_IO_ADDRESS(0x4801e000)
95
96 #define OMAP243X_GPIO1_BASE OMAP2_L4_IO_ADDRESS(0x4900C000)
97 #define OMAP243X_GPIO2_BASE OMAP2_L4_IO_ADDRESS(0x4900E000)
98 #define OMAP243X_GPIO3_BASE OMAP2_L4_IO_ADDRESS(0x49010000)
99 #define OMAP243X_GPIO4_BASE OMAP2_L4_IO_ADDRESS(0x49012000)
100 #define OMAP243X_GPIO5_BASE OMAP2_L4_IO_ADDRESS(0x480B6000)
101
102 #define OMAP24XX_GPIO_REVISION 0x0000
103 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
104 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
105 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
106 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
108 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
109 #define OMAP24XX_GPIO_WAKE_EN 0x0020
110 #define OMAP24XX_GPIO_CTRL 0x0030
111 #define OMAP24XX_GPIO_OE 0x0034
112 #define OMAP24XX_GPIO_DATAIN 0x0038
113 #define OMAP24XX_GPIO_DATAOUT 0x003c
114 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
117 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
118 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
120 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123 #define OMAP24XX_GPIO_SETWKUENA 0x0084
124 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
126
127 #define OMAP4_GPIO_REVISION 0x0000
128 #define OMAP4_GPIO_SYSCONFIG 0x0010
129 #define OMAP4_GPIO_EOI 0x0020
130 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132 #define OMAP4_GPIO_IRQSTATUS0 0x002c
133 #define OMAP4_GPIO_IRQSTATUS1 0x0030
134 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138 #define OMAP4_GPIO_IRQWAKEN0 0x0044
139 #define OMAP4_GPIO_IRQWAKEN1 0x0048
140 #define OMAP4_GPIO_SYSSTATUS 0x0104
141 #define OMAP4_GPIO_CTRL 0x0130
142 #define OMAP4_GPIO_OE 0x0134
143 #define OMAP4_GPIO_DATAIN 0x0138
144 #define OMAP4_GPIO_DATAOUT 0x013c
145 #define OMAP4_GPIO_LEVELDETECT0 0x0140
146 #define OMAP4_GPIO_LEVELDETECT1 0x0144
147 #define OMAP4_GPIO_RISINGDETECT 0x0148
148 #define OMAP4_GPIO_FALLINGDETECT 0x014c
149 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
152 #define OMAP4_GPIO_SETDATAOUT 0x0194
153 /*
154 * omap34xx specific GPIO registers
155 */
156
157 #define OMAP34XX_GPIO1_BASE OMAP2_L4_IO_ADDRESS(0x48310000)
158 #define OMAP34XX_GPIO2_BASE OMAP2_L4_IO_ADDRESS(0x49050000)
159 #define OMAP34XX_GPIO3_BASE OMAP2_L4_IO_ADDRESS(0x49052000)
160 #define OMAP34XX_GPIO4_BASE OMAP2_L4_IO_ADDRESS(0x49054000)
161 #define OMAP34XX_GPIO5_BASE OMAP2_L4_IO_ADDRESS(0x49056000)
162 #define OMAP34XX_GPIO6_BASE OMAP2_L4_IO_ADDRESS(0x49058000)
163
164 /*
165 * OMAP44XX specific GPIO registers
166 */
167 #define OMAP44XX_GPIO1_BASE OMAP2_L4_IO_ADDRESS(0x4a310000)
168 #define OMAP44XX_GPIO2_BASE OMAP2_L4_IO_ADDRESS(0x48055000)
169 #define OMAP44XX_GPIO3_BASE OMAP2_L4_IO_ADDRESS(0x48057000)
170 #define OMAP44XX_GPIO4_BASE OMAP2_L4_IO_ADDRESS(0x48059000)
171 #define OMAP44XX_GPIO5_BASE OMAP2_L4_IO_ADDRESS(0x4805B000)
172 #define OMAP44XX_GPIO6_BASE OMAP2_L4_IO_ADDRESS(0x4805D000)
173
174 struct gpio_bank {
175 void __iomem *base;
176 u16 irq;
177 u16 virtual_irq_start;
178 int method;
179 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
180 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
181 u32 suspend_wakeup;
182 u32 saved_wakeup;
183 #endif
184 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
185 defined(CONFIG_ARCH_OMAP4)
186 u32 non_wakeup_gpios;
187 u32 enabled_non_wakeup_gpios;
188
189 u32 saved_datain;
190 u32 saved_fallingdetect;
191 u32 saved_risingdetect;
192 #endif
193 u32 level_mask;
194 spinlock_t lock;
195 struct gpio_chip chip;
196 struct clk *dbck;
197 };
198
199 #define METHOD_MPUIO 0
200 #define METHOD_GPIO_1510 1
201 #define METHOD_GPIO_1610 2
202 #define METHOD_GPIO_7XX 3
203 #define METHOD_GPIO_24XX 5
204
205 #ifdef CONFIG_ARCH_OMAP16XX
206 static struct gpio_bank gpio_bank_1610[5] = {
207 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
208 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
209 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
210 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
211 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
212 };
213 #endif
214
215 #ifdef CONFIG_ARCH_OMAP15XX
216 static struct gpio_bank gpio_bank_1510[2] = {
217 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
218 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
219 };
220 #endif
221
222 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
223 static struct gpio_bank gpio_bank_7xx[7] = {
224 { OMAP1_MPUIO_VBASE, INT_7XX_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
225 { OMAP7XX_GPIO1_BASE, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_7XX },
226 { OMAP7XX_GPIO2_BASE, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_7XX },
227 { OMAP7XX_GPIO3_BASE, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_7XX },
228 { OMAP7XX_GPIO4_BASE, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_7XX },
229 { OMAP7XX_GPIO5_BASE, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_7XX },
230 { OMAP7XX_GPIO6_BASE, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_7XX },
231 };
232 #endif
233
234 #ifdef CONFIG_ARCH_OMAP24XX
235
236 static struct gpio_bank gpio_bank_242x[4] = {
237 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
238 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
239 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
240 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
241 };
242
243 static struct gpio_bank gpio_bank_243x[5] = {
244 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
245 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
246 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
247 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
248 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
249 };
250
251 #endif
252
253 #ifdef CONFIG_ARCH_OMAP34XX
254 static struct gpio_bank gpio_bank_34xx[6] = {
255 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
256 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
257 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
258 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
259 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
260 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
261 };
262
263 #endif
264
265 #ifdef CONFIG_ARCH_OMAP4
266 static struct gpio_bank gpio_bank_44xx[6] = {
267 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
268 METHOD_GPIO_24XX },
269 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
270 METHOD_GPIO_24XX },
271 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
272 METHOD_GPIO_24XX },
273 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
274 METHOD_GPIO_24XX },
275 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
276 METHOD_GPIO_24XX },
277 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
278 METHOD_GPIO_24XX },
279 };
280
281 #endif
282
283 static struct gpio_bank *gpio_bank;
284 static int gpio_bank_count;
285
286 static inline struct gpio_bank *get_gpio_bank(int gpio)
287 {
288 if (cpu_is_omap15xx()) {
289 if (OMAP_GPIO_IS_MPUIO(gpio))
290 return &gpio_bank[0];
291 return &gpio_bank[1];
292 }
293 if (cpu_is_omap16xx()) {
294 if (OMAP_GPIO_IS_MPUIO(gpio))
295 return &gpio_bank[0];
296 return &gpio_bank[1 + (gpio >> 4)];
297 }
298 if (cpu_is_omap7xx()) {
299 if (OMAP_GPIO_IS_MPUIO(gpio))
300 return &gpio_bank[0];
301 return &gpio_bank[1 + (gpio >> 5)];
302 }
303 if (cpu_is_omap24xx())
304 return &gpio_bank[gpio >> 5];
305 if (cpu_is_omap34xx() || cpu_is_omap44xx())
306 return &gpio_bank[gpio >> 5];
307 BUG();
308 return NULL;
309 }
310
311 static inline int get_gpio_index(int gpio)
312 {
313 if (cpu_is_omap7xx())
314 return gpio & 0x1f;
315 if (cpu_is_omap24xx())
316 return gpio & 0x1f;
317 if (cpu_is_omap34xx() || cpu_is_omap44xx())
318 return gpio & 0x1f;
319 return gpio & 0x0f;
320 }
321
322 static inline int gpio_valid(int gpio)
323 {
324 if (gpio < 0)
325 return -1;
326 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
327 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
328 return -1;
329 return 0;
330 }
331 if (cpu_is_omap15xx() && gpio < 16)
332 return 0;
333 if ((cpu_is_omap16xx()) && gpio < 64)
334 return 0;
335 if (cpu_is_omap7xx() && gpio < 192)
336 return 0;
337 if (cpu_is_omap24xx() && gpio < 128)
338 return 0;
339 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
340 return 0;
341 return -1;
342 }
343
344 static int check_gpio(int gpio)
345 {
346 if (unlikely(gpio_valid(gpio) < 0)) {
347 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
348 dump_stack();
349 return -1;
350 }
351 return 0;
352 }
353
354 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
355 {
356 void __iomem *reg = bank->base;
357 u32 l;
358
359 switch (bank->method) {
360 #ifdef CONFIG_ARCH_OMAP1
361 case METHOD_MPUIO:
362 reg += OMAP_MPUIO_IO_CNTL;
363 break;
364 #endif
365 #ifdef CONFIG_ARCH_OMAP15XX
366 case METHOD_GPIO_1510:
367 reg += OMAP1510_GPIO_DIR_CONTROL;
368 break;
369 #endif
370 #ifdef CONFIG_ARCH_OMAP16XX
371 case METHOD_GPIO_1610:
372 reg += OMAP1610_GPIO_DIRECTION;
373 break;
374 #endif
375 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
376 case METHOD_GPIO_7XX:
377 reg += OMAP7XX_GPIO_DIR_CONTROL;
378 break;
379 #endif
380 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
381 case METHOD_GPIO_24XX:
382 reg += OMAP24XX_GPIO_OE;
383 break;
384 #endif
385 #if defined(CONFIG_ARCH_OMAP4)
386 case METHOD_GPIO_24XX:
387 reg += OMAP4_GPIO_OE;
388 break;
389 #endif
390 default:
391 WARN_ON(1);
392 return;
393 }
394 l = __raw_readl(reg);
395 if (is_input)
396 l |= 1 << gpio;
397 else
398 l &= ~(1 << gpio);
399 __raw_writel(l, reg);
400 }
401
402 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
403 {
404 void __iomem *reg = bank->base;
405 u32 l = 0;
406
407 switch (bank->method) {
408 #ifdef CONFIG_ARCH_OMAP1
409 case METHOD_MPUIO:
410 reg += OMAP_MPUIO_OUTPUT;
411 l = __raw_readl(reg);
412 if (enable)
413 l |= 1 << gpio;
414 else
415 l &= ~(1 << gpio);
416 break;
417 #endif
418 #ifdef CONFIG_ARCH_OMAP15XX
419 case METHOD_GPIO_1510:
420 reg += OMAP1510_GPIO_DATA_OUTPUT;
421 l = __raw_readl(reg);
422 if (enable)
423 l |= 1 << gpio;
424 else
425 l &= ~(1 << gpio);
426 break;
427 #endif
428 #ifdef CONFIG_ARCH_OMAP16XX
429 case METHOD_GPIO_1610:
430 if (enable)
431 reg += OMAP1610_GPIO_SET_DATAOUT;
432 else
433 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
434 l = 1 << gpio;
435 break;
436 #endif
437 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
438 case METHOD_GPIO_7XX:
439 reg += OMAP7XX_GPIO_DATA_OUTPUT;
440 l = __raw_readl(reg);
441 if (enable)
442 l |= 1 << gpio;
443 else
444 l &= ~(1 << gpio);
445 break;
446 #endif
447 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
448 case METHOD_GPIO_24XX:
449 if (enable)
450 reg += OMAP24XX_GPIO_SETDATAOUT;
451 else
452 reg += OMAP24XX_GPIO_CLEARDATAOUT;
453 l = 1 << gpio;
454 break;
455 #endif
456 #ifdef CONFIG_ARCH_OMAP4
457 case METHOD_GPIO_24XX:
458 if (enable)
459 reg += OMAP4_GPIO_SETDATAOUT;
460 else
461 reg += OMAP4_GPIO_CLEARDATAOUT;
462 l = 1 << gpio;
463 break;
464 #endif
465 default:
466 WARN_ON(1);
467 return;
468 }
469 __raw_writel(l, reg);
470 }
471
472 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
473 {
474 void __iomem *reg;
475
476 if (check_gpio(gpio) < 0)
477 return -EINVAL;
478 reg = bank->base;
479 switch (bank->method) {
480 #ifdef CONFIG_ARCH_OMAP1
481 case METHOD_MPUIO:
482 reg += OMAP_MPUIO_INPUT_LATCH;
483 break;
484 #endif
485 #ifdef CONFIG_ARCH_OMAP15XX
486 case METHOD_GPIO_1510:
487 reg += OMAP1510_GPIO_DATA_INPUT;
488 break;
489 #endif
490 #ifdef CONFIG_ARCH_OMAP16XX
491 case METHOD_GPIO_1610:
492 reg += OMAP1610_GPIO_DATAIN;
493 break;
494 #endif
495 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
496 case METHOD_GPIO_7XX:
497 reg += OMAP7XX_GPIO_DATA_INPUT;
498 break;
499 #endif
500 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
501 case METHOD_GPIO_24XX:
502 reg += OMAP24XX_GPIO_DATAIN;
503 break;
504 #endif
505 #ifdef CONFIG_ARCH_OMAP4
506 case METHOD_GPIO_24XX:
507 reg += OMAP4_GPIO_DATAIN;
508 break;
509 #endif
510 default:
511 return -EINVAL;
512 }
513 return (__raw_readl(reg)
514 & (1 << get_gpio_index(gpio))) != 0;
515 }
516
517 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
518 {
519 void __iomem *reg;
520
521 if (check_gpio(gpio) < 0)
522 return -EINVAL;
523 reg = bank->base;
524
525 switch (bank->method) {
526 #ifdef CONFIG_ARCH_OMAP1
527 case METHOD_MPUIO:
528 reg += OMAP_MPUIO_OUTPUT;
529 break;
530 #endif
531 #ifdef CONFIG_ARCH_OMAP15XX
532 case METHOD_GPIO_1510:
533 reg += OMAP1510_GPIO_DATA_OUTPUT;
534 break;
535 #endif
536 #ifdef CONFIG_ARCH_OMAP16XX
537 case METHOD_GPIO_1610:
538 reg += OMAP1610_GPIO_DATAOUT;
539 break;
540 #endif
541 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
542 case METHOD_GPIO_7XX:
543 reg += OMAP7XX_GPIO_DATA_OUTPUT;
544 break;
545 #endif
546 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
547 defined(CONFIG_ARCH_OMAP4)
548 case METHOD_GPIO_24XX:
549 reg += OMAP24XX_GPIO_DATAOUT;
550 break;
551 #endif
552 default:
553 return -EINVAL;
554 }
555
556 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
557 }
558
559 #define MOD_REG_BIT(reg, bit_mask, set) \
560 do { \
561 int l = __raw_readl(base + reg); \
562 if (set) l |= bit_mask; \
563 else l &= ~bit_mask; \
564 __raw_writel(l, base + reg); \
565 } while(0)
566
567 void omap_set_gpio_debounce(int gpio, int enable)
568 {
569 struct gpio_bank *bank;
570 void __iomem *reg;
571 unsigned long flags;
572 u32 val, l = 1 << get_gpio_index(gpio);
573
574 if (cpu_class_is_omap1())
575 return;
576
577 bank = get_gpio_bank(gpio);
578 reg = bank->base;
579 #ifdef CONFIG_ARCH_OMAP4
580 reg += OMAP4_GPIO_DEBOUNCENABLE;
581 #else
582 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
583 #endif
584
585 spin_lock_irqsave(&bank->lock, flags);
586 val = __raw_readl(reg);
587
588 if (enable && !(val & l))
589 val |= l;
590 else if (!enable && (val & l))
591 val &= ~l;
592 else
593 goto done;
594
595 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
596 if (enable)
597 clk_enable(bank->dbck);
598 else
599 clk_disable(bank->dbck);
600 }
601
602 __raw_writel(val, reg);
603 done:
604 spin_unlock_irqrestore(&bank->lock, flags);
605 }
606 EXPORT_SYMBOL(omap_set_gpio_debounce);
607
608 void omap_set_gpio_debounce_time(int gpio, int enc_time)
609 {
610 struct gpio_bank *bank;
611 void __iomem *reg;
612
613 if (cpu_class_is_omap1())
614 return;
615
616 bank = get_gpio_bank(gpio);
617 reg = bank->base;
618
619 enc_time &= 0xff;
620 #ifdef CONFIG_ARCH_OMAP4
621 reg += OMAP4_GPIO_DEBOUNCINGTIME;
622 #else
623 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
624 #endif
625 __raw_writel(enc_time, reg);
626 }
627 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
628
629 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
630 defined(CONFIG_ARCH_OMAP4)
631 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
632 int trigger)
633 {
634 void __iomem *base = bank->base;
635 u32 gpio_bit = 1 << gpio;
636 u32 val;
637
638 if (cpu_is_omap44xx()) {
639 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
640 trigger & IRQ_TYPE_LEVEL_LOW);
641 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
642 trigger & IRQ_TYPE_LEVEL_HIGH);
643 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
644 trigger & IRQ_TYPE_EDGE_RISING);
645 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
646 trigger & IRQ_TYPE_EDGE_FALLING);
647 } else {
648 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
649 trigger & IRQ_TYPE_LEVEL_LOW);
650 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
651 trigger & IRQ_TYPE_LEVEL_HIGH);
652 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
653 trigger & IRQ_TYPE_EDGE_RISING);
654 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
655 trigger & IRQ_TYPE_EDGE_FALLING);
656 }
657 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
658 if (cpu_is_omap44xx()) {
659 if (trigger != 0)
660 __raw_writel(1 << gpio, bank->base+
661 OMAP4_GPIO_IRQWAKEN0);
662 else {
663 val = __raw_readl(bank->base +
664 OMAP4_GPIO_IRQWAKEN0);
665 __raw_writel(val & (~(1 << gpio)), bank->base +
666 OMAP4_GPIO_IRQWAKEN0);
667 }
668 } else {
669 if (trigger != 0)
670 __raw_writel(1 << gpio, bank->base
671 + OMAP24XX_GPIO_SETWKUENA);
672 else
673 __raw_writel(1 << gpio, bank->base
674 + OMAP24XX_GPIO_CLEARWKUENA);
675 }
676 } else {
677 if (trigger != 0)
678 bank->enabled_non_wakeup_gpios |= gpio_bit;
679 else
680 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
681 }
682
683 if (cpu_is_omap44xx()) {
684 bank->level_mask =
685 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
686 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
687 } else {
688 bank->level_mask =
689 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
690 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
691 }
692 }
693 #endif
694
695 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
696 {
697 void __iomem *reg = bank->base;
698 u32 l = 0;
699
700 switch (bank->method) {
701 #ifdef CONFIG_ARCH_OMAP1
702 case METHOD_MPUIO:
703 reg += OMAP_MPUIO_GPIO_INT_EDGE;
704 l = __raw_readl(reg);
705 if (trigger & IRQ_TYPE_EDGE_RISING)
706 l |= 1 << gpio;
707 else if (trigger & IRQ_TYPE_EDGE_FALLING)
708 l &= ~(1 << gpio);
709 else
710 goto bad;
711 break;
712 #endif
713 #ifdef CONFIG_ARCH_OMAP15XX
714 case METHOD_GPIO_1510:
715 reg += OMAP1510_GPIO_INT_CONTROL;
716 l = __raw_readl(reg);
717 if (trigger & IRQ_TYPE_EDGE_RISING)
718 l |= 1 << gpio;
719 else if (trigger & IRQ_TYPE_EDGE_FALLING)
720 l &= ~(1 << gpio);
721 else
722 goto bad;
723 break;
724 #endif
725 #ifdef CONFIG_ARCH_OMAP16XX
726 case METHOD_GPIO_1610:
727 if (gpio & 0x08)
728 reg += OMAP1610_GPIO_EDGE_CTRL2;
729 else
730 reg += OMAP1610_GPIO_EDGE_CTRL1;
731 gpio &= 0x07;
732 l = __raw_readl(reg);
733 l &= ~(3 << (gpio << 1));
734 if (trigger & IRQ_TYPE_EDGE_RISING)
735 l |= 2 << (gpio << 1);
736 if (trigger & IRQ_TYPE_EDGE_FALLING)
737 l |= 1 << (gpio << 1);
738 if (trigger)
739 /* Enable wake-up during idle for dynamic tick */
740 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
741 else
742 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
743 break;
744 #endif
745 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
746 case METHOD_GPIO_7XX:
747 reg += OMAP7XX_GPIO_INT_CONTROL;
748 l = __raw_readl(reg);
749 if (trigger & IRQ_TYPE_EDGE_RISING)
750 l |= 1 << gpio;
751 else if (trigger & IRQ_TYPE_EDGE_FALLING)
752 l &= ~(1 << gpio);
753 else
754 goto bad;
755 break;
756 #endif
757 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
758 defined(CONFIG_ARCH_OMAP4)
759 case METHOD_GPIO_24XX:
760 set_24xx_gpio_triggering(bank, gpio, trigger);
761 break;
762 #endif
763 default:
764 goto bad;
765 }
766 __raw_writel(l, reg);
767 return 0;
768 bad:
769 return -EINVAL;
770 }
771
772 static int gpio_irq_type(unsigned irq, unsigned type)
773 {
774 struct gpio_bank *bank;
775 unsigned gpio;
776 int retval;
777 unsigned long flags;
778
779 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
780 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
781 else
782 gpio = irq - IH_GPIO_BASE;
783
784 if (check_gpio(gpio) < 0)
785 return -EINVAL;
786
787 if (type & ~IRQ_TYPE_SENSE_MASK)
788 return -EINVAL;
789
790 /* OMAP1 allows only only edge triggering */
791 if (!cpu_class_is_omap2()
792 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
793 return -EINVAL;
794
795 bank = get_irq_chip_data(irq);
796 spin_lock_irqsave(&bank->lock, flags);
797 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
798 if (retval == 0) {
799 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
800 irq_desc[irq].status |= type;
801 }
802 spin_unlock_irqrestore(&bank->lock, flags);
803
804 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
805 __set_irq_handler_unlocked(irq, handle_level_irq);
806 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
807 __set_irq_handler_unlocked(irq, handle_edge_irq);
808
809 return retval;
810 }
811
812 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
813 {
814 void __iomem *reg = bank->base;
815
816 switch (bank->method) {
817 #ifdef CONFIG_ARCH_OMAP1
818 case METHOD_MPUIO:
819 /* MPUIO irqstatus is reset by reading the status register,
820 * so do nothing here */
821 return;
822 #endif
823 #ifdef CONFIG_ARCH_OMAP15XX
824 case METHOD_GPIO_1510:
825 reg += OMAP1510_GPIO_INT_STATUS;
826 break;
827 #endif
828 #ifdef CONFIG_ARCH_OMAP16XX
829 case METHOD_GPIO_1610:
830 reg += OMAP1610_GPIO_IRQSTATUS1;
831 break;
832 #endif
833 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
834 case METHOD_GPIO_7XX:
835 reg += OMAP7XX_GPIO_INT_STATUS;
836 break;
837 #endif
838 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
839 case METHOD_GPIO_24XX:
840 reg += OMAP24XX_GPIO_IRQSTATUS1;
841 break;
842 #endif
843 #if defined(CONFIG_ARCH_OMAP4)
844 case METHOD_GPIO_24XX:
845 reg += OMAP4_GPIO_IRQSTATUS0;
846 break;
847 #endif
848 default:
849 WARN_ON(1);
850 return;
851 }
852 __raw_writel(gpio_mask, reg);
853
854 /* Workaround for clearing DSP GPIO interrupts to allow retention */
855 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
856 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
857 #endif
858 #if defined(CONFIG_ARCH_OMAP4)
859 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
860 #endif
861 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
862 __raw_writel(gpio_mask, reg);
863
864 /* Flush posted write for the irq status to avoid spurious interrupts */
865 __raw_readl(reg);
866 }
867 }
868
869 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
870 {
871 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
872 }
873
874 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
875 {
876 void __iomem *reg = bank->base;
877 int inv = 0;
878 u32 l;
879 u32 mask;
880
881 switch (bank->method) {
882 #ifdef CONFIG_ARCH_OMAP1
883 case METHOD_MPUIO:
884 reg += OMAP_MPUIO_GPIO_MASKIT;
885 mask = 0xffff;
886 inv = 1;
887 break;
888 #endif
889 #ifdef CONFIG_ARCH_OMAP15XX
890 case METHOD_GPIO_1510:
891 reg += OMAP1510_GPIO_INT_MASK;
892 mask = 0xffff;
893 inv = 1;
894 break;
895 #endif
896 #ifdef CONFIG_ARCH_OMAP16XX
897 case METHOD_GPIO_1610:
898 reg += OMAP1610_GPIO_IRQENABLE1;
899 mask = 0xffff;
900 break;
901 #endif
902 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
903 case METHOD_GPIO_7XX:
904 reg += OMAP7XX_GPIO_INT_MASK;
905 mask = 0xffffffff;
906 inv = 1;
907 break;
908 #endif
909 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
910 case METHOD_GPIO_24XX:
911 reg += OMAP24XX_GPIO_IRQENABLE1;
912 mask = 0xffffffff;
913 break;
914 #endif
915 #if defined(CONFIG_ARCH_OMAP4)
916 case METHOD_GPIO_24XX:
917 reg += OMAP4_GPIO_IRQSTATUSSET0;
918 mask = 0xffffffff;
919 break;
920 #endif
921 default:
922 WARN_ON(1);
923 return 0;
924 }
925
926 l = __raw_readl(reg);
927 if (inv)
928 l = ~l;
929 l &= mask;
930 return l;
931 }
932
933 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
934 {
935 void __iomem *reg = bank->base;
936 u32 l;
937
938 switch (bank->method) {
939 #ifdef CONFIG_ARCH_OMAP1
940 case METHOD_MPUIO:
941 reg += OMAP_MPUIO_GPIO_MASKIT;
942 l = __raw_readl(reg);
943 if (enable)
944 l &= ~(gpio_mask);
945 else
946 l |= gpio_mask;
947 break;
948 #endif
949 #ifdef CONFIG_ARCH_OMAP15XX
950 case METHOD_GPIO_1510:
951 reg += OMAP1510_GPIO_INT_MASK;
952 l = __raw_readl(reg);
953 if (enable)
954 l &= ~(gpio_mask);
955 else
956 l |= gpio_mask;
957 break;
958 #endif
959 #ifdef CONFIG_ARCH_OMAP16XX
960 case METHOD_GPIO_1610:
961 if (enable)
962 reg += OMAP1610_GPIO_SET_IRQENABLE1;
963 else
964 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
965 l = gpio_mask;
966 break;
967 #endif
968 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
969 case METHOD_GPIO_7XX:
970 reg += OMAP7XX_GPIO_INT_MASK;
971 l = __raw_readl(reg);
972 if (enable)
973 l &= ~(gpio_mask);
974 else
975 l |= gpio_mask;
976 break;
977 #endif
978 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
979 case METHOD_GPIO_24XX:
980 if (enable)
981 reg += OMAP24XX_GPIO_SETIRQENABLE1;
982 else
983 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
984 l = gpio_mask;
985 break;
986 #endif
987 #ifdef CONFIG_ARCH_OMAP4
988 case METHOD_GPIO_24XX:
989 if (enable)
990 reg += OMAP4_GPIO_IRQSTATUSSET0;
991 else
992 reg += OMAP4_GPIO_IRQSTATUSCLR0;
993 l = gpio_mask;
994 break;
995 #endif
996 default:
997 WARN_ON(1);
998 return;
999 }
1000 __raw_writel(l, reg);
1001 }
1002
1003 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1004 {
1005 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1006 }
1007
1008 /*
1009 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1010 * 1510 does not seem to have a wake-up register. If JTAG is connected
1011 * to the target, system will wake up always on GPIO events. While
1012 * system is running all registered GPIO interrupts need to have wake-up
1013 * enabled. When system is suspended, only selected GPIO interrupts need
1014 * to have wake-up enabled.
1015 */
1016 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1017 {
1018 unsigned long flags;
1019
1020 switch (bank->method) {
1021 #ifdef CONFIG_ARCH_OMAP16XX
1022 case METHOD_MPUIO:
1023 case METHOD_GPIO_1610:
1024 spin_lock_irqsave(&bank->lock, flags);
1025 if (enable)
1026 bank->suspend_wakeup |= (1 << gpio);
1027 else
1028 bank->suspend_wakeup &= ~(1 << gpio);
1029 spin_unlock_irqrestore(&bank->lock, flags);
1030 return 0;
1031 #endif
1032 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1033 defined(CONFIG_ARCH_OMAP4)
1034 case METHOD_GPIO_24XX:
1035 if (bank->non_wakeup_gpios & (1 << gpio)) {
1036 printk(KERN_ERR "Unable to modify wakeup on "
1037 "non-wakeup GPIO%d\n",
1038 (bank - gpio_bank) * 32 + gpio);
1039 return -EINVAL;
1040 }
1041 spin_lock_irqsave(&bank->lock, flags);
1042 if (enable)
1043 bank->suspend_wakeup |= (1 << gpio);
1044 else
1045 bank->suspend_wakeup &= ~(1 << gpio);
1046 spin_unlock_irqrestore(&bank->lock, flags);
1047 return 0;
1048 #endif
1049 default:
1050 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1051 bank->method);
1052 return -EINVAL;
1053 }
1054 }
1055
1056 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1057 {
1058 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1059 _set_gpio_irqenable(bank, gpio, 0);
1060 _clear_gpio_irqstatus(bank, gpio);
1061 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1062 }
1063
1064 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1065 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1066 {
1067 unsigned int gpio = irq - IH_GPIO_BASE;
1068 struct gpio_bank *bank;
1069 int retval;
1070
1071 if (check_gpio(gpio) < 0)
1072 return -ENODEV;
1073 bank = get_irq_chip_data(irq);
1074 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1075
1076 return retval;
1077 }
1078
1079 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1080 {
1081 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1082 unsigned long flags;
1083
1084 spin_lock_irqsave(&bank->lock, flags);
1085
1086 /* Set trigger to none. You need to enable the desired trigger with
1087 * request_irq() or set_irq_type().
1088 */
1089 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1090
1091 #ifdef CONFIG_ARCH_OMAP15XX
1092 if (bank->method == METHOD_GPIO_1510) {
1093 void __iomem *reg;
1094
1095 /* Claim the pin for MPU */
1096 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1097 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1098 }
1099 #endif
1100 spin_unlock_irqrestore(&bank->lock, flags);
1101
1102 return 0;
1103 }
1104
1105 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1106 {
1107 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1108 unsigned long flags;
1109
1110 spin_lock_irqsave(&bank->lock, flags);
1111 #ifdef CONFIG_ARCH_OMAP16XX
1112 if (bank->method == METHOD_GPIO_1610) {
1113 /* Disable wake-up during idle for dynamic tick */
1114 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1115 __raw_writel(1 << offset, reg);
1116 }
1117 #endif
1118 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1119 defined(CONFIG_ARCH_OMAP4)
1120 if (bank->method == METHOD_GPIO_24XX) {
1121 /* Disable wake-up during idle for dynamic tick */
1122 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1123 __raw_writel(1 << offset, reg);
1124 }
1125 #endif
1126 _reset_gpio(bank, bank->chip.base + offset);
1127 spin_unlock_irqrestore(&bank->lock, flags);
1128 }
1129
1130 /*
1131 * We need to unmask the GPIO bank interrupt as soon as possible to
1132 * avoid missing GPIO interrupts for other lines in the bank.
1133 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1134 * in the bank to avoid missing nested interrupts for a GPIO line.
1135 * If we wait to unmask individual GPIO lines in the bank after the
1136 * line's interrupt handler has been run, we may miss some nested
1137 * interrupts.
1138 */
1139 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1140 {
1141 void __iomem *isr_reg = NULL;
1142 u32 isr;
1143 unsigned int gpio_irq;
1144 struct gpio_bank *bank;
1145 u32 retrigger = 0;
1146 int unmasked = 0;
1147
1148 desc->chip->ack(irq);
1149
1150 bank = get_irq_data(irq);
1151 #ifdef CONFIG_ARCH_OMAP1
1152 if (bank->method == METHOD_MPUIO)
1153 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1154 #endif
1155 #ifdef CONFIG_ARCH_OMAP15XX
1156 if (bank->method == METHOD_GPIO_1510)
1157 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1158 #endif
1159 #if defined(CONFIG_ARCH_OMAP16XX)
1160 if (bank->method == METHOD_GPIO_1610)
1161 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1162 #endif
1163 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1164 if (bank->method == METHOD_GPIO_7XX)
1165 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1166 #endif
1167 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1168 if (bank->method == METHOD_GPIO_24XX)
1169 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1170 #endif
1171 #if defined(CONFIG_ARCH_OMAP4)
1172 if (bank->method == METHOD_GPIO_24XX)
1173 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1174 #endif
1175 while(1) {
1176 u32 isr_saved, level_mask = 0;
1177 u32 enabled;
1178
1179 enabled = _get_gpio_irqbank_mask(bank);
1180 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1181
1182 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1183 isr &= 0x0000ffff;
1184
1185 if (cpu_class_is_omap2()) {
1186 level_mask = bank->level_mask & enabled;
1187 }
1188
1189 /* clear edge sensitive interrupts before handler(s) are
1190 called so that we don't miss any interrupt occurred while
1191 executing them */
1192 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1193 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1194 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1195
1196 /* if there is only edge sensitive GPIO pin interrupts
1197 configured, we could unmask GPIO bank interrupt immediately */
1198 if (!level_mask && !unmasked) {
1199 unmasked = 1;
1200 desc->chip->unmask(irq);
1201 }
1202
1203 isr |= retrigger;
1204 retrigger = 0;
1205 if (!isr)
1206 break;
1207
1208 gpio_irq = bank->virtual_irq_start;
1209 for (; isr != 0; isr >>= 1, gpio_irq++) {
1210 if (!(isr & 1))
1211 continue;
1212
1213 generic_handle_irq(gpio_irq);
1214 }
1215 }
1216 /* if bank has any level sensitive GPIO pin interrupt
1217 configured, we must unmask the bank interrupt only after
1218 handler(s) are executed in order to avoid spurious bank
1219 interrupt */
1220 if (!unmasked)
1221 desc->chip->unmask(irq);
1222
1223 }
1224
1225 static void gpio_irq_shutdown(unsigned int irq)
1226 {
1227 unsigned int gpio = irq - IH_GPIO_BASE;
1228 struct gpio_bank *bank = get_irq_chip_data(irq);
1229
1230 _reset_gpio(bank, gpio);
1231 }
1232
1233 static void gpio_ack_irq(unsigned int irq)
1234 {
1235 unsigned int gpio = irq - IH_GPIO_BASE;
1236 struct gpio_bank *bank = get_irq_chip_data(irq);
1237
1238 _clear_gpio_irqstatus(bank, gpio);
1239 }
1240
1241 static void gpio_mask_irq(unsigned int irq)
1242 {
1243 unsigned int gpio = irq - IH_GPIO_BASE;
1244 struct gpio_bank *bank = get_irq_chip_data(irq);
1245
1246 _set_gpio_irqenable(bank, gpio, 0);
1247 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1248 }
1249
1250 static void gpio_unmask_irq(unsigned int irq)
1251 {
1252 unsigned int gpio = irq - IH_GPIO_BASE;
1253 struct gpio_bank *bank = get_irq_chip_data(irq);
1254 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1255 struct irq_desc *desc = irq_to_desc(irq);
1256 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1257
1258 if (trigger)
1259 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1260
1261 /* For level-triggered GPIOs, the clearing must be done after
1262 * the HW source is cleared, thus after the handler has run */
1263 if (bank->level_mask & irq_mask) {
1264 _set_gpio_irqenable(bank, gpio, 0);
1265 _clear_gpio_irqstatus(bank, gpio);
1266 }
1267
1268 _set_gpio_irqenable(bank, gpio, 1);
1269 }
1270
1271 static struct irq_chip gpio_irq_chip = {
1272 .name = "GPIO",
1273 .shutdown = gpio_irq_shutdown,
1274 .ack = gpio_ack_irq,
1275 .mask = gpio_mask_irq,
1276 .unmask = gpio_unmask_irq,
1277 .set_type = gpio_irq_type,
1278 .set_wake = gpio_wake_enable,
1279 };
1280
1281 /*---------------------------------------------------------------------*/
1282
1283 #ifdef CONFIG_ARCH_OMAP1
1284
1285 /* MPUIO uses the always-on 32k clock */
1286
1287 static void mpuio_ack_irq(unsigned int irq)
1288 {
1289 /* The ISR is reset automatically, so do nothing here. */
1290 }
1291
1292 static void mpuio_mask_irq(unsigned int irq)
1293 {
1294 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1295 struct gpio_bank *bank = get_irq_chip_data(irq);
1296
1297 _set_gpio_irqenable(bank, gpio, 0);
1298 }
1299
1300 static void mpuio_unmask_irq(unsigned int irq)
1301 {
1302 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1303 struct gpio_bank *bank = get_irq_chip_data(irq);
1304
1305 _set_gpio_irqenable(bank, gpio, 1);
1306 }
1307
1308 static struct irq_chip mpuio_irq_chip = {
1309 .name = "MPUIO",
1310 .ack = mpuio_ack_irq,
1311 .mask = mpuio_mask_irq,
1312 .unmask = mpuio_unmask_irq,
1313 .set_type = gpio_irq_type,
1314 #ifdef CONFIG_ARCH_OMAP16XX
1315 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1316 .set_wake = gpio_wake_enable,
1317 #endif
1318 };
1319
1320
1321 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1322
1323
1324 #ifdef CONFIG_ARCH_OMAP16XX
1325
1326 #include <linux/platform_device.h>
1327
1328 static int omap_mpuio_suspend_noirq(struct device *dev)
1329 {
1330 struct platform_device *pdev = to_platform_device(dev);
1331 struct gpio_bank *bank = platform_get_drvdata(pdev);
1332 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&bank->lock, flags);
1336 bank->saved_wakeup = __raw_readl(mask_reg);
1337 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1338 spin_unlock_irqrestore(&bank->lock, flags);
1339
1340 return 0;
1341 }
1342
1343 static int omap_mpuio_resume_noirq(struct device *dev)
1344 {
1345 struct platform_device *pdev = to_platform_device(dev);
1346 struct gpio_bank *bank = platform_get_drvdata(pdev);
1347 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1348 unsigned long flags;
1349
1350 spin_lock_irqsave(&bank->lock, flags);
1351 __raw_writel(bank->saved_wakeup, mask_reg);
1352 spin_unlock_irqrestore(&bank->lock, flags);
1353
1354 return 0;
1355 }
1356
1357 static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1358 .suspend_noirq = omap_mpuio_suspend_noirq,
1359 .resume_noirq = omap_mpuio_resume_noirq,
1360 };
1361
1362 /* use platform_driver for this, now that there's no longer any
1363 * point to sys_device (other than not disturbing old code).
1364 */
1365 static struct platform_driver omap_mpuio_driver = {
1366 .driver = {
1367 .name = "mpuio",
1368 .pm = &omap_mpuio_dev_pm_ops,
1369 },
1370 };
1371
1372 static struct platform_device omap_mpuio_device = {
1373 .name = "mpuio",
1374 .id = -1,
1375 .dev = {
1376 .driver = &omap_mpuio_driver.driver,
1377 }
1378 /* could list the /proc/iomem resources */
1379 };
1380
1381 static inline void mpuio_init(void)
1382 {
1383 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1384
1385 if (platform_driver_register(&omap_mpuio_driver) == 0)
1386 (void) platform_device_register(&omap_mpuio_device);
1387 }
1388
1389 #else
1390 static inline void mpuio_init(void) {}
1391 #endif /* 16xx */
1392
1393 #else
1394
1395 extern struct irq_chip mpuio_irq_chip;
1396
1397 #define bank_is_mpuio(bank) 0
1398 static inline void mpuio_init(void) {}
1399
1400 #endif
1401
1402 /*---------------------------------------------------------------------*/
1403
1404 /* REVISIT these are stupid implementations! replace by ones that
1405 * don't switch on METHOD_* and which mostly avoid spinlocks
1406 */
1407
1408 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1409 {
1410 struct gpio_bank *bank;
1411 unsigned long flags;
1412
1413 bank = container_of(chip, struct gpio_bank, chip);
1414 spin_lock_irqsave(&bank->lock, flags);
1415 _set_gpio_direction(bank, offset, 1);
1416 spin_unlock_irqrestore(&bank->lock, flags);
1417 return 0;
1418 }
1419
1420 static int gpio_is_input(struct gpio_bank *bank, int mask)
1421 {
1422 void __iomem *reg = bank->base;
1423
1424 switch (bank->method) {
1425 case METHOD_MPUIO:
1426 reg += OMAP_MPUIO_IO_CNTL;
1427 break;
1428 case METHOD_GPIO_1510:
1429 reg += OMAP1510_GPIO_DIR_CONTROL;
1430 break;
1431 case METHOD_GPIO_1610:
1432 reg += OMAP1610_GPIO_DIRECTION;
1433 break;
1434 case METHOD_GPIO_7XX:
1435 reg += OMAP7XX_GPIO_DIR_CONTROL;
1436 break;
1437 case METHOD_GPIO_24XX:
1438 reg += OMAP24XX_GPIO_OE;
1439 break;
1440 }
1441 return __raw_readl(reg) & mask;
1442 }
1443
1444 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1445 {
1446 struct gpio_bank *bank;
1447 void __iomem *reg;
1448 int gpio;
1449 u32 mask;
1450
1451 gpio = chip->base + offset;
1452 bank = get_gpio_bank(gpio);
1453 reg = bank->base;
1454 mask = 1 << get_gpio_index(gpio);
1455
1456 if (gpio_is_input(bank, mask))
1457 return _get_gpio_datain(bank, gpio);
1458 else
1459 return _get_gpio_dataout(bank, gpio);
1460 }
1461
1462 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1463 {
1464 struct gpio_bank *bank;
1465 unsigned long flags;
1466
1467 bank = container_of(chip, struct gpio_bank, chip);
1468 spin_lock_irqsave(&bank->lock, flags);
1469 _set_gpio_dataout(bank, offset, value);
1470 _set_gpio_direction(bank, offset, 0);
1471 spin_unlock_irqrestore(&bank->lock, flags);
1472 return 0;
1473 }
1474
1475 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1476 {
1477 struct gpio_bank *bank;
1478 unsigned long flags;
1479
1480 bank = container_of(chip, struct gpio_bank, chip);
1481 spin_lock_irqsave(&bank->lock, flags);
1482 _set_gpio_dataout(bank, offset, value);
1483 spin_unlock_irqrestore(&bank->lock, flags);
1484 }
1485
1486 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1487 {
1488 struct gpio_bank *bank;
1489
1490 bank = container_of(chip, struct gpio_bank, chip);
1491 return bank->virtual_irq_start + offset;
1492 }
1493
1494 /*---------------------------------------------------------------------*/
1495
1496 static int initialized;
1497 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1498 static struct clk * gpio_ick;
1499 #endif
1500
1501 #if defined(CONFIG_ARCH_OMAP2)
1502 static struct clk * gpio_fck;
1503 #endif
1504
1505 #if defined(CONFIG_ARCH_OMAP2430)
1506 static struct clk * gpio5_ick;
1507 static struct clk * gpio5_fck;
1508 #endif
1509
1510 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1511 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1512 #endif
1513
1514 /* This lock class tells lockdep that GPIO irqs are in a different
1515 * category than their parents, so it won't report false recursion.
1516 */
1517 static struct lock_class_key gpio_lock_class;
1518
1519 static int __init _omap_gpio_init(void)
1520 {
1521 int i;
1522 int gpio = 0;
1523 struct gpio_bank *bank;
1524 char clk_name[11];
1525
1526 initialized = 1;
1527
1528 #if defined(CONFIG_ARCH_OMAP1)
1529 if (cpu_is_omap15xx()) {
1530 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1531 if (IS_ERR(gpio_ick))
1532 printk("Could not get arm_gpio_ck\n");
1533 else
1534 clk_enable(gpio_ick);
1535 }
1536 #endif
1537 #if defined(CONFIG_ARCH_OMAP2)
1538 if (cpu_class_is_omap2()) {
1539 gpio_ick = clk_get(NULL, "gpios_ick");
1540 if (IS_ERR(gpio_ick))
1541 printk("Could not get gpios_ick\n");
1542 else
1543 clk_enable(gpio_ick);
1544 gpio_fck = clk_get(NULL, "gpios_fck");
1545 if (IS_ERR(gpio_fck))
1546 printk("Could not get gpios_fck\n");
1547 else
1548 clk_enable(gpio_fck);
1549
1550 /*
1551 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1552 */
1553 #if defined(CONFIG_ARCH_OMAP2430)
1554 if (cpu_is_omap2430()) {
1555 gpio5_ick = clk_get(NULL, "gpio5_ick");
1556 if (IS_ERR(gpio5_ick))
1557 printk("Could not get gpio5_ick\n");
1558 else
1559 clk_enable(gpio5_ick);
1560 gpio5_fck = clk_get(NULL, "gpio5_fck");
1561 if (IS_ERR(gpio5_fck))
1562 printk("Could not get gpio5_fck\n");
1563 else
1564 clk_enable(gpio5_fck);
1565 }
1566 #endif
1567 }
1568 #endif
1569
1570 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1571 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1572 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1573 sprintf(clk_name, "gpio%d_ick", i + 1);
1574 gpio_iclks[i] = clk_get(NULL, clk_name);
1575 if (IS_ERR(gpio_iclks[i]))
1576 printk(KERN_ERR "Could not get %s\n", clk_name);
1577 else
1578 clk_enable(gpio_iclks[i]);
1579 }
1580 }
1581 #endif
1582
1583
1584 #ifdef CONFIG_ARCH_OMAP15XX
1585 if (cpu_is_omap15xx()) {
1586 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1587 gpio_bank_count = 2;
1588 gpio_bank = gpio_bank_1510;
1589 }
1590 #endif
1591 #if defined(CONFIG_ARCH_OMAP16XX)
1592 if (cpu_is_omap16xx()) {
1593 u32 rev;
1594
1595 gpio_bank_count = 5;
1596 gpio_bank = gpio_bank_1610;
1597 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1598 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1599 (rev >> 4) & 0x0f, rev & 0x0f);
1600 }
1601 #endif
1602 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1603 if (cpu_is_omap7xx()) {
1604 printk(KERN_INFO "OMAP7XX GPIO hardware\n");
1605 gpio_bank_count = 7;
1606 gpio_bank = gpio_bank_7xx;
1607 }
1608 #endif
1609 #ifdef CONFIG_ARCH_OMAP24XX
1610 if (cpu_is_omap242x()) {
1611 int rev;
1612
1613 gpio_bank_count = 4;
1614 gpio_bank = gpio_bank_242x;
1615 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1616 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1617 (rev >> 4) & 0x0f, rev & 0x0f);
1618 }
1619 if (cpu_is_omap243x()) {
1620 int rev;
1621
1622 gpio_bank_count = 5;
1623 gpio_bank = gpio_bank_243x;
1624 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1625 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1626 (rev >> 4) & 0x0f, rev & 0x0f);
1627 }
1628 #endif
1629 #ifdef CONFIG_ARCH_OMAP34XX
1630 if (cpu_is_omap34xx()) {
1631 int rev;
1632
1633 gpio_bank_count = OMAP34XX_NR_GPIOS;
1634 gpio_bank = gpio_bank_34xx;
1635 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1636 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1637 (rev >> 4) & 0x0f, rev & 0x0f);
1638 }
1639 #endif
1640 #ifdef CONFIG_ARCH_OMAP4
1641 if (cpu_is_omap44xx()) {
1642 int rev;
1643
1644 gpio_bank_count = OMAP34XX_NR_GPIOS;
1645 gpio_bank = gpio_bank_44xx;
1646 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1647 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1648 (rev >> 4) & 0x0f, rev & 0x0f);
1649 }
1650 #endif
1651 for (i = 0; i < gpio_bank_count; i++) {
1652 int j, gpio_count = 16;
1653
1654 bank = &gpio_bank[i];
1655 spin_lock_init(&bank->lock);
1656 if (bank_is_mpuio(bank))
1657 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1658 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1659 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1660 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1661 }
1662 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1663 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1664 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1665 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1666 }
1667 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1668 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1669 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1670
1671 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1672 }
1673
1674 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1675 defined(CONFIG_ARCH_OMAP4)
1676 if (bank->method == METHOD_GPIO_24XX) {
1677 static const u32 non_wakeup_gpios[] = {
1678 0xe203ffc0, 0x08700040
1679 };
1680 if (cpu_is_omap44xx()) {
1681 __raw_writel(0xffffffff, bank->base +
1682 OMAP4_GPIO_IRQSTATUSCLR0);
1683 __raw_writew(0x0015, bank->base +
1684 OMAP4_GPIO_SYSCONFIG);
1685 __raw_writel(0x00000000, bank->base +
1686 OMAP4_GPIO_DEBOUNCENABLE);
1687 /* Initialize interface clock ungated, module enabled */
1688 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1689 } else {
1690 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1691 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1692 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1693 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1694
1695 /* Initialize interface clock ungated, module enabled */
1696 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1697 }
1698 if (i < ARRAY_SIZE(non_wakeup_gpios))
1699 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1700 gpio_count = 32;
1701 }
1702 #endif
1703 /* REVISIT eventually switch from OMAP-specific gpio structs
1704 * over to the generic ones
1705 */
1706 bank->chip.request = omap_gpio_request;
1707 bank->chip.free = omap_gpio_free;
1708 bank->chip.direction_input = gpio_input;
1709 bank->chip.get = gpio_get;
1710 bank->chip.direction_output = gpio_output;
1711 bank->chip.set = gpio_set;
1712 bank->chip.to_irq = gpio_2irq;
1713 if (bank_is_mpuio(bank)) {
1714 bank->chip.label = "mpuio";
1715 #ifdef CONFIG_ARCH_OMAP16XX
1716 bank->chip.dev = &omap_mpuio_device.dev;
1717 #endif
1718 bank->chip.base = OMAP_MPUIO(0);
1719 } else {
1720 bank->chip.label = "gpio";
1721 bank->chip.base = gpio;
1722 gpio += gpio_count;
1723 }
1724 bank->chip.ngpio = gpio_count;
1725
1726 gpiochip_add(&bank->chip);
1727
1728 for (j = bank->virtual_irq_start;
1729 j < bank->virtual_irq_start + gpio_count; j++) {
1730 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1731 set_irq_chip_data(j, bank);
1732 if (bank_is_mpuio(bank))
1733 set_irq_chip(j, &mpuio_irq_chip);
1734 else
1735 set_irq_chip(j, &gpio_irq_chip);
1736 set_irq_handler(j, handle_simple_irq);
1737 set_irq_flags(j, IRQF_VALID);
1738 }
1739 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1740 set_irq_data(bank->irq, bank);
1741
1742 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1743 sprintf(clk_name, "gpio%d_dbck", i + 1);
1744 bank->dbck = clk_get(NULL, clk_name);
1745 if (IS_ERR(bank->dbck))
1746 printk(KERN_ERR "Could not get %s\n", clk_name);
1747 }
1748 }
1749
1750 /* Enable system clock for GPIO module.
1751 * The CAM_CLK_CTRL *is* really the right place. */
1752 if (cpu_is_omap16xx())
1753 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1754
1755 /* Enable autoidle for the OCP interface */
1756 if (cpu_is_omap24xx())
1757 omap_writel(1 << 0, 0x48019010);
1758 if (cpu_is_omap34xx())
1759 omap_writel(1 << 0, 0x48306814);
1760
1761 return 0;
1762 }
1763
1764 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1765 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1766 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1767 {
1768 int i;
1769
1770 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1771 return 0;
1772
1773 for (i = 0; i < gpio_bank_count; i++) {
1774 struct gpio_bank *bank = &gpio_bank[i];
1775 void __iomem *wake_status;
1776 void __iomem *wake_clear;
1777 void __iomem *wake_set;
1778 unsigned long flags;
1779
1780 switch (bank->method) {
1781 #ifdef CONFIG_ARCH_OMAP16XX
1782 case METHOD_GPIO_1610:
1783 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1784 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1785 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1786 break;
1787 #endif
1788 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1789 case METHOD_GPIO_24XX:
1790 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1791 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1792 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1793 break;
1794 #endif
1795 #ifdef CONFIG_ARCH_OMAP4
1796 case METHOD_GPIO_24XX:
1797 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1798 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1799 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1800 break;
1801 #endif
1802 default:
1803 continue;
1804 }
1805
1806 spin_lock_irqsave(&bank->lock, flags);
1807 bank->saved_wakeup = __raw_readl(wake_status);
1808 __raw_writel(0xffffffff, wake_clear);
1809 __raw_writel(bank->suspend_wakeup, wake_set);
1810 spin_unlock_irqrestore(&bank->lock, flags);
1811 }
1812
1813 return 0;
1814 }
1815
1816 static int omap_gpio_resume(struct sys_device *dev)
1817 {
1818 int i;
1819
1820 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1821 return 0;
1822
1823 for (i = 0; i < gpio_bank_count; i++) {
1824 struct gpio_bank *bank = &gpio_bank[i];
1825 void __iomem *wake_clear;
1826 void __iomem *wake_set;
1827 unsigned long flags;
1828
1829 switch (bank->method) {
1830 #ifdef CONFIG_ARCH_OMAP16XX
1831 case METHOD_GPIO_1610:
1832 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1833 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1834 break;
1835 #endif
1836 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1837 case METHOD_GPIO_24XX:
1838 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1839 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1840 break;
1841 #endif
1842 #ifdef CONFIG_ARCH_OMAP4
1843 case METHOD_GPIO_24XX:
1844 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1845 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1846 break;
1847 #endif
1848 default:
1849 continue;
1850 }
1851
1852 spin_lock_irqsave(&bank->lock, flags);
1853 __raw_writel(0xffffffff, wake_clear);
1854 __raw_writel(bank->saved_wakeup, wake_set);
1855 spin_unlock_irqrestore(&bank->lock, flags);
1856 }
1857
1858 return 0;
1859 }
1860
1861 static struct sysdev_class omap_gpio_sysclass = {
1862 .name = "gpio",
1863 .suspend = omap_gpio_suspend,
1864 .resume = omap_gpio_resume,
1865 };
1866
1867 static struct sys_device omap_gpio_device = {
1868 .id = 0,
1869 .cls = &omap_gpio_sysclass,
1870 };
1871
1872 #endif
1873
1874 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1875 defined(CONFIG_ARCH_OMAP4)
1876
1877 static int workaround_enabled;
1878
1879 void omap2_gpio_prepare_for_retention(void)
1880 {
1881 int i, c = 0;
1882
1883 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1884 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1885 for (i = 0; i < gpio_bank_count; i++) {
1886 struct gpio_bank *bank = &gpio_bank[i];
1887 u32 l1, l2;
1888
1889 if (!(bank->enabled_non_wakeup_gpios))
1890 continue;
1891 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1892 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1893 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1894 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1895 #endif
1896 #ifdef CONFIG_ARCH_OMAP4
1897 bank->saved_datain = __raw_readl(bank->base +
1898 OMAP4_GPIO_DATAIN);
1899 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1900 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
1901 #endif
1902 bank->saved_fallingdetect = l1;
1903 bank->saved_risingdetect = l2;
1904 l1 &= ~bank->enabled_non_wakeup_gpios;
1905 l2 &= ~bank->enabled_non_wakeup_gpios;
1906 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1907 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1908 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1909 #endif
1910 #ifdef CONFIG_ARCH_OMAP4
1911 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1912 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1913 #endif
1914 c++;
1915 }
1916 if (!c) {
1917 workaround_enabled = 0;
1918 return;
1919 }
1920 workaround_enabled = 1;
1921 }
1922
1923 void omap2_gpio_resume_after_retention(void)
1924 {
1925 int i;
1926
1927 if (!workaround_enabled)
1928 return;
1929 for (i = 0; i < gpio_bank_count; i++) {
1930 struct gpio_bank *bank = &gpio_bank[i];
1931 u32 l, gen, gen0, gen1;
1932
1933 if (!(bank->enabled_non_wakeup_gpios))
1934 continue;
1935 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1936 __raw_writel(bank->saved_fallingdetect,
1937 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1938 __raw_writel(bank->saved_risingdetect,
1939 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1940 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1941 #endif
1942 #ifdef CONFIG_ARCH_OMAP4
1943 __raw_writel(bank->saved_fallingdetect,
1944 bank->base + OMAP4_GPIO_FALLINGDETECT);
1945 __raw_writel(bank->saved_risingdetect,
1946 bank->base + OMAP4_GPIO_RISINGDETECT);
1947 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1948 #endif
1949 /* Check if any of the non-wakeup interrupt GPIOs have changed
1950 * state. If so, generate an IRQ by software. This is
1951 * horribly racy, but it's the best we can do to work around
1952 * this silicon bug. */
1953 l ^= bank->saved_datain;
1954 l &= bank->non_wakeup_gpios;
1955
1956 /*
1957 * No need to generate IRQs for the rising edge for gpio IRQs
1958 * configured with falling edge only; and vice versa.
1959 */
1960 gen0 = l & bank->saved_fallingdetect;
1961 gen0 &= bank->saved_datain;
1962
1963 gen1 = l & bank->saved_risingdetect;
1964 gen1 &= ~(bank->saved_datain);
1965
1966 /* FIXME: Consider GPIO IRQs with level detections properly! */
1967 gen = l & (~(bank->saved_fallingdetect) &
1968 ~(bank->saved_risingdetect));
1969 /* Consider all GPIO IRQs needed to be updated */
1970 gen |= gen0 | gen1;
1971
1972 if (gen) {
1973 u32 old0, old1;
1974 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1975 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1976 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1977 __raw_writel(old0 | gen, bank->base +
1978 OMAP24XX_GPIO_LEVELDETECT0);
1979 __raw_writel(old1 | gen, bank->base +
1980 OMAP24XX_GPIO_LEVELDETECT1);
1981 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1982 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1983 #endif
1984 #ifdef CONFIG_ARCH_OMAP4
1985 old0 = __raw_readl(bank->base +
1986 OMAP4_GPIO_LEVELDETECT0);
1987 old1 = __raw_readl(bank->base +
1988 OMAP4_GPIO_LEVELDETECT1);
1989 __raw_writel(old0 | l, bank->base +
1990 OMAP4_GPIO_LEVELDETECT0);
1991 __raw_writel(old1 | l, bank->base +
1992 OMAP4_GPIO_LEVELDETECT1);
1993 __raw_writel(old0, bank->base +
1994 OMAP4_GPIO_LEVELDETECT0);
1995 __raw_writel(old1, bank->base +
1996 OMAP4_GPIO_LEVELDETECT1);
1997 #endif
1998 }
1999 }
2000
2001 }
2002
2003 #endif
2004
2005 /*
2006 * This may get called early from board specific init
2007 * for boards that have interrupts routed via FPGA.
2008 */
2009 int __init omap_gpio_init(void)
2010 {
2011 if (!initialized)
2012 return _omap_gpio_init();
2013 else
2014 return 0;
2015 }
2016
2017 static int __init omap_gpio_sysinit(void)
2018 {
2019 int ret = 0;
2020
2021 if (!initialized)
2022 ret = _omap_gpio_init();
2023
2024 mpuio_init();
2025
2026 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2027 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2028 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2029 if (ret == 0) {
2030 ret = sysdev_class_register(&omap_gpio_sysclass);
2031 if (ret == 0)
2032 ret = sysdev_register(&omap_gpio_device);
2033 }
2034 }
2035 #endif
2036
2037 return ret;
2038 }
2039
2040 arch_initcall(omap_gpio_sysinit);
2041
2042
2043 #ifdef CONFIG_DEBUG_FS
2044
2045 #include <linux/debugfs.h>
2046 #include <linux/seq_file.h>
2047
2048 static int dbg_gpio_show(struct seq_file *s, void *unused)
2049 {
2050 unsigned i, j, gpio;
2051
2052 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2053 struct gpio_bank *bank = gpio_bank + i;
2054 unsigned bankwidth = 16;
2055 u32 mask = 1;
2056
2057 if (bank_is_mpuio(bank))
2058 gpio = OMAP_MPUIO(0);
2059 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2060 bankwidth = 32;
2061
2062 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2063 unsigned irq, value, is_in, irqstat;
2064 const char *label;
2065
2066 label = gpiochip_is_requested(&bank->chip, j);
2067 if (!label)
2068 continue;
2069
2070 irq = bank->virtual_irq_start + j;
2071 value = gpio_get_value(gpio);
2072 is_in = gpio_is_input(bank, mask);
2073
2074 if (bank_is_mpuio(bank))
2075 seq_printf(s, "MPUIO %2d ", j);
2076 else
2077 seq_printf(s, "GPIO %3d ", gpio);
2078 seq_printf(s, "(%-20.20s): %s %s",
2079 label,
2080 is_in ? "in " : "out",
2081 value ? "hi" : "lo");
2082
2083 /* FIXME for at least omap2, show pullup/pulldown state */
2084
2085 irqstat = irq_desc[irq].status;
2086 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2087 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2088 if (is_in && ((bank->suspend_wakeup & mask)
2089 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2090 char *trigger = NULL;
2091
2092 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2093 case IRQ_TYPE_EDGE_FALLING:
2094 trigger = "falling";
2095 break;
2096 case IRQ_TYPE_EDGE_RISING:
2097 trigger = "rising";
2098 break;
2099 case IRQ_TYPE_EDGE_BOTH:
2100 trigger = "bothedge";
2101 break;
2102 case IRQ_TYPE_LEVEL_LOW:
2103 trigger = "low";
2104 break;
2105 case IRQ_TYPE_LEVEL_HIGH:
2106 trigger = "high";
2107 break;
2108 case IRQ_TYPE_NONE:
2109 trigger = "(?)";
2110 break;
2111 }
2112 seq_printf(s, ", irq-%d %-8s%s",
2113 irq, trigger,
2114 (bank->suspend_wakeup & mask)
2115 ? " wakeup" : "");
2116 }
2117 #endif
2118 seq_printf(s, "\n");
2119 }
2120
2121 if (bank_is_mpuio(bank)) {
2122 seq_printf(s, "\n");
2123 gpio = 0;
2124 }
2125 }
2126 return 0;
2127 }
2128
2129 static int dbg_gpio_open(struct inode *inode, struct file *file)
2130 {
2131 return single_open(file, dbg_gpio_show, &inode->i_private);
2132 }
2133
2134 static const struct file_operations debug_fops = {
2135 .open = dbg_gpio_open,
2136 .read = seq_read,
2137 .llseek = seq_lseek,
2138 .release = single_release,
2139 };
2140
2141 static int __init omap_gpio_debuginit(void)
2142 {
2143 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2144 NULL, NULL, &debug_fops);
2145 return 0;
2146 }
2147 late_initcall(omap_gpio_debuginit);
2148 #endif
mm of the moment repository