2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
22 select HAVE_FUNCTION_GRAPH_TRACER
23 select HAVE_FUNCTION_TRACER
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
29 select ARCH_WANT_OPTIONAL_GPIOLIB
38 config GENERIC_FIND_NEXT_BIT
41 config GENERIC_HWEIGHT
44 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
50 config GENERIC_HARDIRQS_NO__DO_IRQ
56 config FORCE_MAX_ZONEORDER
60 config GENERIC_CALIBRATE_DELAY
63 config LOCKDEP_SUPPORT
66 config STACKTRACE_SUPPORT
69 config TRACE_IRQFLAGS_SUPPORT
74 source "kernel/Kconfig.preempt"
76 source "kernel/Kconfig.freezer"
78 menu "Blackfin Processor Options"
80 comment "Processor and Board Settings"
89 BF512 Processor Support.
94 BF514 Processor Support.
99 BF516 Processor Support.
104 BF518 Processor Support.
109 BF522 Processor Support.
114 BF523 Processor Support.
119 BF524 Processor Support.
124 BF525 Processor Support.
129 BF526 Processor Support.
134 BF527 Processor Support.
139 BF531 Processor Support.
144 BF532 Processor Support.
149 BF533 Processor Support.
154 BF534 Processor Support.
159 BF536 Processor Support.
164 BF537 Processor Support.
169 BF538 Processor Support.
174 BF539 Processor Support.
179 BF542 Processor Support.
184 BF542 Processor Support.
189 BF544 Processor Support.
194 BF544 Processor Support.
199 BF547 Processor Support.
204 BF547 Processor Support.
209 BF548 Processor Support.
214 BF548 Processor Support.
219 BF549 Processor Support.
224 BF549 Processor Support.
229 BF561 Processor Support.
235 select GENERIC_CLOCKEVENTS
236 bool "Symmetric multi-processing support"
238 This enables support for systems with more than one CPU,
239 like the dual core BF561. If you have a system with only one
240 CPU, say N. If you have a system with more than one CPU, say Y.
242 If you don't know what to do here, say N.
256 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
257 default 2 if (BF537 || BF536 || BF534)
258 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
259 default 4 if (BF538 || BF539)
263 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
264 default 3 if (BF537 || BF536 || BF534 || BF54xM)
265 default 5 if (BF561 || BF538 || BF539)
266 default 6 if (BF533 || BF532 || BF531)
270 default BF_REV_0_0 if (BF51x || BF52x)
271 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
272 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
276 depends on (BF51x || BF52x || (BF54x && !BF54xM))
280 depends on (BF51x || BF52x || (BF54x && !BF54xM))
284 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
288 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
292 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
296 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
300 depends on (BF533 || BF532 || BF531)
312 depends on (BF512 || BF514 || BF516 || BF518)
317 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
322 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
327 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
332 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
335 config MEM_GENERIC_BOARD
337 depends on GENERIC_BOARD
340 config MEM_MT48LC64M4A2FB_7E
342 depends on (BFIN533_STAMP)
345 config MEM_MT48LC16M16A2TG_75
347 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
348 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
349 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
350 || BFIN527_BLUETECHNIX_CM)
353 config MEM_MT48LC32M8A2_75
355 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
358 config MEM_MT48LC8M32B2B5_7
360 depends on (BFIN561_BLUETECHNIX_CM)
363 config MEM_MT48LC32M16A2TG_75
365 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
368 config MEM_MT48LC32M8A2_75
370 depends on (BFIN518F_EZBRD)
373 config MEM_MT48H32M16LFCJ_75
375 depends on (BFIN526_EZBRD)
378 source "arch/blackfin/mach-bf518/Kconfig"
379 source "arch/blackfin/mach-bf527/Kconfig"
380 source "arch/blackfin/mach-bf533/Kconfig"
381 source "arch/blackfin/mach-bf561/Kconfig"
382 source "arch/blackfin/mach-bf537/Kconfig"
383 source "arch/blackfin/mach-bf538/Kconfig"
384 source "arch/blackfin/mach-bf548/Kconfig"
386 menu "Board customizations"
389 bool "Default bootloader kernel arguments"
392 string "Initial kernel command string"
393 depends on CMDLINE_BOOL
394 default "console=ttyBF0,57600"
396 If you don't have a boot loader capable of passing a command line string
397 to the kernel, you may specify one here. As a minimum, you should specify
398 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
401 hex "Kernel load address for booting"
403 range 0x1000 0x20000000
405 This option allows you to set the load address of the kernel.
406 This can be useful if you are on a board which has a small amount
407 of memory or you wish to reserve some memory at the beginning of
410 Note that you need to keep this value above 4k (0x1000) as this
411 memory region is used to capture NULL pointer references as well
412 as some core kernel functions.
415 hex "Kernel ROM Base"
418 range 0x20000000 0x20400000 if !(BF54x || BF561)
419 range 0x20000000 0x30000000 if (BF54x || BF561)
422 comment "Clock/PLL Setup"
425 int "Frequency of the crystal on the board in Hz"
426 default "10000000" if BFIN532_IP0X
427 default "11059200" if BFIN533_STAMP
428 default "24576000" if PNAV10
429 default "25000000" # most people use this
430 default "27000000" if BFIN533_EZKIT
431 default "30000000" if BFIN561_EZKIT
433 The frequency of CLKIN crystal oscillator on the board in Hz.
434 Warning: This value should match the crystal on the board. Otherwise,
435 peripherals won't work properly.
437 config BFIN_KERNEL_CLOCK
438 bool "Re-program Clocks while Kernel boots?"
441 This option decides if kernel clocks are re-programed from the
442 bootloader settings. If the clocks are not set, the SDRAM settings
443 are also not changed, and the Bootloader does 100% of the hardware
448 depends on BFIN_KERNEL_CLOCK
453 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
456 If this is set the clock will be divided by 2, before it goes to the PLL.
460 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
462 default "22" if BFIN533_EZKIT
463 default "45" if BFIN533_STAMP
464 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
465 default "22" if BFIN533_BLUETECHNIX_CM
466 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
467 default "20" if BFIN561_EZKIT
468 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
470 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
471 PLL Frequency = (Crystal Frequency) * (this setting)
474 prompt "Core Clock Divider"
475 depends on BFIN_KERNEL_CLOCK
478 This sets the frequency of the core. It can be 1, 2, 4 or 8
479 Core Frequency = (PLL frequency) / (this setting)
495 int "System Clock Divider"
496 depends on BFIN_KERNEL_CLOCK
500 This sets the frequency of the system clock (including SDRAM or DDR).
501 This can be between 1 and 15
502 System Clock = (PLL frequency) / (this setting)
505 prompt "DDR SDRAM Chip Type"
506 depends on BFIN_KERNEL_CLOCK
508 default MEM_MT46V32M16_5B
510 config MEM_MT46V32M16_6T
513 config MEM_MT46V32M16_5B
518 prompt "DDR/SDRAM Timing"
519 depends on BFIN_KERNEL_CLOCK
520 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
522 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
523 The calculated SDRAM timing parameters may not be 100%
524 accurate - This option is therefore marked experimental.
526 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
527 bool "Calculate Timings (EXPERIMENTAL)"
528 depends on EXPERIMENTAL
530 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
531 bool "Provide accurate Timings based on target SCLK"
533 Please consult the Blackfin Hardware Reference Manuals as well
534 as the memory device datasheet.
535 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
538 menu "Memory Init Control"
539 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
556 config MEM_EBIU_DDRQUE
573 # Max & Min Speeds for various Chips
577 default 400000000 if BF512
578 default 400000000 if BF514
579 default 400000000 if BF516
580 default 400000000 if BF518
581 default 400000000 if BF522
582 default 600000000 if BF523
583 default 400000000 if BF524
584 default 600000000 if BF525
585 default 400000000 if BF526
586 default 600000000 if BF527
587 default 400000000 if BF531
588 default 400000000 if BF532
589 default 750000000 if BF533
590 default 500000000 if BF534
591 default 400000000 if BF536
592 default 600000000 if BF537
593 default 533333333 if BF538
594 default 533333333 if BF539
595 default 600000000 if BF542
596 default 533333333 if BF544
597 default 600000000 if BF547
598 default 600000000 if BF548
599 default 533333333 if BF549
600 default 600000000 if BF561
614 comment "Kernel Timer/Scheduler"
616 source kernel/Kconfig.hz
621 config GENERIC_CLOCKEVENTS
622 bool "Generic clock events"
626 prompt "Kernel Tick Source"
627 depends on GENERIC_CLOCKEVENTS
628 default TICKSOURCE_CORETMR
630 config TICKSOURCE_GPTMR0
631 bool "Gptimer0 (SCLK domain)"
634 config TICKSOURCE_CORETMR
635 bool "Core timer (CCLK domain)"
639 config CYCLES_CLOCKSOURCE
640 bool "Use 'CYCLES' as a clocksource"
641 depends on GENERIC_CLOCKEVENTS
642 depends on !BFIN_SCRATCH_REG_CYCLES
645 If you say Y here, you will enable support for using the 'cycles'
646 registers as a clock source. Doing so means you will be unable to
647 safely write to the 'cycles' register during runtime. You will
648 still be able to read it (such as for performance monitoring), but
649 writing the registers will most likely crash the kernel.
651 config GPTMR0_CLOCKSOURCE
652 bool "Use GPTimer0 as a clocksource"
654 depends on GENERIC_CLOCKEVENTS
655 depends on !TICKSOURCE_GPTMR0
657 config ARCH_USES_GETTIMEOFFSET
658 depends on !GENERIC_CLOCKEVENTS
661 source kernel/time/Kconfig
666 prompt "Blackfin Exception Scratch Register"
667 default BFIN_SCRATCH_REG_RETN
669 Select the resource to reserve for the Exception handler:
670 - RETN: Non-Maskable Interrupt (NMI)
671 - RETE: Exception Return (JTAG/ICE)
672 - CYCLES: Performance counter
674 If you are unsure, please select "RETN".
676 config BFIN_SCRATCH_REG_RETN
679 Use the RETN register in the Blackfin exception handler
680 as a stack scratch register. This means you cannot
681 safely use NMI on the Blackfin while running Linux, but
682 you can debug the system with a JTAG ICE and use the
683 CYCLES performance registers.
685 If you are unsure, please select "RETN".
687 config BFIN_SCRATCH_REG_RETE
690 Use the RETE register in the Blackfin exception handler
691 as a stack scratch register. This means you cannot
692 safely use a JTAG ICE while debugging a Blackfin board,
693 but you can safely use the CYCLES performance registers
696 If you are unsure, please select "RETN".
698 config BFIN_SCRATCH_REG_CYCLES
701 Use the CYCLES register in the Blackfin exception handler
702 as a stack scratch register. This means you cannot
703 safely use the CYCLES performance registers on a Blackfin
704 board at anytime, but you can debug the system with a JTAG
707 If you are unsure, please select "RETN".
714 menu "Blackfin Kernel Optimizations"
717 comment "Memory Optimizations"
720 bool "Locate interrupt entry code in L1 Memory"
723 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
724 into L1 instruction memory. (less latency)
726 config EXCPT_IRQ_SYSC_L1
727 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
730 If enabled, the entire ASM lowlevel exception and interrupt entry code
731 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
735 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
738 If enabled, the frequently called do_irq dispatcher function is linked
739 into L1 instruction memory. (less latency)
741 config CORE_TIMER_IRQ_L1
742 bool "Locate frequently called timer_interrupt() function in L1 Memory"
745 If enabled, the frequently called timer_interrupt() function is linked
746 into L1 instruction memory. (less latency)
749 bool "Locate frequently idle function in L1 Memory"
752 If enabled, the frequently called idle function is linked
753 into L1 instruction memory. (less latency)
756 bool "Locate kernel schedule function in L1 Memory"
759 If enabled, the frequently called kernel schedule is linked
760 into L1 instruction memory. (less latency)
762 config ARITHMETIC_OPS_L1
763 bool "Locate kernel owned arithmetic functions in L1 Memory"
766 If enabled, arithmetic functions are linked
767 into L1 instruction memory. (less latency)
770 bool "Locate access_ok function in L1 Memory"
773 If enabled, the access_ok function is linked
774 into L1 instruction memory. (less latency)
777 bool "Locate memset function in L1 Memory"
780 If enabled, the memset function is linked
781 into L1 instruction memory. (less latency)
784 bool "Locate memcpy function in L1 Memory"
787 If enabled, the memcpy function is linked
788 into L1 instruction memory. (less latency)
790 config SYS_BFIN_SPINLOCK_L1
791 bool "Locate sys_bfin_spinlock function in L1 Memory"
794 If enabled, sys_bfin_spinlock function is linked
795 into L1 instruction memory. (less latency)
797 config IP_CHECKSUM_L1
798 bool "Locate IP Checksum function in L1 Memory"
801 If enabled, the IP Checksum function is linked
802 into L1 instruction memory. (less latency)
804 config CACHELINE_ALIGNED_L1
805 bool "Locate cacheline_aligned data to L1 Data Memory"
810 If enabled, cacheline_aligned data is linked
811 into L1 data memory. (less latency)
813 config SYSCALL_TAB_L1
814 bool "Locate Syscall Table L1 Data Memory"
818 If enabled, the Syscall LUT is linked
819 into L1 data memory. (less latency)
821 config CPLB_SWITCH_TAB_L1
822 bool "Locate CPLB Switch Tables L1 Data Memory"
826 If enabled, the CPLB Switch Tables are linked
827 into L1 data memory. (less latency)
830 bool "Support locating application stack in L1 Scratch Memory"
833 If enabled the application stack can be located in L1
834 scratch memory (less latency).
836 Currently only works with FLAT binaries.
838 config EXCEPTION_L1_SCRATCH
839 bool "Locate exception stack in L1 Scratch Memory"
841 depends on !APP_STACK_L1
843 Whenever an exception occurs, use the L1 Scratch memory for
844 stack storage. You cannot place the stacks of FLAT binaries
845 in L1 when using this option.
847 If you don't use L1 Scratch, then you should say Y here.
849 comment "Speed Optimizations"
850 config BFIN_INS_LOWOVERHEAD
851 bool "ins[bwl] low overhead, higher interrupt latency"
854 Reads on the Blackfin are speculative. In Blackfin terms, this means
855 they can be interrupted at any time (even after they have been issued
856 on to the external bus), and re-issued after the interrupt occurs.
857 For memory - this is not a big deal, since memory does not change if
860 If a FIFO is sitting on the end of the read, it will see two reads,
861 when the core only sees one since the FIFO receives both the read
862 which is cancelled (and not delivered to the core) and the one which
863 is re-issued (which is delivered to the core).
865 To solve this, interrupts are turned off before reads occur to
866 I/O space. This option controls which the overhead/latency of
867 controlling interrupts during this time
868 "n" turns interrupts off every read
869 (higher overhead, but lower interrupt latency)
870 "y" turns interrupts off every loop
871 (low overhead, but longer interrupt latency)
873 default behavior is to leave this set to on (type "Y"). If you are experiencing
874 interrupt latency issues, it is safe and OK to turn this off.
879 prompt "Kernel executes from"
881 Choose the memory type that the kernel will be running in.
886 The kernel will be resident in RAM when running.
891 The kernel will be resident in FLASH/ROM when running.
898 tristate "Enable Blackfin General Purpose Timers API"
901 Enable support for the General Purpose Timers API. If you
904 To compile this driver as a module, choose M here: the module
905 will be called gptimers.
908 prompt "Uncached DMA region"
909 default DMA_UNCACHED_1M
910 config DMA_UNCACHED_4M
911 bool "Enable 4M DMA region"
912 config DMA_UNCACHED_2M
913 bool "Enable 2M DMA region"
914 config DMA_UNCACHED_1M
915 bool "Enable 1M DMA region"
916 config DMA_UNCACHED_NONE
917 bool "Disable DMA region"
921 comment "Cache Support"
926 config BFIN_EXTMEM_ICACHEABLE
927 bool "Enable ICACHE for external memory"
928 depends on BFIN_ICACHE
930 config BFIN_L2_ICACHEABLE
931 bool "Enable ICACHE for L2 SRAM"
932 depends on BFIN_ICACHE
933 depends on BF54x || BF561
939 config BFIN_DCACHE_BANKA
940 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
941 depends on BFIN_DCACHE && !BF531
943 config BFIN_EXTMEM_DCACHEABLE
944 bool "Enable DCACHE for external memory"
945 depends on BFIN_DCACHE
948 prompt "External memory DCACHE policy"
949 depends on BFIN_EXTMEM_DCACHEABLE
950 default BFIN_EXTMEM_WRITEBACK if !SMP
951 default BFIN_EXTMEM_WRITETHROUGH if SMP
952 config BFIN_EXTMEM_WRITEBACK
957 Cached data will be written back to SDRAM only when needed.
958 This can give a nice increase in performance, but beware of
959 broken drivers that do not properly invalidate/flush their
962 Write Through Policy:
963 Cached data will always be written back to SDRAM when the
964 cache is updated. This is a completely safe setting, but
965 performance is worse than Write Back.
967 If you are unsure of the options and you want to be safe,
968 then go with Write Through.
970 config BFIN_EXTMEM_WRITETHROUGH
974 Cached data will be written back to SDRAM only when needed.
975 This can give a nice increase in performance, but beware of
976 broken drivers that do not properly invalidate/flush their
979 Write Through Policy:
980 Cached data will always be written back to SDRAM when the
981 cache is updated. This is a completely safe setting, but
982 performance is worse than Write Back.
984 If you are unsure of the options and you want to be safe,
985 then go with Write Through.
989 config BFIN_L2_DCACHEABLE
990 bool "Enable DCACHE for L2 SRAM"
991 depends on BFIN_DCACHE
992 depends on (BF54x || BF561) && !SMP
995 prompt "L2 SRAM DCACHE policy"
996 depends on BFIN_L2_DCACHEABLE
997 default BFIN_L2_WRITEBACK
998 config BFIN_L2_WRITEBACK
1001 config BFIN_L2_WRITETHROUGH
1002 bool "Write through"
1006 comment "Memory Protection Unit"
1008 bool "Enable the memory protection unit (EXPERIMENTAL)"
1011 Use the processor's MPU to protect applications from accessing
1012 memory they do not own. This comes at a performance penalty
1013 and is recommended only for debugging.
1015 comment "Asynchronous Memory Configuration"
1017 menu "EBIU_AMGCTL Global Control"
1019 bool "Enable CLKOUT"
1023 bool "DMA has priority over core for ext. accesses"
1028 bool "Bank 0 16 bit packing enable"
1033 bool "Bank 1 16 bit packing enable"
1038 bool "Bank 2 16 bit packing enable"
1043 bool "Bank 3 16 bit packing enable"
1047 prompt "Enable Asynchronous Memory Banks"
1051 bool "Disable All Banks"
1054 bool "Enable Bank 0"
1056 config C_AMBEN_B0_B1
1057 bool "Enable Bank 0 & 1"
1059 config C_AMBEN_B0_B1_B2
1060 bool "Enable Bank 0 & 1 & 2"
1063 bool "Enable All Banks"
1067 menu "EBIU_AMBCTL Control"
1069 hex "Bank 0 (AMBCTL0.L)"
1072 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1073 used to control the Asynchronous Memory Bank 0 settings.
1076 hex "Bank 1 (AMBCTL0.H)"
1078 default 0x5558 if BF54x
1080 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1081 used to control the Asynchronous Memory Bank 1 settings.
1084 hex "Bank 2 (AMBCTL1.L)"
1087 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1088 used to control the Asynchronous Memory Bank 2 settings.
1091 hex "Bank 3 (AMBCTL1.H)"
1094 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1095 used to control the Asynchronous Memory Bank 3 settings.
1099 config EBIU_MBSCTLVAL
1100 hex "EBIU Bank Select Control Register"
1105 hex "Flash Memory Mode Control Register"
1110 hex "Flash Memory Bank Control Register"
1115 #############################################################################
1116 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1122 Support for PCI bus.
1124 source "drivers/pci/Kconfig"
1127 bool "Support for hot-pluggable device"
1129 Say Y here if you want to plug devices into your computer while
1130 the system is running, and be able to use them quickly. In many
1131 cases, the devices can likewise be unplugged at any time too.
1133 One well known example of this is PCMCIA- or PC-cards, credit-card
1134 size devices such as network cards, modems or hard drives which are
1135 plugged into slots found on all modern laptop computers. Another
1136 example, used on modern desktops as well as laptops, is USB.
1138 Enable HOTPLUG and build a modular kernel. Get agent software
1139 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1140 Then your kernel will automatically call out to a user mode "policy
1141 agent" (/sbin/hotplug) to load modules and set up software needed
1142 to use devices as you hotplug them.
1144 source "drivers/pcmcia/Kconfig"
1146 source "drivers/pci/hotplug/Kconfig"
1150 menu "Executable file formats"
1152 source "fs/Kconfig.binfmt"
1156 menu "Power management options"
1159 source "kernel/power/Kconfig"
1161 config ARCH_SUSPEND_POSSIBLE
1165 prompt "Standby Power Saving Mode"
1167 default PM_BFIN_SLEEP_DEEPER
1168 config PM_BFIN_SLEEP_DEEPER
1171 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1172 power dissipation by disabling the clock to the processor core (CCLK).
1173 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1174 to 0.85 V to provide the greatest power savings, while preserving the
1176 The PLL and system clock (SCLK) continue to operate at a very low
1177 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1178 the SDRAM is put into Self Refresh Mode. Typically an external event
1179 such as GPIO interrupt or RTC activity wakes up the processor.
1180 Various Peripherals such as UART, SPORT, PPI may not function as
1181 normal during Sleep Deeper, due to the reduced SCLK frequency.
1182 When in the sleep mode, system DMA access to L1 memory is not supported.
1184 If unsure, select "Sleep Deeper".
1186 config PM_BFIN_SLEEP
1189 Sleep Mode (High Power Savings) - The sleep mode reduces power
1190 dissipation by disabling the clock to the processor core (CCLK).
1191 The PLL and system clock (SCLK), however, continue to operate in
1192 this mode. Typically an external event or RTC activity will wake
1193 up the processor. When in the sleep mode, system DMA access to L1
1194 memory is not supported.
1196 If unsure, select "Sleep Deeper".
1199 config PM_WAKEUP_BY_GPIO
1200 bool "Allow Wakeup from Standby by GPIO"
1201 depends on PM && !BF54x
1203 config PM_WAKEUP_GPIO_NUMBER
1206 depends on PM_WAKEUP_BY_GPIO
1210 prompt "GPIO Polarity"
1211 depends on PM_WAKEUP_BY_GPIO
1212 default PM_WAKEUP_GPIO_POLAR_H
1213 config PM_WAKEUP_GPIO_POLAR_H
1215 config PM_WAKEUP_GPIO_POLAR_L
1217 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1219 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1221 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1225 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1228 config PM_BFIN_WAKE_PH6
1229 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1230 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1233 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1235 config PM_BFIN_WAKE_GP
1236 bool "Allow Wake-Up from GPIOs"
1237 depends on PM && BF54x
1240 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1241 (all processors, except ADSP-BF549). This option sets
1242 the general-purpose wake-up enable (GPWE) control bit to enable
1243 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1244 On ADSP-BF549 this option enables the the same functionality on the
1245 /MRXON pin also PH7.
1249 menu "CPU Frequency scaling"
1252 source "drivers/cpufreq/Kconfig"
1254 config BFIN_CPU_FREQ
1257 select CPU_FREQ_TABLE
1261 bool "CPU Voltage scaling"
1262 depends on EXPERIMENTAL
1266 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1267 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1268 manuals. There is a theoretical risk that during VDDINT transitions
1273 source "net/Kconfig"
1275 source "drivers/Kconfig"
1279 source "arch/blackfin/Kconfig.debug"
1281 source "security/Kconfig"
1283 source "crypto/Kconfig"
1285 source "lib/Kconfig"