3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
33 /* Macro to make the code more readable. */
34 #ifdef CONFIG_8xx_CPU6
35 #define DO_8xx_CPU6(val, reg) \
40 #define DO_8xx_CPU6(val, reg)
47 * This port was done on an MBX board with an 860. Right now I only
48 * support an ELF compressed (zImage) boot from EPPC-Bug because the
49 * code there loads up some registers before calling us:
50 * r3: ptr to board info data
51 * r4: initrd_start or if no initrd then 0
52 * r5: initrd_end - unused if r4 is 0
53 * r6: Start of command line string
54 * r7: End of command line string
56 * I decided to use conditional compilation instead of checking PVR and
57 * adding more processor specific branches around code I don't need.
58 * Since this is an embedded processor, I also appreciate any memory
61 * The MPC8xx does not have any BATs, but it supports large page sizes.
62 * We first initialize the MMU to support 8M byte pages, then load one
63 * entry into each of the instruction and data TLBs to map the first
64 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
65 * the "internal" processor registers before MMU_init is called.
67 * The TLB code currently contains a major hack. Since I use the condition
68 * code register, I have to save and restore it. I am out of registers, so
69 * I just store it in memory location 0 (the TLB handlers are not reentrant).
70 * To avoid making any decisions, I need to use the "segment" valid bit
71 * in the first level table, but that would require many changes to the
72 * Linux page directory/table functions that I don't want to do right now.
74 * I used to use SPRG2 for a temporary register in the TLB handler, but it
75 * has since been put to other uses. I now use a hack to save a register
76 * and the CCR at memory location 0.....Someday I'll fix this.....
81 mr r31,r3 /* save parameters */
87 /* We have to turn on the MMU right away so we get cache modes
92 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
98 ori r0,r0,MSR_DR|MSR_IR
101 ori r0,r0,start_here@l
104 rfi /* enables MMU */
107 * Exception entry code. This code runs with address translation
108 * turned off, i.e. using physical addresses.
109 * We assume sprg3 has the physical address of the current
110 * task's thread_struct.
112 #define EXCEPTION_PROLOG \
113 mtspr SPRN_SPRG_SCRATCH0,r10; \
114 mtspr SPRN_SPRG_SCRATCH1,r11; \
116 EXCEPTION_PROLOG_1; \
119 #define EXCEPTION_PROLOG_1 \
120 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
121 andi. r11,r11,MSR_PR; \
122 tophys(r11,r1); /* use tophys(r1) if kernel */ \
124 mfspr r11,SPRN_SPRG_THREAD; \
125 lwz r11,THREAD_INFO-THREAD(r11); \
126 addi r11,r11,THREAD_SIZE; \
128 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
131 #define EXCEPTION_PROLOG_2 \
133 stw r10,_CCR(r11); /* save registers */ \
134 stw r12,GPR12(r11); \
136 mfspr r10,SPRN_SPRG_SCRATCH0; \
137 stw r10,GPR10(r11); \
138 mfspr r12,SPRN_SPRG_SCRATCH1; \
139 stw r12,GPR11(r11); \
141 stw r10,_LINK(r11); \
142 mfspr r12,SPRN_SRR0; \
143 mfspr r9,SPRN_SRR1; \
146 tovirt(r1,r11); /* set new kernel sp */ \
147 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
148 MTMSRD(r10); /* (except for mach check in rtas) */ \
150 SAVE_4GPRS(3, r11); \
154 * Note: code which follows this uses cr0.eq (set if from kernel),
155 * r11, r12 (SRR0), and r9 (SRR1).
157 * Note2: once we have set r1 we are in a position to take exceptions
158 * again, and we could thus set MSR:RI at that point.
164 #define EXCEPTION(n, label, hdlr, xfer) \
168 addi r3,r1,STACK_FRAME_OVERHEAD; \
171 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
173 stw r10,_TRAP(r11); \
181 #define COPY_EE(d, s) rlwimi d,s,0,16,16
184 #define EXC_XFER_STD(n, hdlr) \
185 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
186 ret_from_except_full)
188 #define EXC_XFER_LITE(n, hdlr) \
189 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
192 #define EXC_XFER_EE(n, hdlr) \
193 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
194 ret_from_except_full)
196 #define EXC_XFER_EE_LITE(n, hdlr) \
197 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
201 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
211 addi r3,r1,STACK_FRAME_OVERHEAD
212 EXC_XFER_STD(0x200, machine_check_exception)
214 /* Data access exception.
215 * This is "never generated" by the MPC8xx. We jump to it for other
216 * translation errors.
225 EXC_XFER_EE_LITE(0x300, handle_page_fault)
227 /* Instruction access exception.
228 * This is "never generated" by the MPC8xx. We jump to it for other
229 * translation errors.
236 EXC_XFER_EE_LITE(0x400, handle_page_fault)
238 /* External interrupt */
239 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
241 /* Alignment exception */
249 addi r3,r1,STACK_FRAME_OVERHEAD
250 EXC_XFER_EE(0x600, alignment_exception)
252 /* Program check exception */
253 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
255 /* No FPU on MPC8xx. This exception is not supposed to happen.
257 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
260 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
262 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
263 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
269 EXC_XFER_EE_LITE(0xc00, DoSyscall)
271 /* Single step - not used on 601 */
272 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
273 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
274 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
276 /* On the MPC8xx, this is a software emulation interrupt. It occurs
277 * for all unimplemented and illegal instructions.
279 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
283 * For the MPC8xx, this is a software tablewalk to load the instruction
284 * TLB. It is modelled after the example in the Motorola manual. The task
285 * switch loads the M_TWB register with the pointer to the first level table.
286 * If we discover there is no second level table (value is zero) or if there
287 * is an invalid pte, we load that into the TLB, which causes another fault
288 * into the TLB Error interrupt where we can handle such problems.
289 * We have to use the MD_xxx registers for the tablewalk because the
290 * equivalent MI_xxx registers only perform the attribute functions.
293 #ifdef CONFIG_8xx_CPU6
296 DO_8xx_CPU6(0x3f80, r3)
297 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
301 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
302 #ifdef CONFIG_8xx_CPU15
303 addi r11, r10, 0x1000
305 addi r11, r10, -0x1000
308 DO_8xx_CPU6(0x3780, r3)
309 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
310 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
312 /* If we are faulting a kernel address, we have to use the
313 * kernel page tables.
315 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
317 lis r11, swapper_pg_dir@h
318 ori r11, r11, swapper_pg_dir@l
319 rlwimi r10, r11, 0, 2, 19
321 lwz r11, 0(r10) /* Get the level 1 entry */
322 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
323 beq 2f /* If zero, don't try to find a pte */
325 /* We have a pte table, so load the MI_TWC with the attributes
326 * for this "segment."
328 ori r11,r11,1 /* Set valid bit */
329 DO_8xx_CPU6(0x2b80, r3)
330 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
331 DO_8xx_CPU6(0x3b80, r3)
332 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
333 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
334 lwz r10, 0(r11) /* Get the pte */
337 /* do not set the _PAGE_ACCESSED bit of a non-present page */
338 andi. r11, r10, _PAGE_PRESENT
340 ori r10, r10, _PAGE_ACCESSED
341 mfspr r11, SPRN_MD_TWC /* get the pte address again */
345 ori r10, r10, _PAGE_ACCESSED
349 /* The Linux PTE won't go exactly into the MMU TLB.
350 * Software indicator bits 21, 22 and 28 must be clear.
351 * Software indicator bits 24, 25, 26, and 27 must be
352 * set. All other Linux PTE bits control the behavior
356 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
357 DO_8xx_CPU6(0x2d80, r3)
358 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
360 mfspr r10, SPRN_M_TW /* Restore registers */
364 #ifdef CONFIG_8xx_CPU6
371 #ifdef CONFIG_8xx_CPU6
374 DO_8xx_CPU6(0x3f80, r3)
375 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
379 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
381 /* If we are faulting a kernel address, we have to use the
382 * kernel page tables.
384 andi. r11, r10, 0x0800
386 lis r11, swapper_pg_dir@h
387 ori r11, r11, swapper_pg_dir@l
388 rlwimi r10, r11, 0, 2, 19
390 lwz r11, 0(r10) /* Get the level 1 entry */
391 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
392 beq 2f /* If zero, don't try to find a pte */
394 /* We have a pte table, so load fetch the pte from the table.
396 ori r11, r11, 1 /* Set valid bit in physical L2 page */
397 DO_8xx_CPU6(0x3b80, r3)
398 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
399 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
400 lwz r10, 0(r10) /* Get the pte */
402 /* Insert the Guarded flag into the TWC from the Linux PTE.
403 * It is bit 27 of both the Linux PTE and the TWC (at least
404 * I got that right :-). It will be better when we can put
405 * this into the Linux pgd/pmd and load it in the operation
408 rlwimi r11, r10, 0, 27, 27
409 DO_8xx_CPU6(0x3b80, r3)
410 mtspr SPRN_MD_TWC, r11
413 /* do not set the _PAGE_ACCESSED bit of a non-present page */
414 andi. r11, r10, _PAGE_PRESENT
416 ori r10, r10, _PAGE_ACCESSED
418 /* and update pte in table */
420 ori r10, r10, _PAGE_ACCESSED
422 mfspr r11, SPRN_MD_TWC /* get the pte address again */
425 /* The Linux PTE won't go exactly into the MMU TLB.
426 * Software indicator bits 21, 22 and 28 must be clear.
427 * Software indicator bits 24, 25, 26, and 27 must be
428 * set. All other Linux PTE bits control the behavior
432 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
433 DO_8xx_CPU6(0x3d80, r3)
434 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
436 mfspr r10, SPRN_M_TW /* Restore registers */
440 #ifdef CONFIG_8xx_CPU6
445 /* This is an instruction TLB error on the MPC8xx. This could be due
446 * to many reasons, such as executing guarded memory or illegal instruction
447 * addresses. There is nothing to do but handle a big time error fault.
453 /* This is the data TLB error on the MPC8xx. This could be due to
454 * many reasons, including a dirty update to a pte. We can catch that
455 * one here, but anything else is an error. First, we track down the
456 * Linux pte. If it is valid, write access is allowed, but the
457 * page dirty bit is not set, we will set it and reload the TLB. For
458 * any other case, we bail out to a higher level function that can
463 #ifdef CONFIG_8xx_CPU6
466 DO_8xx_CPU6(0x3f80, r3)
467 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
472 /* First, make sure this was a store operation.
474 mfspr r10, SPRN_DSISR
475 andis. r11, r10, 0x0200 /* If set, indicates store op */
478 /* The EA of a data TLB miss is automatically stored in the MD_EPN
479 * register. The EA of a data TLB error is automatically stored in
480 * the DAR, but not the MD_EPN register. We must copy the 20 most
481 * significant bits of the EA from the DAR to MD_EPN before we
482 * start walking the page tables. We also need to copy the CASID
483 * value from the M_CASID register.
484 * Addendum: The EA of a data TLB error is _supposed_ to be stored
485 * in DAR, but it seems that this doesn't happen in some cases, such
486 * as when the error is due to a dcbi instruction to a page with a
487 * TLB that doesn't have the changed bit set. In such cases, there
488 * does not appear to be any way to recover the EA of the error
489 * since it is neither in DAR nor MD_EPN. As a workaround, the
490 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
491 * are initialized in mapin_ram(). This will avoid the problem,
492 * assuming we only use the dcbi instruction on kernel addresses.
495 rlwinm r11, r10, 0, 0, 19
496 ori r11, r11, MD_EVALID
497 mfspr r10, SPRN_M_CASID
498 rlwimi r11, r10, 0, 28, 31
499 DO_8xx_CPU6(0x3780, r3)
500 mtspr SPRN_MD_EPN, r11
502 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
504 /* If we are faulting a kernel address, we have to use the
505 * kernel page tables.
507 andi. r11, r10, 0x0800
509 lis r11, swapper_pg_dir@h
510 ori r11, r11, swapper_pg_dir@l
511 rlwimi r10, r11, 0, 2, 19
513 lwz r11, 0(r10) /* Get the level 1 entry */
514 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
515 beq 2f /* If zero, bail */
517 /* We have a pte table, so fetch the pte from the table.
519 ori r11, r11, 1 /* Set valid bit in physical L2 page */
520 DO_8xx_CPU6(0x3b80, r3)
521 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
522 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
523 lwz r10, 0(r11) /* Get the pte */
525 andi. r11, r10, _PAGE_RW /* Is it writeable? */
526 beq 2f /* Bail out if not */
528 /* Update 'changed', among others.
531 ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
532 /* do not set the _PAGE_ACCESSED bit of a non-present page */
533 andi. r11, r10, _PAGE_PRESENT
535 ori r10, r10, _PAGE_ACCESSED
538 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
540 mfspr r11, SPRN_MD_TWC /* Get pte address again */
541 stw r10, 0(r11) /* and update pte in table */
543 /* The Linux PTE won't go exactly into the MMU TLB.
544 * Software indicator bits 21, 22 and 28 must be clear.
545 * Software indicator bits 24, 25, 26, and 27 must be
546 * set. All other Linux PTE bits control the behavior
550 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
551 DO_8xx_CPU6(0x3d80, r3)
552 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
554 mfspr r10, SPRN_M_TW /* Restore registers */
558 #ifdef CONFIG_8xx_CPU6
563 mfspr r10, SPRN_M_TW /* Restore registers */
567 #ifdef CONFIG_8xx_CPU6
572 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
573 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
574 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
575 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
576 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
577 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
578 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
580 /* On the MPC8xx, these next four traps are used for development
581 * support of breakpoints and such. Someday I will get around to
584 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
585 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
586 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
587 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
596 * This is where the main kernel code starts.
601 ori r2,r2,init_task@l
603 /* ptr to phys current thread */
605 addi r4,r4,THREAD /* init task's THREAD */
606 mtspr SPRN_SPRG_THREAD,r4
608 /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */
609 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
612 lis r1,init_thread_union@ha
613 addi r1,r1,init_thread_union@l
615 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
617 bl early_init /* We have to do this with MMU on */
620 * Decide what sort of machine this is and initialize the MMU.
631 * Go back to running unmapped so we can load up new values
632 * and change to using our exception vectors.
633 * On the 8xx, all we have to do is invalidate the TLB to clear
634 * the old 8M byte TLB mappings and load the page table base register.
636 /* The right way to do this would be to track it down through
637 * init's THREAD like the context switch code does, but this is
638 * easier......until someone changes init's static structures.
640 lis r6, swapper_pg_dir@h
641 ori r6, r6, swapper_pg_dir@l
643 #ifdef CONFIG_8xx_CPU6
644 lis r4, cpu6_errata_word@h
645 ori r4, r4, cpu6_errata_word@l
654 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
658 /* Load up the kernel context */
660 SYNC /* Force all PTE updates to finish */
661 tlbia /* Clear all TLB entries */
662 sync /* wait for tlbia/tlbie to finish */
663 TLBSYNC /* ... on all CPUs */
665 /* set up the PTE pointers for the Abatron bdiGDB.
668 lis r5, abatron_pteptrs@h
669 ori r5, r5, abatron_pteptrs@l
670 stw r5, 0xf0(r0) /* Must match your Abatron config file */
674 /* Now turn on the MMU for real! */
676 lis r3,start_kernel@h
677 ori r3,r3,start_kernel@l
680 rfi /* enable MMU and jump to start_kernel */
682 /* Set up the initial MMU state so we can do the first level of
683 * kernel initialization. This maps the first 8 MBytes of memory 1:1
684 * virtual to physical. Also, set the cache mode since that is defined
685 * by TLB entries and perform any additional mapping (like of the IMMR).
686 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
687 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
688 * these mappings is mapped by page tables.
691 tlbia /* Invalidate all TLB entries */
692 #ifdef CONFIG_PIN_TLB
698 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
700 #ifdef CONFIG_PIN_TLB
701 lis r10, (MD_RSV4I | MD_RESETVAL)@h
705 lis r10, MD_RESETVAL@h
707 #ifndef CONFIG_8xx_COPYBACK
708 oris r10, r10, MD_WTDEF@h
710 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
712 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
713 * we can load the instruction and data TLB registers with the
716 lis r8, KERNELBASE@h /* Create vaddr for TLB */
717 ori r8, r8, MI_EVALID /* Mark it valid */
718 mtspr SPRN_MI_EPN, r8
719 mtspr SPRN_MD_EPN, r8
720 li r8, MI_PS8MEG /* Set 8M byte page */
721 ori r8, r8, MI_SVALID /* Make it valid */
722 mtspr SPRN_MI_TWC, r8
723 mtspr SPRN_MD_TWC, r8
724 li r8, MI_BOOTINIT /* Create RPN for address 0 */
725 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
726 mtspr SPRN_MD_RPN, r8
727 lis r8, MI_Kp@h /* Set the protection mode */
731 /* Map another 8 MByte at the IMMR to get the processor
732 * internal registers (among other things).
734 #ifdef CONFIG_PIN_TLB
735 addi r10, r10, 0x0100
736 mtspr SPRN_MD_CTR, r10
738 mfspr r9, 638 /* Get current IMMR */
739 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
741 mr r8, r9 /* Create vaddr for TLB */
742 ori r8, r8, MD_EVALID /* Mark it valid */
743 mtspr SPRN_MD_EPN, r8
744 li r8, MD_PS8MEG /* Set 8M byte page */
745 ori r8, r8, MD_SVALID /* Make it valid */
746 mtspr SPRN_MD_TWC, r8
747 mr r8, r9 /* Create paddr for TLB */
748 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
749 mtspr SPRN_MD_RPN, r8
751 #ifdef CONFIG_PIN_TLB
752 /* Map two more 8M kernel data pages.
754 addi r10, r10, 0x0100
755 mtspr SPRN_MD_CTR, r10
757 lis r8, KERNELBASE@h /* Create vaddr for TLB */
758 addis r8, r8, 0x0080 /* Add 8M */
759 ori r8, r8, MI_EVALID /* Mark it valid */
760 mtspr SPRN_MD_EPN, r8
761 li r9, MI_PS8MEG /* Set 8M byte page */
762 ori r9, r9, MI_SVALID /* Make it valid */
763 mtspr SPRN_MD_TWC, r9
764 li r11, MI_BOOTINIT /* Create RPN for address 0 */
765 addis r11, r11, 0x0080 /* Add 8M */
766 mtspr SPRN_MD_RPN, r11
768 addis r8, r8, 0x0080 /* Add 8M */
769 mtspr SPRN_MD_EPN, r8
770 mtspr SPRN_MD_TWC, r9
771 addis r11, r11, 0x0080 /* Add 8M */
772 mtspr SPRN_MD_RPN, r11
775 /* Since the cache is enabled according to the information we
776 * just loaded into the TLB, invalidate and enable the caches here.
777 * We should probably check/set other modes....later.
780 mtspr SPRN_IC_CST, r8
781 mtspr SPRN_DC_CST, r8
783 mtspr SPRN_IC_CST, r8
784 #ifdef CONFIG_8xx_COPYBACK
785 mtspr SPRN_DC_CST, r8
787 /* For a debug option, I left this here to easily enable
788 * the write through cache mode
791 mtspr SPRN_DC_CST, r8
793 mtspr SPRN_DC_CST, r8
799 * Set up to use a given MMU context.
800 * r3 is context number, r4 is PGD pointer.
802 * We place the physical address of the new task page directory loaded
803 * into the MMU base register, and set the ASID compare register with
808 #ifdef CONFIG_BDI_SWITCH
809 /* Context switch the PTE pointer for the Abatron BDI2000.
810 * The PGDIR is passed as second argument.
817 #ifdef CONFIG_8xx_CPU6
818 lis r6, cpu6_errata_word@h
819 ori r6, r6, cpu6_errata_word@l
824 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
828 mtspr SPRN_M_CASID, r3 /* Update context */
830 mtspr SPRN_M_CASID,r3 /* Update context */
832 mtspr SPRN_M_TWB, r4 /* and pgd */
837 #ifdef CONFIG_8xx_CPU6
838 /* It's here because it is unique to the 8xx.
839 * It is important we get called with interrupts disabled. I used to
840 * do that, but it appears that all code that calls this already had
841 * interrupt disabled.
845 lis r7, cpu6_errata_word@h
846 ori r7, r7, cpu6_errata_word@l
850 mtspr 22, r3 /* Update Decrementer */
856 * We put a few things here that have to be page-aligned.
857 * This stuff goes at the beginning of the data segment,
858 * which is page-aligned.
863 .globl empty_zero_page
867 .globl swapper_pg_dir
871 /* Room for two PTE table poiners, usually the kernel and current user
872 * pointer to their respective root page table (pgdir).
877 #ifdef CONFIG_8xx_CPU6
878 .globl cpu6_errata_word