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fed up with those stupid warnings
[mmotm.git] / arch / x86 / kvm / emulate.c
blobd226dff47d77e07c235dce78145729c76d38e7b4
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #include "kvm_cache_regs.h"
30 #define DPRINTF(x...) do {} while (0)
31 #endif
32 #include <linux/module.h>
33 #include <asm/kvm_emulate.h>
34
35 #include "mmu.h" /* for is_long_mode() */
36
37 /*
38 * Opcode effective-address decode tables.
39 * Note that we only emulate instructions that have at least one memory
40 * operand (excluding implicit stack references). We assume that stack
41 * references and instruction fetches will never occur in special memory
42 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 * not be handled.
44 */
45
46 /* Operand sizes: 8-bit operands or specified/overridden size. */
47 #define ByteOp (1<<0) /* 8-bit operands. */
48 /* Destination operand type. */
49 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
50 #define DstReg (2<<1) /* Register operand. */
51 #define DstMem (3<<1) /* Memory operand. */
52 #define DstAcc (4<<1) /* Destination Accumulator */
53 #define DstMask (7<<1)
54 /* Source operand type. */
55 #define SrcNone (0<<4) /* No source operand. */
56 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
57 #define SrcReg (1<<4) /* Register operand. */
58 #define SrcMem (2<<4) /* Memory operand. */
59 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
60 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
61 #define SrcImm (5<<4) /* Immediate operand. */
62 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
63 #define SrcOne (7<<4) /* Implied '1' */
64 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
65 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
66 #define SrcMask (0xf<<4)
67 /* Generic ModRM decode. */
68 #define ModRM (1<<8)
69 /* Destination is only written; never read. */
70 #define Mov (1<<9)
71 #define BitOp (1<<10)
72 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
73 #define String (1<<12) /* String instruction (rep capable) */
74 #define Stack (1<<13) /* Stack instruction (push/pop) */
75 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
76 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
77 #define GroupMask 0xff /* Group number stored in bits 0:7 */
78 /* Misc flags */
79 #define No64 (1<<28)
80 /* Source 2 operand type */
81 #define Src2None (0<<29)
82 #define Src2CL (1<<29)
83 #define Src2ImmByte (2<<29)
84 #define Src2One (3<<29)
85 #define Src2Imm16 (4<<29)
86 #define Src2Mask (7<<29)
87
88 enum {
89 Group1_80, Group1_81, Group1_82, Group1_83,
90 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
91 };
92
93 static u32 opcode_table[256] = {
94 /* 0x00 - 0x07 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
97 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
98 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
99 /* 0x08 - 0x0F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
102 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
103 ImplicitOps | Stack | No64, 0,
104 /* 0x10 - 0x17 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
107 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
108 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
109 /* 0x18 - 0x1F */
110 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
111 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
112 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
113 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
114 /* 0x20 - 0x27 */
115 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
117 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
118 /* 0x28 - 0x2F */
119 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
120 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
121 0, 0, 0, 0,
122 /* 0x30 - 0x37 */
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
125 0, 0, 0, 0,
126 /* 0x38 - 0x3F */
127 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
128 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
129 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
130 0, 0,
131 /* 0x40 - 0x47 */
132 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
133 /* 0x48 - 0x4F */
134 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
135 /* 0x50 - 0x57 */
136 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
137 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
138 /* 0x58 - 0x5F */
139 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
140 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
141 /* 0x60 - 0x67 */
142 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
143 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
144 0, 0, 0, 0,
145 /* 0x68 - 0x6F */
146 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
147 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
148 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
149 /* 0x70 - 0x77 */
150 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
151 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
152 /* 0x78 - 0x7F */
153 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
154 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
155 /* 0x80 - 0x87 */
156 Group | Group1_80, Group | Group1_81,
157 Group | Group1_82, Group | Group1_83,
158 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
159 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
160 /* 0x88 - 0x8F */
161 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
162 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
163 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
164 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
165 /* 0x90 - 0x97 */
166 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
167 /* 0x98 - 0x9F */
168 0, 0, SrcImm | Src2Imm16 | No64, 0,
169 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
170 /* 0xA0 - 0xA7 */
171 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
172 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
173 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
174 ByteOp | ImplicitOps | String, ImplicitOps | String,
175 /* 0xA8 - 0xAF */
176 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
177 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
178 ByteOp | ImplicitOps | String, ImplicitOps | String,
179 /* 0xB0 - 0xB7 */
180 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
181 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
182 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
183 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
184 /* 0xB8 - 0xBF */
185 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
186 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
187 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
188 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
189 /* 0xC0 - 0xC7 */
190 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
191 0, ImplicitOps | Stack, 0, 0,
192 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
193 /* 0xC8 - 0xCF */
194 0, 0, 0, ImplicitOps | Stack,
195 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
196 /* 0xD0 - 0xD7 */
197 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
198 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
199 0, 0, 0, 0,
200 /* 0xD8 - 0xDF */
201 0, 0, 0, 0, 0, 0, 0, 0,
202 /* 0xE0 - 0xE7 */
203 0, 0, 0, 0,
204 ByteOp | SrcImmUByte, SrcImmUByte,
205 ByteOp | SrcImmUByte, SrcImmUByte,
206 /* 0xE8 - 0xEF */
207 SrcImm | Stack, SrcImm | ImplicitOps,
208 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
209 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
210 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
211 /* 0xF0 - 0xF7 */
212 0, 0, 0, 0,
213 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
214 /* 0xF8 - 0xFF */
215 ImplicitOps, 0, ImplicitOps, ImplicitOps,
216 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
217 };
218
219 static u32 twobyte_table[256] = {
220 /* 0x00 - 0x0F */
221 0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0,
222 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
223 /* 0x10 - 0x1F */
224 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
225 /* 0x20 - 0x2F */
226 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
227 0, 0, 0, 0, 0, 0, 0, 0,
228 /* 0x30 - 0x3F */
229 ImplicitOps, 0, ImplicitOps, 0,
230 ImplicitOps, ImplicitOps, 0, 0,
231 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0x40 - 0x47 */
233 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
234 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
235 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
236 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
237 /* 0x48 - 0x4F */
238 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
239 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
241 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
242 /* 0x50 - 0x5F */
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
244 /* 0x60 - 0x6F */
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
246 /* 0x70 - 0x7F */
247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
248 /* 0x80 - 0x8F */
249 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
250 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
251 /* 0x90 - 0x9F */
252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
253 /* 0xA0 - 0xA7 */
254 ImplicitOps | Stack, ImplicitOps | Stack,
255 0, DstMem | SrcReg | ModRM | BitOp,
256 DstMem | SrcReg | Src2ImmByte | ModRM,
257 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
258 /* 0xA8 - 0xAF */
259 ImplicitOps | Stack, ImplicitOps | Stack,
260 0, DstMem | SrcReg | ModRM | BitOp,
261 DstMem | SrcReg | Src2ImmByte | ModRM,
262 DstMem | SrcReg | Src2CL | ModRM,
263 ModRM, 0,
264 /* 0xB0 - 0xB7 */
265 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
266 DstMem | SrcReg | ModRM | BitOp,
267 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
268 DstReg | SrcMem16 | ModRM | Mov,
269 /* 0xB8 - 0xBF */
270 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
271 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
272 DstReg | SrcMem16 | ModRM | Mov,
273 /* 0xC0 - 0xCF */
274 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
275 0, 0, 0, 0, 0, 0, 0, 0,
276 /* 0xD0 - 0xDF */
277 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
278 /* 0xE0 - 0xEF */
279 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
280 /* 0xF0 - 0xFF */
281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
282 };
283
284 static u32 group_table[] = {
285 [Group1_80*8] =
286 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
287 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
288 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
289 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
290 [Group1_81*8] =
291 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
292 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
293 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
294 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
295 [Group1_82*8] =
296 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
297 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
298 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
299 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
300 [Group1_83*8] =
301 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
302 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
303 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
304 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
305 [Group1A*8] =
306 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
307 [Group3_Byte*8] =
308 ByteOp | SrcImm | DstMem | ModRM, 0,
309 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
310 0, 0, 0, 0,
311 [Group3*8] =
312 DstMem | SrcImm | ModRM, 0,
313 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
314 0, 0, 0, 0,
315 [Group4*8] =
316 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
317 0, 0, 0, 0, 0, 0,
318 [Group5*8] =
319 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
320 SrcMem | ModRM | Stack, 0,
321 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
322 [Group7*8] =
323 0, 0, ModRM | SrcMem, ModRM | SrcMem,
324 SrcNone | ModRM | DstMem | Mov, 0,
325 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
326 };
327
328 static u32 group2_table[] = {
329 [Group7*8] =
330 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
331 SrcNone | ModRM | DstMem | Mov, 0,
332 SrcMem16 | ModRM | Mov, 0,
333 };
334
335 /* EFLAGS bit definitions. */
336 #define EFLG_VM (1<<17)
337 #define EFLG_RF (1<<16)
338 #define EFLG_OF (1<<11)
339 #define EFLG_DF (1<<10)
340 #define EFLG_IF (1<<9)
341 #define EFLG_SF (1<<7)
342 #define EFLG_ZF (1<<6)
343 #define EFLG_AF (1<<4)
344 #define EFLG_PF (1<<2)
345 #define EFLG_CF (1<<0)
346
347 /*
348 * Instruction emulation:
349 * Most instructions are emulated directly via a fragment of inline assembly
350 * code. This allows us to save/restore EFLAGS and thus very easily pick up
351 * any modified flags.
352 */
353
354 #if defined(CONFIG_X86_64)
355 #define _LO32 "k" /* force 32-bit operand */
356 #define _STK "%%rsp" /* stack pointer */
357 #elif defined(__i386__)
358 #define _LO32 "" /* force 32-bit operand */
359 #define _STK "%%esp" /* stack pointer */
360 #endif
361
362 /*
363 * These EFLAGS bits are restored from saved value during emulation, and
364 * any changes are written back to the saved value after emulation.
365 */
366 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
367
368 /* Before executing instruction: restore necessary bits in EFLAGS. */
369 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
370 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
371 "movl %"_sav",%"_LO32 _tmp"; " \
372 "push %"_tmp"; " \
373 "push %"_tmp"; " \
374 "movl %"_msk",%"_LO32 _tmp"; " \
375 "andl %"_LO32 _tmp",("_STK"); " \
376 "pushf; " \
377 "notl %"_LO32 _tmp"; " \
378 "andl %"_LO32 _tmp",("_STK"); " \
379 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
380 "pop %"_tmp"; " \
381 "orl %"_LO32 _tmp",("_STK"); " \
382 "popf; " \
383 "pop %"_sav"; "
384
385 /* After executing instruction: write-back necessary bits in EFLAGS. */
386 #define _POST_EFLAGS(_sav, _msk, _tmp) \
387 /* _sav |= EFLAGS & _msk; */ \
388 "pushf; " \
389 "pop %"_tmp"; " \
390 "andl %"_msk",%"_LO32 _tmp"; " \
391 "orl %"_LO32 _tmp",%"_sav"; "
392
393 #ifdef CONFIG_X86_64
394 #define ON64(x) x
395 #else
396 #define ON64(x)
397 #endif
398
399 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
400 do { \
401 __asm__ __volatile__ ( \
402 _PRE_EFLAGS("0", "4", "2") \
403 _op _suffix " %"_x"3,%1; " \
404 _POST_EFLAGS("0", "4", "2") \
405 : "=m" (_eflags), "=m" ((_dst).val), \
406 "=&r" (_tmp) \
407 : _y ((_src).val), "i" (EFLAGS_MASK)); \
408 } while (0)
409
410
411 /* Raw emulation: instruction has two explicit operands. */
412 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
413 do { \
414 unsigned long _tmp; \
415 \
416 switch ((_dst).bytes) { \
417 case 2: \
418 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
419 break; \
420 case 4: \
421 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
422 break; \
423 case 8: \
424 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
425 break; \
426 } \
427 } while (0)
428
429 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
430 do { \
431 unsigned long _tmp; \
432 switch ((_dst).bytes) { \
433 case 1: \
434 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
435 break; \
436 default: \
437 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
438 _wx, _wy, _lx, _ly, _qx, _qy); \
439 break; \
440 } \
441 } while (0)
442
443 /* Source operand is byte-sized and may be restricted to just %cl. */
444 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
445 __emulate_2op(_op, _src, _dst, _eflags, \
446 "b", "c", "b", "c", "b", "c", "b", "c")
447
448 /* Source operand is byte, word, long or quad sized. */
449 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
450 __emulate_2op(_op, _src, _dst, _eflags, \
451 "b", "q", "w", "r", _LO32, "r", "", "r")
452
453 /* Source operand is word, long or quad sized. */
454 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
455 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
456 "w", "r", _LO32, "r", "", "r")
457
458 /* Instruction has three operands and one operand is stored in ECX register */
459 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
460 do { \
461 unsigned long _tmp; \
462 _type _clv = (_cl).val; \
463 _type _srcv = (_src).val; \
464 _type _dstv = (_dst).val; \
465 \
466 __asm__ __volatile__ ( \
467 _PRE_EFLAGS("0", "5", "2") \
468 _op _suffix " %4,%1 \n" \
469 _POST_EFLAGS("0", "5", "2") \
470 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
471 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
472 ); \
473 \
474 (_cl).val = (unsigned long) _clv; \
475 (_src).val = (unsigned long) _srcv; \
476 (_dst).val = (unsigned long) _dstv; \
477 } while (0)
478
479 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
480 do { \
481 switch ((_dst).bytes) { \
482 case 2: \
483 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
484 "w", unsigned short); \
485 break; \
486 case 4: \
487 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
488 "l", unsigned int); \
489 break; \
490 case 8: \
491 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
492 "q", unsigned long)); \
493 break; \
494 } \
495 } while (0)
496
497 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
498 do { \
499 unsigned long _tmp; \
500 \
501 __asm__ __volatile__ ( \
502 _PRE_EFLAGS("0", "3", "2") \
503 _op _suffix " %1; " \
504 _POST_EFLAGS("0", "3", "2") \
505 : "=m" (_eflags), "+m" ((_dst).val), \
506 "=&r" (_tmp) \
507 : "i" (EFLAGS_MASK)); \
508 } while (0)
509
510 /* Instruction has only one explicit operand (no source operand). */
511 #define emulate_1op(_op, _dst, _eflags) \
512 do { \
513 switch ((_dst).bytes) { \
514 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
515 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
516 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
517 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
518 } \
519 } while (0)
520
521 /* Fetch next part of the instruction being emulated. */
522 #define insn_fetch(_type, _size, _eip) \
523 ({ unsigned long _x; \
524 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
525 if (rc != 0) \
526 goto done; \
527 (_eip) += (_size); \
528 (_type)_x; \
529 })
530
531 static inline unsigned long ad_mask(struct decode_cache *c)
532 {
533 return (1UL << (c->ad_bytes << 3)) - 1;
534 }
535
536 /* Access/update address held in a register, based on addressing mode. */
537 static inline unsigned long
538 address_mask(struct decode_cache *c, unsigned long reg)
539 {
540 if (c->ad_bytes == sizeof(unsigned long))
541 return reg;
542 else
543 return reg & ad_mask(c);
544 }
545
546 static inline unsigned long
547 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
548 {
549 return base + address_mask(c, reg);
550 }
551
552 static inline void
553 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
554 {
555 if (c->ad_bytes == sizeof(unsigned long))
556 *reg += inc;
557 else
558 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
559 }
560
561 static inline void jmp_rel(struct decode_cache *c, int rel)
562 {
563 register_address_increment(c, &c->eip, rel);
564 }
565
566 static void set_seg_override(struct decode_cache *c, int seg)
567 {
568 c->has_seg_override = true;
569 c->seg_override = seg;
570 }
571
572 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
573 {
574 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
575 return 0;
576
577 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
578 }
579
580 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
581 struct decode_cache *c)
582 {
583 if (!c->has_seg_override)
584 return 0;
585
586 return seg_base(ctxt, c->seg_override);
587 }
588
589 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
590 {
591 return seg_base(ctxt, VCPU_SREG_ES);
592 }
593
594 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
595 {
596 return seg_base(ctxt, VCPU_SREG_SS);
597 }
598
599 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
600 struct x86_emulate_ops *ops,
601 unsigned long linear, u8 *dest)
602 {
603 struct fetch_cache *fc = &ctxt->decode.fetch;
604 int rc;
605 int size;
606
607 if (linear < fc->start || linear >= fc->end) {
608 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
609 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
610 if (rc)
611 return rc;
612 fc->start = linear;
613 fc->end = linear + size;
614 }
615 *dest = fc->data[linear - fc->start];
616 return 0;
617 }
618
619 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
620 struct x86_emulate_ops *ops,
621 unsigned long eip, void *dest, unsigned size)
622 {
623 int rc = 0;
624
625 eip += ctxt->cs_base;
626 while (size--) {
627 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
628 if (rc)
629 return rc;
630 }
631 return 0;
632 }
633
634 /*
635 * Given the 'reg' portion of a ModRM byte, and a register block, return a
636 * pointer into the block that addresses the relevant register.
637 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
638 */
639 static void *decode_register(u8 modrm_reg, unsigned long *regs,
640 int highbyte_regs)
641 {
642 void *p;
643
644 p = &regs[modrm_reg];
645 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
646 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
647 return p;
648 }
649
650 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
651 struct x86_emulate_ops *ops,
652 void *ptr,
653 u16 *size, unsigned long *address, int op_bytes)
654 {
655 int rc;
656
657 if (op_bytes == 2)
658 op_bytes = 3;
659 *address = 0;
660 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
661 ctxt->vcpu);
662 if (rc)
663 return rc;
664 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
665 ctxt->vcpu);
666 return rc;
667 }
668
669 static int test_cc(unsigned int condition, unsigned int flags)
670 {
671 int rc = 0;
672
673 switch ((condition & 15) >> 1) {
674 case 0: /* o */
675 rc |= (flags & EFLG_OF);
676 break;
677 case 1: /* b/c/nae */
678 rc |= (flags & EFLG_CF);
679 break;
680 case 2: /* z/e */
681 rc |= (flags & EFLG_ZF);
682 break;
683 case 3: /* be/na */
684 rc |= (flags & (EFLG_CF|EFLG_ZF));
685 break;
686 case 4: /* s */
687 rc |= (flags & EFLG_SF);
688 break;
689 case 5: /* p/pe */
690 rc |= (flags & EFLG_PF);
691 break;
692 case 7: /* le/ng */
693 rc |= (flags & EFLG_ZF);
694 /* fall through */
695 case 6: /* l/nge */
696 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
697 break;
698 }
699
700 /* Odd condition identifiers (lsb == 1) have inverted sense. */
701 return (!!rc ^ (condition & 1));
702 }
703
704 static void decode_register_operand(struct operand *op,
705 struct decode_cache *c,
706 int inhibit_bytereg)
707 {
708 unsigned reg = c->modrm_reg;
709 int highbyte_regs = c->rex_prefix == 0;
710
711 if (!(c->d & ModRM))
712 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
713 op->type = OP_REG;
714 if ((c->d & ByteOp) && !inhibit_bytereg) {
715 op->ptr = decode_register(reg, c->regs, highbyte_regs);
716 op->val = *(u8 *)op->ptr;
717 op->bytes = 1;
718 } else {
719 op->ptr = decode_register(reg, c->regs, 0);
720 op->bytes = c->op_bytes;
721 switch (op->bytes) {
722 case 2:
723 op->val = *(u16 *)op->ptr;
724 break;
725 case 4:
726 op->val = *(u32 *)op->ptr;
727 break;
728 case 8:
729 op->val = *(u64 *) op->ptr;
730 break;
731 }
732 }
733 op->orig_val = op->val;
734 }
735
736 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
737 struct x86_emulate_ops *ops)
738 {
739 struct decode_cache *c = &ctxt->decode;
740 u8 sib;
741 int index_reg = 0, base_reg = 0, scale;
742 int rc = 0;
743
744 if (c->rex_prefix) {
745 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
746 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
747 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
748 }
749
750 c->modrm = insn_fetch(u8, 1, c->eip);
751 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
752 c->modrm_reg |= (c->modrm & 0x38) >> 3;
753 c->modrm_rm |= (c->modrm & 0x07);
754 c->modrm_ea = 0;
755 c->use_modrm_ea = 1;
756
757 if (c->modrm_mod == 3) {
758 c->modrm_ptr = decode_register(c->modrm_rm,
759 c->regs, c->d & ByteOp);
760 c->modrm_val = *(unsigned long *)c->modrm_ptr;
761 return rc;
762 }
763
764 if (c->ad_bytes == 2) {
765 unsigned bx = c->regs[VCPU_REGS_RBX];
766 unsigned bp = c->regs[VCPU_REGS_RBP];
767 unsigned si = c->regs[VCPU_REGS_RSI];
768 unsigned di = c->regs[VCPU_REGS_RDI];
769
770 /* 16-bit ModR/M decode. */
771 switch (c->modrm_mod) {
772 case 0:
773 if (c->modrm_rm == 6)
774 c->modrm_ea += insn_fetch(u16, 2, c->eip);
775 break;
776 case 1:
777 c->modrm_ea += insn_fetch(s8, 1, c->eip);
778 break;
779 case 2:
780 c->modrm_ea += insn_fetch(u16, 2, c->eip);
781 break;
782 }
783 switch (c->modrm_rm) {
784 case 0:
785 c->modrm_ea += bx + si;
786 break;
787 case 1:
788 c->modrm_ea += bx + di;
789 break;
790 case 2:
791 c->modrm_ea += bp + si;
792 break;
793 case 3:
794 c->modrm_ea += bp + di;
795 break;
796 case 4:
797 c->modrm_ea += si;
798 break;
799 case 5:
800 c->modrm_ea += di;
801 break;
802 case 6:
803 if (c->modrm_mod != 0)
804 c->modrm_ea += bp;
805 break;
806 case 7:
807 c->modrm_ea += bx;
808 break;
809 }
810 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
811 (c->modrm_rm == 6 && c->modrm_mod != 0))
812 if (!c->has_seg_override)
813 set_seg_override(c, VCPU_SREG_SS);
814 c->modrm_ea = (u16)c->modrm_ea;
815 } else {
816 /* 32/64-bit ModR/M decode. */
817 if ((c->modrm_rm & 7) == 4) {
818 sib = insn_fetch(u8, 1, c->eip);
819 index_reg |= (sib >> 3) & 7;
820 base_reg |= sib & 7;
821 scale = sib >> 6;
822
823 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
824 c->modrm_ea += insn_fetch(s32, 4, c->eip);
825 else
826 c->modrm_ea += c->regs[base_reg];
827 if (index_reg != 4)
828 c->modrm_ea += c->regs[index_reg] << scale;
829 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
830 if (ctxt->mode == X86EMUL_MODE_PROT64)
831 c->rip_relative = 1;
832 } else
833 c->modrm_ea += c->regs[c->modrm_rm];
834 switch (c->modrm_mod) {
835 case 0:
836 if (c->modrm_rm == 5)
837 c->modrm_ea += insn_fetch(s32, 4, c->eip);
838 break;
839 case 1:
840 c->modrm_ea += insn_fetch(s8, 1, c->eip);
841 break;
842 case 2:
843 c->modrm_ea += insn_fetch(s32, 4, c->eip);
844 break;
845 }
846 }
847 done:
848 return rc;
849 }
850
851 static int decode_abs(struct x86_emulate_ctxt *ctxt,
852 struct x86_emulate_ops *ops)
853 {
854 struct decode_cache *c = &ctxt->decode;
855 int rc = 0;
856
857 switch (c->ad_bytes) {
858 case 2:
859 c->modrm_ea = insn_fetch(u16, 2, c->eip);
860 break;
861 case 4:
862 c->modrm_ea = insn_fetch(u32, 4, c->eip);
863 break;
864 case 8:
865 c->modrm_ea = insn_fetch(u64, 8, c->eip);
866 break;
867 }
868 done:
869 return rc;
870 }
871
872 int
873 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
874 {
875 struct decode_cache *c = &ctxt->decode;
876 int rc = 0;
877 int mode = ctxt->mode;
878 int def_op_bytes, def_ad_bytes, group;
879
880 /* Shadow copy of register state. Committed on successful emulation. */
881
882 memset(c, 0, sizeof(struct decode_cache));
883 c->eip = kvm_rip_read(ctxt->vcpu);
884 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
885 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
886
887 switch (mode) {
888 case X86EMUL_MODE_REAL:
889 case X86EMUL_MODE_PROT16:
890 def_op_bytes = def_ad_bytes = 2;
891 break;
892 case X86EMUL_MODE_PROT32:
893 def_op_bytes = def_ad_bytes = 4;
894 break;
895 #ifdef CONFIG_X86_64
896 case X86EMUL_MODE_PROT64:
897 def_op_bytes = 4;
898 def_ad_bytes = 8;
899 break;
900 #endif
901 default:
902 return -1;
903 }
904
905 c->op_bytes = def_op_bytes;
906 c->ad_bytes = def_ad_bytes;
907
908 /* Legacy prefixes. */
909 for (;;) {
910 switch (c->b = insn_fetch(u8, 1, c->eip)) {
911 case 0x66: /* operand-size override */
912 /* switch between 2/4 bytes */
913 c->op_bytes = def_op_bytes ^ 6;
914 break;
915 case 0x67: /* address-size override */
916 if (mode == X86EMUL_MODE_PROT64)
917 /* switch between 4/8 bytes */
918 c->ad_bytes = def_ad_bytes ^ 12;
919 else
920 /* switch between 2/4 bytes */
921 c->ad_bytes = def_ad_bytes ^ 6;
922 break;
923 case 0x26: /* ES override */
924 case 0x2e: /* CS override */
925 case 0x36: /* SS override */
926 case 0x3e: /* DS override */
927 set_seg_override(c, (c->b >> 3) & 3);
928 break;
929 case 0x64: /* FS override */
930 case 0x65: /* GS override */
931 set_seg_override(c, c->b & 7);
932 break;
933 case 0x40 ... 0x4f: /* REX */
934 if (mode != X86EMUL_MODE_PROT64)
935 goto done_prefixes;
936 c->rex_prefix = c->b;
937 continue;
938 case 0xf0: /* LOCK */
939 c->lock_prefix = 1;
940 break;
941 case 0xf2: /* REPNE/REPNZ */
942 c->rep_prefix = REPNE_PREFIX;
943 break;
944 case 0xf3: /* REP/REPE/REPZ */
945 c->rep_prefix = REPE_PREFIX;
946 break;
947 default:
948 goto done_prefixes;
949 }
950
951 /* Any legacy prefix after a REX prefix nullifies its effect. */
952
953 c->rex_prefix = 0;
954 }
955
956 done_prefixes:
957
958 /* REX prefix. */
959 if (c->rex_prefix)
960 if (c->rex_prefix & 8)
961 c->op_bytes = 8; /* REX.W */
962
963 /* Opcode byte(s). */
964 c->d = opcode_table[c->b];
965 if (c->d == 0) {
966 /* Two-byte opcode? */
967 if (c->b == 0x0f) {
968 c->twobyte = 1;
969 c->b = insn_fetch(u8, 1, c->eip);
970 c->d = twobyte_table[c->b];
971 }
972 }
973
974 if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
975 kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");;
976 return -1;
977 }
978
979 if (c->d & Group) {
980 group = c->d & GroupMask;
981 c->modrm = insn_fetch(u8, 1, c->eip);
982 --c->eip;
983
984 group = (group << 3) + ((c->modrm >> 3) & 7);
985 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
986 c->d = group2_table[group];
987 else
988 c->d = group_table[group];
989 }
990
991 /* Unrecognised? */
992 if (c->d == 0) {
993 DPRINTF("Cannot emulate %02x\n", c->b);
994 return -1;
995 }
996
997 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
998 c->op_bytes = 8;
999
1000 /* ModRM and SIB bytes. */
1001 if (c->d & ModRM)
1002 rc = decode_modrm(ctxt, ops);
1003 else if (c->d & MemAbs)
1004 rc = decode_abs(ctxt, ops);
1005 if (rc)
1006 goto done;
1007
1008 if (!c->has_seg_override)
1009 set_seg_override(c, VCPU_SREG_DS);
1010
1011 if (!(!c->twobyte && c->b == 0x8d))
1012 c->modrm_ea += seg_override_base(ctxt, c);
1013
1014 if (c->ad_bytes != 8)
1015 c->modrm_ea = (u32)c->modrm_ea;
1016 /*
1017 * Decode and fetch the source operand: register, memory
1018 * or immediate.
1019 */
1020 switch (c->d & SrcMask) {
1021 case SrcNone:
1022 break;
1023 case SrcReg:
1024 decode_register_operand(&c->src, c, 0);
1025 break;
1026 case SrcMem16:
1027 c->src.bytes = 2;
1028 goto srcmem_common;
1029 case SrcMem32:
1030 c->src.bytes = 4;
1031 goto srcmem_common;
1032 case SrcMem:
1033 c->src.bytes = (c->d & ByteOp) ? 1 :
1034 c->op_bytes;
1035 /* Don't fetch the address for invlpg: it could be unmapped. */
1036 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1037 break;
1038 srcmem_common:
1039 /*
1040 * For instructions with a ModR/M byte, switch to register
1041 * access if Mod = 3.
1042 */
1043 if ((c->d & ModRM) && c->modrm_mod == 3) {
1044 c->src.type = OP_REG;
1045 c->src.val = c->modrm_val;
1046 c->src.ptr = c->modrm_ptr;
1047 break;
1048 }
1049 c->src.type = OP_MEM;
1050 break;
1051 case SrcImm:
1052 case SrcImmU:
1053 c->src.type = OP_IMM;
1054 c->src.ptr = (unsigned long *)c->eip;
1055 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1056 if (c->src.bytes == 8)
1057 c->src.bytes = 4;
1058 /* NB. Immediates are sign-extended as necessary. */
1059 switch (c->src.bytes) {
1060 case 1:
1061 c->src.val = insn_fetch(s8, 1, c->eip);
1062 break;
1063 case 2:
1064 c->src.val = insn_fetch(s16, 2, c->eip);
1065 break;
1066 case 4:
1067 c->src.val = insn_fetch(s32, 4, c->eip);
1068 break;
1069 }
1070 if ((c->d & SrcMask) == SrcImmU) {
1071 switch (c->src.bytes) {
1072 case 1:
1073 c->src.val &= 0xff;
1074 break;
1075 case 2:
1076 c->src.val &= 0xffff;
1077 break;
1078 case 4:
1079 c->src.val &= 0xffffffff;
1080 break;
1081 }
1082 }
1083 break;
1084 case SrcImmByte:
1085 case SrcImmUByte:
1086 c->src.type = OP_IMM;
1087 c->src.ptr = (unsigned long *)c->eip;
1088 c->src.bytes = 1;
1089 if ((c->d & SrcMask) == SrcImmByte)
1090 c->src.val = insn_fetch(s8, 1, c->eip);
1091 else
1092 c->src.val = insn_fetch(u8, 1, c->eip);
1093 break;
1094 case SrcOne:
1095 c->src.bytes = 1;
1096 c->src.val = 1;
1097 break;
1098 }
1099
1100 /*
1101 * Decode and fetch the second source operand: register, memory
1102 * or immediate.
1103 */
1104 switch (c->d & Src2Mask) {
1105 case Src2None:
1106 break;
1107 case Src2CL:
1108 c->src2.bytes = 1;
1109 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1110 break;
1111 case Src2ImmByte:
1112 c->src2.type = OP_IMM;
1113 c->src2.ptr = (unsigned long *)c->eip;
1114 c->src2.bytes = 1;
1115 c->src2.val = insn_fetch(u8, 1, c->eip);
1116 break;
1117 case Src2Imm16:
1118 c->src2.type = OP_IMM;
1119 c->src2.ptr = (unsigned long *)c->eip;
1120 c->src2.bytes = 2;
1121 c->src2.val = insn_fetch(u16, 2, c->eip);
1122 break;
1123 case Src2One:
1124 c->src2.bytes = 1;
1125 c->src2.val = 1;
1126 break;
1127 }
1128
1129 /* Decode and fetch the destination operand: register or memory. */
1130 switch (c->d & DstMask) {
1131 case ImplicitOps:
1132 /* Special instructions do their own operand decoding. */
1133 return 0;
1134 case DstReg:
1135 decode_register_operand(&c->dst, c,
1136 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1137 break;
1138 case DstMem:
1139 if ((c->d & ModRM) && c->modrm_mod == 3) {
1140 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1141 c->dst.type = OP_REG;
1142 c->dst.val = c->dst.orig_val = c->modrm_val;
1143 c->dst.ptr = c->modrm_ptr;
1144 break;
1145 }
1146 c->dst.type = OP_MEM;
1147 break;
1148 case DstAcc:
1149 c->dst.type = OP_REG;
1150 c->dst.bytes = c->op_bytes;
1151 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1152 switch (c->op_bytes) {
1153 case 1:
1154 c->dst.val = *(u8 *)c->dst.ptr;
1155 break;
1156 case 2:
1157 c->dst.val = *(u16 *)c->dst.ptr;
1158 break;
1159 case 4:
1160 c->dst.val = *(u32 *)c->dst.ptr;
1161 break;
1162 }
1163 c->dst.orig_val = c->dst.val;
1164 break;
1165 }
1166
1167 if (c->rip_relative)
1168 c->modrm_ea += c->eip;
1169
1170 done:
1171 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1172 }
1173
1174 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1175 {
1176 struct decode_cache *c = &ctxt->decode;
1177
1178 c->dst.type = OP_MEM;
1179 c->dst.bytes = c->op_bytes;
1180 c->dst.val = c->src.val;
1181 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1182 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1183 c->regs[VCPU_REGS_RSP]);
1184 }
1185
1186 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1187 struct x86_emulate_ops *ops,
1188 void *dest, int len)
1189 {
1190 struct decode_cache *c = &ctxt->decode;
1191 int rc;
1192
1193 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1194 c->regs[VCPU_REGS_RSP]),
1195 dest, len, ctxt->vcpu);
1196 if (rc != 0)
1197 return rc;
1198
1199 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1200 return rc;
1201 }
1202
1203 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1204 {
1205 struct decode_cache *c = &ctxt->decode;
1206 struct kvm_segment segment;
1207
1208 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1209
1210 c->src.val = segment.selector;
1211 emulate_push(ctxt);
1212 }
1213
1214 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1215 struct x86_emulate_ops *ops, int seg)
1216 {
1217 struct decode_cache *c = &ctxt->decode;
1218 unsigned long selector;
1219 int rc;
1220
1221 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1222 if (rc != 0)
1223 return rc;
1224
1225 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg);
1226 return rc;
1227 }
1228
1229 static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1230 {
1231 struct decode_cache *c = &ctxt->decode;
1232 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1233 int reg = VCPU_REGS_RAX;
1234
1235 while (reg <= VCPU_REGS_RDI) {
1236 (reg == VCPU_REGS_RSP) ?
1237 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1238
1239 emulate_push(ctxt);
1240 ++reg;
1241 }
1242 }
1243
1244 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1245 struct x86_emulate_ops *ops)
1246 {
1247 struct decode_cache *c = &ctxt->decode;
1248 int rc = 0;
1249 int reg = VCPU_REGS_RDI;
1250
1251 while (reg >= VCPU_REGS_RAX) {
1252 if (reg == VCPU_REGS_RSP) {
1253 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1254 c->op_bytes);
1255 --reg;
1256 }
1257
1258 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1259 if (rc != 0)
1260 break;
1261 --reg;
1262 }
1263 return rc;
1264 }
1265
1266 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1267 struct x86_emulate_ops *ops)
1268 {
1269 struct decode_cache *c = &ctxt->decode;
1270 int rc;
1271
1272 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1273 if (rc != 0)
1274 return rc;
1275 return 0;
1276 }
1277
1278 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1279 {
1280 struct decode_cache *c = &ctxt->decode;
1281 switch (c->modrm_reg) {
1282 case 0: /* rol */
1283 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1284 break;
1285 case 1: /* ror */
1286 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1287 break;
1288 case 2: /* rcl */
1289 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1290 break;
1291 case 3: /* rcr */
1292 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1293 break;
1294 case 4: /* sal/shl */
1295 case 6: /* sal/shl */
1296 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1297 break;
1298 case 5: /* shr */
1299 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1300 break;
1301 case 7: /* sar */
1302 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1303 break;
1304 }
1305 }
1306
1307 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1308 struct x86_emulate_ops *ops)
1309 {
1310 struct decode_cache *c = &ctxt->decode;
1311 int rc = 0;
1312
1313 switch (c->modrm_reg) {
1314 case 0 ... 1: /* test */
1315 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1316 break;
1317 case 2: /* not */
1318 c->dst.val = ~c->dst.val;
1319 break;
1320 case 3: /* neg */
1321 emulate_1op("neg", c->dst, ctxt->eflags);
1322 break;
1323 default:
1324 DPRINTF("Cannot emulate %02x\n", c->b);
1325 rc = X86EMUL_UNHANDLEABLE;
1326 break;
1327 }
1328 return rc;
1329 }
1330
1331 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1332 struct x86_emulate_ops *ops)
1333 {
1334 struct decode_cache *c = &ctxt->decode;
1335
1336 switch (c->modrm_reg) {
1337 case 0: /* inc */
1338 emulate_1op("inc", c->dst, ctxt->eflags);
1339 break;
1340 case 1: /* dec */
1341 emulate_1op("dec", c->dst, ctxt->eflags);
1342 break;
1343 case 2: /* call near abs */ {
1344 long int old_eip;
1345 old_eip = c->eip;
1346 c->eip = c->src.val;
1347 c->src.val = old_eip;
1348 emulate_push(ctxt);
1349 break;
1350 }
1351 case 4: /* jmp abs */
1352 c->eip = c->src.val;
1353 break;
1354 case 6: /* push */
1355 emulate_push(ctxt);
1356 break;
1357 }
1358 return 0;
1359 }
1360
1361 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1362 struct x86_emulate_ops *ops,
1363 unsigned long memop)
1364 {
1365 struct decode_cache *c = &ctxt->decode;
1366 u64 old, new;
1367 int rc;
1368
1369 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1370 if (rc != 0)
1371 return rc;
1372
1373 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1374 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1375
1376 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1377 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1378 ctxt->eflags &= ~EFLG_ZF;
1379
1380 } else {
1381 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1382 (u32) c->regs[VCPU_REGS_RBX];
1383
1384 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1385 if (rc != 0)
1386 return rc;
1387 ctxt->eflags |= EFLG_ZF;
1388 }
1389 return 0;
1390 }
1391
1392 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1393 struct x86_emulate_ops *ops)
1394 {
1395 struct decode_cache *c = &ctxt->decode;
1396 int rc;
1397 unsigned long cs;
1398
1399 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1400 if (rc)
1401 return rc;
1402 if (c->op_bytes == 4)
1403 c->eip = (u32)c->eip;
1404 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1405 if (rc)
1406 return rc;
1407 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1408 return rc;
1409 }
1410
1411 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1412 struct x86_emulate_ops *ops)
1413 {
1414 int rc;
1415 struct decode_cache *c = &ctxt->decode;
1416
1417 switch (c->dst.type) {
1418 case OP_REG:
1419 /* The 4-byte case *is* correct:
1420 * in 64-bit mode we zero-extend.
1421 */
1422 switch (c->dst.bytes) {
1423 case 1:
1424 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1425 break;
1426 case 2:
1427 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1428 break;
1429 case 4:
1430 *c->dst.ptr = (u32)c->dst.val;
1431 break; /* 64b: zero-ext */
1432 case 8:
1433 *c->dst.ptr = c->dst.val;
1434 break;
1435 }
1436 break;
1437 case OP_MEM:
1438 if (c->lock_prefix)
1439 rc = ops->cmpxchg_emulated(
1440 (unsigned long)c->dst.ptr,
1441 &c->dst.orig_val,
1442 &c->dst.val,
1443 c->dst.bytes,
1444 ctxt->vcpu);
1445 else
1446 rc = ops->write_emulated(
1447 (unsigned long)c->dst.ptr,
1448 &c->dst.val,
1449 c->dst.bytes,
1450 ctxt->vcpu);
1451 if (rc != 0)
1452 return rc;
1453 break;
1454 case OP_NONE:
1455 /* no writeback */
1456 break;
1457 default:
1458 break;
1459 }
1460 return 0;
1461 }
1462
1463 static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
1464 {
1465 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1466 /*
1467 * an sti; sti; sequence only disable interrupts for the first
1468 * instruction. So, if the last instruction, be it emulated or
1469 * not, left the system with the INT_STI flag enabled, it
1470 * means that the last instruction is an sti. We should not
1471 * leave the flag on in this case. The same goes for mov ss
1472 */
1473 if (!(int_shadow & mask))
1474 ctxt->interruptibility = mask;
1475 }
1476
1477 static inline void
1478 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1479 struct kvm_segment *cs, struct kvm_segment *ss)
1480 {
1481 memset(cs, 0, sizeof(struct kvm_segment));
1482 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1483 memset(ss, 0, sizeof(struct kvm_segment));
1484
1485 cs->l = 0; /* will be adjusted later */
1486 cs->base = 0; /* flat segment */
1487 cs->g = 1; /* 4kb granularity */
1488 cs->limit = 0xffffffff; /* 4GB limit */
1489 cs->type = 0x0b; /* Read, Execute, Accessed */
1490 cs->s = 1;
1491 cs->dpl = 0; /* will be adjusted later */
1492 cs->present = 1;
1493 cs->db = 1;
1494
1495 ss->unusable = 0;
1496 ss->base = 0; /* flat segment */
1497 ss->limit = 0xffffffff; /* 4GB limit */
1498 ss->g = 1; /* 4kb granularity */
1499 ss->s = 1;
1500 ss->type = 0x03; /* Read/Write, Accessed */
1501 ss->db = 1; /* 32bit stack segment */
1502 ss->dpl = 0;
1503 ss->present = 1;
1504 }
1505
1506 static int
1507 emulate_syscall(struct x86_emulate_ctxt *ctxt)
1508 {
1509 struct decode_cache *c = &ctxt->decode;
1510 struct kvm_segment cs, ss;
1511 u64 msr_data;
1512
1513 /* syscall is not available in real mode */
1514 if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
1515 || !(ctxt->vcpu->arch.cr0 & X86_CR0_PE))
1516 return -1;
1517
1518 setup_syscalls_segments(ctxt, &cs, &ss);
1519
1520 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1521 msr_data >>= 32;
1522 cs.selector = (u16)(msr_data & 0xfffc);
1523 ss.selector = (u16)(msr_data + 8);
1524
1525 if (is_long_mode(ctxt->vcpu)) {
1526 cs.db = 0;
1527 cs.l = 1;
1528 }
1529 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1530 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1531
1532 c->regs[VCPU_REGS_RCX] = c->eip;
1533 if (is_long_mode(ctxt->vcpu)) {
1534 #ifdef CONFIG_X86_64
1535 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1536
1537 kvm_x86_ops->get_msr(ctxt->vcpu,
1538 ctxt->mode == X86EMUL_MODE_PROT64 ?
1539 MSR_LSTAR : MSR_CSTAR, &msr_data);
1540 c->eip = msr_data;
1541
1542 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1543 ctxt->eflags &= ~(msr_data | EFLG_RF);
1544 #endif
1545 } else {
1546 /* legacy mode */
1547 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1548 c->eip = (u32)msr_data;
1549
1550 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1551 }
1552
1553 return 0;
1554 }
1555
1556 static int
1557 emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1558 {
1559 struct decode_cache *c = &ctxt->decode;
1560 struct kvm_segment cs, ss;
1561 u64 msr_data;
1562
1563 /* inject #UD if LOCK prefix is used */
1564 if (c->lock_prefix)
1565 return -1;
1566
1567 /* inject #GP if in real mode or paging is disabled */
1568 if (ctxt->mode == X86EMUL_MODE_REAL ||
1569 !(ctxt->vcpu->arch.cr0 & X86_CR0_PE)) {
1570 kvm_inject_gp(ctxt->vcpu, 0);
1571 return -1;
1572 }
1573
1574 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1575 * Therefore, we inject an #UD.
1576 */
1577 if (ctxt->mode == X86EMUL_MODE_PROT64)
1578 return -1;
1579
1580 setup_syscalls_segments(ctxt, &cs, &ss);
1581
1582 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1583 switch (ctxt->mode) {
1584 case X86EMUL_MODE_PROT32:
1585 if ((msr_data & 0xfffc) == 0x0) {
1586 kvm_inject_gp(ctxt->vcpu, 0);
1587 return -1;
1588 }
1589 break;
1590 case X86EMUL_MODE_PROT64:
1591 if (msr_data == 0x0) {
1592 kvm_inject_gp(ctxt->vcpu, 0);
1593 return -1;
1594 }
1595 break;
1596 }
1597
1598 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1599 cs.selector = (u16)msr_data;
1600 cs.selector &= ~SELECTOR_RPL_MASK;
1601 ss.selector = cs.selector + 8;
1602 ss.selector &= ~SELECTOR_RPL_MASK;
1603 if (ctxt->mode == X86EMUL_MODE_PROT64
1604 || is_long_mode(ctxt->vcpu)) {
1605 cs.db = 0;
1606 cs.l = 1;
1607 }
1608
1609 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1610 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1611
1612 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1613 c->eip = msr_data;
1614
1615 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1616 c->regs[VCPU_REGS_RSP] = msr_data;
1617
1618 return 0;
1619 }
1620
1621 static int
1622 emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1623 {
1624 struct decode_cache *c = &ctxt->decode;
1625 struct kvm_segment cs, ss;
1626 u64 msr_data;
1627 int usermode;
1628
1629 /* inject #UD if LOCK prefix is used */
1630 if (c->lock_prefix)
1631 return -1;
1632
1633 /* inject #GP if in real mode or paging is disabled */
1634 if (ctxt->mode == X86EMUL_MODE_REAL
1635 || !(ctxt->vcpu->arch.cr0 & X86_CR0_PE)) {
1636 kvm_inject_gp(ctxt->vcpu, 0);
1637 return -1;
1638 }
1639
1640 /* sysexit must be called from CPL 0 */
1641 if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) {
1642 kvm_inject_gp(ctxt->vcpu, 0);
1643 return -1;
1644 }
1645
1646 setup_syscalls_segments(ctxt, &cs, &ss);
1647
1648 if ((c->rex_prefix & 0x8) != 0x0)
1649 usermode = X86EMUL_MODE_PROT64;
1650 else
1651 usermode = X86EMUL_MODE_PROT32;
1652
1653 cs.dpl = 3;
1654 ss.dpl = 3;
1655 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1656 switch (usermode) {
1657 case X86EMUL_MODE_PROT32:
1658 cs.selector = (u16)(msr_data + 16);
1659 if ((msr_data & 0xfffc) == 0x0) {
1660 kvm_inject_gp(ctxt->vcpu, 0);
1661 return -1;
1662 }
1663 ss.selector = (u16)(msr_data + 24);
1664 break;
1665 case X86EMUL_MODE_PROT64:
1666 cs.selector = (u16)(msr_data + 32);
1667 if (msr_data == 0x0) {
1668 kvm_inject_gp(ctxt->vcpu, 0);
1669 return -1;
1670 }
1671 ss.selector = cs.selector + 8;
1672 cs.db = 0;
1673 cs.l = 1;
1674 break;
1675 }
1676 cs.selector |= SELECTOR_RPL_MASK;
1677 ss.selector |= SELECTOR_RPL_MASK;
1678
1679 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1680 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1681
1682 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1683 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1684
1685 return 0;
1686 }
1687
1688 int
1689 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1690 {
1691 unsigned long memop = 0;
1692 u64 msr_data;
1693 unsigned long saved_eip = 0;
1694 struct decode_cache *c = &ctxt->decode;
1695 unsigned int port;
1696 int io_dir_in;
1697 int rc = 0;
1698
1699 ctxt->interruptibility = 0;
1700
1701 /* Shadow copy of register state. Committed on successful emulation.
1702 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1703 * modify them.
1704 */
1705
1706 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1707 saved_eip = c->eip;
1708
1709 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1710 memop = c->modrm_ea;
1711
1712 if (c->rep_prefix && (c->d & String)) {
1713 /* All REP prefixes have the same first termination condition */
1714 if (c->regs[VCPU_REGS_RCX] == 0) {
1715 kvm_rip_write(ctxt->vcpu, c->eip);
1716 goto done;
1717 }
1718 /* The second termination condition only applies for REPE
1719 * and REPNE. Test if the repeat string operation prefix is
1720 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1721 * corresponding termination condition according to:
1722 * - if REPE/REPZ and ZF = 0 then done
1723 * - if REPNE/REPNZ and ZF = 1 then done
1724 */
1725 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1726 (c->b == 0xae) || (c->b == 0xaf)) {
1727 if ((c->rep_prefix == REPE_PREFIX) &&
1728 ((ctxt->eflags & EFLG_ZF) == 0)) {
1729 kvm_rip_write(ctxt->vcpu, c->eip);
1730 goto done;
1731 }
1732 if ((c->rep_prefix == REPNE_PREFIX) &&
1733 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1734 kvm_rip_write(ctxt->vcpu, c->eip);
1735 goto done;
1736 }
1737 }
1738 c->regs[VCPU_REGS_RCX]--;
1739 c->eip = kvm_rip_read(ctxt->vcpu);
1740 }
1741
1742 if (c->src.type == OP_MEM) {
1743 c->src.ptr = (unsigned long *)memop;
1744 c->src.val = 0;
1745 rc = ops->read_emulated((unsigned long)c->src.ptr,
1746 &c->src.val,
1747 c->src.bytes,
1748 ctxt->vcpu);
1749 if (rc != 0)
1750 goto done;
1751 c->src.orig_val = c->src.val;
1752 }
1753
1754 if ((c->d & DstMask) == ImplicitOps)
1755 goto special_insn;
1756
1757
1758 if (c->dst.type == OP_MEM) {
1759 c->dst.ptr = (unsigned long *)memop;
1760 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1761 c->dst.val = 0;
1762 if (c->d & BitOp) {
1763 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1764
1765 c->dst.ptr = (void *)c->dst.ptr +
1766 (c->src.val & mask) / 8;
1767 }
1768 if (!(c->d & Mov) &&
1769 /* optimisation - avoid slow emulated read */
1770 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1771 &c->dst.val,
1772 c->dst.bytes, ctxt->vcpu)) != 0))
1773 goto done;
1774 }
1775 c->dst.orig_val = c->dst.val;
1776
1777 special_insn:
1778
1779 if (c->twobyte)
1780 goto twobyte_insn;
1781
1782 switch (c->b) {
1783 case 0x00 ... 0x05:
1784 add: /* add */
1785 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1786 break;
1787 case 0x06: /* push es */
1788 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1789 break;
1790 case 0x07: /* pop es */
1791 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1792 if (rc != 0)
1793 goto done;
1794 break;
1795 case 0x08 ... 0x0d:
1796 or: /* or */
1797 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1798 break;
1799 case 0x0e: /* push cs */
1800 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1801 break;
1802 case 0x10 ... 0x15:
1803 adc: /* adc */
1804 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1805 break;
1806 case 0x16: /* push ss */
1807 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1808 break;
1809 case 0x17: /* pop ss */
1810 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1811 if (rc != 0)
1812 goto done;
1813 break;
1814 case 0x18 ... 0x1d:
1815 sbb: /* sbb */
1816 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1817 break;
1818 case 0x1e: /* push ds */
1819 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1820 break;
1821 case 0x1f: /* pop ds */
1822 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1823 if (rc != 0)
1824 goto done;
1825 break;
1826 case 0x20 ... 0x25:
1827 and: /* and */
1828 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1829 break;
1830 case 0x28 ... 0x2d:
1831 sub: /* sub */
1832 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1833 break;
1834 case 0x30 ... 0x35:
1835 xor: /* xor */
1836 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1837 break;
1838 case 0x38 ... 0x3d:
1839 cmp: /* cmp */
1840 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1841 break;
1842 case 0x40 ... 0x47: /* inc r16/r32 */
1843 emulate_1op("inc", c->dst, ctxt->eflags);
1844 break;
1845 case 0x48 ... 0x4f: /* dec r16/r32 */
1846 emulate_1op("dec", c->dst, ctxt->eflags);
1847 break;
1848 case 0x50 ... 0x57: /* push reg */
1849 emulate_push(ctxt);
1850 break;
1851 case 0x58 ... 0x5f: /* pop reg */
1852 pop_instruction:
1853 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1854 if (rc != 0)
1855 goto done;
1856 break;
1857 case 0x60: /* pusha */
1858 emulate_pusha(ctxt);
1859 break;
1860 case 0x61: /* popa */
1861 rc = emulate_popa(ctxt, ops);
1862 if (rc != 0)
1863 goto done;
1864 break;
1865 case 0x63: /* movsxd */
1866 if (ctxt->mode != X86EMUL_MODE_PROT64)
1867 goto cannot_emulate;
1868 c->dst.val = (s32) c->src.val;
1869 break;
1870 case 0x68: /* push imm */
1871 case 0x6a: /* push imm8 */
1872 emulate_push(ctxt);
1873 break;
1874 case 0x6c: /* insb */
1875 case 0x6d: /* insw/insd */
1876 if (kvm_emulate_pio_string(ctxt->vcpu,
1877 1,
1878 (c->d & ByteOp) ? 1 : c->op_bytes,
1879 c->rep_prefix ?
1880 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1881 (ctxt->eflags & EFLG_DF),
1882 register_address(c, es_base(ctxt),
1883 c->regs[VCPU_REGS_RDI]),
1884 c->rep_prefix,
1885 c->regs[VCPU_REGS_RDX]) == 0) {
1886 c->eip = saved_eip;
1887 return -1;
1888 }
1889 return 0;
1890 case 0x6e: /* outsb */
1891 case 0x6f: /* outsw/outsd */
1892 if (kvm_emulate_pio_string(ctxt->vcpu,
1893 0,
1894 (c->d & ByteOp) ? 1 : c->op_bytes,
1895 c->rep_prefix ?
1896 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1897 (ctxt->eflags & EFLG_DF),
1898 register_address(c,
1899 seg_override_base(ctxt, c),
1900 c->regs[VCPU_REGS_RSI]),
1901 c->rep_prefix,
1902 c->regs[VCPU_REGS_RDX]) == 0) {
1903 c->eip = saved_eip;
1904 return -1;
1905 }
1906 return 0;
1907 case 0x70 ... 0x7f: /* jcc (short) */
1908 if (test_cc(c->b, ctxt->eflags))
1909 jmp_rel(c, c->src.val);
1910 break;
1911 case 0x80 ... 0x83: /* Grp1 */
1912 switch (c->modrm_reg) {
1913 case 0:
1914 goto add;
1915 case 1:
1916 goto or;
1917 case 2:
1918 goto adc;
1919 case 3:
1920 goto sbb;
1921 case 4:
1922 goto and;
1923 case 5:
1924 goto sub;
1925 case 6:
1926 goto xor;
1927 case 7:
1928 goto cmp;
1929 }
1930 break;
1931 case 0x84 ... 0x85:
1932 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1933 break;
1934 case 0x86 ... 0x87: /* xchg */
1935 xchg:
1936 /* Write back the register source. */
1937 switch (c->dst.bytes) {
1938 case 1:
1939 *(u8 *) c->src.ptr = (u8) c->dst.val;
1940 break;
1941 case 2:
1942 *(u16 *) c->src.ptr = (u16) c->dst.val;
1943 break;
1944 case 4:
1945 *c->src.ptr = (u32) c->dst.val;
1946 break; /* 64b reg: zero-extend */
1947 case 8:
1948 *c->src.ptr = c->dst.val;
1949 break;
1950 }
1951 /*
1952 * Write back the memory destination with implicit LOCK
1953 * prefix.
1954 */
1955 c->dst.val = c->src.val;
1956 c->lock_prefix = 1;
1957 break;
1958 case 0x88 ... 0x8b: /* mov */
1959 goto mov;
1960 case 0x8c: { /* mov r/m, sreg */
1961 struct kvm_segment segreg;
1962
1963 if (c->modrm_reg <= 5)
1964 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1965 else {
1966 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1967 c->modrm);
1968 goto cannot_emulate;
1969 }
1970 c->dst.val = segreg.selector;
1971 break;
1972 }
1973 case 0x8d: /* lea r16/r32, m */
1974 c->dst.val = c->modrm_ea;
1975 break;
1976 case 0x8e: { /* mov seg, r/m16 */
1977 uint16_t sel;
1978 int type_bits;
1979 int err;
1980
1981 sel = c->src.val;
1982 if (c->modrm_reg == VCPU_SREG_SS)
1983 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
1984
1985 if (c->modrm_reg <= 5) {
1986 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1987 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1988 type_bits, c->modrm_reg);
1989 } else {
1990 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1991 c->modrm);
1992 goto cannot_emulate;
1993 }
1994
1995 if (err < 0)
1996 goto cannot_emulate;
1997
1998 c->dst.type = OP_NONE; /* Disable writeback. */
1999 break;
2000 }
2001 case 0x8f: /* pop (sole member of Grp1a) */
2002 rc = emulate_grp1a(ctxt, ops);
2003 if (rc != 0)
2004 goto done;
2005 break;
2006 case 0x90: /* nop / xchg r8,rax */
2007 if (!(c->rex_prefix & 1)) { /* nop */
2008 c->dst.type = OP_NONE;
2009 break;
2010 }
2011 case 0x91 ... 0x97: /* xchg reg,rax */
2012 c->src.type = c->dst.type = OP_REG;
2013 c->src.bytes = c->dst.bytes = c->op_bytes;
2014 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2015 c->src.val = *(c->src.ptr);
2016 goto xchg;
2017 case 0x9c: /* pushf */
2018 c->src.val = (unsigned long) ctxt->eflags;
2019 emulate_push(ctxt);
2020 break;
2021 case 0x9d: /* popf */
2022 c->dst.type = OP_REG;
2023 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2024 c->dst.bytes = c->op_bytes;
2025 goto pop_instruction;
2026 case 0xa0 ... 0xa1: /* mov */
2027 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2028 c->dst.val = c->src.val;
2029 break;
2030 case 0xa2 ... 0xa3: /* mov */
2031 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2032 break;
2033 case 0xa4 ... 0xa5: /* movs */
2034 c->dst.type = OP_MEM;
2035 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2036 c->dst.ptr = (unsigned long *)register_address(c,
2037 es_base(ctxt),
2038 c->regs[VCPU_REGS_RDI]);
2039 if ((rc = ops->read_emulated(register_address(c,
2040 seg_override_base(ctxt, c),
2041 c->regs[VCPU_REGS_RSI]),
2042 &c->dst.val,
2043 c->dst.bytes, ctxt->vcpu)) != 0)
2044 goto done;
2045 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
2046 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2047 : c->dst.bytes);
2048 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
2049 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2050 : c->dst.bytes);
2051 break;
2052 case 0xa6 ... 0xa7: /* cmps */
2053 c->src.type = OP_NONE; /* Disable writeback. */
2054 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2055 c->src.ptr = (unsigned long *)register_address(c,
2056 seg_override_base(ctxt, c),
2057 c->regs[VCPU_REGS_RSI]);
2058 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
2059 &c->src.val,
2060 c->src.bytes,
2061 ctxt->vcpu)) != 0)
2062 goto done;
2063
2064 c->dst.type = OP_NONE; /* Disable writeback. */
2065 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2066 c->dst.ptr = (unsigned long *)register_address(c,
2067 es_base(ctxt),
2068 c->regs[VCPU_REGS_RDI]);
2069 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
2070 &c->dst.val,
2071 c->dst.bytes,
2072 ctxt->vcpu)) != 0)
2073 goto done;
2074
2075 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2076
2077 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2078
2079 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
2080 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2081 : c->src.bytes);
2082 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
2083 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2084 : c->dst.bytes);
2085
2086 break;
2087 case 0xaa ... 0xab: /* stos */
2088 c->dst.type = OP_MEM;
2089 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2090 c->dst.ptr = (unsigned long *)register_address(c,
2091 es_base(ctxt),
2092 c->regs[VCPU_REGS_RDI]);
2093 c->dst.val = c->regs[VCPU_REGS_RAX];
2094 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
2095 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2096 : c->dst.bytes);
2097 break;
2098 case 0xac ... 0xad: /* lods */
2099 c->dst.type = OP_REG;
2100 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2101 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2102 if ((rc = ops->read_emulated(register_address(c,
2103 seg_override_base(ctxt, c),
2104 c->regs[VCPU_REGS_RSI]),
2105 &c->dst.val,
2106 c->dst.bytes,
2107 ctxt->vcpu)) != 0)
2108 goto done;
2109 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
2110 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2111 : c->dst.bytes);
2112 break;
2113 case 0xae ... 0xaf: /* scas */
2114 DPRINTF("Urk! I don't handle SCAS.\n");
2115 goto cannot_emulate;
2116 case 0xb0 ... 0xbf: /* mov r, imm */
2117 goto mov;
2118 case 0xc0 ... 0xc1:
2119 emulate_grp2(ctxt);
2120 break;
2121 case 0xc3: /* ret */
2122 c->dst.type = OP_REG;
2123 c->dst.ptr = &c->eip;
2124 c->dst.bytes = c->op_bytes;
2125 goto pop_instruction;
2126 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2127 mov:
2128 c->dst.val = c->src.val;
2129 break;
2130 case 0xcb: /* ret far */
2131 rc = emulate_ret_far(ctxt, ops);
2132 if (rc)
2133 goto done;
2134 break;
2135 case 0xd0 ... 0xd1: /* Grp2 */
2136 c->src.val = 1;
2137 emulate_grp2(ctxt);
2138 break;
2139 case 0xd2 ... 0xd3: /* Grp2 */
2140 c->src.val = c->regs[VCPU_REGS_RCX];
2141 emulate_grp2(ctxt);
2142 break;
2143 case 0xe4: /* inb */
2144 case 0xe5: /* in */
2145 port = c->src.val;
2146 io_dir_in = 1;
2147 goto do_io;
2148 case 0xe6: /* outb */
2149 case 0xe7: /* out */
2150 port = c->src.val;
2151 io_dir_in = 0;
2152 goto do_io;
2153 case 0xe8: /* call (near) */ {
2154 long int rel = c->src.val;
2155 c->src.val = (unsigned long) c->eip;
2156 jmp_rel(c, rel);
2157 emulate_push(ctxt);
2158 break;
2159 }
2160 case 0xe9: /* jmp rel */
2161 goto jmp;
2162 case 0xea: /* jmp far */
2163 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
2164 VCPU_SREG_CS) < 0) {
2165 DPRINTF("jmp far: Failed to load CS descriptor\n");
2166 goto cannot_emulate;
2167 }
2168
2169 c->eip = c->src.val;
2170 break;
2171 case 0xeb:
2172 jmp: /* jmp rel short */
2173 jmp_rel(c, c->src.val);
2174 c->dst.type = OP_NONE; /* Disable writeback. */
2175 break;
2176 case 0xec: /* in al,dx */
2177 case 0xed: /* in (e/r)ax,dx */
2178 port = c->regs[VCPU_REGS_RDX];
2179 io_dir_in = 1;
2180 goto do_io;
2181 case 0xee: /* out al,dx */
2182 case 0xef: /* out (e/r)ax,dx */
2183 port = c->regs[VCPU_REGS_RDX];
2184 io_dir_in = 0;
2185 do_io: if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
2186 (c->d & ByteOp) ? 1 : c->op_bytes,
2187 port) != 0) {
2188 c->eip = saved_eip;
2189 goto cannot_emulate;
2190 }
2191 break;
2192 case 0xf4: /* hlt */
2193 ctxt->vcpu->arch.halt_request = 1;
2194 break;
2195 case 0xf5: /* cmc */
2196 /* complement carry flag from eflags reg */
2197 ctxt->eflags ^= EFLG_CF;
2198 c->dst.type = OP_NONE; /* Disable writeback. */
2199 break;
2200 case 0xf6 ... 0xf7: /* Grp3 */
2201 rc = emulate_grp3(ctxt, ops);
2202 if (rc != 0)
2203 goto done;
2204 break;
2205 case 0xf8: /* clc */
2206 ctxt->eflags &= ~EFLG_CF;
2207 c->dst.type = OP_NONE; /* Disable writeback. */
2208 break;
2209 case 0xfa: /* cli */
2210 ctxt->eflags &= ~X86_EFLAGS_IF;
2211 c->dst.type = OP_NONE; /* Disable writeback. */
2212 break;
2213 case 0xfb: /* sti */
2214 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
2215 ctxt->eflags |= X86_EFLAGS_IF;
2216 c->dst.type = OP_NONE; /* Disable writeback. */
2217 break;
2218 case 0xfc: /* cld */
2219 ctxt->eflags &= ~EFLG_DF;
2220 c->dst.type = OP_NONE; /* Disable writeback. */
2221 break;
2222 case 0xfd: /* std */
2223 ctxt->eflags |= EFLG_DF;
2224 c->dst.type = OP_NONE; /* Disable writeback. */
2225 break;
2226 case 0xfe ... 0xff: /* Grp4/Grp5 */
2227 rc = emulate_grp45(ctxt, ops);
2228 if (rc != 0)
2229 goto done;
2230 break;
2231 }
2232
2233 writeback:
2234 rc = writeback(ctxt, ops);
2235 if (rc != 0)
2236 goto done;
2237
2238 /* Commit shadow register state. */
2239 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2240 kvm_rip_write(ctxt->vcpu, c->eip);
2241
2242 done:
2243 if (rc == X86EMUL_UNHANDLEABLE) {
2244 c->eip = saved_eip;
2245 return -1;
2246 }
2247 return 0;
2248
2249 twobyte_insn:
2250 switch (c->b) {
2251 case 0x01: /* lgdt, lidt, lmsw */
2252 switch (c->modrm_reg) {
2253 u16 size;
2254 unsigned long address;
2255
2256 case 0: /* vmcall */
2257 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2258 goto cannot_emulate;
2259
2260 rc = kvm_fix_hypercall(ctxt->vcpu);
2261 if (rc)
2262 goto done;
2263
2264 /* Let the processor re-execute the fixed hypercall */
2265 c->eip = kvm_rip_read(ctxt->vcpu);
2266 /* Disable writeback. */
2267 c->dst.type = OP_NONE;
2268 break;
2269 case 2: /* lgdt */
2270 rc = read_descriptor(ctxt, ops, c->src.ptr,
2271 &size, &address, c->op_bytes);
2272 if (rc)
2273 goto done;
2274 realmode_lgdt(ctxt->vcpu, size, address);
2275 /* Disable writeback. */
2276 c->dst.type = OP_NONE;
2277 break;
2278 case 3: /* lidt/vmmcall */
2279 if (c->modrm_mod == 3) {
2280 switch (c->modrm_rm) {
2281 case 1:
2282 rc = kvm_fix_hypercall(ctxt->vcpu);
2283 if (rc)
2284 goto done;
2285 break;
2286 default:
2287 goto cannot_emulate;
2288 }
2289 } else {
2290 rc = read_descriptor(ctxt, ops, c->src.ptr,
2291 &size, &address,
2292 c->op_bytes);
2293 if (rc)
2294 goto done;
2295 realmode_lidt(ctxt->vcpu, size, address);
2296 }
2297 /* Disable writeback. */
2298 c->dst.type = OP_NONE;
2299 break;
2300 case 4: /* smsw */
2301 c->dst.bytes = 2;
2302 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
2303 break;
2304 case 6: /* lmsw */
2305 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2306 &ctxt->eflags);
2307 c->dst.type = OP_NONE;
2308 break;
2309 case 7: /* invlpg*/
2310 emulate_invlpg(ctxt->vcpu, memop);
2311 /* Disable writeback. */
2312 c->dst.type = OP_NONE;
2313 break;
2314 default:
2315 goto cannot_emulate;
2316 }
2317 break;
2318 case 0x05: /* syscall */
2319 if (emulate_syscall(ctxt) == -1)
2320 goto cannot_emulate;
2321 else
2322 goto writeback;
2323 break;
2324 case 0x06:
2325 emulate_clts(ctxt->vcpu);
2326 c->dst.type = OP_NONE;
2327 break;
2328 case 0x08: /* invd */
2329 case 0x09: /* wbinvd */
2330 case 0x0d: /* GrpP (prefetch) */
2331 case 0x18: /* Grp16 (prefetch/nop) */
2332 c->dst.type = OP_NONE;
2333 break;
2334 case 0x20: /* mov cr, reg */
2335 if (c->modrm_mod != 3)
2336 goto cannot_emulate;
2337 c->regs[c->modrm_rm] =
2338 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2339 c->dst.type = OP_NONE; /* no writeback */
2340 break;
2341 case 0x21: /* mov from dr to reg */
2342 if (c->modrm_mod != 3)
2343 goto cannot_emulate;
2344 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
2345 if (rc)
2346 goto cannot_emulate;
2347 c->dst.type = OP_NONE; /* no writeback */
2348 break;
2349 case 0x22: /* mov reg, cr */
2350 if (c->modrm_mod != 3)
2351 goto cannot_emulate;
2352 realmode_set_cr(ctxt->vcpu,
2353 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2354 c->dst.type = OP_NONE;
2355 break;
2356 case 0x23: /* mov from reg to dr */
2357 if (c->modrm_mod != 3)
2358 goto cannot_emulate;
2359 rc = emulator_set_dr(ctxt, c->modrm_reg,
2360 c->regs[c->modrm_rm]);
2361 if (rc)
2362 goto cannot_emulate;
2363 c->dst.type = OP_NONE; /* no writeback */
2364 break;
2365 case 0x30:
2366 /* wrmsr */
2367 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2368 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2369 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2370 if (rc) {
2371 kvm_inject_gp(ctxt->vcpu, 0);
2372 c->eip = kvm_rip_read(ctxt->vcpu);
2373 }
2374 rc = X86EMUL_CONTINUE;
2375 c->dst.type = OP_NONE;
2376 break;
2377 case 0x32:
2378 /* rdmsr */
2379 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2380 if (rc) {
2381 kvm_inject_gp(ctxt->vcpu, 0);
2382 c->eip = kvm_rip_read(ctxt->vcpu);
2383 } else {
2384 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2385 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2386 }
2387 rc = X86EMUL_CONTINUE;
2388 c->dst.type = OP_NONE;
2389 break;
2390 case 0x34: /* sysenter */
2391 if (emulate_sysenter(ctxt) == -1)
2392 goto cannot_emulate;
2393 else
2394 goto writeback;
2395 break;
2396 case 0x35: /* sysexit */
2397 if (emulate_sysexit(ctxt) == -1)
2398 goto cannot_emulate;
2399 else
2400 goto writeback;
2401 break;
2402 case 0x40 ... 0x4f: /* cmov */
2403 c->dst.val = c->dst.orig_val = c->src.val;
2404 if (!test_cc(c->b, ctxt->eflags))
2405 c->dst.type = OP_NONE; /* no writeback */
2406 break;
2407 case 0x80 ... 0x8f: /* jnz rel, etc*/
2408 if (test_cc(c->b, ctxt->eflags))
2409 jmp_rel(c, c->src.val);
2410 c->dst.type = OP_NONE;
2411 break;
2412 case 0xa0: /* push fs */
2413 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2414 break;
2415 case 0xa1: /* pop fs */
2416 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2417 if (rc != 0)
2418 goto done;
2419 break;
2420 case 0xa3:
2421 bt: /* bt */
2422 c->dst.type = OP_NONE;
2423 /* only subword offset */
2424 c->src.val &= (c->dst.bytes << 3) - 1;
2425 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
2426 break;
2427 case 0xa4: /* shld imm8, r, r/m */
2428 case 0xa5: /* shld cl, r, r/m */
2429 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2430 break;
2431 case 0xa8: /* push gs */
2432 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2433 break;
2434 case 0xa9: /* pop gs */
2435 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2436 if (rc != 0)
2437 goto done;
2438 break;
2439 case 0xab:
2440 bts: /* bts */
2441 /* only subword offset */
2442 c->src.val &= (c->dst.bytes << 3) - 1;
2443 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
2444 break;
2445 case 0xac: /* shrd imm8, r, r/m */
2446 case 0xad: /* shrd cl, r, r/m */
2447 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2448 break;
2449 case 0xae: /* clflush */
2450 break;
2451 case 0xb0 ... 0xb1: /* cmpxchg */
2452 /*
2453 * Save real source value, then compare EAX against
2454 * destination.
2455 */
2456 c->src.orig_val = c->src.val;
2457 c->src.val = c->regs[VCPU_REGS_RAX];
2458 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2459 if (ctxt->eflags & EFLG_ZF) {
2460 /* Success: write back to memory. */
2461 c->dst.val = c->src.orig_val;
2462 } else {
2463 /* Failure: write the value we saw to EAX. */
2464 c->dst.type = OP_REG;
2465 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2466 }
2467 break;
2468 case 0xb3:
2469 btr: /* btr */
2470 /* only subword offset */
2471 c->src.val &= (c->dst.bytes << 3) - 1;
2472 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
2473 break;
2474 case 0xb6 ... 0xb7: /* movzx */
2475 c->dst.bytes = c->op_bytes;
2476 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2477 : (u16) c->src.val;
2478 break;
2479 case 0xba: /* Grp8 */
2480 switch (c->modrm_reg & 3) {
2481 case 0:
2482 goto bt;
2483 case 1:
2484 goto bts;
2485 case 2:
2486 goto btr;
2487 case 3:
2488 goto btc;
2489 }
2490 break;
2491 case 0xbb:
2492 btc: /* btc */
2493 /* only subword offset */
2494 c->src.val &= (c->dst.bytes << 3) - 1;
2495 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
2496 break;
2497 case 0xbe ... 0xbf: /* movsx */
2498 c->dst.bytes = c->op_bytes;
2499 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2500 (s16) c->src.val;
2501 break;
2502 case 0xc3: /* movnti */
2503 c->dst.bytes = c->op_bytes;
2504 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2505 (u64) c->src.val;
2506 break;
2507 case 0xc7: /* Grp9 (cmpxchg8b) */
2508 rc = emulate_grp9(ctxt, ops, memop);
2509 if (rc != 0)
2510 goto done;
2511 c->dst.type = OP_NONE;
2512 break;
2513 }
2514 goto writeback;
2515
2516 cannot_emulate:
2517 DPRINTF("Cannot emulate %02x\n", c->b);
2518 c->eip = saved_eip;
2519 return -1;
2520 }
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