2 * @file op_model_ppro.h
3 * Family 6 perfmon and architectural perfmon MSR operations
5 * @remark Copyright 2002 OProfile authors
6 * @remark Copyright 2008 Intel Corporation
7 * @remark Read the file COPYING
10 * @author Philippe Elie
11 * @author Graydon Hoare
13 * @author Robert Richter <robert.richter@amd.com>
16 #include <linux/oprofile.h>
17 #include <linux/slab.h>
18 #include <asm/ptrace.h>
23 #include "op_x86_model.h"
24 #include "op_counter.h"
26 static int num_counters
= 2;
27 static int counter_width
= 32;
29 #define MSR_PPRO_EVENTSEL_RESERVED ((0xFFFFFFFFULL<<32)|(1ULL<<21))
31 static u64
*reset_value
;
33 static void ppro_fill_in_addresses(struct op_msrs
* const msrs
)
37 for (i
= 0; i
< num_counters
; i
++) {
38 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0
+ i
))
39 msrs
->counters
[i
].addr
= MSR_P6_PERFCTR0
+ i
;
41 msrs
->counters
[i
].addr
= 0;
44 for (i
= 0; i
< num_counters
; i
++) {
45 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0
+ i
))
46 msrs
->controls
[i
].addr
= MSR_P6_EVNTSEL0
+ i
;
48 msrs
->controls
[i
].addr
= 0;
53 static void ppro_setup_ctrs(struct op_x86_model_spec
const *model
,
54 struct op_msrs
const * const msrs
)
60 reset_value
= kmalloc(sizeof(reset_value
[0]) * num_counters
,
66 if (cpu_has_arch_perfmon
) {
67 union cpuid10_eax eax
;
68 eax
.full
= cpuid_eax(0xa);
71 * For Core2 (family 6, model 15), don't reset the
74 if (!(eax
.split
.version_id
== 0 &&
75 current_cpu_data
.x86
== 6 &&
76 current_cpu_data
.x86_model
== 15)) {
78 if (counter_width
< eax
.split
.bit_width
)
79 counter_width
= eax
.split
.bit_width
;
83 /* clear all counters */
84 for (i
= 0; i
< num_counters
; ++i
) {
85 if (unlikely(!msrs
->controls
[i
].addr
))
87 rdmsrl(msrs
->controls
[i
].addr
, val
);
88 val
&= model
->reserved
;
89 wrmsrl(msrs
->controls
[i
].addr
, val
);
92 /* avoid a false detection of ctr overflows in NMI handler */
93 for (i
= 0; i
< num_counters
; ++i
) {
94 if (unlikely(!msrs
->counters
[i
].addr
))
96 wrmsrl(msrs
->counters
[i
].addr
, -1LL);
99 /* enable active counters */
100 for (i
= 0; i
< num_counters
; ++i
) {
101 if (counter_config
[i
].enabled
&& msrs
->counters
[i
].addr
) {
102 reset_value
[i
] = counter_config
[i
].count
;
103 wrmsrl(msrs
->counters
[i
].addr
, -reset_value
[i
]);
104 rdmsrl(msrs
->controls
[i
].addr
, val
);
105 val
&= model
->reserved
;
106 val
|= op_x86_get_ctrl(model
, &counter_config
[i
]);
107 wrmsrl(msrs
->controls
[i
].addr
, val
);
115 static int ppro_check_ctrs(struct pt_regs
* const regs
,
116 struct op_msrs
const * const msrs
)
122 * This can happen if perf counters are in use when
123 * we steal the die notifier NMI.
125 if (unlikely(!reset_value
))
128 for (i
= 0; i
< num_counters
; ++i
) {
131 rdmsrl(msrs
->counters
[i
].addr
, val
);
132 if (val
& (1ULL << (counter_width
- 1)))
134 oprofile_add_sample(regs
, i
);
135 wrmsrl(msrs
->counters
[i
].addr
, -reset_value
[i
]);
139 /* Only P6 based Pentium M need to re-unmask the apic vector but it
140 * doesn't hurt other P6 variant */
141 apic_write(APIC_LVTPC
, apic_read(APIC_LVTPC
) & ~APIC_LVT_MASKED
);
143 /* We can't work out if we really handled an interrupt. We
144 * might have caught a *second* counter just after overflowing
145 * the interrupt for this counter then arrives
146 * and we don't find a counter that's overflowed, so we
147 * would return 0 and get dazed + confused. Instead we always
148 * assume we found an overflow. This sucks.
154 static void ppro_start(struct op_msrs
const * const msrs
)
161 for (i
= 0; i
< num_counters
; ++i
) {
162 if (reset_value
[i
]) {
163 rdmsrl(msrs
->controls
[i
].addr
, val
);
164 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
165 wrmsrl(msrs
->controls
[i
].addr
, val
);
171 static void ppro_stop(struct op_msrs
const * const msrs
)
178 for (i
= 0; i
< num_counters
; ++i
) {
181 rdmsrl(msrs
->controls
[i
].addr
, val
);
182 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
183 wrmsrl(msrs
->controls
[i
].addr
, val
);
187 static void ppro_shutdown(struct op_msrs
const * const msrs
)
191 for (i
= 0; i
< num_counters
; ++i
) {
192 if (msrs
->counters
[i
].addr
)
193 release_perfctr_nmi(MSR_P6_PERFCTR0
+ i
);
195 for (i
= 0; i
< num_counters
; ++i
) {
196 if (msrs
->controls
[i
].addr
)
197 release_evntsel_nmi(MSR_P6_EVNTSEL0
+ i
);
206 struct op_x86_model_spec op_ppro_spec
= {
209 .reserved
= MSR_PPRO_EVENTSEL_RESERVED
,
210 .fill_in_addresses
= &ppro_fill_in_addresses
,
211 .setup_ctrs
= &ppro_setup_ctrs
,
212 .check_ctrs
= &ppro_check_ctrs
,
213 .start
= &ppro_start
,
215 .shutdown
= &ppro_shutdown
219 * Architectural performance monitoring.
221 * Newer Intel CPUs (Core1+) have support for architectural
222 * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
223 * The advantage of this is that it can be done without knowing about
227 static void arch_perfmon_setup_counters(void)
229 union cpuid10_eax eax
;
231 eax
.full
= cpuid_eax(0xa);
233 /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
234 if (eax
.split
.version_id
== 0 && current_cpu_data
.x86
== 6 &&
235 current_cpu_data
.x86_model
== 15) {
236 eax
.split
.version_id
= 2;
237 eax
.split
.num_events
= 2;
238 eax
.split
.bit_width
= 40;
241 num_counters
= eax
.split
.num_events
;
243 op_arch_perfmon_spec
.num_counters
= num_counters
;
244 op_arch_perfmon_spec
.num_controls
= num_counters
;
247 static int arch_perfmon_init(struct oprofile_operations
*ignore
)
249 arch_perfmon_setup_counters();
253 struct op_x86_model_spec op_arch_perfmon_spec
= {
254 .reserved
= MSR_PPRO_EVENTSEL_RESERVED
,
255 .init
= &arch_perfmon_init
,
256 /* num_counters/num_controls filled in at runtime */
257 .fill_in_addresses
= &ppro_fill_in_addresses
,
258 /* user space does the cpuid check for available events */
259 .setup_ctrs
= &ppro_setup_ctrs
,
260 .check_ctrs
= &ppro_check_ctrs
,
261 .start
= &ppro_start
,
263 .shutdown
= &ppro_shutdown