arch/xtensa/include/asm/regs.h

   1 /*
   2  * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2.1 of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it would be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  11  *
  12  * Further, this software is distributed without any warranty that it is
  13  * free of the rightful claim of any third person regarding infringement
  14  * or the like.  Any license provided herein, whether implied or
  15  * otherwise, applies only to this software file.  Patent licenses, if
  16  * any, provided herein do not apply to combinations of this program with
  17  * other software, or any other product whatsoever.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this program; if not, write the Free Software
  21  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
  22  * USA.
  23  */
  24
  25 #ifndef _XTENSA_REGS_H
  26 #define _XTENSA_REGS_H
  27
  28 /*  Special registers.  */
  29
  30 #define LBEG            0
  31 #define LEND            1
  32 #define LCOUNT          2
  33 #define SAR             3
  34 #define BR              4
  35 #define SCOMPARE1       12
  36 #define ACCHI           16
  37 #define ACCLO           17
  38 #define MR              32
  39 #define WINDOWBASE      72
  40 #define WINDOWSTART     73
  41 #define PTEVADDR        83
  42 #define RASID           90
  43 #define ITLBCFG         91
  44 #define DTLBCFG         92
  45 #define IBREAKENABLE    96
  46 #define DDR             104
  47 #define IBREAKA         128
  48 #define DBREAKA         144
  49 #define DBREAKC         160
  50 #define EPC             176
  51 #define EPC_1           177
  52 #define DEPC            192
  53 #define EPS             192
  54 #define EPS_1           193
  55 #define EXCSAVE         208
  56 #define EXCSAVE_1       209
  57 #define INTERRUPT       226
  58 #define INTENABLE       228
  59 #define PS              230
  60 #define THREADPTR       231
  61 #define EXCCAUSE        232
  62 #define DEBUGCAUSE      233
  63 #define CCOUNT          234
  64 #define PRID            235
  65 #define ICOUNT          236
  66 #define ICOUNTLEVEL     237
  67 #define EXCVADDR        238
  68 #define CCOMPARE        240
  69 #define MISC            244
  70
  71 /*  Special names for read-only and write-only interrupt registers.  */
  72
  73 #define INTREAD         226
  74 #define INTSET          226
  75 #define INTCLEAR        227
  76
  77 /*  EXCCAUSE register fields  */
  78
  79 #define EXCCAUSE_EXCCAUSE_SHIFT 0
  80 #define EXCCAUSE_EXCCAUSE_MASK  0x3F
  81
  82 #define EXCCAUSE_ILLEGAL_INSTRUCTION            0
  83 #define EXCCAUSE_SYSTEM_CALL                    1
  84 #define EXCCAUSE_INSTRUCTION_FETCH_ERROR        2
  85 #define EXCCAUSE_LOAD_STORE_ERROR               3
  86 #define EXCCAUSE_LEVEL1_INTERRUPT               4
  87 #define EXCCAUSE_ALLOCA                         5
  88 #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO         6
  89 #define EXCCAUSE_SPECULATION                    7
  90 #define EXCCAUSE_PRIVILEGED                     8
  91 #define EXCCAUSE_UNALIGNED                      9
  92 #define EXCCAUSE_ITLB_MISS                      16
  93 #define EXCCAUSE_ITLB_MULTIHIT                  17
  94 #define EXCCAUSE_ITLB_PRIVILEGE                 18
  95 #define EXCCAUSE_ITLB_SIZE_RESTRICTION          19
  96 #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE          20
  97 #define EXCCAUSE_DTLB_MISS                      24
  98 #define EXCCAUSE_DTLB_MULTIHIT                  25
  99 #define EXCCAUSE_DTLB_PRIVILEGE                 26
 100 #define EXCCAUSE_DTLB_SIZE_RESTRICTION          27
 101 #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE           28
 102 #define EXCCAUSE_STORE_CACHE_ATTRIBUTE          29
 103 #define EXCCAUSE_COPROCESSOR0_DISABLED          32
 104 #define EXCCAUSE_COPROCESSOR1_DISABLED          33
 105 #define EXCCAUSE_COPROCESSOR2_DISABLED          34
 106 #define EXCCAUSE_COPROCESSOR3_DISABLED          35
 107 #define EXCCAUSE_COPROCESSOR4_DISABLED          36
 108 #define EXCCAUSE_COPROCESSOR5_DISABLED          37
 109 #define EXCCAUSE_COPROCESSOR6_DISABLED          38
 110 #define EXCCAUSE_COPROCESSOR7_DISABLED          39
 111
 112 /*  PS register fields.  */
 113
 114 #define PS_WOE_BIT              18
 115 #define PS_CALLINC_SHIFT        16
 116 #define PS_CALLINC_MASK         0x00030000
 117 #define PS_OWB_SHIFT            8
 118 #define PS_OWB_MASK             0x00000F00
 119 #define PS_RING_SHIFT           6
 120 #define PS_RING_MASK            0x000000C0
 121 #define PS_UM_BIT               5
 122 #define PS_EXCM_BIT             4
 123 #define PS_INTLEVEL_SHIFT       0
 124 #define PS_INTLEVEL_MASK        0x0000000F
 125
 126 /*  DBREAKCn register fields.  */
 127
 128 #define DBREAKC_MASK_BIT                0
 129 #define DBREAKC_MASK_MASK               0x0000003F
 130 #define DBREAKC_LOAD_BIT                30
 131 #define DBREAKC_LOAD_MASK               0x40000000
 132 #define DBREAKC_STOR_BIT                31
 133 #define DBREAKC_STOR_MASK               0x80000000
 134
 135 /*  DEBUGCAUSE register fields.  */
 136
 137 #define DEBUGCAUSE_DEBUGINT_BIT         5       /* External debug interrupt */
 138 #define DEBUGCAUSE_BREAKN_BIT           4       /* BREAK.N instruction */
 139 #define DEBUGCAUSE_BREAK_BIT            3       /* BREAK instruction */
 140 #define DEBUGCAUSE_DBREAK_BIT           2       /* DBREAK match */
 141 #define DEBUGCAUSE_IBREAK_BIT           1       /* IBREAK match */
 142 #define DEBUGCAUSE_ICOUNT_BIT           0       /* ICOUNT would incr. to zero */
 143
 144 #endif /* _XTENSA_SPECREG_H */
 145