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Make sure x86 ATOMIC_CAS doesn't overwrite its own operands.
[mono-debugger.git] / mono / mini / mini-amd64.c
blobc3a918fa7f2138dcfbb8124956e1915458c18a3b
1 /*
2 * mini-amd64.c: AMD64 backend for the Mono code generator
3 *
4 * Based on mini-x86.c.
5 *
6 * Authors:
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
9 * Patrik Torstensson
10 * Zoltan Varga (vargaz@gmail.com)
11 *
12 * (C) 2003 Ximian, Inc.
13 */
14 #include "mini.h"
15 #include <string.h>
16 #include <math.h>
17 #ifdef HAVE_UNISTD_H
18 #include <unistd.h>
19 #endif
20
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/utils/mono-math.h>
27
28 #include "trace.h"
29 #include "ir-emit.h"
30 #include "mini-amd64.h"
31 #include "cpu-amd64.h"
32
33 /*
34 * Can't define this in mini-amd64.h cause that would turn on the generic code in
35 * method-to-ir.c.
36 */
37 #define MONO_ARCH_IMT_REG AMD64_R11
38
39 static gint lmf_tls_offset = -1;
40 static gint lmf_addr_tls_offset = -1;
41 static gint appdomain_tls_offset = -1;
42 static gint thread_tls_offset = -1;
43
44 #ifdef MONO_XEN_OPT
45 static gboolean optimize_for_xen = TRUE;
46 #else
47 #define optimize_for_xen 0
48 #endif
49
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
51
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
53
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
55
56 #ifdef PLATFORM_WIN32
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
59 #else
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
61 #endif
62
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
66 static CRITICAL_SECTION mini_arch_mutex;
67
68 MonoBreakpointInfo
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
70
71 #ifdef PLATFORM_WIN32
72 /* On Win64 always reserve first 32 bytes for first four arguments */
73 #define ARGS_OFFSET 48
74 #else
75 #define ARGS_OFFSET 16
76 #endif
77 #define GP_SCRATCH_REG AMD64_R11
78
79 /*
80 * AMD64 register usage:
81 * - callee saved registers are used for global register allocation
82 * - %r11 is used for materializing 64 bit constants in opcodes
83 * - the rest is used for local allocation
84 */
85
86 /*
87 * Floating point comparison results:
88 * ZF PF CF
89 * A > B 0 0 0
90 * A < B 0 0 1
91 * A = B 1 0 0
92 * A > B 0 0 0
93 * UNORDERED 1 1 1
94 */
95
96 const char*
97 mono_arch_regname (int reg)
98 {
99 switch (reg) {
100 case AMD64_RAX: return "%rax";
101 case AMD64_RBX: return "%rbx";
102 case AMD64_RCX: return "%rcx";
103 case AMD64_RDX: return "%rdx";
104 case AMD64_RSP: return "%rsp";
105 case AMD64_RBP: return "%rbp";
106 case AMD64_RDI: return "%rdi";
107 case AMD64_RSI: return "%rsi";
108 case AMD64_R8: return "%r8";
109 case AMD64_R9: return "%r9";
110 case AMD64_R10: return "%r10";
111 case AMD64_R11: return "%r11";
112 case AMD64_R12: return "%r12";
113 case AMD64_R13: return "%r13";
114 case AMD64_R14: return "%r14";
115 case AMD64_R15: return "%r15";
116 }
117 return "unknown";
118 }
119
120 static const char * xmmregs [] = {
121 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
122 "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
123 };
124
125 const char*
126 mono_arch_fregname (int reg)
127 {
128 if (reg < AMD64_XMM_NREG)
129 return xmmregs [reg];
130 else
131 return "unknown";
132 }
133
134 G_GNUC_UNUSED static void
135 break_count (void)
136 {
137 }
138
139 G_GNUC_UNUSED static gboolean
140 debug_count (void)
141 {
142 static int count = 0;
143 count ++;
144
145 if (!getenv ("COUNT"))
146 return TRUE;
147
148 if (count == atoi (getenv ("COUNT"))) {
149 break_count ();
150 }
151
152 if (count > atoi (getenv ("COUNT"))) {
153 return FALSE;
154 }
155
156 return TRUE;
157 }
158
159 static gboolean
160 debug_omit_fp (void)
161 {
162 #if 0
163 return debug_count ();
164 #else
165 return TRUE;
166 #endif
167 }
168
169 static inline gboolean
170 amd64_is_near_call (guint8 *code)
171 {
172 /* Skip REX */
173 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
174 code += 1;
175
176 return code [0] == 0xe8;
177 }
178
179 static inline void
180 amd64_patch (unsigned char* code, gpointer target)
181 {
182 guint8 rex = 0;
183
184 /* Skip REX */
185 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
186 rex = code [0];
187 code += 1;
188 }
189
190 if ((code [0] & 0xf8) == 0xb8) {
191 /* amd64_set_reg_template */
192 *(guint64*)(code + 1) = (guint64)target;
193 }
194 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
195 /* mov 0(%rip), %dreg */
196 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
197 }
198 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
199 /* call *<OFFSET>(%rip) */
200 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
201 }
202 else if ((code [0] == 0xe8)) {
203 /* call <DISP> */
204 gint64 disp = (guint8*)target - (guint8*)code;
205 g_assert (amd64_is_imm32 (disp));
206 x86_patch (code, (unsigned char*)target);
207 }
208 else
209 x86_patch (code, (unsigned char*)target);
210 }
211
212 void
213 mono_amd64_patch (unsigned char* code, gpointer target)
214 {
215 amd64_patch (code, target);
216 }
217
218 typedef enum {
219 ArgInIReg,
220 ArgInFloatSSEReg,
221 ArgInDoubleSSEReg,
222 ArgOnStack,
223 ArgValuetypeInReg,
224 ArgValuetypeAddrInIReg,
225 ArgNone /* only in pair_storage */
226 } ArgStorage;
227
228 typedef struct {
229 gint16 offset;
230 gint8 reg;
231 ArgStorage storage;
232
233 /* Only if storage == ArgValuetypeInReg */
234 ArgStorage pair_storage [2];
235 gint8 pair_regs [2];
236 } ArgInfo;
237
238 typedef struct {
239 int nargs;
240 guint32 stack_usage;
241 guint32 reg_usage;
242 guint32 freg_usage;
243 gboolean need_stack_align;
244 ArgInfo ret;
245 ArgInfo sig_cookie;
246 ArgInfo args [1];
247 } CallInfo;
248
249 #define DEBUG(a) if (cfg->verbose_level > 1) a
250
251 #ifdef PLATFORM_WIN32
252 #define PARAM_REGS 4
253
254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
255
256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
257 #else
258 #define PARAM_REGS 6
259
260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
261
262 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
263 #endif
264
265 static void inline
266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
267 {
268 ainfo->offset = *stack_size;
269
270 if (*gr >= PARAM_REGS) {
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer);
273 }
274 else {
275 ainfo->storage = ArgInIReg;
276 ainfo->reg = param_regs [*gr];
277 (*gr) ++;
278 }
279 }
280
281 #ifdef PLATFORM_WIN32
282 #define FLOAT_PARAM_REGS 4
283 #else
284 #define FLOAT_PARAM_REGS 8
285 #endif
286
287 static void inline
288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
289 {
290 ainfo->offset = *stack_size;
291
292 if (*gr >= FLOAT_PARAM_REGS) {
293 ainfo->storage = ArgOnStack;
294 (*stack_size) += sizeof (gpointer);
295 }
296 else {
297 /* A double register */
298 if (is_double)
299 ainfo->storage = ArgInDoubleSSEReg;
300 else
301 ainfo->storage = ArgInFloatSSEReg;
302 ainfo->reg = *gr;
303 (*gr) += 1;
304 }
305 }
306
307 typedef enum ArgumentClass {
308 ARG_CLASS_NO_CLASS,
309 ARG_CLASS_MEMORY,
310 ARG_CLASS_INTEGER,
311 ARG_CLASS_SSE
312 } ArgumentClass;
313
314 static ArgumentClass
315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
316 {
317 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
318 MonoType *ptype;
319
320 ptype = mini_type_get_underlying_type (NULL, type);
321 switch (ptype->type) {
322 case MONO_TYPE_BOOLEAN:
323 case MONO_TYPE_CHAR:
324 case MONO_TYPE_I1:
325 case MONO_TYPE_U1:
326 case MONO_TYPE_I2:
327 case MONO_TYPE_U2:
328 case MONO_TYPE_I4:
329 case MONO_TYPE_U4:
330 case MONO_TYPE_I:
331 case MONO_TYPE_U:
332 case MONO_TYPE_STRING:
333 case MONO_TYPE_OBJECT:
334 case MONO_TYPE_CLASS:
335 case MONO_TYPE_SZARRAY:
336 case MONO_TYPE_PTR:
337 case MONO_TYPE_FNPTR:
338 case MONO_TYPE_ARRAY:
339 case MONO_TYPE_I8:
340 case MONO_TYPE_U8:
341 class2 = ARG_CLASS_INTEGER;
342 break;
343 case MONO_TYPE_R4:
344 case MONO_TYPE_R8:
345 #ifdef PLATFORM_WIN32
346 class2 = ARG_CLASS_INTEGER;
347 #else
348 class2 = ARG_CLASS_SSE;
349 #endif
350 break;
351
352 case MONO_TYPE_TYPEDBYREF:
353 g_assert_not_reached ();
354
355 case MONO_TYPE_GENERICINST:
356 if (!mono_type_generic_inst_is_valuetype (ptype)) {
357 class2 = ARG_CLASS_INTEGER;
358 break;
359 }
360 /* fall through */
361 case MONO_TYPE_VALUETYPE: {
362 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
363 int i;
364
365 for (i = 0; i < info->num_fields; ++i) {
366 class2 = class1;
367 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
368 }
369 break;
370 }
371 default:
372 g_assert_not_reached ();
373 }
374
375 /* Merge */
376 if (class1 == class2)
377 ;
378 else if (class1 == ARG_CLASS_NO_CLASS)
379 class1 = class2;
380 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
381 class1 = ARG_CLASS_MEMORY;
382 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
383 class1 = ARG_CLASS_INTEGER;
384 else
385 class1 = ARG_CLASS_SSE;
386
387 return class1;
388 }
389
390 static void
391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
392 gboolean is_return,
393 guint32 *gr, guint32 *fr, guint32 *stack_size)
394 {
395 guint32 size, quad, nquads, i;
396 ArgumentClass args [2];
397 MonoMarshalType *info = NULL;
398 MonoClass *klass;
399 MonoGenericSharingContext tmp_gsctx;
400
401 /*
402 * The gsctx currently contains no data, it is only used for checking whenever
403 * open types are allowed, some callers like mono_arch_get_argument_info ()
404 * don't pass it to us, so work around that.
405 */
406 if (!gsctx)
407 gsctx = &tmp_gsctx;
408
409 klass = mono_class_from_mono_type (type);
410 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
411 #ifndef PLATFORM_WIN32
412 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
413 /* We pass and return vtypes of size 8 in a register */
414 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
415 #else
416 if (!sig->pinvoke) {
417 #endif
418 /* Allways pass in memory */
419 ainfo->offset = *stack_size;
420 *stack_size += ALIGN_TO (size, 8);
421 ainfo->storage = ArgOnStack;
422
423 return;
424 }
425
426 /* FIXME: Handle structs smaller than 8 bytes */
427 //if ((size % 8) != 0)
428 // NOT_IMPLEMENTED;
429
430 if (size > 8)
431 nquads = 2;
432 else
433 nquads = 1;
434
435 if (!sig->pinvoke) {
436 /* Always pass in 1 or 2 integer registers */
437 args [0] = ARG_CLASS_INTEGER;
438 args [1] = ARG_CLASS_INTEGER;
439 /* Only the simplest cases are supported */
440 if (is_return && nquads != 1) {
441 args [0] = ARG_CLASS_MEMORY;
442 args [1] = ARG_CLASS_MEMORY;
443 }
444 } else {
445 /*
446 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
447 * The X87 and SSEUP stuff is left out since there are no such types in
448 * the CLR.
449 */
450 info = mono_marshal_load_type_info (klass);
451 g_assert (info);
452
453 #ifndef PLATFORM_WIN32
454 if (info->native_size > 16) {
455 ainfo->offset = *stack_size;
456 *stack_size += ALIGN_TO (info->native_size, 8);
457 ainfo->storage = ArgOnStack;
458
459 return;
460 }
461 #else
462 switch (info->native_size) {
463 case 1: case 2: case 4: case 8:
464 break;
465 default:
466 if (is_return) {
467 ainfo->storage = ArgOnStack;
468 ainfo->offset = *stack_size;
469 *stack_size += ALIGN_TO (info->native_size, 8);
470 }
471 else {
472 ainfo->storage = ArgValuetypeAddrInIReg;
473
474 if (*gr < PARAM_REGS) {
475 ainfo->pair_storage [0] = ArgInIReg;
476 ainfo->pair_regs [0] = param_regs [*gr];
477 (*gr) ++;
478 }
479 else {
480 ainfo->pair_storage [0] = ArgOnStack;
481 ainfo->offset = *stack_size;
482 *stack_size += 8;
483 }
484 }
485
486 return;
487 }
488 #endif
489
490 args [0] = ARG_CLASS_NO_CLASS;
491 args [1] = ARG_CLASS_NO_CLASS;
492 for (quad = 0; quad < nquads; ++quad) {
493 int size;
494 guint32 align;
495 ArgumentClass class1;
496
497 if (info->num_fields == 0)
498 class1 = ARG_CLASS_MEMORY;
499 else
500 class1 = ARG_CLASS_NO_CLASS;
501 for (i = 0; i < info->num_fields; ++i) {
502 size = mono_marshal_type_size (info->fields [i].field->type,
503 info->fields [i].mspec,
504 &align, TRUE, klass->unicode);
505 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
506 /* Unaligned field */
507 NOT_IMPLEMENTED;
508 }
509
510 /* Skip fields in other quad */
511 if ((quad == 0) && (info->fields [i].offset >= 8))
512 continue;
513 if ((quad == 1) && (info->fields [i].offset < 8))
514 continue;
515
516 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
517 }
518 g_assert (class1 != ARG_CLASS_NO_CLASS);
519 args [quad] = class1;
520 }
521 }
522
523 /* Post merger cleanup */
524 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
525 args [0] = args [1] = ARG_CLASS_MEMORY;
526
527 /* Allocate registers */
528 {
529 int orig_gr = *gr;
530 int orig_fr = *fr;
531
532 ainfo->storage = ArgValuetypeInReg;
533 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
534 for (quad = 0; quad < nquads; ++quad) {
535 switch (args [quad]) {
536 case ARG_CLASS_INTEGER:
537 if (*gr >= PARAM_REGS)
538 args [quad] = ARG_CLASS_MEMORY;
539 else {
540 ainfo->pair_storage [quad] = ArgInIReg;
541 if (is_return)
542 ainfo->pair_regs [quad] = return_regs [*gr];
543 else
544 ainfo->pair_regs [quad] = param_regs [*gr];
545 (*gr) ++;
546 }
547 break;
548 case ARG_CLASS_SSE:
549 if (*fr >= FLOAT_PARAM_REGS)
550 args [quad] = ARG_CLASS_MEMORY;
551 else {
552 ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
553 ainfo->pair_regs [quad] = *fr;
554 (*fr) ++;
555 }
556 break;
557 case ARG_CLASS_MEMORY:
558 break;
559 default:
560 g_assert_not_reached ();
561 }
562 }
563
564 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
565 /* Revert possible register assignments */
566 *gr = orig_gr;
567 *fr = orig_fr;
568
569 ainfo->offset = *stack_size;
570 if (sig->pinvoke)
571 *stack_size += ALIGN_TO (info->native_size, 8);
572 else
573 *stack_size += nquads * sizeof (gpointer);
574 ainfo->storage = ArgOnStack;
575 }
576 }
577 }
578
579 /*
580 * get_call_info:
581 *
582 * Obtain information about a call according to the calling convention.
583 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
584 * Draft Version 0.23" document for more information.
585 */
586 static CallInfo*
587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
588 {
589 guint32 i, gr, fr;
590 MonoType *ret_type;
591 int n = sig->hasthis + sig->param_count;
592 guint32 stack_size = 0;
593 CallInfo *cinfo;
594
595 if (mp)
596 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
597 else
598 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
599
600 gr = 0;
601 fr = 0;
602
603 /* return value */
604 {
605 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
606 switch (ret_type->type) {
607 case MONO_TYPE_BOOLEAN:
608 case MONO_TYPE_I1:
609 case MONO_TYPE_U1:
610 case MONO_TYPE_I2:
611 case MONO_TYPE_U2:
612 case MONO_TYPE_CHAR:
613 case MONO_TYPE_I4:
614 case MONO_TYPE_U4:
615 case MONO_TYPE_I:
616 case MONO_TYPE_U:
617 case MONO_TYPE_PTR:
618 case MONO_TYPE_FNPTR:
619 case MONO_TYPE_CLASS:
620 case MONO_TYPE_OBJECT:
621 case MONO_TYPE_SZARRAY:
622 case MONO_TYPE_ARRAY:
623 case MONO_TYPE_STRING:
624 cinfo->ret.storage = ArgInIReg;
625 cinfo->ret.reg = AMD64_RAX;
626 break;
627 case MONO_TYPE_U8:
628 case MONO_TYPE_I8:
629 cinfo->ret.storage = ArgInIReg;
630 cinfo->ret.reg = AMD64_RAX;
631 break;
632 case MONO_TYPE_R4:
633 cinfo->ret.storage = ArgInFloatSSEReg;
634 cinfo->ret.reg = AMD64_XMM0;
635 break;
636 case MONO_TYPE_R8:
637 cinfo->ret.storage = ArgInDoubleSSEReg;
638 cinfo->ret.reg = AMD64_XMM0;
639 break;
640 case MONO_TYPE_GENERICINST:
641 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
642 cinfo->ret.storage = ArgInIReg;
643 cinfo->ret.reg = AMD64_RAX;
644 break;
645 }
646 /* fall through */
647 case MONO_TYPE_VALUETYPE: {
648 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
649
650 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
651 if (cinfo->ret.storage == ArgOnStack)
652 /* The caller passes the address where the value is stored */
653 add_general (&gr, &stack_size, &cinfo->ret);
654 break;
655 }
656 case MONO_TYPE_TYPEDBYREF:
657 /* Same as a valuetype with size 24 */
658 add_general (&gr, &stack_size, &cinfo->ret);
659 ;
660 break;
661 case MONO_TYPE_VOID:
662 break;
663 default:
664 g_error ("Can't handle as return value 0x%x", sig->ret->type);
665 }
666 }
667
668 /* this */
669 if (sig->hasthis)
670 add_general (&gr, &stack_size, cinfo->args + 0);
671
672 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
673 gr = PARAM_REGS;
674 fr = FLOAT_PARAM_REGS;
675
676 /* Emit the signature cookie just before the implicit arguments */
677 add_general (&gr, &stack_size, &cinfo->sig_cookie);
678 }
679
680 for (i = 0; i < sig->param_count; ++i) {
681 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
682 MonoType *ptype;
683
684 #ifdef PLATFORM_WIN32
685 /* The float param registers and other param registers must be the same index on Windows x64.*/
686 if (gr > fr)
687 fr = gr;
688 else if (fr > gr)
689 gr = fr;
690 #endif
691
692 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
693 /* We allways pass the sig cookie on the stack for simplicity */
694 /*
695 * Prevent implicit arguments + the sig cookie from being passed
696 * in registers.
697 */
698 gr = PARAM_REGS;
699 fr = FLOAT_PARAM_REGS;
700
701 /* Emit the signature cookie just before the implicit arguments */
702 add_general (&gr, &stack_size, &cinfo->sig_cookie);
703 }
704
705 if (sig->params [i]->byref) {
706 add_general (&gr, &stack_size, ainfo);
707 continue;
708 }
709 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
710 switch (ptype->type) {
711 case MONO_TYPE_BOOLEAN:
712 case MONO_TYPE_I1:
713 case MONO_TYPE_U1:
714 add_general (&gr, &stack_size, ainfo);
715 break;
716 case MONO_TYPE_I2:
717 case MONO_TYPE_U2:
718 case MONO_TYPE_CHAR:
719 add_general (&gr, &stack_size, ainfo);
720 break;
721 case MONO_TYPE_I4:
722 case MONO_TYPE_U4:
723 add_general (&gr, &stack_size, ainfo);
724 break;
725 case MONO_TYPE_I:
726 case MONO_TYPE_U:
727 case MONO_TYPE_PTR:
728 case MONO_TYPE_FNPTR:
729 case MONO_TYPE_CLASS:
730 case MONO_TYPE_OBJECT:
731 case MONO_TYPE_STRING:
732 case MONO_TYPE_SZARRAY:
733 case MONO_TYPE_ARRAY:
734 add_general (&gr, &stack_size, ainfo);
735 break;
736 case MONO_TYPE_GENERICINST:
737 if (!mono_type_generic_inst_is_valuetype (ptype)) {
738 add_general (&gr, &stack_size, ainfo);
739 break;
740 }
741 /* fall through */
742 case MONO_TYPE_VALUETYPE:
743 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
744 break;
745 case MONO_TYPE_TYPEDBYREF:
746 #ifdef PLATFORM_WIN32
747 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
748 #else
749 stack_size += sizeof (MonoTypedRef);
750 ainfo->storage = ArgOnStack;
751 #endif
752 break;
753 case MONO_TYPE_U8:
754 case MONO_TYPE_I8:
755 add_general (&gr, &stack_size, ainfo);
756 break;
757 case MONO_TYPE_R4:
758 add_float (&fr, &stack_size, ainfo, FALSE);
759 break;
760 case MONO_TYPE_R8:
761 add_float (&fr, &stack_size, ainfo, TRUE);
762 break;
763 default:
764 g_assert_not_reached ();
765 }
766 }
767
768 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
769 gr = PARAM_REGS;
770 fr = FLOAT_PARAM_REGS;
771
772 /* Emit the signature cookie just before the implicit arguments */
773 add_general (&gr, &stack_size, &cinfo->sig_cookie);
774 }
775
776 #ifdef PLATFORM_WIN32
777 // There always is 32 bytes reserved on the stack when calling on Winx64
778 stack_size += 0x20;
779 #endif
780
781 if (stack_size & 0x8) {
782 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
783 cinfo->need_stack_align = TRUE;
784 stack_size += 8;
785 }
786
787 cinfo->stack_usage = stack_size;
788 cinfo->reg_usage = gr;
789 cinfo->freg_usage = fr;
790 return cinfo;
791 }
792
793 /*
794 * mono_arch_get_argument_info:
795 * @csig: a method signature
796 * @param_count: the number of parameters to consider
797 * @arg_info: an array to store the result infos
798 *
799 * Gathers information on parameters such as size, alignment and
800 * padding. arg_info should be large enought to hold param_count + 1 entries.
801 *
802 * Returns the size of the argument area on the stack.
803 */
804 int
805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
806 {
807 int k;
808 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
809 guint32 args_size = cinfo->stack_usage;
810
811 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
812 if (csig->hasthis) {
813 arg_info [0].offset = 0;
814 }
815
816 for (k = 0; k < param_count; k++) {
817 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
818 /* FIXME: */
819 arg_info [k + 1].size = 0;
820 }
821
822 g_free (cinfo);
823
824 return args_size;
825 }
826
827 static int
828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
829 {
830 #ifndef _MSC_VER
831 __asm__ __volatile__ ("cpuid"
832 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
833 : "a" (id));
834 #else
835 int info[4];
836 __cpuid(info, id);
837 *p_eax = info[0];
838 *p_ebx = info[1];
839 *p_ecx = info[2];
840 *p_edx = info[3];
841 #endif
842 return 1;
843 }
844
845 /*
846 * Initialize the cpu to execute managed code.
847 */
848 void
849 mono_arch_cpu_init (void)
850 {
851 #ifndef _MSC_VER
852 guint16 fpcw;
853
854 /* spec compliance requires running with double precision */
855 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
856 fpcw &= ~X86_FPCW_PRECC_MASK;
857 fpcw |= X86_FPCW_PREC_DOUBLE;
858 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
859 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
860 #else
861 /* TODO: This is crashing on Win64 right now.
862 * _control87 (_PC_53, MCW_PC);
863 */
864 #endif
865 }
866
867 /*
868 * Initialize architecture specific code.
869 */
870 void
871 mono_arch_init (void)
872 {
873 InitializeCriticalSection (&mini_arch_mutex);
874 }
875
876 /*
877 * Cleanup architecture specific code.
878 */
879 void
880 mono_arch_cleanup (void)
881 {
882 DeleteCriticalSection (&mini_arch_mutex);
883 }
884
885 /*
886 * This function returns the optimizations supported on this cpu.
887 */
888 guint32
889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
890 {
891 int eax, ebx, ecx, edx;
892 guint32 opts = 0;
893
894 /* FIXME: AMD64 */
895
896 *exclude_mask = 0;
897 /* Feature Flags function, flags returned in EDX. */
898 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
899 if (edx & (1 << 15)) {
900 opts |= MONO_OPT_CMOV;
901 if (edx & 1)
902 opts |= MONO_OPT_FCMOV;
903 else
904 *exclude_mask |= MONO_OPT_FCMOV;
905 } else
906 *exclude_mask |= MONO_OPT_CMOV;
907 }
908
909 return opts;
910 }
911
912 GList *
913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
914 {
915 GList *vars = NULL;
916 int i;
917
918 for (i = 0; i < cfg->num_varinfo; i++) {
919 MonoInst *ins = cfg->varinfo [i];
920 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
921
922 /* unused vars */
923 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
924 continue;
925
926 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
927 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
928 continue;
929
930 if (mono_is_regsize_var (ins->inst_vtype)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
934 }
935 }
936
937 vars = mono_varlist_sort (cfg, vars, 0);
938
939 return vars;
940 }
941
942 /**
943 * mono_arch_compute_omit_fp:
944 *
945 * Determine whenever the frame pointer can be eliminated.
946 */
947 static void
948 mono_arch_compute_omit_fp (MonoCompile *cfg)
949 {
950 MonoMethodSignature *sig;
951 MonoMethodHeader *header;
952 int i, locals_size;
953 CallInfo *cinfo;
954
955 if (cfg->arch.omit_fp_computed)
956 return;
957
958 header = mono_method_get_header (cfg->method);
959
960 sig = mono_method_signature (cfg->method);
961
962 if (!cfg->arch.cinfo)
963 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
964 cinfo = cfg->arch.cinfo;
965
966 /*
967 * FIXME: Remove some of the restrictions.
968 */
969 cfg->arch.omit_fp = TRUE;
970 cfg->arch.omit_fp_computed = TRUE;
971
972 if (cfg->disable_omit_fp)
973 cfg->arch.omit_fp = FALSE;
974
975 if (!debug_omit_fp ())
976 cfg->arch.omit_fp = FALSE;
977 /*
978 if (cfg->method->save_lmf)
979 cfg->arch.omit_fp = FALSE;
980 */
981 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
982 cfg->arch.omit_fp = FALSE;
983 if (header->num_clauses)
984 cfg->arch.omit_fp = FALSE;
985 if (cfg->param_area)
986 cfg->arch.omit_fp = FALSE;
987 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
988 cfg->arch.omit_fp = FALSE;
989 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
990 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
991 cfg->arch.omit_fp = FALSE;
992 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
993 ArgInfo *ainfo = &cinfo->args [i];
994
995 if (ainfo->storage == ArgOnStack) {
996 /*
997 * The stack offset can only be determined when the frame
998 * size is known.
999 */
1000 cfg->arch.omit_fp = FALSE;
1001 }
1002 }
1003
1004 locals_size = 0;
1005 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006 MonoInst *ins = cfg->varinfo [i];
1007 int ialign;
1008
1009 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1010 }
1011
1012 if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1013 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1014 cfg->arch.omit_fp = FALSE;
1015 }
1016 }
1017
1018 GList *
1019 mono_arch_get_global_int_regs (MonoCompile *cfg)
1020 {
1021 GList *regs = NULL;
1022
1023 mono_arch_compute_omit_fp (cfg);
1024
1025 if (cfg->globalra) {
1026 if (cfg->arch.omit_fp)
1027 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1028
1029 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1030 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1031 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1032 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1033 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1034
1035 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1036 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1037 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1038 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1039 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1040 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1041 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1042 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1043 } else {
1044 if (cfg->arch.omit_fp)
1045 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1046
1047 /* We use the callee saved registers for global allocation */
1048 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1049 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1050 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1051 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1052 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1053 #ifdef PLATFORM_WIN32
1054 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1055 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1056 #endif
1057 }
1058
1059 return regs;
1060 }
1061
1062 GList*
1063 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1064 {
1065 GList *regs = NULL;
1066 int i;
1067
1068 /* All XMM registers */
1069 for (i = 0; i < 16; ++i)
1070 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1071
1072 return regs;
1073 }
1074
1075 GList*
1076 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1077 {
1078 static GList *r = NULL;
1079
1080 if (r == NULL) {
1081 GList *regs = NULL;
1082
1083 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1084 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1085 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1086 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1087 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1088 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1089
1090 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1091 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1092 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1093 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1094 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1095 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1096 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1097 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1098
1099 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1100 }
1101
1102 return r;
1103 }
1104
1105 GList*
1106 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1107 {
1108 int i;
1109 static GList *r = NULL;
1110
1111 if (r == NULL) {
1112 GList *regs = NULL;
1113
1114 for (i = 0; i < AMD64_XMM_NREG; ++i)
1115 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1116
1117 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1118 }
1119
1120 return r;
1121 }
1122
1123 /*
1124 * mono_arch_regalloc_cost:
1125 *
1126 * Return the cost, in number of memory references, of the action of
1127 * allocating the variable VMV into a register during global register
1128 * allocation.
1129 */
1130 guint32
1131 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1132 {
1133 MonoInst *ins = cfg->varinfo [vmv->idx];
1134
1135 if (cfg->method->save_lmf)
1136 /* The register is already saved */
1137 /* substract 1 for the invisible store in the prolog */
1138 return (ins->opcode == OP_ARG) ? 0 : 1;
1139 else
1140 /* push+pop */
1141 return (ins->opcode == OP_ARG) ? 1 : 2;
1142 }
1143
1144 /*
1145 * mono_arch_fill_argument_info:
1146 *
1147 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1148 * of the method.
1149 */
1150 void
1151 mono_arch_fill_argument_info (MonoCompile *cfg)
1152 {
1153 MonoMethodSignature *sig;
1154 MonoMethodHeader *header;
1155 MonoInst *ins;
1156 int i;
1157 CallInfo *cinfo;
1158
1159 header = mono_method_get_header (cfg->method);
1160
1161 sig = mono_method_signature (cfg->method);
1162
1163 cinfo = cfg->arch.cinfo;
1164
1165 /*
1166 * Contrary to mono_arch_allocate_vars (), the information should describe
1167 * where the arguments are at the beginning of the method, not where they can be
1168 * accessed during the execution of the method. The later makes no sense for the
1169 * global register allocator, since a variable can be in more than one location.
1170 */
1171 if (sig->ret->type != MONO_TYPE_VOID) {
1172 switch (cinfo->ret.storage) {
1173 case ArgInIReg:
1174 case ArgInFloatSSEReg:
1175 case ArgInDoubleSSEReg:
1176 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1177 cfg->vret_addr->opcode = OP_REGVAR;
1178 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1179 }
1180 else {
1181 cfg->ret->opcode = OP_REGVAR;
1182 cfg->ret->inst_c0 = cinfo->ret.reg;
1183 }
1184 break;
1185 case ArgValuetypeInReg:
1186 cfg->ret->opcode = OP_REGOFFSET;
1187 cfg->ret->inst_basereg = -1;
1188 cfg->ret->inst_offset = -1;
1189 break;
1190 default:
1191 g_assert_not_reached ();
1192 }
1193 }
1194
1195 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1196 ArgInfo *ainfo = &cinfo->args [i];
1197 MonoType *arg_type;
1198
1199 ins = cfg->args [i];
1200
1201 if (sig->hasthis && (i == 0))
1202 arg_type = &mono_defaults.object_class->byval_arg;
1203 else
1204 arg_type = sig->params [i - sig->hasthis];
1205
1206 switch (ainfo->storage) {
1207 case ArgInIReg:
1208 case ArgInFloatSSEReg:
1209 case ArgInDoubleSSEReg:
1210 ins->opcode = OP_REGVAR;
1211 ins->inst_c0 = ainfo->reg;
1212 break;
1213 case ArgOnStack:
1214 ins->opcode = OP_REGOFFSET;
1215 ins->inst_basereg = -1;
1216 ins->inst_offset = -1;
1217 break;
1218 case ArgValuetypeInReg:
1219 /* Dummy */
1220 ins->opcode = OP_NOP;
1221 break;
1222 default:
1223 g_assert_not_reached ();
1224 }
1225 }
1226 }
1227
1228 void
1229 mono_arch_allocate_vars (MonoCompile *cfg)
1230 {
1231 MonoMethodSignature *sig;
1232 MonoMethodHeader *header;
1233 MonoInst *ins;
1234 int i, offset;
1235 guint32 locals_stack_size, locals_stack_align;
1236 gint32 *offsets;
1237 CallInfo *cinfo;
1238
1239 header = mono_method_get_header (cfg->method);
1240
1241 sig = mono_method_signature (cfg->method);
1242
1243 cinfo = cfg->arch.cinfo;
1244
1245 mono_arch_compute_omit_fp (cfg);
1246
1247 /*
1248 * We use the ABI calling conventions for managed code as well.
1249 * Exception: valuetypes are never passed or returned in registers.
1250 */
1251
1252 if (cfg->arch.omit_fp) {
1253 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1254 cfg->frame_reg = AMD64_RSP;
1255 offset = 0;
1256 } else {
1257 /* Locals are allocated backwards from %fp */
1258 cfg->frame_reg = AMD64_RBP;
1259 offset = 0;
1260 }
1261
1262 if (cfg->method->save_lmf) {
1263 /* Reserve stack space for saving LMF */
1264 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1265 g_assert (offset == 0);
1266 if (cfg->arch.omit_fp) {
1267 cfg->arch.lmf_offset = offset;
1268 offset += sizeof (MonoLMF);
1269 }
1270 else {
1271 offset += sizeof (MonoLMF);
1272 cfg->arch.lmf_offset = -offset;
1273 }
1274 } else {
1275 if (cfg->arch.omit_fp)
1276 cfg->arch.reg_save_area_offset = offset;
1277 /* Reserve space for caller saved registers */
1278 for (i = 0; i < AMD64_NREG; ++i)
1279 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1280 offset += sizeof (gpointer);
1281 }
1282 }
1283
1284 if (sig->ret->type != MONO_TYPE_VOID) {
1285 switch (cinfo->ret.storage) {
1286 case ArgInIReg:
1287 case ArgInFloatSSEReg:
1288 case ArgInDoubleSSEReg:
1289 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1290 if (cfg->globalra) {
1291 cfg->vret_addr->opcode = OP_REGVAR;
1292 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1293 } else {
1294 /* The register is volatile */
1295 cfg->vret_addr->opcode = OP_REGOFFSET;
1296 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1297 if (cfg->arch.omit_fp) {
1298 cfg->vret_addr->inst_offset = offset;
1299 offset += 8;
1300 } else {
1301 offset += 8;
1302 cfg->vret_addr->inst_offset = -offset;
1303 }
1304 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1305 printf ("vret_addr =");
1306 mono_print_ins (cfg->vret_addr);
1307 }
1308 }
1309 }
1310 else {
1311 cfg->ret->opcode = OP_REGVAR;
1312 cfg->ret->inst_c0 = cinfo->ret.reg;
1313 }
1314 break;
1315 case ArgValuetypeInReg:
1316 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1317 cfg->ret->opcode = OP_REGOFFSET;
1318 cfg->ret->inst_basereg = cfg->frame_reg;
1319 if (cfg->arch.omit_fp) {
1320 cfg->ret->inst_offset = offset;
1321 offset += 16;
1322 } else {
1323 offset += 16;
1324 cfg->ret->inst_offset = - offset;
1325 }
1326 break;
1327 default:
1328 g_assert_not_reached ();
1329 }
1330 if (!cfg->globalra)
1331 cfg->ret->dreg = cfg->ret->inst_c0;
1332 }
1333
1334 /* Allocate locals */
1335 if (!cfg->globalra) {
1336 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1337 if (locals_stack_align) {
1338 offset += (locals_stack_align - 1);
1339 offset &= ~(locals_stack_align - 1);
1340 }
1341 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1342 if (offsets [i] != -1) {
1343 MonoInst *ins = cfg->varinfo [i];
1344 ins->opcode = OP_REGOFFSET;
1345 ins->inst_basereg = cfg->frame_reg;
1346 if (cfg->arch.omit_fp)
1347 ins->inst_offset = (offset + offsets [i]);
1348 else
1349 ins->inst_offset = - (offset + offsets [i]);
1350 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1351 }
1352 }
1353 offset += locals_stack_size;
1354 }
1355
1356 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1357 g_assert (!cfg->arch.omit_fp);
1358 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1359 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1360 }
1361
1362 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1363 ins = cfg->args [i];
1364 if (ins->opcode != OP_REGVAR) {
1365 ArgInfo *ainfo = &cinfo->args [i];
1366 gboolean inreg = TRUE;
1367 MonoType *arg_type;
1368
1369 if (sig->hasthis && (i == 0))
1370 arg_type = &mono_defaults.object_class->byval_arg;
1371 else
1372 arg_type = sig->params [i - sig->hasthis];
1373
1374 if (cfg->globalra) {
1375 /* The new allocator needs info about the original locations of the arguments */
1376 switch (ainfo->storage) {
1377 case ArgInIReg:
1378 case ArgInFloatSSEReg:
1379 case ArgInDoubleSSEReg:
1380 ins->opcode = OP_REGVAR;
1381 ins->inst_c0 = ainfo->reg;
1382 break;
1383 case ArgOnStack:
1384 g_assert (!cfg->arch.omit_fp);
1385 ins->opcode = OP_REGOFFSET;
1386 ins->inst_basereg = cfg->frame_reg;
1387 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1388 break;
1389 case ArgValuetypeInReg:
1390 ins->opcode = OP_REGOFFSET;
1391 ins->inst_basereg = cfg->frame_reg;
1392 /* These arguments are saved to the stack in the prolog */
1393 offset = ALIGN_TO (offset, sizeof (gpointer));
1394 if (cfg->arch.omit_fp) {
1395 ins->inst_offset = offset;
1396 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1397 } else {
1398 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1399 ins->inst_offset = - offset;
1400 }
1401 break;
1402 default:
1403 g_assert_not_reached ();
1404 }
1405
1406 continue;
1407 }
1408
1409 /* FIXME: Allocate volatile arguments to registers */
1410 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1411 inreg = FALSE;
1412
1413 /*
1414 * Under AMD64, all registers used to pass arguments to functions
1415 * are volatile across calls.
1416 * FIXME: Optimize this.
1417 */
1418 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1419 inreg = FALSE;
1420
1421 ins->opcode = OP_REGOFFSET;
1422
1423 switch (ainfo->storage) {
1424 case ArgInIReg:
1425 case ArgInFloatSSEReg:
1426 case ArgInDoubleSSEReg:
1427 if (inreg) {
1428 ins->opcode = OP_REGVAR;
1429 ins->dreg = ainfo->reg;
1430 }
1431 break;
1432 case ArgOnStack:
1433 g_assert (!cfg->arch.omit_fp);
1434 ins->opcode = OP_REGOFFSET;
1435 ins->inst_basereg = cfg->frame_reg;
1436 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1437 break;
1438 case ArgValuetypeInReg:
1439 break;
1440 case ArgValuetypeAddrInIReg: {
1441 MonoInst *indir;
1442 g_assert (!cfg->arch.omit_fp);
1443
1444 MONO_INST_NEW (cfg, indir, 0);
1445 indir->opcode = OP_REGOFFSET;
1446 if (ainfo->pair_storage [0] == ArgInIReg) {
1447 indir->inst_basereg = cfg->frame_reg;
1448 offset = ALIGN_TO (offset, sizeof (gpointer));
1449 offset += (sizeof (gpointer));
1450 indir->inst_offset = - offset;
1451 }
1452 else {
1453 indir->inst_basereg = cfg->frame_reg;
1454 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1455 }
1456
1457 ins->opcode = OP_VTARG_ADDR;
1458 ins->inst_left = indir;
1459
1460 break;
1461 }
1462 default:
1463 NOT_IMPLEMENTED;
1464 }
1465
1466 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1467 ins->opcode = OP_REGOFFSET;
1468 ins->inst_basereg = cfg->frame_reg;
1469 /* These arguments are saved to the stack in the prolog */
1470 offset = ALIGN_TO (offset, sizeof (gpointer));
1471 if (cfg->arch.omit_fp) {
1472 ins->inst_offset = offset;
1473 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1474 } else {
1475 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1476 ins->inst_offset = - offset;
1477 }
1478 }
1479 }
1480 }
1481
1482 cfg->stack_offset = offset;
1483 }
1484
1485 void
1486 mono_arch_create_vars (MonoCompile *cfg)
1487 {
1488 MonoMethodSignature *sig;
1489 CallInfo *cinfo;
1490
1491 sig = mono_method_signature (cfg->method);
1492
1493 if (!cfg->arch.cinfo)
1494 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1495 cinfo = cfg->arch.cinfo;
1496
1497 if (cinfo->ret.storage == ArgValuetypeInReg)
1498 cfg->ret_var_is_local = TRUE;
1499
1500 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1501 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1502 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1503 printf ("vret_addr = ");
1504 mono_print_ins (cfg->vret_addr);
1505 }
1506 }
1507 }
1508
1509 static void
1510 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1511 {
1512 MonoInst *ins;
1513
1514 switch (storage) {
1515 case ArgInIReg:
1516 MONO_INST_NEW (cfg, ins, OP_MOVE);
1517 ins->dreg = mono_alloc_ireg (cfg);
1518 ins->sreg1 = tree->dreg;
1519 MONO_ADD_INS (cfg->cbb, ins);
1520 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1521 break;
1522 case ArgInFloatSSEReg:
1523 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1524 ins->dreg = mono_alloc_freg (cfg);
1525 ins->sreg1 = tree->dreg;
1526 MONO_ADD_INS (cfg->cbb, ins);
1527
1528 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1529 break;
1530 case ArgInDoubleSSEReg:
1531 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1532 ins->dreg = mono_alloc_freg (cfg);
1533 ins->sreg1 = tree->dreg;
1534 MONO_ADD_INS (cfg->cbb, ins);
1535
1536 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1537
1538 break;
1539 default:
1540 g_assert_not_reached ();
1541 }
1542 }
1543
1544 static int
1545 arg_storage_to_load_membase (ArgStorage storage)
1546 {
1547 switch (storage) {
1548 case ArgInIReg:
1549 return OP_LOAD_MEMBASE;
1550 case ArgInDoubleSSEReg:
1551 return OP_LOADR8_MEMBASE;
1552 case ArgInFloatSSEReg:
1553 return OP_LOADR4_MEMBASE;
1554 default:
1555 g_assert_not_reached ();
1556 }
1557
1558 return -1;
1559 }
1560
1561 static void
1562 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1563 {
1564 MonoInst *arg;
1565 MonoMethodSignature *tmp_sig;
1566 MonoInst *sig_arg;
1567
1568 if (call->tail_call)
1569 NOT_IMPLEMENTED;
1570
1571 /* FIXME: Add support for signature tokens to AOT */
1572 cfg->disable_aot = TRUE;
1573
1574 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1575
1576 /*
1577 * mono_ArgIterator_Setup assumes the signature cookie is
1578 * passed first and all the arguments which were before it are
1579 * passed on the stack after the signature. So compensate by
1580 * passing a different signature.
1581 */
1582 tmp_sig = mono_metadata_signature_dup (call->signature);
1583 tmp_sig->param_count -= call->signature->sentinelpos;
1584 tmp_sig->sentinelpos = 0;
1585 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1586
1587 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1588 sig_arg->dreg = mono_alloc_ireg (cfg);
1589 sig_arg->inst_p0 = tmp_sig;
1590 MONO_ADD_INS (cfg->cbb, sig_arg);
1591
1592 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1593 arg->sreg1 = sig_arg->dreg;
1594 MONO_ADD_INS (cfg->cbb, arg);
1595 }
1596
1597 void
1598 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1599 {
1600 MonoInst *arg, *in;
1601 MonoMethodSignature *sig;
1602 int i, n, stack_size;
1603 CallInfo *cinfo;
1604 ArgInfo *ainfo;
1605
1606 stack_size = 0;
1607
1608 sig = call->signature;
1609 n = sig->param_count + sig->hasthis;
1610
1611 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1612
1613 if (cinfo->need_stack_align) {
1614 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1615 }
1616
1617 /*
1618 * Emit all parameters passed in registers in non-reverse order for better readability
1619 * and to help the optimization in emit_prolog ().
1620 */
1621 for (i = 0; i < n; ++i) {
1622 ainfo = cinfo->args + i;
1623
1624 in = call->args [i];
1625
1626 if (ainfo->storage == ArgInIReg)
1627 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1628 }
1629
1630 for (i = n - 1; i >= 0; --i) {
1631 ainfo = cinfo->args + i;
1632
1633 in = call->args [i];
1634
1635 switch (ainfo->storage) {
1636 case ArgInIReg:
1637 /* Already done */
1638 break;
1639 case ArgInFloatSSEReg:
1640 case ArgInDoubleSSEReg:
1641 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1642 break;
1643 case ArgOnStack:
1644 case ArgValuetypeInReg:
1645 case ArgValuetypeAddrInIReg:
1646 if (ainfo->storage == ArgOnStack && call->tail_call) {
1647 MonoInst *call_inst = (MonoInst*)call;
1648 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1649 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1650 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1651 guint32 align;
1652 guint32 size;
1653
1654 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1655 size = sizeof (MonoTypedRef);
1656 align = sizeof (gpointer);
1657 }
1658 else {
1659 if (sig->pinvoke)
1660 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1661 else {
1662 /*
1663 * Other backends use mono_type_stack_size (), but that
1664 * aligns the size to 8, which is larger than the size of
1665 * the source, leading to reads of invalid memory if the
1666 * source is at the end of address space.
1667 */
1668 size = mono_class_value_size (in->klass, &align);
1669 }
1670 }
1671 g_assert (in->klass);
1672
1673 if (size > 0) {
1674 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1675 arg->sreg1 = in->dreg;
1676 arg->klass = in->klass;
1677 arg->backend.size = size;
1678 arg->inst_p0 = call;
1679 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1680 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1681
1682 MONO_ADD_INS (cfg->cbb, arg);
1683 }
1684 } else {
1685 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1686 arg->sreg1 = in->dreg;
1687 if (!sig->params [i - sig->hasthis]->byref) {
1688 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1689 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1690 arg->opcode = OP_STORER4_MEMBASE_REG;
1691 arg->inst_destbasereg = X86_ESP;
1692 arg->inst_offset = 0;
1693 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1694 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1695 arg->opcode = OP_STORER8_MEMBASE_REG;
1696 arg->inst_destbasereg = X86_ESP;
1697 arg->inst_offset = 0;
1698 }
1699 }
1700 MONO_ADD_INS (cfg->cbb, arg);
1701 }
1702 break;
1703 default:
1704 g_assert_not_reached ();
1705 }
1706
1707 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1708 /* Emit the signature cookie just before the implicit arguments */
1709 emit_sig_cookie (cfg, call, cinfo);
1710 }
1711
1712 /* Handle the case where there are no implicit arguments */
1713 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1714 emit_sig_cookie (cfg, call, cinfo);
1715
1716 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1717 MonoInst *vtarg;
1718
1719 if (cinfo->ret.storage == ArgValuetypeInReg) {
1720 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1721 /*
1722 * Tell the JIT to use a more efficient calling convention: call using
1723 * OP_CALL, compute the result location after the call, and save the
1724 * result there.
1725 */
1726 call->vret_in_reg = TRUE;
1727 /*
1728 * Nullify the instruction computing the vret addr to enable
1729 * future optimizations.
1730 */
1731 if (call->vret_var)
1732 NULLIFY_INS (call->vret_var);
1733 } else {
1734 if (call->tail_call)
1735 NOT_IMPLEMENTED;
1736 /*
1737 * The valuetype is in RAX:RDX after the call, need to be copied to
1738 * the stack. Push the address here, so the call instruction can
1739 * access it.
1740 */
1741 if (!cfg->arch.vret_addr_loc) {
1742 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1743 /* Prevent it from being register allocated or optimized away */
1744 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1745 }
1746
1747 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1748 }
1749 }
1750 else {
1751 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1752 vtarg->sreg1 = call->vret_var->dreg;
1753 vtarg->dreg = mono_alloc_preg (cfg);
1754 MONO_ADD_INS (cfg->cbb, vtarg);
1755
1756 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1757 }
1758 }
1759
1760 #ifdef PLATFORM_WIN32
1761 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1762 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1763 }
1764 #endif
1765
1766 if (cfg->method->save_lmf) {
1767 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1768 MONO_ADD_INS (cfg->cbb, arg);
1769 }
1770
1771 call->stack_usage = cinfo->stack_usage;
1772 }
1773
1774 void
1775 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1776 {
1777 MonoInst *arg;
1778 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1779 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1780 int size = ins->backend.size;
1781
1782 if (ainfo->storage == ArgValuetypeInReg) {
1783 MonoInst *load;
1784 int part;
1785
1786 for (part = 0; part < 2; ++part) {
1787 if (ainfo->pair_storage [part] == ArgNone)
1788 continue;
1789
1790 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1791 load->inst_basereg = src->dreg;
1792 load->inst_offset = part * sizeof (gpointer);
1793
1794 switch (ainfo->pair_storage [part]) {
1795 case ArgInIReg:
1796 load->dreg = mono_alloc_ireg (cfg);
1797 break;
1798 case ArgInDoubleSSEReg:
1799 case ArgInFloatSSEReg:
1800 load->dreg = mono_alloc_freg (cfg);
1801 break;
1802 default:
1803 g_assert_not_reached ();
1804 }
1805 MONO_ADD_INS (cfg->cbb, load);
1806
1807 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1808 }
1809 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1810 MonoInst *vtaddr, *load;
1811 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1812
1813 MONO_INST_NEW (cfg, load, OP_LDADDR);
1814 load->inst_p0 = vtaddr;
1815 vtaddr->flags |= MONO_INST_INDIRECT;
1816 load->type = STACK_MP;
1817 load->klass = vtaddr->klass;
1818 load->dreg = mono_alloc_ireg (cfg);
1819 MONO_ADD_INS (cfg->cbb, load);
1820 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1821
1822 if (ainfo->pair_storage [0] == ArgInIReg) {
1823 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1824 arg->dreg = mono_alloc_ireg (cfg);
1825 arg->sreg1 = load->dreg;
1826 arg->inst_imm = 0;
1827 MONO_ADD_INS (cfg->cbb, arg);
1828 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1829 } else {
1830 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1831 arg->sreg1 = load->dreg;
1832 MONO_ADD_INS (cfg->cbb, arg);
1833 }
1834 } else {
1835 if (size == 8) {
1836 /* Can't use this for < 8 since it does an 8 byte memory load */
1837 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1838 arg->inst_basereg = src->dreg;
1839 arg->inst_offset = 0;
1840 MONO_ADD_INS (cfg->cbb, arg);
1841 } else if (size <= 40) {
1842 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1843 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1844 } else {
1845 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1846 arg->inst_basereg = src->dreg;
1847 arg->inst_offset = 0;
1848 arg->inst_imm = size;
1849 MONO_ADD_INS (cfg->cbb, arg);
1850 }
1851 }
1852 }
1853
1854 void
1855 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1856 {
1857 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1858
1859 if (!ret->byref) {
1860 if (ret->type == MONO_TYPE_R4) {
1861 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1862 return;
1863 } else if (ret->type == MONO_TYPE_R8) {
1864 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1865 return;
1866 }
1867 }
1868
1869 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1870 }
1871
1872 #define EMIT_COND_BRANCH(ins,cond,sign) \
1873 if (ins->flags & MONO_INST_BRLABEL) { \
1874 if (ins->inst_i0->inst_c0) { \
1875 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1876 } else { \
1877 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1878 if ((cfg->opt & MONO_OPT_BRANCH) && \
1879 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1880 x86_branch8 (code, cond, 0, sign); \
1881 else \
1882 x86_branch32 (code, cond, 0, sign); \
1883 } \
1884 } else { \
1885 if (ins->inst_true_bb->native_offset) { \
1886 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1887 } else { \
1888 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1889 if ((cfg->opt & MONO_OPT_BRANCH) && \
1890 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1891 x86_branch8 (code, cond, 0, sign); \
1892 else \
1893 x86_branch32 (code, cond, 0, sign); \
1894 } \
1895 }
1896
1897 /* emit an exception if condition is fail */
1898 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1899 do { \
1900 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1901 if (tins == NULL) { \
1902 mono_add_patch_info (cfg, code - cfg->native_code, \
1903 MONO_PATCH_INFO_EXC, exc_name); \
1904 x86_branch32 (code, cond, 0, signed); \
1905 } else { \
1906 EMIT_COND_BRANCH (tins, cond, signed); \
1907 } \
1908 } while (0);
1909
1910 #define EMIT_FPCOMPARE(code) do { \
1911 amd64_fcompp (code); \
1912 amd64_fnstsw (code); \
1913 } while (0);
1914
1915 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1916 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1917 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1918 amd64_ ##op (code); \
1919 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1920 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1921 } while (0);
1922
1923 static guint8*
1924 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1925 {
1926 gboolean no_patch = FALSE;
1927
1928 /*
1929 * FIXME: Add support for thunks
1930 */
1931 {
1932 gboolean near_call = FALSE;
1933
1934 /*
1935 * Indirect calls are expensive so try to make a near call if possible.
1936 * The caller memory is allocated by the code manager so it is
1937 * guaranteed to be at a 32 bit offset.
1938 */
1939
1940 if (patch_type != MONO_PATCH_INFO_ABS) {
1941 /* The target is in memory allocated using the code manager */
1942 near_call = TRUE;
1943
1944 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1945 if (((MonoMethod*)data)->klass->image->aot_module)
1946 /* The callee might be an AOT method */
1947 near_call = FALSE;
1948 if (((MonoMethod*)data)->dynamic)
1949 /* The target is in malloc-ed memory */
1950 near_call = FALSE;
1951 }
1952
1953 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1954 /*
1955 * The call might go directly to a native function without
1956 * the wrapper.
1957 */
1958 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1959 if (mi) {
1960 gconstpointer target = mono_icall_get_wrapper (mi);
1961 if ((((guint64)target) >> 32) != 0)
1962 near_call = FALSE;
1963 }
1964 }
1965 }
1966 else {
1967 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1968 /*
1969 * This is not really an optimization, but required because the
1970 * generic class init trampolines use R11 to pass the vtable.
1971 */
1972 near_call = TRUE;
1973 } else {
1974 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1975 if (info) {
1976 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1977 strstr (cfg->method->name, info->name)) {
1978 /* A call to the wrapped function */
1979 if ((((guint64)data) >> 32) == 0)
1980 near_call = TRUE;
1981 no_patch = TRUE;
1982 }
1983 else if (info->func == info->wrapper) {
1984 /* No wrapper */
1985 if ((((guint64)info->func) >> 32) == 0)
1986 near_call = TRUE;
1987 }
1988 else {
1989 /* See the comment in mono_codegen () */
1990 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1991 near_call = TRUE;
1992 }
1993 }
1994 else if ((((guint64)data) >> 32) == 0) {
1995 near_call = TRUE;
1996 no_patch = TRUE;
1997 }
1998 }
1999 }
2000
2001 if (cfg->method->dynamic)
2002 /* These methods are allocated using malloc */
2003 near_call = FALSE;
2004
2005 if (cfg->compile_aot) {
2006 near_call = TRUE;
2007 no_patch = TRUE;
2008 }
2009
2010 #ifdef MONO_ARCH_NOMAP32BIT
2011 near_call = FALSE;
2012 #endif
2013
2014 if (near_call) {
2015 /*
2016 * Align the call displacement to an address divisible by 4 so it does
2017 * not span cache lines. This is required for code patching to work on SMP
2018 * systems.
2019 */
2020 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2021 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2022 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2023 amd64_call_code (code, 0);
2024 }
2025 else {
2026 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2027 amd64_set_reg_template (code, GP_SCRATCH_REG);
2028 amd64_call_reg (code, GP_SCRATCH_REG);
2029 }
2030 }
2031
2032 return code;
2033 }
2034
2035 static inline guint8*
2036 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2037 {
2038 #ifdef PLATFORM_WIN32
2039 if (win64_adjust_stack)
2040 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2041 #endif
2042 code = emit_call_body (cfg, code, patch_type, data);
2043 #ifdef PLATFORM_WIN32
2044 if (win64_adjust_stack)
2045 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2046 #endif
2047
2048 return code;
2049 }
2050
2051 static inline int
2052 store_membase_imm_to_store_membase_reg (int opcode)
2053 {
2054 switch (opcode) {
2055 case OP_STORE_MEMBASE_IMM:
2056 return OP_STORE_MEMBASE_REG;
2057 case OP_STOREI4_MEMBASE_IMM:
2058 return OP_STOREI4_MEMBASE_REG;
2059 case OP_STOREI8_MEMBASE_IMM:
2060 return OP_STOREI8_MEMBASE_REG;
2061 }
2062
2063 return -1;
2064 }
2065
2066 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2067
2068 /*
2069 * mono_arch_peephole_pass_1:
2070 *
2071 * Perform peephole opts which should/can be performed before local regalloc
2072 */
2073 void
2074 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2075 {
2076 MonoInst *ins, *n;
2077
2078 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2079 MonoInst *last_ins = ins->prev;
2080
2081 switch (ins->opcode) {
2082 case OP_ADD_IMM:
2083 case OP_IADD_IMM:
2084 case OP_LADD_IMM:
2085 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2086 /*
2087 * X86_LEA is like ADD, but doesn't have the
2088 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2089 * its operand to 64 bit.
2090 */
2091 ins->opcode = OP_X86_LEA_MEMBASE;
2092 ins->inst_basereg = ins->sreg1;
2093 }
2094 break;
2095 case OP_LXOR:
2096 case OP_IXOR:
2097 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2098 MonoInst *ins2;
2099
2100 /*
2101 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2102 * the latter has length 2-3 instead of 6 (reverse constant
2103 * propagation). These instruction sequences are very common
2104 * in the initlocals bblock.
2105 */
2106 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2107 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2108 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2109 ins2->sreg1 = ins->dreg;
2110 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2111 /* Continue */
2112 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2113 NULLIFY_INS (ins2);
2114 /* Continue */
2115 } else {
2116 break;
2117 }
2118 }
2119 }
2120 break;
2121 case OP_COMPARE_IMM:
2122 case OP_LCOMPARE_IMM:
2123 /* OP_COMPARE_IMM (reg, 0)
2124 * -->
2125 * OP_AMD64_TEST_NULL (reg)
2126 */
2127 if (!ins->inst_imm)
2128 ins->opcode = OP_AMD64_TEST_NULL;
2129 break;
2130 case OP_ICOMPARE_IMM:
2131 if (!ins->inst_imm)
2132 ins->opcode = OP_X86_TEST_NULL;
2133 break;
2134 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2135 /*
2136 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2137 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2138 * -->
2139 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2140 * OP_COMPARE_IMM reg, imm
2141 *
2142 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2143 */
2144 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2145 ins->inst_basereg == last_ins->inst_destbasereg &&
2146 ins->inst_offset == last_ins->inst_offset) {
2147 ins->opcode = OP_ICOMPARE_IMM;
2148 ins->sreg1 = last_ins->sreg1;
2149
2150 /* check if we can remove cmp reg,0 with test null */
2151 if (!ins->inst_imm)
2152 ins->opcode = OP_X86_TEST_NULL;
2153 }
2154
2155 break;
2156 }
2157
2158 mono_peephole_ins (bb, ins);
2159 }
2160 }
2161
2162 void
2163 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2164 {
2165 MonoInst *ins, *n;
2166
2167 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2168 switch (ins->opcode) {
2169 case OP_ICONST:
2170 case OP_I8CONST: {
2171 /* reg = 0 -> XOR (reg, reg) */
2172 /* XOR sets cflags on x86, so we cant do it always */
2173 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2174 ins->opcode = OP_LXOR;
2175 ins->sreg1 = ins->dreg;
2176 ins->sreg2 = ins->dreg;
2177 /* Fall through */
2178 } else {
2179 break;
2180 }
2181 }
2182 case OP_LXOR:
2183 /*
2184 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2185 * 0 result into 64 bits.
2186 */
2187 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2188 ins->opcode = OP_IXOR;
2189 }
2190 /* Fall through */
2191 case OP_IXOR:
2192 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2193 MonoInst *ins2;
2194
2195 /*
2196 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2197 * the latter has length 2-3 instead of 6 (reverse constant
2198 * propagation). These instruction sequences are very common
2199 * in the initlocals bblock.
2200 */
2201 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2202 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2203 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2204 ins2->sreg1 = ins->dreg;
2205 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2206 /* Continue */
2207 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2208 NULLIFY_INS (ins2);
2209 /* Continue */
2210 } else {
2211 break;
2212 }
2213 }
2214 }
2215 break;
2216 case OP_IADD_IMM:
2217 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2218 ins->opcode = OP_X86_INC_REG;
2219 break;
2220 case OP_ISUB_IMM:
2221 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2222 ins->opcode = OP_X86_DEC_REG;
2223 break;
2224 }
2225
2226 mono_peephole_ins (bb, ins);
2227 }
2228 }
2229
2230 #define NEW_INS(cfg,ins,dest,op) do { \
2231 MONO_INST_NEW ((cfg), (dest), (op)); \
2232 (dest)->cil_code = (ins)->cil_code; \
2233 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2234 } while (0)
2235
2236 /*
2237 * mono_arch_lowering_pass:
2238 *
2239 * Converts complex opcodes into simpler ones so that each IR instruction
2240 * corresponds to one machine instruction.
2241 */
2242 void
2243 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2244 {
2245 MonoInst *ins, *n, *temp;
2246
2247 /*
2248 * FIXME: Need to add more instructions, but the current machine
2249 * description can't model some parts of the composite instructions like
2250 * cdq.
2251 */
2252 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2253 switch (ins->opcode) {
2254 case OP_DIV_IMM:
2255 case OP_REM_IMM:
2256 case OP_IDIV_IMM:
2257 case OP_IDIV_UN_IMM:
2258 case OP_IREM_UN_IMM:
2259 mono_decompose_op_imm (cfg, bb, ins);
2260 break;
2261 case OP_IREM_IMM:
2262 /* Keep the opcode if we can implement it efficiently */
2263 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2264 mono_decompose_op_imm (cfg, bb, ins);
2265 break;
2266 case OP_COMPARE_IMM:
2267 case OP_LCOMPARE_IMM:
2268 if (!amd64_is_imm32 (ins->inst_imm)) {
2269 NEW_INS (cfg, ins, temp, OP_I8CONST);
2270 temp->inst_c0 = ins->inst_imm;
2271 temp->dreg = mono_alloc_ireg (cfg);
2272 ins->opcode = OP_COMPARE;
2273 ins->sreg2 = temp->dreg;
2274 }
2275 break;
2276 case OP_LOAD_MEMBASE:
2277 case OP_LOADI8_MEMBASE:
2278 if (!amd64_is_imm32 (ins->inst_offset)) {
2279 NEW_INS (cfg, ins, temp, OP_I8CONST);
2280 temp->inst_c0 = ins->inst_offset;
2281 temp->dreg = mono_alloc_ireg (cfg);
2282 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2283 ins->inst_indexreg = temp->dreg;
2284 }
2285 break;
2286 case OP_STORE_MEMBASE_IMM:
2287 case OP_STOREI8_MEMBASE_IMM:
2288 if (!amd64_is_imm32 (ins->inst_imm)) {
2289 NEW_INS (cfg, ins, temp, OP_I8CONST);
2290 temp->inst_c0 = ins->inst_imm;
2291 temp->dreg = mono_alloc_ireg (cfg);
2292 ins->opcode = OP_STOREI8_MEMBASE_REG;
2293 ins->sreg1 = temp->dreg;
2294 }
2295 break;
2296 default:
2297 break;
2298 }
2299 }
2300
2301 bb->max_vreg = cfg->next_vreg;
2302 }
2303
2304 static const int
2305 branch_cc_table [] = {
2306 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2307 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2308 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2309 };
2310
2311 /* Maps CMP_... constants to X86_CC_... constants */
2312 static const int
2313 cc_table [] = {
2314 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2315 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2316 };
2317
2318 static const int
2319 cc_signed_table [] = {
2320 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2321 FALSE, FALSE, FALSE, FALSE
2322 };
2323
2324 /*#include "cprop.c"*/
2325
2326 static unsigned char*
2327 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2328 {
2329 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2330
2331 if (size == 1)
2332 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2333 else if (size == 2)
2334 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2335 return code;
2336 }
2337
2338 static unsigned char*
2339 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2340 {
2341 int sreg = tree->sreg1;
2342 int need_touch = FALSE;
2343
2344 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2345 if (!tree->flags & MONO_INST_INIT)
2346 need_touch = TRUE;
2347 #endif
2348
2349 if (need_touch) {
2350 guint8* br[5];
2351
2352 /*
2353 * Under Windows:
2354 * If requested stack size is larger than one page,
2355 * perform stack-touch operation
2356 */
2357 /*
2358 * Generate stack probe code.
2359 * Under Windows, it is necessary to allocate one page at a time,
2360 * "touching" stack after each successful sub-allocation. This is
2361 * because of the way stack growth is implemented - there is a
2362 * guard page before the lowest stack page that is currently commited.
2363 * Stack normally grows sequentially so OS traps access to the
2364 * guard page and commits more pages when needed.
2365 */
2366 amd64_test_reg_imm (code, sreg, ~0xFFF);
2367 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2368
2369 br[2] = code; /* loop */
2370 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2371 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2372 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2373 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2374 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2375 amd64_patch (br[3], br[2]);
2376 amd64_test_reg_reg (code, sreg, sreg);
2377 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2378 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2379
2380 br[1] = code; x86_jump8 (code, 0);
2381
2382 amd64_patch (br[0], code);
2383 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2384 amd64_patch (br[1], code);
2385 amd64_patch (br[4], code);
2386 }
2387 else
2388 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2389
2390 if (tree->flags & MONO_INST_INIT) {
2391 int offset = 0;
2392 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2393 amd64_push_reg (code, AMD64_RAX);
2394 offset += 8;
2395 }
2396 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2397 amd64_push_reg (code, AMD64_RCX);
2398 offset += 8;
2399 }
2400 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2401 amd64_push_reg (code, AMD64_RDI);
2402 offset += 8;
2403 }
2404
2405 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2406 if (sreg != AMD64_RCX)
2407 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2408 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2409
2410 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2411 amd64_cld (code);
2412 amd64_prefix (code, X86_REP_PREFIX);
2413 amd64_stosl (code);
2414
2415 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2416 amd64_pop_reg (code, AMD64_RDI);
2417 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2418 amd64_pop_reg (code, AMD64_RCX);
2419 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2420 amd64_pop_reg (code, AMD64_RAX);
2421 }
2422 return code;
2423 }
2424
2425 static guint8*
2426 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2427 {
2428 CallInfo *cinfo;
2429 guint32 quad;
2430
2431 /* Move return value to the target register */
2432 /* FIXME: do this in the local reg allocator */
2433 switch (ins->opcode) {
2434 case OP_CALL:
2435 case OP_CALL_REG:
2436 case OP_CALL_MEMBASE:
2437 case OP_LCALL:
2438 case OP_LCALL_REG:
2439 case OP_LCALL_MEMBASE:
2440 g_assert (ins->dreg == AMD64_RAX);
2441 break;
2442 case OP_FCALL:
2443 case OP_FCALL_REG:
2444 case OP_FCALL_MEMBASE:
2445 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2446 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2447 }
2448 else {
2449 if (ins->dreg != AMD64_XMM0)
2450 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2451 }
2452 break;
2453 case OP_VCALL:
2454 case OP_VCALL_REG:
2455 case OP_VCALL_MEMBASE:
2456 case OP_VCALL2:
2457 case OP_VCALL2_REG:
2458 case OP_VCALL2_MEMBASE:
2459 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2460 if (cinfo->ret.storage == ArgValuetypeInReg) {
2461 MonoInst *loc = cfg->arch.vret_addr_loc;
2462
2463 /* Load the destination address */
2464 g_assert (loc->opcode == OP_REGOFFSET);
2465 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2466
2467 for (quad = 0; quad < 2; quad ++) {
2468 switch (cinfo->ret.pair_storage [quad]) {
2469 case ArgInIReg:
2470 amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2471 break;
2472 case ArgInFloatSSEReg:
2473 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2474 break;
2475 case ArgInDoubleSSEReg:
2476 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2477 break;
2478 case ArgNone:
2479 break;
2480 default:
2481 NOT_IMPLEMENTED;
2482 }
2483 }
2484 }
2485 break;
2486 }
2487
2488 return code;
2489 }
2490
2491 /*
2492 * mono_amd64_emit_tls_get:
2493 * @code: buffer to store code to
2494 * @dreg: hard register where to place the result
2495 * @tls_offset: offset info
2496 *
2497 * mono_amd64_emit_tls_get emits in @code the native code that puts in
2498 * the dreg register the item in the thread local storage identified
2499 * by tls_offset.
2500 *
2501 * Returns: a pointer to the end of the stored code
2502 */
2503 guint8*
2504 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2505 {
2506 #ifdef PLATFORM_WIN32
2507 g_assert (tls_offset < 64);
2508 x86_prefix (code, X86_GS_PREFIX);
2509 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2510 #else
2511 if (optimize_for_xen) {
2512 x86_prefix (code, X86_FS_PREFIX);
2513 amd64_mov_reg_mem (code, dreg, 0, 8);
2514 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2515 } else {
2516 x86_prefix (code, X86_FS_PREFIX);
2517 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2518 }
2519 #endif
2520 return code;
2521 }
2522
2523 #define REAL_PRINT_REG(text,reg) \
2524 mono_assert (reg >= 0); \
2525 amd64_push_reg (code, AMD64_RAX); \
2526 amd64_push_reg (code, AMD64_RDX); \
2527 amd64_push_reg (code, AMD64_RCX); \
2528 amd64_push_reg (code, reg); \
2529 amd64_push_imm (code, reg); \
2530 amd64_push_imm (code, text " %d %p\n"); \
2531 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2532 amd64_call_reg (code, AMD64_RAX); \
2533 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2534 amd64_pop_reg (code, AMD64_RCX); \
2535 amd64_pop_reg (code, AMD64_RDX); \
2536 amd64_pop_reg (code, AMD64_RAX);
2537
2538 /* benchmark and set based on cpu */
2539 #define LOOP_ALIGNMENT 8
2540 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2541
2542 #ifndef DISABLE_JIT
2543
2544 void
2545 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2546 {
2547 MonoInst *ins;
2548 MonoCallInst *call;
2549 guint offset;
2550 guint8 *code = cfg->native_code + cfg->code_len;
2551 MonoInst *last_ins = NULL;
2552 guint last_offset = 0;
2553 int max_len, cpos;
2554
2555 if (cfg->opt & MONO_OPT_LOOP) {
2556 int pad, align = LOOP_ALIGNMENT;
2557 /* set alignment depending on cpu */
2558 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2559 pad = align - pad;
2560 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2561 amd64_padding (code, pad);
2562 cfg->code_len += pad;
2563 bb->native_offset = cfg->code_len;
2564 }
2565 }
2566
2567 if (cfg->verbose_level > 2)
2568 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2569
2570 cpos = bb->max_offset;
2571
2572 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2573 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2574 g_assert (!cfg->compile_aot);
2575 cpos += 6;
2576
2577 cov->data [bb->dfn].cil_code = bb->cil_code;
2578 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2579 /* this is not thread save, but good enough */
2580 amd64_inc_membase (code, AMD64_R11, 0);
2581 }
2582
2583 offset = code - cfg->native_code;
2584
2585 mono_debug_open_block (cfg, bb, offset);
2586
2587 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2588 x86_breakpoint (code);
2589
2590 MONO_BB_FOR_EACH_INS (bb, ins) {
2591 offset = code - cfg->native_code;
2592
2593 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2594
2595 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2596 cfg->code_size *= 2;
2597 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2598 code = cfg->native_code + offset;
2599 mono_jit_stats.code_reallocs++;
2600 }
2601
2602 if (cfg->debug_info)
2603 mono_debug_record_line_number (cfg, ins, offset);
2604
2605 switch (ins->opcode) {
2606 case OP_BIGMUL:
2607 amd64_mul_reg (code, ins->sreg2, TRUE);
2608 break;
2609 case OP_BIGMUL_UN:
2610 amd64_mul_reg (code, ins->sreg2, FALSE);
2611 break;
2612 case OP_X86_SETEQ_MEMBASE:
2613 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2614 break;
2615 case OP_STOREI1_MEMBASE_IMM:
2616 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2617 break;
2618 case OP_STOREI2_MEMBASE_IMM:
2619 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2620 break;
2621 case OP_STOREI4_MEMBASE_IMM:
2622 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2623 break;
2624 case OP_STOREI1_MEMBASE_REG:
2625 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2626 break;
2627 case OP_STOREI2_MEMBASE_REG:
2628 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2629 break;
2630 case OP_STORE_MEMBASE_REG:
2631 case OP_STOREI8_MEMBASE_REG:
2632 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2633 break;
2634 case OP_STOREI4_MEMBASE_REG:
2635 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2636 break;
2637 case OP_STORE_MEMBASE_IMM:
2638 case OP_STOREI8_MEMBASE_IMM:
2639 g_assert (amd64_is_imm32 (ins->inst_imm));
2640 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2641 break;
2642 case OP_LOAD_MEM:
2643 case OP_LOADI8_MEM:
2644 // FIXME: Decompose this earlier
2645 if (amd64_is_imm32 (ins->inst_imm))
2646 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2647 else {
2648 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2649 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2650 }
2651 break;
2652 case OP_LOADI4_MEM:
2653 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2654 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2655 break;
2656 case OP_LOADU4_MEM:
2657 // FIXME: Decompose this earlier
2658 if (amd64_is_imm32 (ins->inst_imm))
2659 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2660 else {
2661 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2662 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2663 }
2664 break;
2665 case OP_LOADU1_MEM:
2666 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2667 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2668 break;
2669 case OP_LOADU2_MEM:
2670 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2671 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2672 break;
2673 case OP_LOAD_MEMBASE:
2674 case OP_LOADI8_MEMBASE:
2675 g_assert (amd64_is_imm32 (ins->inst_offset));
2676 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2677 break;
2678 case OP_LOADI4_MEMBASE:
2679 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2680 break;
2681 case OP_LOADU4_MEMBASE:
2682 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2683 break;
2684 case OP_LOADU1_MEMBASE:
2685 /* The cpu zero extends the result into 64 bits */
2686 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2687 break;
2688 case OP_LOADI1_MEMBASE:
2689 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2690 break;
2691 case OP_LOADU2_MEMBASE:
2692 /* The cpu zero extends the result into 64 bits */
2693 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2694 break;
2695 case OP_LOADI2_MEMBASE:
2696 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2697 break;
2698 case OP_AMD64_LOADI8_MEMINDEX:
2699 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2700 break;
2701 case OP_LCONV_TO_I1:
2702 case OP_ICONV_TO_I1:
2703 case OP_SEXT_I1:
2704 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2705 break;
2706 case OP_LCONV_TO_I2:
2707 case OP_ICONV_TO_I2:
2708 case OP_SEXT_I2:
2709 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2710 break;
2711 case OP_LCONV_TO_U1:
2712 case OP_ICONV_TO_U1:
2713 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2714 break;
2715 case OP_LCONV_TO_U2:
2716 case OP_ICONV_TO_U2:
2717 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2718 break;
2719 case OP_ZEXT_I4:
2720 /* Clean out the upper word */
2721 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2722 break;
2723 case OP_SEXT_I4:
2724 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2725 break;
2726 case OP_COMPARE:
2727 case OP_LCOMPARE:
2728 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2729 break;
2730 case OP_COMPARE_IMM:
2731 case OP_LCOMPARE_IMM:
2732 g_assert (amd64_is_imm32 (ins->inst_imm));
2733 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2734 break;
2735 case OP_X86_COMPARE_REG_MEMBASE:
2736 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2737 break;
2738 case OP_X86_TEST_NULL:
2739 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2740 break;
2741 case OP_AMD64_TEST_NULL:
2742 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2743 break;
2744
2745 case OP_X86_ADD_REG_MEMBASE:
2746 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2747 break;
2748 case OP_X86_SUB_REG_MEMBASE:
2749 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2750 break;
2751 case OP_X86_AND_REG_MEMBASE:
2752 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2753 break;
2754 case OP_X86_OR_REG_MEMBASE:
2755 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2756 break;
2757 case OP_X86_XOR_REG_MEMBASE:
2758 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2759 break;
2760
2761 case OP_X86_ADD_MEMBASE_IMM:
2762 /* FIXME: Make a 64 version too */
2763 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2764 break;
2765 case OP_X86_SUB_MEMBASE_IMM:
2766 g_assert (amd64_is_imm32 (ins->inst_imm));
2767 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2768 break;
2769 case OP_X86_AND_MEMBASE_IMM:
2770 g_assert (amd64_is_imm32 (ins->inst_imm));
2771 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2772 break;
2773 case OP_X86_OR_MEMBASE_IMM:
2774 g_assert (amd64_is_imm32 (ins->inst_imm));
2775 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2776 break;
2777 case OP_X86_XOR_MEMBASE_IMM:
2778 g_assert (amd64_is_imm32 (ins->inst_imm));
2779 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2780 break;
2781 case OP_X86_ADD_MEMBASE_REG:
2782 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2783 break;
2784 case OP_X86_SUB_MEMBASE_REG:
2785 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2786 break;
2787 case OP_X86_AND_MEMBASE_REG:
2788 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2789 break;
2790 case OP_X86_OR_MEMBASE_REG:
2791 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2792 break;
2793 case OP_X86_XOR_MEMBASE_REG:
2794 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2795 break;
2796 case OP_X86_INC_MEMBASE:
2797 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2798 break;
2799 case OP_X86_INC_REG:
2800 amd64_inc_reg_size (code, ins->dreg, 4);
2801 break;
2802 case OP_X86_DEC_MEMBASE:
2803 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2804 break;
2805 case OP_X86_DEC_REG:
2806 amd64_dec_reg_size (code, ins->dreg, 4);
2807 break;
2808 case OP_X86_MUL_REG_MEMBASE:
2809 case OP_X86_MUL_MEMBASE_REG:
2810 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2811 break;
2812 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2813 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2814 break;
2815 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2816 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2817 break;
2818 case OP_AMD64_COMPARE_MEMBASE_REG:
2819 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2820 break;
2821 case OP_AMD64_COMPARE_MEMBASE_IMM:
2822 g_assert (amd64_is_imm32 (ins->inst_imm));
2823 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2824 break;
2825 case OP_X86_COMPARE_MEMBASE8_IMM:
2826 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2827 break;
2828 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2829 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2830 break;
2831 case OP_AMD64_COMPARE_REG_MEMBASE:
2832 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2833 break;
2834
2835 case OP_AMD64_ADD_REG_MEMBASE:
2836 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2837 break;
2838 case OP_AMD64_SUB_REG_MEMBASE:
2839 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2840 break;
2841 case OP_AMD64_AND_REG_MEMBASE:
2842 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2843 break;
2844 case OP_AMD64_OR_REG_MEMBASE:
2845 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2846 break;
2847 case OP_AMD64_XOR_REG_MEMBASE:
2848 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2849 break;
2850
2851 case OP_AMD64_ADD_MEMBASE_REG:
2852 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2853 break;
2854 case OP_AMD64_SUB_MEMBASE_REG:
2855 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2856 break;
2857 case OP_AMD64_AND_MEMBASE_REG:
2858 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2859 break;
2860 case OP_AMD64_OR_MEMBASE_REG:
2861 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2862 break;
2863 case OP_AMD64_XOR_MEMBASE_REG:
2864 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2865 break;
2866
2867 case OP_AMD64_ADD_MEMBASE_IMM:
2868 g_assert (amd64_is_imm32 (ins->inst_imm));
2869 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2870 break;
2871 case OP_AMD64_SUB_MEMBASE_IMM:
2872 g_assert (amd64_is_imm32 (ins->inst_imm));
2873 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2874 break;
2875 case OP_AMD64_AND_MEMBASE_IMM:
2876 g_assert (amd64_is_imm32 (ins->inst_imm));
2877 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2878 break;
2879 case OP_AMD64_OR_MEMBASE_IMM:
2880 g_assert (amd64_is_imm32 (ins->inst_imm));
2881 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2882 break;
2883 case OP_AMD64_XOR_MEMBASE_IMM:
2884 g_assert (amd64_is_imm32 (ins->inst_imm));
2885 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2886 break;
2887
2888 case OP_BREAK:
2889 amd64_breakpoint (code);
2890 break;
2891 case OP_RELAXED_NOP:
2892 x86_prefix (code, X86_REP_PREFIX);
2893 x86_nop (code);
2894 break;
2895 case OP_HARD_NOP:
2896 x86_nop (code);
2897 break;
2898 case OP_NOP:
2899 case OP_DUMMY_USE:
2900 case OP_DUMMY_STORE:
2901 case OP_NOT_REACHED:
2902 case OP_NOT_NULL:
2903 break;
2904 case OP_ADDCC:
2905 case OP_LADD:
2906 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2907 break;
2908 case OP_ADC:
2909 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2910 break;
2911 case OP_ADD_IMM:
2912 case OP_LADD_IMM:
2913 g_assert (amd64_is_imm32 (ins->inst_imm));
2914 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2915 break;
2916 case OP_ADC_IMM:
2917 g_assert (amd64_is_imm32 (ins->inst_imm));
2918 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2919 break;
2920 case OP_SUBCC:
2921 case OP_LSUB:
2922 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2923 break;
2924 case OP_SBB:
2925 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2926 break;
2927 case OP_SUB_IMM:
2928 case OP_LSUB_IMM:
2929 g_assert (amd64_is_imm32 (ins->inst_imm));
2930 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2931 break;
2932 case OP_SBB_IMM:
2933 g_assert (amd64_is_imm32 (ins->inst_imm));
2934 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2935 break;
2936 case OP_LAND:
2937 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2938 break;
2939 case OP_AND_IMM:
2940 case OP_LAND_IMM:
2941 g_assert (amd64_is_imm32 (ins->inst_imm));
2942 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2943 break;
2944 case OP_LMUL:
2945 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2946 break;
2947 case OP_MUL_IMM:
2948 case OP_LMUL_IMM:
2949 case OP_IMUL_IMM: {
2950 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2951
2952 switch (ins->inst_imm) {
2953 case 2:
2954 /* MOV r1, r2 */
2955 /* ADD r1, r1 */
2956 if (ins->dreg != ins->sreg1)
2957 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2958 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2959 break;
2960 case 3:
2961 /* LEA r1, [r2 + r2*2] */
2962 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2963 break;
2964 case 5:
2965 /* LEA r1, [r2 + r2*4] */
2966 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2967 break;
2968 case 6:
2969 /* LEA r1, [r2 + r2*2] */
2970 /* ADD r1, r1 */
2971 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2972 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2973 break;
2974 case 9:
2975 /* LEA r1, [r2 + r2*8] */
2976 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2977 break;
2978 case 10:
2979 /* LEA r1, [r2 + r2*4] */
2980 /* ADD r1, r1 */
2981 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2982 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2983 break;
2984 case 12:
2985 /* LEA r1, [r2 + r2*2] */
2986 /* SHL r1, 2 */
2987 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2988 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2989 break;
2990 case 25:
2991 /* LEA r1, [r2 + r2*4] */
2992 /* LEA r1, [r1 + r1*4] */
2993 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2994 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2995 break;
2996 case 100:
2997 /* LEA r1, [r2 + r2*4] */
2998 /* SHL r1, 2 */
2999 /* LEA r1, [r1 + r1*4] */
3000 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3001 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3002 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3003 break;
3004 default:
3005 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3006 break;
3007 }
3008 break;
3009 }
3010 case OP_LDIV:
3011 case OP_LREM:
3012 /* Regalloc magic makes the div/rem cases the same */
3013 if (ins->sreg2 == AMD64_RDX) {
3014 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3015 amd64_cdq (code);
3016 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3017 } else {
3018 amd64_cdq (code);
3019 amd64_div_reg (code, ins->sreg2, TRUE);
3020 }
3021 break;
3022 case OP_LDIV_UN:
3023 case OP_LREM_UN:
3024 if (ins->sreg2 == AMD64_RDX) {
3025 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3026 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3027 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3028 } else {
3029 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3030 amd64_div_reg (code, ins->sreg2, FALSE);
3031 }
3032 break;
3033 case OP_IDIV:
3034 case OP_IREM:
3035 if (ins->sreg2 == AMD64_RDX) {
3036 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3037 amd64_cdq_size (code, 4);
3038 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3039 } else {
3040 amd64_cdq_size (code, 4);
3041 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3042 }
3043 break;
3044 case OP_IDIV_UN:
3045 case OP_IREM_UN:
3046 if (ins->sreg2 == AMD64_RDX) {
3047 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3048 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3049 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3050 } else {
3051 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3052 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3053 }
3054 break;
3055 case OP_IREM_IMM: {
3056 int power = mono_is_power_of_two (ins->inst_imm);
3057
3058 g_assert (ins->sreg1 == X86_EAX);
3059 g_assert (ins->dreg == X86_EAX);
3060 g_assert (power >= 0);
3061
3062 /* Based on gcc code */
3063
3064 /* Add compensation for negative dividents */
3065 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3066 if (power > 1)
3067 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3068 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3069 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3070 /* Compute remainder */
3071 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3072 /* Remove compensation */
3073 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3074 break;
3075 }
3076 case OP_LMUL_OVF:
3077 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3078 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3079 break;
3080 case OP_LOR:
3081 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3082 break;
3083 case OP_OR_IMM:
3084 case OP_LOR_IMM:
3085 g_assert (amd64_is_imm32 (ins->inst_imm));
3086 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3087 break;
3088 case OP_LXOR:
3089 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3090 break;
3091 case OP_XOR_IMM:
3092 case OP_LXOR_IMM:
3093 g_assert (amd64_is_imm32 (ins->inst_imm));
3094 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3095 break;
3096 case OP_LSHL:
3097 g_assert (ins->sreg2 == AMD64_RCX);
3098 amd64_shift_reg (code, X86_SHL, ins->dreg);
3099 break;
3100 case OP_LSHR:
3101 g_assert (ins->sreg2 == AMD64_RCX);
3102 amd64_shift_reg (code, X86_SAR, ins->dreg);
3103 break;
3104 case OP_SHR_IMM:
3105 g_assert (amd64_is_imm32 (ins->inst_imm));
3106 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3107 break;
3108 case OP_LSHR_IMM:
3109 g_assert (amd64_is_imm32 (ins->inst_imm));
3110 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3111 break;
3112 case OP_SHR_UN_IMM:
3113 g_assert (amd64_is_imm32 (ins->inst_imm));
3114 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3115 break;
3116 case OP_LSHR_UN_IMM:
3117 g_assert (amd64_is_imm32 (ins->inst_imm));
3118 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3119 break;
3120 case OP_LSHR_UN:
3121 g_assert (ins->sreg2 == AMD64_RCX);
3122 amd64_shift_reg (code, X86_SHR, ins->dreg);
3123 break;
3124 case OP_SHL_IMM:
3125 g_assert (amd64_is_imm32 (ins->inst_imm));
3126 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3127 break;
3128 case OP_LSHL_IMM:
3129 g_assert (amd64_is_imm32 (ins->inst_imm));
3130 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3131 break;
3132
3133 case OP_IADDCC:
3134 case OP_IADD:
3135 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3136 break;
3137 case OP_IADC:
3138 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3139 break;
3140 case OP_IADD_IMM:
3141 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3142 break;
3143 case OP_IADC_IMM:
3144 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3145 break;
3146 case OP_ISUBCC:
3147 case OP_ISUB:
3148 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3149 break;
3150 case OP_ISBB:
3151 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3152 break;
3153 case OP_ISUB_IMM:
3154 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3155 break;
3156 case OP_ISBB_IMM:
3157 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3158 break;
3159 case OP_IAND:
3160 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3161 break;
3162 case OP_IAND_IMM:
3163 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3164 break;
3165 case OP_IOR:
3166 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3167 break;
3168 case OP_IOR_IMM:
3169 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3170 break;
3171 case OP_IXOR:
3172 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3173 break;
3174 case OP_IXOR_IMM:
3175 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3176 break;
3177 case OP_INEG:
3178 amd64_neg_reg_size (code, ins->sreg1, 4);
3179 break;
3180 case OP_INOT:
3181 amd64_not_reg_size (code, ins->sreg1, 4);
3182 break;
3183 case OP_ISHL:
3184 g_assert (ins->sreg2 == AMD64_RCX);
3185 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3186 break;
3187 case OP_ISHR:
3188 g_assert (ins->sreg2 == AMD64_RCX);
3189 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3190 break;
3191 case OP_ISHR_IMM:
3192 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3193 break;
3194 case OP_ISHR_UN_IMM:
3195 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3196 break;
3197 case OP_ISHR_UN:
3198 g_assert (ins->sreg2 == AMD64_RCX);
3199 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3200 break;
3201 case OP_ISHL_IMM:
3202 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3203 break;
3204 case OP_IMUL:
3205 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3206 break;
3207 case OP_IMUL_OVF:
3208 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3209 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3210 break;
3211 case OP_IMUL_OVF_UN:
3212 case OP_LMUL_OVF_UN: {
3213 /* the mul operation and the exception check should most likely be split */
3214 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3215 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3216 /*g_assert (ins->sreg2 == X86_EAX);
3217 g_assert (ins->dreg == X86_EAX);*/
3218 if (ins->sreg2 == X86_EAX) {
3219 non_eax_reg = ins->sreg1;
3220 } else if (ins->sreg1 == X86_EAX) {
3221 non_eax_reg = ins->sreg2;
3222 } else {
3223 /* no need to save since we're going to store to it anyway */
3224 if (ins->dreg != X86_EAX) {
3225 saved_eax = TRUE;
3226 amd64_push_reg (code, X86_EAX);
3227 }
3228 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3229 non_eax_reg = ins->sreg2;
3230 }
3231 if (ins->dreg == X86_EDX) {
3232 if (!saved_eax) {
3233 saved_eax = TRUE;
3234 amd64_push_reg (code, X86_EAX);
3235 }
3236 } else {
3237 saved_edx = TRUE;
3238 amd64_push_reg (code, X86_EDX);
3239 }
3240 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3241 /* save before the check since pop and mov don't change the flags */
3242 if (ins->dreg != X86_EAX)
3243 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3244 if (saved_edx)
3245 amd64_pop_reg (code, X86_EDX);
3246 if (saved_eax)
3247 amd64_pop_reg (code, X86_EAX);
3248 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3249 break;
3250 }
3251 case OP_ICOMPARE:
3252 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3253 break;
3254 case OP_ICOMPARE_IMM:
3255 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3256 break;
3257 case OP_IBEQ:
3258 case OP_IBLT:
3259 case OP_IBGT:
3260 case OP_IBGE:
3261 case OP_IBLE:
3262 case OP_LBEQ:
3263 case OP_LBLT:
3264 case OP_LBGT:
3265 case OP_LBGE:
3266 case OP_LBLE:
3267 case OP_IBNE_UN:
3268 case OP_IBLT_UN:
3269 case OP_IBGT_UN:
3270 case OP_IBGE_UN:
3271 case OP_IBLE_UN:
3272 case OP_LBNE_UN:
3273 case OP_LBLT_UN:
3274 case OP_LBGT_UN:
3275 case OP_LBGE_UN:
3276 case OP_LBLE_UN:
3277 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3278 break;
3279
3280 case OP_CMOV_IEQ:
3281 case OP_CMOV_IGE:
3282 case OP_CMOV_IGT:
3283 case OP_CMOV_ILE:
3284 case OP_CMOV_ILT:
3285 case OP_CMOV_INE_UN:
3286 case OP_CMOV_IGE_UN:
3287 case OP_CMOV_IGT_UN:
3288 case OP_CMOV_ILE_UN:
3289 case OP_CMOV_ILT_UN:
3290 case OP_CMOV_LEQ:
3291 case OP_CMOV_LGE:
3292 case OP_CMOV_LGT:
3293 case OP_CMOV_LLE:
3294 case OP_CMOV_LLT:
3295 case OP_CMOV_LNE_UN:
3296 case OP_CMOV_LGE_UN:
3297 case OP_CMOV_LGT_UN:
3298 case OP_CMOV_LLE_UN:
3299 case OP_CMOV_LLT_UN:
3300 g_assert (ins->dreg == ins->sreg1);
3301 /* This needs to operate on 64 bit values */
3302 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3303 break;
3304
3305 case OP_LNOT:
3306 amd64_not_reg (code, ins->sreg1);
3307 break;
3308 case OP_LNEG:
3309 amd64_neg_reg (code, ins->sreg1);
3310 break;
3311
3312 case OP_ICONST:
3313 case OP_I8CONST:
3314 if ((((guint64)ins->inst_c0) >> 32) == 0)
3315 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3316 else
3317 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3318 break;
3319 case OP_AOTCONST:
3320 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3321 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3322 break;
3323 case OP_JUMP_TABLE:
3324 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3325 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3326 break;
3327 case OP_MOVE:
3328 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3329 break;
3330 case OP_AMD64_SET_XMMREG_R4: {
3331 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3332 break;
3333 }
3334 case OP_AMD64_SET_XMMREG_R8: {
3335 if (ins->dreg != ins->sreg1)
3336 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3337 break;
3338 }
3339 case OP_TAILCALL: {
3340 /*
3341 * Note: this 'frame destruction' logic is useful for tail calls, too.
3342 * Keep in sync with the code in emit_epilog.
3343 */
3344 int pos = 0, i;
3345
3346 /* FIXME: no tracing support... */
3347 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3348 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3349
3350 g_assert (!cfg->method->save_lmf);
3351
3352 if (cfg->arch.omit_fp) {
3353 guint32 save_offset = 0;
3354 /* Pop callee-saved registers */
3355 for (i = 0; i < AMD64_NREG; ++i)
3356 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3357 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3358 save_offset += 8;
3359 }
3360 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3361 }
3362 else {
3363 for (i = 0; i < AMD64_NREG; ++i)
3364 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3365 pos -= sizeof (gpointer);
3366
3367 if (pos)
3368 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3369
3370 /* Pop registers in reverse order */
3371 for (i = AMD64_NREG - 1; i > 0; --i)
3372 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3373 amd64_pop_reg (code, i);
3374 }
3375
3376 amd64_leave (code);
3377 }
3378
3379 offset = code - cfg->native_code;
3380 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3381 if (cfg->compile_aot)
3382 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3383 else
3384 amd64_set_reg_template (code, AMD64_R11);
3385 amd64_jump_reg (code, AMD64_R11);
3386 break;
3387 }
3388 case OP_CHECK_THIS:
3389 /* ensure ins->sreg1 is not NULL */
3390 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3391 break;
3392 case OP_ARGLIST: {
3393 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3394 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3395 break;
3396 }
3397 case OP_CALL:
3398 case OP_FCALL:
3399 case OP_LCALL:
3400 case OP_VCALL:
3401 case OP_VCALL2:
3402 case OP_VOIDCALL:
3403 call = (MonoCallInst*)ins;
3404 /*
3405 * The AMD64 ABI forces callers to know about varargs.
3406 */
3407 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3408 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3409 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3410 /*
3411 * Since the unmanaged calling convention doesn't contain a
3412 * 'vararg' entry, we have to treat every pinvoke call as a
3413 * potential vararg call.
3414 */
3415 guint32 nregs, i;
3416 nregs = 0;
3417 for (i = 0; i < AMD64_XMM_NREG; ++i)
3418 if (call->used_fregs & (1 << i))
3419 nregs ++;
3420 if (!nregs)
3421 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3422 else
3423 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3424 }
3425
3426 if (ins->flags & MONO_INST_HAS_METHOD)
3427 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3428 else
3429 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3430 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3431 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3432 code = emit_move_return_value (cfg, ins, code);
3433 break;
3434 case OP_FCALL_REG:
3435 case OP_LCALL_REG:
3436 case OP_VCALL_REG:
3437 case OP_VCALL2_REG:
3438 case OP_VOIDCALL_REG:
3439 case OP_CALL_REG:
3440 call = (MonoCallInst*)ins;
3441
3442 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3443 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3444 ins->sreg1 = AMD64_R11;
3445 }
3446
3447 /*
3448 * The AMD64 ABI forces callers to know about varargs.
3449 */
3450 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3451 if (ins->sreg1 == AMD64_RAX) {
3452 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3453 ins->sreg1 = AMD64_R11;
3454 }
3455 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3456 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3457 /*
3458 * Since the unmanaged calling convention doesn't contain a
3459 * 'vararg' entry, we have to treat every pinvoke call as a
3460 * potential vararg call.
3461 */
3462 guint32 nregs, i;
3463 nregs = 0;
3464 for (i = 0; i < AMD64_XMM_NREG; ++i)
3465 if (call->used_fregs & (1 << i))
3466 nregs ++;
3467 if (ins->sreg1 == AMD64_RAX) {
3468 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3469 ins->sreg1 = AMD64_R11;
3470 }
3471 if (!nregs)
3472 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3473 else
3474 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3475 }
3476
3477 amd64_call_reg (code, ins->sreg1);
3478 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3479 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3480 code = emit_move_return_value (cfg, ins, code);
3481 break;
3482 case OP_FCALL_MEMBASE:
3483 case OP_LCALL_MEMBASE:
3484 case OP_VCALL_MEMBASE:
3485 case OP_VCALL2_MEMBASE:
3486 case OP_VOIDCALL_MEMBASE:
3487 case OP_CALL_MEMBASE:
3488 call = (MonoCallInst*)ins;
3489
3490 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3491 /*
3492 * Can't use R11 because it is clobbered by the trampoline
3493 * code, and the reg value is needed by get_vcall_slot_addr.
3494 */
3495 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3496 ins->sreg1 = AMD64_RAX;
3497 }
3498
3499 if (call->method && ins->inst_offset < 0) {
3500 gssize val;
3501
3502 /*
3503 * This is a possible IMT call so save the IMT method in the proper
3504 * register. We don't use the generic code in method-to-ir.c, because
3505 * we need to disassemble this in get_vcall_slot_addr (), so we have to
3506 * maintain control over the layout of the code.
3507 * Also put the base reg in %rax to simplify find_imt_method ().
3508 */
3509 if (ins->sreg1 != AMD64_RAX) {
3510 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3511 ins->sreg1 = AMD64_RAX;
3512 }
3513 val = (gssize)(gpointer)call->method;
3514
3515 // FIXME: Generics sharing
3516 #if 0
3517 if ((((guint64)val) >> 32) == 0)
3518 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3519 else
3520 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3521 #endif
3522 }
3523
3524 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3525 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3526 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3527 code = emit_move_return_value (cfg, ins, code);
3528 break;
3529 case OP_AMD64_SAVE_SP_TO_LMF:
3530 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3531 break;
3532 case OP_X86_PUSH:
3533 amd64_push_reg (code, ins->sreg1);
3534 break;
3535 case OP_X86_PUSH_IMM:
3536 g_assert (amd64_is_imm32 (ins->inst_imm));
3537 amd64_push_imm (code, ins->inst_imm);
3538 break;
3539 case OP_X86_PUSH_MEMBASE:
3540 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3541 break;
3542 case OP_X86_PUSH_OBJ: {
3543 int size = ALIGN_TO (ins->inst_imm, 8);
3544 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3545 amd64_push_reg (code, AMD64_RDI);
3546 amd64_push_reg (code, AMD64_RSI);
3547 amd64_push_reg (code, AMD64_RCX);
3548 if (ins->inst_offset)
3549 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3550 else
3551 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3552 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3553 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3554 amd64_cld (code);
3555 amd64_prefix (code, X86_REP_PREFIX);
3556 amd64_movsd (code);
3557 amd64_pop_reg (code, AMD64_RCX);
3558 amd64_pop_reg (code, AMD64_RSI);
3559 amd64_pop_reg (code, AMD64_RDI);
3560 break;
3561 }
3562 case OP_X86_LEA:
3563 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3564 break;
3565 case OP_X86_LEA_MEMBASE:
3566 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3567 break;
3568 case OP_X86_XCHG:
3569 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3570 break;
3571 case OP_LOCALLOC:
3572 /* keep alignment */
3573 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3574 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3575 code = mono_emit_stack_alloc (code, ins);
3576 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3577 break;
3578 case OP_LOCALLOC_IMM: {
3579 guint32 size = ins->inst_imm;
3580 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3581
3582 if (ins->flags & MONO_INST_INIT) {
3583 if (size < 64) {
3584 int i;
3585
3586 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3587 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3588
3589 for (i = 0; i < size; i += 8)
3590 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3591 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3592 } else {
3593 amd64_mov_reg_imm (code, ins->dreg, size);
3594 ins->sreg1 = ins->dreg;
3595
3596 code = mono_emit_stack_alloc (code, ins);
3597 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3598 }
3599 } else {
3600 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3601 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3602 }
3603 break;
3604 }
3605 case OP_THROW: {
3606 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3607 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3608 (gpointer)"mono_arch_throw_exception", FALSE);
3609 break;
3610 }
3611 case OP_RETHROW: {
3612 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3613 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3614 (gpointer)"mono_arch_rethrow_exception", FALSE);
3615 break;
3616 }
3617 case OP_CALL_HANDLER:
3618 /* Align stack */
3619 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3620 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3621 amd64_call_imm (code, 0);
3622 /* Restore stack alignment */
3623 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3624 break;
3625 case OP_START_HANDLER: {
3626 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3627 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3628 break;
3629 }
3630 case OP_ENDFINALLY: {
3631 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3632 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3633 amd64_ret (code);
3634 break;
3635 }
3636 case OP_ENDFILTER: {
3637 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3638 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3639 /* The local allocator will put the result into RAX */
3640 amd64_ret (code);
3641 break;
3642 }
3643
3644 case OP_LABEL:
3645 ins->inst_c0 = code - cfg->native_code;
3646 break;
3647 case OP_BR:
3648 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3649 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3650 //break;
3651 if (ins->flags & MONO_INST_BRLABEL) {
3652 if (ins->inst_i0->inst_c0) {
3653 amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3654 } else {
3655 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3656 if ((cfg->opt & MONO_OPT_BRANCH) &&
3657 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3658 x86_jump8 (code, 0);
3659 else
3660 x86_jump32 (code, 0);
3661 }
3662 } else {
3663 if (ins->inst_target_bb->native_offset) {
3664 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3665 } else {
3666 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3667 if ((cfg->opt & MONO_OPT_BRANCH) &&
3668 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3669 x86_jump8 (code, 0);
3670 else
3671 x86_jump32 (code, 0);
3672 }
3673 }
3674 break;
3675 case OP_BR_REG:
3676 amd64_jump_reg (code, ins->sreg1);
3677 break;
3678 case OP_CEQ:
3679 case OP_LCEQ:
3680 case OP_ICEQ:
3681 case OP_CLT:
3682 case OP_LCLT:
3683 case OP_ICLT:
3684 case OP_CGT:
3685 case OP_ICGT:
3686 case OP_LCGT:
3687 case OP_CLT_UN:
3688 case OP_LCLT_UN:
3689 case OP_ICLT_UN:
3690 case OP_CGT_UN:
3691 case OP_LCGT_UN:
3692 case OP_ICGT_UN:
3693 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3694 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3695 break;
3696 case OP_COND_EXC_EQ:
3697 case OP_COND_EXC_NE_UN:
3698 case OP_COND_EXC_LT:
3699 case OP_COND_EXC_LT_UN:
3700 case OP_COND_EXC_GT:
3701 case OP_COND_EXC_GT_UN:
3702 case OP_COND_EXC_GE:
3703 case OP_COND_EXC_GE_UN:
3704 case OP_COND_EXC_LE:
3705 case OP_COND_EXC_LE_UN:
3706 case OP_COND_EXC_IEQ:
3707 case OP_COND_EXC_INE_UN:
3708 case OP_COND_EXC_ILT:
3709 case OP_COND_EXC_ILT_UN:
3710 case OP_COND_EXC_IGT:
3711 case OP_COND_EXC_IGT_UN:
3712 case OP_COND_EXC_IGE:
3713 case OP_COND_EXC_IGE_UN:
3714 case OP_COND_EXC_ILE:
3715 case OP_COND_EXC_ILE_UN:
3716 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3717 break;
3718 case OP_COND_EXC_OV:
3719 case OP_COND_EXC_NO:
3720 case OP_COND_EXC_C:
3721 case OP_COND_EXC_NC:
3722 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3723 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3724 break;
3725 case OP_COND_EXC_IOV:
3726 case OP_COND_EXC_INO:
3727 case OP_COND_EXC_IC:
3728 case OP_COND_EXC_INC:
3729 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3730 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3731 break;
3732
3733 /* floating point opcodes */
3734 case OP_R8CONST: {
3735 double d = *(double *)ins->inst_p0;
3736
3737 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3738 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3739 }
3740 else {
3741 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3742 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3743 }
3744 break;
3745 }
3746 case OP_R4CONST: {
3747 float f = *(float *)ins->inst_p0;
3748
3749 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3750 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3751 }
3752 else {
3753 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3754 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3755 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3756 }
3757 break;
3758 }
3759 case OP_STORER8_MEMBASE_REG:
3760 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3761 break;
3762 case OP_LOADR8_SPILL_MEMBASE:
3763 g_assert_not_reached ();
3764 break;
3765 case OP_LOADR8_MEMBASE:
3766 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3767 break;
3768 case OP_STORER4_MEMBASE_REG:
3769 /* This requires a double->single conversion */
3770 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3771 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3772 break;
3773 case OP_LOADR4_MEMBASE:
3774 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3775 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3776 break;
3777 case OP_ICONV_TO_R4: /* FIXME: change precision */
3778 case OP_ICONV_TO_R8:
3779 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3780 break;
3781 case OP_LCONV_TO_R4: /* FIXME: change precision */
3782 case OP_LCONV_TO_R8:
3783 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3784 break;
3785 case OP_FCONV_TO_R4:
3786 /* FIXME: nothing to do ?? */
3787 break;
3788 case OP_FCONV_TO_I1:
3789 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3790 break;
3791 case OP_FCONV_TO_U1:
3792 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3793 break;
3794 case OP_FCONV_TO_I2:
3795 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3796 break;
3797 case OP_FCONV_TO_U2:
3798 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3799 break;
3800 case OP_FCONV_TO_U4:
3801 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3802 break;
3803 case OP_FCONV_TO_I4:
3804 case OP_FCONV_TO_I:
3805 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3806 break;
3807 case OP_FCONV_TO_I8:
3808 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3809 break;
3810 case OP_LCONV_TO_R_UN: {
3811 guint8 *br [2];
3812
3813 /* Based on gcc code */
3814 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3815 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3816
3817 /* Positive case */
3818 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3819 br [1] = code; x86_jump8 (code, 0);
3820 amd64_patch (br [0], code);
3821
3822 /* Negative case */
3823 /* Save to the red zone */
3824 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3825 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3826 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3827 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3828 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3829 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3830 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3831 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3832 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3833 /* Restore */
3834 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3835 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3836 amd64_patch (br [1], code);
3837 break;
3838 }
3839 case OP_LCONV_TO_OVF_U4:
3840 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3841 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3842 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3843 break;
3844 case OP_LCONV_TO_OVF_I4_UN:
3845 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3846 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3847 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3848 break;
3849 case OP_FMOVE:
3850 if (ins->dreg != ins->sreg1)
3851 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3852 break;
3853 case OP_FADD:
3854 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3855 break;
3856 case OP_FSUB:
3857 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3858 break;
3859 case OP_FMUL:
3860 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3861 break;
3862 case OP_FDIV:
3863 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3864 break;
3865 case OP_FNEG: {
3866 static double r8_0 = -0.0;
3867
3868 g_assert (ins->sreg1 == ins->dreg);
3869
3870 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3871 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3872 break;
3873 }
3874 case OP_SIN:
3875 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3876 break;
3877 case OP_COS:
3878 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3879 break;
3880 case OP_ABS: {
3881 static guint64 d = 0x7fffffffffffffffUL;
3882
3883 g_assert (ins->sreg1 == ins->dreg);
3884
3885 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3886 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3887 break;
3888 }
3889 case OP_SQRT:
3890 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3891 break;
3892 case OP_IMIN:
3893 g_assert (cfg->opt & MONO_OPT_CMOV);
3894 g_assert (ins->dreg == ins->sreg1);
3895 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3896 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3897 break;
3898 case OP_IMIN_UN:
3899 g_assert (cfg->opt & MONO_OPT_CMOV);
3900 g_assert (ins->dreg == ins->sreg1);
3901 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3902 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3903 break;
3904 case OP_IMAX:
3905 g_assert (cfg->opt & MONO_OPT_CMOV);
3906 g_assert (ins->dreg == ins->sreg1);
3907 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3908 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3909 break;
3910 case OP_IMAX_UN:
3911 g_assert (cfg->opt & MONO_OPT_CMOV);
3912 g_assert (ins->dreg == ins->sreg1);
3913 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3914 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3915 break;
3916 case OP_LMIN:
3917 g_assert (cfg->opt & MONO_OPT_CMOV);
3918 g_assert (ins->dreg == ins->sreg1);
3919 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3920 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3921 break;
3922 case OP_LMIN_UN:
3923 g_assert (cfg->opt & MONO_OPT_CMOV);
3924 g_assert (ins->dreg == ins->sreg1);
3925 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3926 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3927 break;
3928 case OP_LMAX:
3929 g_assert (cfg->opt & MONO_OPT_CMOV);
3930 g_assert (ins->dreg == ins->sreg1);
3931 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3932 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3933 break;
3934 case OP_LMAX_UN:
3935 g_assert (cfg->opt & MONO_OPT_CMOV);
3936 g_assert (ins->dreg == ins->sreg1);
3937 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3938 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3939 break;
3940 case OP_X86_FPOP:
3941 break;
3942 case OP_FCOMPARE:
3943 /*
3944 * The two arguments are swapped because the fbranch instructions
3945 * depend on this for the non-sse case to work.
3946 */
3947 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3948 break;
3949 case OP_FCEQ: {
3950 /* zeroing the register at the start results in
3951 * shorter and faster code (we can also remove the widening op)
3952 */
3953 guchar *unordered_check;
3954 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3955 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3956 unordered_check = code;
3957 x86_branch8 (code, X86_CC_P, 0, FALSE);
3958 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3959 amd64_patch (unordered_check, code);
3960 break;
3961 }
3962 case OP_FCLT:
3963 case OP_FCLT_UN:
3964 /* zeroing the register at the start results in
3965 * shorter and faster code (we can also remove the widening op)
3966 */
3967 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3968 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3969 if (ins->opcode == OP_FCLT_UN) {
3970 guchar *unordered_check = code;
3971 guchar *jump_to_end;
3972 x86_branch8 (code, X86_CC_P, 0, FALSE);
3973 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3974 jump_to_end = code;
3975 x86_jump8 (code, 0);
3976 amd64_patch (unordered_check, code);
3977 amd64_inc_reg (code, ins->dreg);
3978 amd64_patch (jump_to_end, code);
3979 } else {
3980 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3981 }
3982 break;
3983 case OP_FCGT:
3984 case OP_FCGT_UN: {
3985 /* zeroing the register at the start results in
3986 * shorter and faster code (we can also remove the widening op)
3987 */
3988 guchar *unordered_check;
3989 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3990 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3991 if (ins->opcode == OP_FCGT) {
3992 unordered_check = code;
3993 x86_branch8 (code, X86_CC_P, 0, FALSE);
3994 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3995 amd64_patch (unordered_check, code);
3996 } else {
3997 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3998 }
3999 break;
4000 }
4001 case OP_FCLT_MEMBASE:
4002 case OP_FCGT_MEMBASE:
4003 case OP_FCLT_UN_MEMBASE:
4004 case OP_FCGT_UN_MEMBASE:
4005 case OP_FCEQ_MEMBASE: {
4006 guchar *unordered_check, *jump_to_end;
4007 int x86_cond;
4008
4009 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4010 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4011
4012 switch (ins->opcode) {
4013 case OP_FCEQ_MEMBASE:
4014 x86_cond = X86_CC_EQ;
4015 break;
4016 case OP_FCLT_MEMBASE:
4017 case OP_FCLT_UN_MEMBASE:
4018 x86_cond = X86_CC_LT;
4019 break;
4020 case OP_FCGT_MEMBASE:
4021 case OP_FCGT_UN_MEMBASE:
4022 x86_cond = X86_CC_GT;
4023 break;
4024 default:
4025 g_assert_not_reached ();
4026 }
4027
4028 unordered_check = code;
4029 x86_branch8 (code, X86_CC_P, 0, FALSE);
4030 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4031
4032 switch (ins->opcode) {
4033 case OP_FCEQ_MEMBASE:
4034 case OP_FCLT_MEMBASE:
4035 case OP_FCGT_MEMBASE:
4036 amd64_patch (unordered_check, code);
4037 break;
4038 case OP_FCLT_UN_MEMBASE:
4039 case OP_FCGT_UN_MEMBASE:
4040 jump_to_end = code;
4041 x86_jump8 (code, 0);
4042 amd64_patch (unordered_check, code);
4043 amd64_inc_reg (code, ins->dreg);
4044 amd64_patch (jump_to_end, code);
4045 break;
4046 default:
4047 break;
4048 }
4049 break;
4050 }
4051 case OP_FBEQ: {
4052 guchar *jump = code;
4053 x86_branch8 (code, X86_CC_P, 0, TRUE);
4054 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4055 amd64_patch (jump, code);
4056 break;
4057 }
4058 case OP_FBNE_UN:
4059 /* Branch if C013 != 100 */
4060 /* branch if !ZF or (PF|CF) */
4061 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4062 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4063 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4064 break;
4065 case OP_FBLT:
4066 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4067 break;
4068 case OP_FBLT_UN:
4069 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4070 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4071 break;
4072 case OP_FBGT:
4073 case OP_FBGT_UN:
4074 if (ins->opcode == OP_FBGT) {
4075 guchar *br1;
4076
4077 /* skip branch if C1=1 */
4078 br1 = code;
4079 x86_branch8 (code, X86_CC_P, 0, FALSE);
4080 /* branch if (C0 | C3) = 1 */
4081 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4082 amd64_patch (br1, code);
4083 break;
4084 } else {
4085 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4086 }
4087 break;
4088 case OP_FBGE: {
4089 /* Branch if C013 == 100 or 001 */
4090 guchar *br1;
4091
4092 /* skip branch if C1=1 */
4093 br1 = code;
4094 x86_branch8 (code, X86_CC_P, 0, FALSE);
4095 /* branch if (C0 | C3) = 1 */
4096 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4097 amd64_patch (br1, code);
4098 break;
4099 }
4100 case OP_FBGE_UN:
4101 /* Branch if C013 == 000 */
4102 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4103 break;
4104 case OP_FBLE: {
4105 /* Branch if C013=000 or 100 */
4106 guchar *br1;
4107
4108 /* skip branch if C1=1 */
4109 br1 = code;
4110 x86_branch8 (code, X86_CC_P, 0, FALSE);
4111 /* branch if C0=0 */
4112 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4113 amd64_patch (br1, code);
4114 break;
4115 }
4116 case OP_FBLE_UN:
4117 /* Branch if C013 != 001 */
4118 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4119 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4120 break;
4121 case OP_CKFINITE:
4122 /* Transfer value to the fp stack */
4123 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4124 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4125 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4126
4127 amd64_push_reg (code, AMD64_RAX);
4128 amd64_fxam (code);
4129 amd64_fnstsw (code);
4130 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4131 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4132 amd64_pop_reg (code, AMD64_RAX);
4133 amd64_fstp (code, 0);
4134 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4135 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4136 break;
4137 case OP_TLS_GET: {
4138 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4139 break;
4140 }
4141 case OP_MEMORY_BARRIER: {
4142 /* Not needed on amd64 */
4143 break;
4144 }
4145 case OP_ATOMIC_ADD_I4:
4146 case OP_ATOMIC_ADD_I8: {
4147 int dreg = ins->dreg;
4148 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4149
4150 if (dreg == ins->inst_basereg)
4151 dreg = AMD64_R11;
4152
4153 if (dreg != ins->sreg2)
4154 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4155
4156 x86_prefix (code, X86_LOCK_PREFIX);
4157 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4158
4159 if (dreg != ins->dreg)
4160 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4161
4162 break;
4163 }
4164 case OP_ATOMIC_ADD_NEW_I4:
4165 case OP_ATOMIC_ADD_NEW_I8: {
4166 int dreg = ins->dreg;
4167 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4168
4169 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4170 dreg = AMD64_R11;
4171
4172 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4173 amd64_prefix (code, X86_LOCK_PREFIX);
4174 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4175 /* dreg contains the old value, add with sreg2 value */
4176 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4177
4178 if (ins->dreg != dreg)
4179 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4180
4181 break;
4182 }
4183 case OP_ATOMIC_EXCHANGE_I4:
4184 case OP_ATOMIC_EXCHANGE_I8:
4185 case OP_ATOMIC_CAS_IMM_I4: {
4186 guchar *br[2];
4187 int sreg2 = ins->sreg2;
4188 int breg = ins->inst_basereg;
4189 guint32 size;
4190 gboolean need_push = FALSE, rdx_pushed = FALSE;
4191
4192 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4193 size = 8;
4194 else
4195 size = 4;
4196
4197 /*
4198 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4199 * an explanation of how this works.
4200 */
4201
4202 /* cmpxchg uses eax as comperand, need to make sure we can use it
4203 * hack to overcome limits in x86 reg allocator
4204 * (req: dreg == eax and sreg2 != eax and breg != eax)
4205 */
4206 g_assert (ins->dreg == AMD64_RAX);
4207
4208 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4209 /* Highly unlikely, but possible */
4210 need_push = TRUE;
4211
4212 /* The pushes invalidate rsp */
4213 if ((breg == AMD64_RAX) || need_push) {
4214 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4215 breg = AMD64_R11;
4216 }
4217
4218 /* We need the EAX reg for the comparand */
4219 if (ins->sreg2 == AMD64_RAX) {
4220 if (breg != AMD64_R11) {
4221 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4222 sreg2 = AMD64_R11;
4223 } else {
4224 g_assert (need_push);
4225 amd64_push_reg (code, AMD64_RDX);
4226 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4227 sreg2 = AMD64_RDX;
4228 rdx_pushed = TRUE;
4229 }
4230 }
4231
4232 if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4233 if (ins->backend.data == NULL)
4234 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4235 else
4236 amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4237
4238 amd64_prefix (code, X86_LOCK_PREFIX);
4239 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4240 } else {
4241 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4242
4243 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4244 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4245 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4246 amd64_patch (br [1], br [0]);
4247 }
4248
4249 if (rdx_pushed)
4250 amd64_pop_reg (code, AMD64_RDX);
4251
4252 break;
4253 }
4254 case OP_LIVERANGE_START: {
4255 if (cfg->verbose_level > 1)
4256 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4257 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4258 break;
4259 }
4260 case OP_LIVERANGE_END: {
4261 if (cfg->verbose_level > 1)
4262 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4263 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4264 break;
4265 }
4266 default:
4267 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4268 g_assert_not_reached ();
4269 }
4270
4271 if ((code - cfg->native_code - offset) > max_len) {
4272 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4273 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4274 g_assert_not_reached ();
4275 }
4276
4277 cpos += max_len;
4278
4279 last_ins = ins;
4280 last_offset = offset;
4281 }
4282
4283 cfg->code_len = code - cfg->native_code;
4284 }
4285
4286 #endif /* DISABLE_JIT */
4287
4288 void
4289 mono_arch_register_lowlevel_calls (void)
4290 {
4291 /* The signature doesn't matter */
4292 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4293 }
4294
4295 void
4296 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4297 {
4298 MonoJumpInfo *patch_info;
4299 gboolean compile_aot = !run_cctors;
4300
4301 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4302 unsigned char *ip = patch_info->ip.i + code;
4303 unsigned char *target;
4304
4305 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4306
4307 if (compile_aot) {
4308 switch (patch_info->type) {
4309 case MONO_PATCH_INFO_BB:
4310 case MONO_PATCH_INFO_LABEL:
4311 break;
4312 default:
4313 /* No need to patch these */
4314 continue;
4315 }
4316 }
4317
4318 switch (patch_info->type) {
4319 case MONO_PATCH_INFO_NONE:
4320 continue;
4321 case MONO_PATCH_INFO_METHOD_REL:
4322 case MONO_PATCH_INFO_R8:
4323 case MONO_PATCH_INFO_R4:
4324 g_assert_not_reached ();
4325 continue;
4326 case MONO_PATCH_INFO_BB:
4327 break;
4328 default:
4329 break;
4330 }
4331
4332 /*
4333 * Debug code to help track down problems where the target of a near call is
4334 * is not valid.
4335 */
4336 if (amd64_is_near_call (ip)) {
4337 gint64 disp = (guint8*)target - (guint8*)ip;
4338
4339 if (!amd64_is_imm32 (disp)) {
4340 printf ("TYPE: %d\n", patch_info->type);
4341 switch (patch_info->type) {
4342 case MONO_PATCH_INFO_INTERNAL_METHOD:
4343 printf ("V: %s\n", patch_info->data.name);
4344 break;
4345 case MONO_PATCH_INFO_METHOD_JUMP:
4346 case MONO_PATCH_INFO_METHOD:
4347 printf ("V: %s\n", patch_info->data.method->name);
4348 break;
4349 default:
4350 break;
4351 }
4352 }
4353 }
4354
4355 amd64_patch (ip, (gpointer)target);
4356 }
4357 }
4358
4359 static int
4360 get_max_epilog_size (MonoCompile *cfg)
4361 {
4362 int max_epilog_size = 16;
4363
4364 if (cfg->method->save_lmf)
4365 max_epilog_size += 256;
4366
4367 if (mono_jit_trace_calls != NULL)
4368 max_epilog_size += 50;
4369
4370 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4371 max_epilog_size += 50;
4372
4373 max_epilog_size += (AMD64_NREG * 2);
4374
4375 return max_epilog_size;
4376 }
4377
4378 /*
4379 * This macro is used for testing whenever the unwinder works correctly at every point
4380 * where an async exception can happen.
4381 */
4382 /* This will generate a SIGSEGV at the given point in the code */
4383 #define async_exc_point(code) do { \
4384 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4385 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4386 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4387 cfg->arch.async_point_count ++; \
4388 } \
4389 } while (0)
4390
4391 guint8 *
4392 mono_arch_emit_prolog (MonoCompile *cfg)
4393 {
4394 MonoMethod *method = cfg->method;
4395 MonoBasicBlock *bb;
4396 MonoMethodSignature *sig;
4397 MonoInst *ins;
4398 int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4399 guint8 *code;
4400 CallInfo *cinfo;
4401 gint32 lmf_offset = cfg->arch.lmf_offset;
4402 gboolean args_clobbered = FALSE;
4403 gboolean trace = FALSE;
4404
4405 cfg->code_size = MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4406
4407 code = cfg->native_code = g_malloc (cfg->code_size);
4408
4409 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4410 trace = TRUE;
4411
4412 /* Amount of stack space allocated by register saving code */
4413 pos = 0;
4414
4415 /* Offset between RSP and the CFA */
4416 cfa_offset = 0;
4417
4418 /*
4419 * The prolog consists of the following parts:
4420 * FP present:
4421 * - push rbp, mov rbp, rsp
4422 * - save callee saved regs using pushes
4423 * - allocate frame
4424 * - save rgctx if needed
4425 * - save lmf if needed
4426 * FP not present:
4427 * - allocate frame
4428 * - save rgctx if needed
4429 * - save lmf if needed
4430 * - save callee saved regs using moves
4431 */
4432
4433 // CFA = sp + 8
4434 cfa_offset = 8;
4435 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4436 // IP saved at CFA - 8
4437 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4438 async_exc_point (code);
4439
4440 if (!cfg->arch.omit_fp) {
4441 amd64_push_reg (code, AMD64_RBP);
4442 cfa_offset += 8;
4443 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4444 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4445 async_exc_point (code);
4446 #ifdef PLATFORM_WIN32
4447 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4448 #endif
4449
4450 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4451 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4452 async_exc_point (code);
4453 #ifdef PLATFORM_WIN32
4454 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4455 #endif
4456 }
4457
4458 /* Save callee saved registers */
4459 if (!cfg->arch.omit_fp && !method->save_lmf) {
4460 int offset = cfa_offset;
4461
4462 for (i = 0; i < AMD64_NREG; ++i)
4463 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4464 amd64_push_reg (code, i);
4465 pos += sizeof (gpointer);
4466 offset += 8;
4467 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4468 async_exc_point (code);
4469 }
4470 }
4471
4472 if (cfg->arch.omit_fp) {
4473 /*
4474 * On enter, the stack is misaligned by the the pushing of the return
4475 * address. It is either made aligned by the pushing of %rbp, or by
4476 * this.
4477 */
4478 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4479 if ((alloc_size % 16) == 0)
4480 alloc_size += 8;
4481 } else {
4482 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4483
4484 alloc_size -= pos;
4485 }
4486
4487 cfg->arch.stack_alloc_size = alloc_size;
4488
4489 /* Allocate stack frame */
4490 if (alloc_size) {
4491 /* See mono_emit_stack_alloc */
4492 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4493 guint32 remaining_size = alloc_size;
4494 while (remaining_size >= 0x1000) {
4495 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4496 if (cfg->arch.omit_fp) {
4497 cfa_offset += 0x1000;
4498 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4499 }
4500 async_exc_point (code);
4501 #ifdef PLATFORM_WIN32
4502 if (cfg->arch.omit_fp)
4503 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4504 #endif
4505
4506 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4507 remaining_size -= 0x1000;
4508 }
4509 if (remaining_size) {
4510 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4511 if (cfg->arch.omit_fp) {
4512 cfa_offset += remaining_size;
4513 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4514 async_exc_point (code);
4515 }
4516 #ifdef PLATFORM_WIN32
4517 if (cfg->arch.omit_fp)
4518 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4519 #endif
4520 }
4521 #else
4522 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4523 if (cfg->arch.omit_fp) {
4524 cfa_offset += alloc_size;
4525 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4526 async_exc_point (code);
4527 }
4528 #endif
4529 }
4530
4531 /* Stack alignment check */
4532 #if 0
4533 {
4534 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4535 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4536 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4537 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4538 amd64_breakpoint (code);
4539 }
4540 #endif
4541
4542 /* Save LMF */
4543 if (method->save_lmf) {
4544 /*
4545 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4546 */
4547 /* sp is saved right before calls */
4548 /* Skip method (only needed for trampoline LMF frames) */
4549 /* Save callee saved regs */
4550 for (i = 0; i < MONO_MAX_IREGS; ++i) {
4551 int offset;
4552
4553 switch (i) {
4554 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
4555 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
4556 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
4557 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
4558 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
4559 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
4560 #ifdef PLATFORM_WIN32
4561 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
4562 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
4563 #endif
4564 default:
4565 offset = -1;
4566 break;
4567 }
4568
4569 if (offset != -1) {
4570 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
4571 if (cfg->arch.omit_fp || (i != AMD64_RBP))
4572 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
4573 }
4574 }
4575 }
4576
4577 /* Save callee saved registers */
4578 if (cfg->arch.omit_fp && !method->save_lmf) {
4579 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4580
4581 /* Save caller saved registers after sp is adjusted */
4582 /* The registers are saved at the bottom of the frame */
4583 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4584 for (i = 0; i < AMD64_NREG; ++i)
4585 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4586 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4587 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4588 save_area_offset += 8;
4589 async_exc_point (code);
4590 }
4591 }
4592
4593 /* store runtime generic context */
4594 if (cfg->rgctx_var) {
4595 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4596 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4597
4598 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4599 }
4600
4601 /* compute max_offset in order to use short forward jumps */
4602 max_offset = 0;
4603 max_epilog_size = get_max_epilog_size (cfg);
4604 if (cfg->opt & MONO_OPT_BRANCH) {
4605 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4606 MonoInst *ins;
4607 bb->max_offset = max_offset;
4608
4609 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4610 max_offset += 6;
4611 /* max alignment for loops */
4612 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4613 max_offset += LOOP_ALIGNMENT;
4614
4615 MONO_BB_FOR_EACH_INS (bb, ins) {
4616 if (ins->opcode == OP_LABEL)
4617 ins->inst_c1 = max_offset;
4618
4619 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4620 }
4621
4622 if (mono_jit_trace_calls && bb == cfg->bb_exit)
4623 /* The tracing code can be quite large */
4624 max_offset += max_epilog_size;
4625 }
4626 }
4627
4628 sig = mono_method_signature (method);
4629 pos = 0;
4630
4631 cinfo = cfg->arch.cinfo;
4632
4633 if (sig->ret->type != MONO_TYPE_VOID) {
4634 /* Save volatile arguments to the stack */
4635 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4636 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4637 }
4638
4639 /* Keep this in sync with emit_load_volatile_arguments */
4640 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4641 ArgInfo *ainfo = cinfo->args + i;
4642 gint32 stack_offset;
4643 MonoType *arg_type;
4644
4645 ins = cfg->args [i];
4646
4647 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4648 /* Unused arguments */
4649 continue;
4650
4651 if (sig->hasthis && (i == 0))
4652 arg_type = &mono_defaults.object_class->byval_arg;
4653 else
4654 arg_type = sig->params [i - sig->hasthis];
4655
4656 stack_offset = ainfo->offset + ARGS_OFFSET;
4657
4658 if (cfg->globalra) {
4659 /* All the other moves are done by the register allocator */
4660 switch (ainfo->storage) {
4661 case ArgInFloatSSEReg:
4662 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4663 break;
4664 case ArgValuetypeInReg:
4665 for (quad = 0; quad < 2; quad ++) {
4666 switch (ainfo->pair_storage [quad]) {
4667 case ArgInIReg:
4668 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4669 break;
4670 case ArgInFloatSSEReg:
4671 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4672 break;
4673 case ArgInDoubleSSEReg:
4674 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4675 break;
4676 case ArgNone:
4677 break;
4678 default:
4679 g_assert_not_reached ();
4680 }
4681 }
4682 break;
4683 default:
4684 break;
4685 }
4686
4687 continue;
4688 }
4689
4690 /* Save volatile arguments to the stack */
4691 if (ins->opcode != OP_REGVAR) {
4692 switch (ainfo->storage) {
4693 case ArgInIReg: {
4694 guint32 size = 8;
4695
4696 /* FIXME: I1 etc */
4697 /*
4698 if (stack_offset & 0x1)
4699 size = 1;
4700 else if (stack_offset & 0x2)
4701 size = 2;
4702 else if (stack_offset & 0x4)
4703 size = 4;
4704 else
4705 size = 8;
4706 */
4707 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4708 break;
4709 }
4710 case ArgInFloatSSEReg:
4711 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4712 break;
4713 case ArgInDoubleSSEReg:
4714 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4715 break;
4716 case ArgValuetypeInReg:
4717 for (quad = 0; quad < 2; quad ++) {
4718 switch (ainfo->pair_storage [quad]) {
4719 case ArgInIReg:
4720 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4721 break;
4722 case ArgInFloatSSEReg:
4723 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4724 break;
4725 case ArgInDoubleSSEReg:
4726 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4727 break;
4728 case ArgNone:
4729 break;
4730 default:
4731 g_assert_not_reached ();
4732 }
4733 }
4734 break;
4735 case ArgValuetypeAddrInIReg:
4736 if (ainfo->pair_storage [0] == ArgInIReg)
4737 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
4738 break;
4739 default:
4740 break;
4741 }
4742 } else {
4743 /* Argument allocated to (non-volatile) register */
4744 switch (ainfo->storage) {
4745 case ArgInIReg:
4746 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4747 break;
4748 case ArgOnStack:
4749 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4750 break;
4751 default:
4752 g_assert_not_reached ();
4753 }
4754 }
4755 }
4756
4757 /* Might need to attach the thread to the JIT or change the domain for the callback */
4758 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4759 guint64 domain = (guint64)cfg->domain;
4760
4761 args_clobbered = TRUE;
4762
4763 /*
4764 * The call might clobber argument registers, but they are already
4765 * saved to the stack/global regs.
4766 */
4767 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4768 guint8 *buf, *no_domain_branch;
4769
4770 code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4771 if ((domain >> 32) == 0)
4772 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4773 else
4774 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4775 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4776 no_domain_branch = code;
4777 x86_branch8 (code, X86_CC_NE, 0, 0);
4778 code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4779 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4780 buf = code;
4781 x86_branch8 (code, X86_CC_NE, 0, 0);
4782 amd64_patch (no_domain_branch, code);
4783 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4784 (gpointer)"mono_jit_thread_attach", TRUE);
4785 amd64_patch (buf, code);
4786 #ifdef PLATFORM_WIN32
4787 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4788 /* FIXME: Add a separate key for LMF to avoid this */
4789 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4790 #endif
4791 } else {
4792 g_assert (!cfg->compile_aot);
4793 if ((domain >> 32) == 0)
4794 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4795 else
4796 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4797 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4798 (gpointer)"mono_jit_thread_attach", TRUE);
4799 }
4800 }
4801
4802 if (method->save_lmf) {
4803 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4804 /*
4805 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4806 * through the mono_lmf_addr TLS variable.
4807 */
4808 /* %rax = previous_lmf */
4809 x86_prefix (code, X86_FS_PREFIX);
4810 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4811
4812 /* Save previous_lmf */
4813 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4814 /* Set new lmf */
4815 if (lmf_offset == 0) {
4816 x86_prefix (code, X86_FS_PREFIX);
4817 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4818 } else {
4819 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4820 x86_prefix (code, X86_FS_PREFIX);
4821 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4822 }
4823 } else {
4824 if (lmf_addr_tls_offset != -1) {
4825 /* Load lmf quicky using the FS register */
4826 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4827 #ifdef PLATFORM_WIN32
4828 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4829 /* FIXME: Add a separate key for LMF to avoid this */
4830 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4831 #endif
4832 }
4833 else {
4834 /*
4835 * The call might clobber argument registers, but they are already
4836 * saved to the stack/global regs.
4837 */
4838 args_clobbered = TRUE;
4839 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4840 (gpointer)"mono_get_lmf_addr", TRUE);
4841 }
4842
4843 /* Save lmf_addr */
4844 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4845 /* Save previous_lmf */
4846 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4847 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4848 /* Set new lmf */
4849 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4850 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4851 }
4852 }
4853
4854 if (trace) {
4855 args_clobbered = TRUE;
4856 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4857 }
4858
4859 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4860 args_clobbered = TRUE;
4861
4862 /*
4863 * Optimize the common case of the first bblock making a call with the same
4864 * arguments as the method. This works because the arguments are still in their
4865 * original argument registers.
4866 * FIXME: Generalize this
4867 */
4868 if (!args_clobbered) {
4869 MonoBasicBlock *first_bb = cfg->bb_entry;
4870 MonoInst *next;
4871
4872 next = mono_bb_first_ins (first_bb);
4873 if (!next && first_bb->next_bb) {
4874 first_bb = first_bb->next_bb;
4875 next = mono_bb_first_ins (first_bb);
4876 }
4877
4878 if (first_bb->in_count > 1)
4879 next = NULL;
4880
4881 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4882 ArgInfo *ainfo = cinfo->args + i;
4883 gboolean match = FALSE;
4884
4885 ins = cfg->args [i];
4886 if (ins->opcode != OP_REGVAR) {
4887 switch (ainfo->storage) {
4888 case ArgInIReg: {
4889 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4890 if (next->dreg == ainfo->reg) {
4891 NULLIFY_INS (next);
4892 match = TRUE;
4893 } else {
4894 next->opcode = OP_MOVE;
4895 next->sreg1 = ainfo->reg;
4896 /* Only continue if the instruction doesn't change argument regs */
4897 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4898 match = TRUE;
4899 }
4900 }
4901 break;
4902 }
4903 default:
4904 break;
4905 }
4906 } else {
4907 /* Argument allocated to (non-volatile) register */
4908 switch (ainfo->storage) {
4909 case ArgInIReg:
4910 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4911 NULLIFY_INS (next);
4912 match = TRUE;
4913 }
4914 break;
4915 default:
4916 break;
4917 }
4918 }
4919
4920 if (match) {
4921 next = next->next;
4922 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4923 if (!next)
4924 break;
4925 }
4926 }
4927 }
4928
4929 cfg->code_len = code - cfg->native_code;
4930
4931 g_assert (cfg->code_len < cfg->code_size);
4932
4933 return code;
4934 }
4935
4936 void
4937 mono_arch_emit_epilog (MonoCompile *cfg)
4938 {
4939 MonoMethod *method = cfg->method;
4940 int quad, pos, i;
4941 guint8 *code;
4942 int max_epilog_size;
4943 CallInfo *cinfo;
4944 gint32 lmf_offset = cfg->arch.lmf_offset;
4945
4946 max_epilog_size = get_max_epilog_size (cfg);
4947
4948 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4949 cfg->code_size *= 2;
4950 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4951 mono_jit_stats.code_reallocs++;
4952 }
4953
4954 code = cfg->native_code + cfg->code_len;
4955
4956 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4957 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4958
4959 /* the code restoring the registers must be kept in sync with OP_JMP */
4960 pos = 0;
4961
4962 if (method->save_lmf) {
4963 /* check if we need to restore protection of the stack after a stack overflow */
4964 if (mono_get_jit_tls_offset () != -1) {
4965 guint8 *patch;
4966 code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4967 /* we load the value in a separate instruction: this mechanism may be
4968 * used later as a safer way to do thread interruption
4969 */
4970 amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
4971 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4972 patch = code;
4973 x86_branch8 (code, X86_CC_Z, 0, FALSE);
4974 /* note that the call trampoline will preserve eax/edx */
4975 x86_call_reg (code, X86_ECX);
4976 x86_patch (patch, code);
4977 } else {
4978 /* FIXME: maybe save the jit tls in the prolog */
4979 }
4980 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4981 /*
4982 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4983 * through the mono_lmf_addr TLS variable.
4984 */
4985 /* reg = previous_lmf */
4986 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4987 x86_prefix (code, X86_FS_PREFIX);
4988 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4989 } else {
4990 /* Restore previous lmf */
4991 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4992 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4993 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4994 }
4995
4996 /* Restore caller saved regs */
4997 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4998 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
4999 }
5000 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5001 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5002 }
5003 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5004 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5005 }
5006 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5007 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5008 }
5009 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5010 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5011 }
5012 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5013 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5014 }
5015 #ifdef PLATFORM_WIN32
5016 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5017 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5018 }
5019 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5020 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5021 }
5022 #endif
5023 } else {
5024
5025 if (cfg->arch.omit_fp) {
5026 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5027
5028 for (i = 0; i < AMD64_NREG; ++i)
5029 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5030 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5031 save_area_offset += 8;
5032 }
5033 }
5034 else {
5035 for (i = 0; i < AMD64_NREG; ++i)
5036 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5037 pos -= sizeof (gpointer);
5038
5039 if (pos) {
5040 if (pos == - sizeof (gpointer)) {
5041 /* Only one register, so avoid lea */
5042 for (i = AMD64_NREG - 1; i > 0; --i)
5043 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5044 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5045 }
5046 }
5047 else {
5048 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5049
5050 /* Pop registers in reverse order */
5051 for (i = AMD64_NREG - 1; i > 0; --i)
5052 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5053 amd64_pop_reg (code, i);
5054 }
5055 }
5056 }
5057 }
5058 }
5059
5060 /* Load returned vtypes into registers if needed */
5061 cinfo = cfg->arch.cinfo;
5062 if (cinfo->ret.storage == ArgValuetypeInReg) {
5063 ArgInfo *ainfo = &cinfo->ret;
5064 MonoInst *inst = cfg->ret;
5065
5066 for (quad = 0; quad < 2; quad ++) {
5067 switch (ainfo->pair_storage [quad]) {
5068 case ArgInIReg:
5069 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5070 break;
5071 case ArgInFloatSSEReg:
5072 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5073 break;
5074 case ArgInDoubleSSEReg:
5075 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5076 break;
5077 case ArgNone:
5078 break;
5079 default:
5080 g_assert_not_reached ();
5081 }
5082 }
5083 }
5084
5085 if (cfg->arch.omit_fp) {
5086 if (cfg->arch.stack_alloc_size)
5087 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5088 } else {
5089 amd64_leave (code);
5090 }
5091 async_exc_point (code);
5092 amd64_ret (code);
5093
5094 cfg->code_len = code - cfg->native_code;
5095
5096 g_assert (cfg->code_len < cfg->code_size);
5097
5098 if (cfg->arch.omit_fp) {
5099 /*
5100 * Encode the stack size into used_int_regs so the exception handler
5101 * can access it.
5102 */
5103 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5104 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5105 }
5106 }
5107
5108 void
5109 mono_arch_emit_exceptions (MonoCompile *cfg)
5110 {
5111 MonoJumpInfo *patch_info;
5112 int nthrows, i;
5113 guint8 *code;
5114 MonoClass *exc_classes [16];
5115 guint8 *exc_throw_start [16], *exc_throw_end [16];
5116 guint32 code_size = 0;
5117
5118 /* Compute needed space */
5119 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5120 if (patch_info->type == MONO_PATCH_INFO_EXC)
5121 code_size += 40;
5122 if (patch_info->type == MONO_PATCH_INFO_R8)
5123 code_size += 8 + 15; /* sizeof (double) + alignment */
5124 if (patch_info->type == MONO_PATCH_INFO_R4)
5125 code_size += 4 + 15; /* sizeof (float) + alignment */
5126 }
5127
5128 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5129 cfg->code_size *= 2;
5130 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5131 mono_jit_stats.code_reallocs++;
5132 }
5133
5134 code = cfg->native_code + cfg->code_len;
5135
5136 /* add code to raise exceptions */
5137 nthrows = 0;
5138 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5139 switch (patch_info->type) {
5140 case MONO_PATCH_INFO_EXC: {
5141 MonoClass *exc_class;
5142 guint8 *buf, *buf2;
5143 guint32 throw_ip;
5144
5145 amd64_patch (patch_info->ip.i + cfg->native_code, code);
5146
5147 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5148 g_assert (exc_class);
5149 throw_ip = patch_info->ip.i;
5150
5151 //x86_breakpoint (code);
5152 /* Find a throw sequence for the same exception class */
5153 for (i = 0; i < nthrows; ++i)
5154 if (exc_classes [i] == exc_class)
5155 break;
5156 if (i < nthrows) {
5157 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5158 x86_jump_code (code, exc_throw_start [i]);
5159 patch_info->type = MONO_PATCH_INFO_NONE;
5160 }
5161 else {
5162 buf = code;
5163 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5164 buf2 = code;
5165
5166 if (nthrows < 16) {
5167 exc_classes [nthrows] = exc_class;
5168 exc_throw_start [nthrows] = code;
5169 }
5170 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5171
5172 patch_info->type = MONO_PATCH_INFO_NONE;
5173
5174 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5175
5176 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5177 while (buf < buf2)
5178 x86_nop (buf);
5179
5180 if (nthrows < 16) {
5181 exc_throw_end [nthrows] = code;
5182 nthrows ++;
5183 }
5184 }
5185 break;
5186 }
5187 default:
5188 /* do nothing */
5189 break;
5190 }
5191 }
5192
5193 /* Handle relocations with RIP relative addressing */
5194 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5195 gboolean remove = FALSE;
5196
5197 switch (patch_info->type) {
5198 case MONO_PATCH_INFO_R8:
5199 case MONO_PATCH_INFO_R4: {
5200 guint8 *pos;
5201
5202 /* The SSE opcodes require a 16 byte alignment */
5203 code = (guint8*)ALIGN_TO (code, 16);
5204
5205 pos = cfg->native_code + patch_info->ip.i;
5206
5207 if (IS_REX (pos [1]))
5208 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5209 else
5210 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5211
5212 if (patch_info->type == MONO_PATCH_INFO_R8) {
5213 *(double*)code = *(double*)patch_info->data.target;
5214 code += sizeof (double);
5215 } else {
5216 *(float*)code = *(float*)patch_info->data.target;
5217 code += sizeof (float);
5218 }
5219
5220 remove = TRUE;
5221 break;
5222 }
5223 default:
5224 break;
5225 }
5226
5227 if (remove) {
5228 if (patch_info == cfg->patch_info)
5229 cfg->patch_info = patch_info->next;
5230 else {
5231 MonoJumpInfo *tmp;
5232
5233 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5234 ;
5235 tmp->next = patch_info->next;
5236 }
5237 }
5238 }
5239
5240 cfg->code_len = code - cfg->native_code;
5241
5242 g_assert (cfg->code_len < cfg->code_size);
5243
5244 }
5245
5246 void*
5247 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5248 {
5249 guchar *code = p;
5250 CallInfo *cinfo = NULL;
5251 MonoMethodSignature *sig;
5252 MonoInst *inst;
5253 int i, n, stack_area = 0;
5254
5255 /* Keep this in sync with mono_arch_get_argument_info */
5256
5257 if (enable_arguments) {
5258 /* Allocate a new area on the stack and save arguments there */
5259 sig = mono_method_signature (cfg->method);
5260
5261 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5262
5263 n = sig->param_count + sig->hasthis;
5264
5265 stack_area = ALIGN_TO (n * 8, 16);
5266
5267 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5268
5269 for (i = 0; i < n; ++i) {
5270 inst = cfg->args [i];
5271
5272 if (inst->opcode == OP_REGVAR)
5273 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5274 else {
5275 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5276 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5277 }
5278 }
5279 }
5280
5281 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5282 amd64_set_reg_template (code, AMD64_ARG_REG1);
5283 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5284 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5285
5286 if (enable_arguments)
5287 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5288
5289 return code;
5290 }
5291
5292 enum {
5293 SAVE_NONE,
5294 SAVE_STRUCT,
5295 SAVE_EAX,
5296 SAVE_EAX_EDX,
5297 SAVE_XMM
5298 };
5299
5300 void*
5301 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5302 {
5303 guchar *code = p;
5304 int save_mode = SAVE_NONE;
5305 MonoMethod *method = cfg->method;
5306 int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5307
5308 switch (rtype) {
5309 case MONO_TYPE_VOID:
5310 /* special case string .ctor icall */
5311 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5312 save_mode = SAVE_EAX;
5313 else
5314 save_mode = SAVE_NONE;
5315 break;
5316 case MONO_TYPE_I8:
5317 case MONO_TYPE_U8:
5318 save_mode = SAVE_EAX;
5319 break;
5320 case MONO_TYPE_R4:
5321 case MONO_TYPE_R8:
5322 save_mode = SAVE_XMM;
5323 break;
5324 case MONO_TYPE_GENERICINST:
5325 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5326 save_mode = SAVE_EAX;
5327 break;
5328 }
5329 /* Fall through */
5330 case MONO_TYPE_VALUETYPE:
5331 save_mode = SAVE_STRUCT;
5332 break;
5333 default:
5334 save_mode = SAVE_EAX;
5335 break;
5336 }
5337
5338 /* Save the result and copy it into the proper argument register */
5339 switch (save_mode) {
5340 case SAVE_EAX:
5341 amd64_push_reg (code, AMD64_RAX);
5342 /* Align stack */
5343 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5344 if (enable_arguments)
5345 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5346 break;
5347 case SAVE_STRUCT:
5348 /* FIXME: */
5349 if (enable_arguments)
5350 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5351 break;
5352 case SAVE_XMM:
5353 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5354 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5355 /* Align stack */
5356 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5357 /*
5358 * The result is already in the proper argument register so no copying
5359 * needed.
5360 */
5361 break;
5362 case SAVE_NONE:
5363 break;
5364 default:
5365 g_assert_not_reached ();
5366 }
5367
5368 /* Set %al since this is a varargs call */
5369 if (save_mode == SAVE_XMM)
5370 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5371 else
5372 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5373
5374 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5375 amd64_set_reg_template (code, AMD64_ARG_REG1);
5376 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5377
5378 /* Restore result */
5379 switch (save_mode) {
5380 case SAVE_EAX:
5381 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5382 amd64_pop_reg (code, AMD64_RAX);
5383 break;
5384 case SAVE_STRUCT:
5385 /* FIXME: */
5386 break;
5387 case SAVE_XMM:
5388 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5389 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5390 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5391 break;
5392 case SAVE_NONE:
5393 break;
5394 default:
5395 g_assert_not_reached ();
5396 }
5397
5398 return code;
5399 }
5400
5401 void
5402 mono_arch_flush_icache (guint8 *code, gint size)
5403 {
5404 /* Not needed */
5405 }
5406
5407 void
5408 mono_arch_flush_register_windows (void)
5409 {
5410 }
5411
5412 gboolean
5413 mono_arch_is_inst_imm (gint64 imm)
5414 {
5415 return amd64_is_imm32 (imm);
5416 }
5417
5418 /*
5419 * Determine whenever the trap whose info is in SIGINFO is caused by
5420 * integer overflow.
5421 */
5422 gboolean
5423 mono_arch_is_int_overflow (void *sigctx, void *info)
5424 {
5425 MonoContext ctx;
5426 guint8* rip;
5427 int reg;
5428 gint64 value;
5429
5430 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5431
5432 rip = (guint8*)ctx.rip;
5433
5434 if (IS_REX (rip [0])) {
5435 reg = amd64_rex_b (rip [0]);
5436 rip ++;
5437 }
5438 else
5439 reg = 0;
5440
5441 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5442 /* idiv REG */
5443 reg += x86_modrm_rm (rip [1]);
5444
5445 switch (reg) {
5446 case AMD64_RAX:
5447 value = ctx.rax;
5448 break;
5449 case AMD64_RBX:
5450 value = ctx.rbx;
5451 break;
5452 case AMD64_RCX:
5453 value = ctx.rcx;
5454 break;
5455 case AMD64_RDX:
5456 value = ctx.rdx;
5457 break;
5458 case AMD64_RBP:
5459 value = ctx.rbp;
5460 break;
5461 case AMD64_RSP:
5462 value = ctx.rsp;
5463 break;
5464 case AMD64_RSI:
5465 value = ctx.rsi;
5466 break;
5467 case AMD64_RDI:
5468 value = ctx.rdi;
5469 break;
5470 case AMD64_R12:
5471 value = ctx.r12;
5472 break;
5473 case AMD64_R13:
5474 value = ctx.r13;
5475 break;
5476 case AMD64_R14:
5477 value = ctx.r14;
5478 break;
5479 case AMD64_R15:
5480 value = ctx.r15;
5481 break;
5482 default:
5483 g_assert_not_reached ();
5484 reg = -1;
5485 }
5486
5487 if (value == -1)
5488 return TRUE;
5489 }
5490
5491 return FALSE;
5492 }
5493
5494 guint32
5495 mono_arch_get_patch_offset (guint8 *code)
5496 {
5497 return 3;
5498 }
5499
5500 /**
5501 * mono_breakpoint_clean_code:
5502 *
5503 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5504 * breakpoints in the original code, they are removed in the copy.
5505 *
5506 * Returns TRUE if no sw breakpoint was present.
5507 */
5508 gboolean
5509 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5510 {
5511 int i;
5512 gboolean can_write = TRUE;
5513 /*
5514 * If method_start is non-NULL we need to perform bound checks, since we access memory
5515 * at code - offset we could go before the start of the method and end up in a different
5516 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5517 * instead.
5518 */
5519 if (!method_start || code - offset >= method_start) {
5520 memcpy (buf, code - offset, size);
5521 } else {
5522 int diff = code - method_start;
5523 memset (buf, 0, size);
5524 memcpy (buf + offset - diff, method_start, diff + size - offset);
5525 }
5526 code -= offset;
5527 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5528 int idx = mono_breakpoint_info_index [i];
5529 guint8 *ptr;
5530 if (idx < 1)
5531 continue;
5532 ptr = mono_breakpoint_info [idx].address;
5533 if (ptr >= code && ptr < code + size) {
5534 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5535 can_write = FALSE;
5536 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5537 buf [ptr - code] = saved_byte;
5538 }
5539 }
5540 return can_write;
5541 }
5542
5543 gpointer
5544 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5545 {
5546 guint8 buf [10];
5547 guint32 reg;
5548 gint32 disp;
5549 guint8 rex = 0;
5550
5551 mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5552 code = buf + 9;
5553
5554 *displacement = 0;
5555
5556 /* go to the start of the call instruction
5557 *
5558 * address_byte = (m << 6) | (o << 3) | reg
5559 * call opcode: 0xff address_byte displacement
5560 * 0xff m=1,o=2 imm8
5561 * 0xff m=2,o=2 imm32
5562 */
5563 code -= 7;
5564
5565 /*
5566 * A given byte sequence can match more than case here, so we have to be
5567 * really careful about the ordering of the cases. Longer sequences
5568 * come first.
5569 * Some of the rules are only needed because the imm in the mov could
5570 * match the
5571 * code [2] == 0xe8 case below.
5572 */
5573 #ifdef MONO_ARCH_HAVE_IMT
5574 if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5575 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5576 * 41 bb 14 f8 28 08 mov $0x828f814,%r11d
5577 * ff 50 fc call *0xfffffffc(%rax)
5578 */
5579 reg = amd64_modrm_rm (code [5]);
5580 disp = (signed char)code [6];
5581 /* R10 is clobbered by the IMT thunk code */
5582 g_assert (reg != AMD64_R10);
5583 }
5584 #else
5585 if (0) {
5586 }
5587 #endif
5588 else if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5589 /*
5590 * 41 bb e8 e8 e8 e8 mov $0xe8e8e8e8,%r11d
5591 * ff 50 60 callq *0x60(%rax)
5592 */
5593 if (IS_REX (code [3]))
5594 rex = code [3];
5595 reg = amd64_modrm_rm (code [5]);
5596 disp = *(gint8*)(code + 6);
5597 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5598 } else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5599 /*
5600 * This is a interface call
5601 * 48 8b 80 f0 e8 ff ff mov 0xffffffffffffe8f0(%rax),%rax
5602 * ff 10 callq *(%rax)
5603 */
5604 if (IS_REX (code [4]))
5605 rex = code [4];
5606 reg = amd64_modrm_rm (code [6]);
5607 disp = 0;
5608 /* R10 is clobbered by the IMT thunk code */
5609 g_assert (reg != AMD64_R10);
5610 } else if ((code [-1] >= 0xb8) && (code [-1] < 0xb8 + 8) && (code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5611 /*
5612 * ba e8 e8 e8 e8 mov $0xe8e8e8e8,%edx
5613 * ff 50 60 callq *0x60(%rax)
5614 */
5615 if (IS_REX (code [3]))
5616 rex = code [3];
5617 reg = amd64_modrm_rm (code [5]);
5618 disp = *(gint8*)(code + 6);
5619 } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5620 /* call OFFSET(%rip) */
5621 disp = *(guint32*)(code + 3);
5622 return (gpointer*)(code + disp + 7);
5623 } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5624 /* call *[r12+disp32] */
5625 if (IS_REX (code [-1]))
5626 rex = code [-1];
5627 reg = AMD64_RSP;
5628 disp = *(gint32*)(code + 3);
5629 } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5630 /* call *[reg+disp32] */
5631 if (IS_REX (code [0]))
5632 rex = code [0];
5633 reg = amd64_modrm_rm (code [2]);
5634 disp = *(gint32*)(code + 3);
5635 /* R10 is clobbered by the IMT thunk code */
5636 g_assert (reg != AMD64_R10);
5637 } else if (code [2] == 0xe8) {
5638 /* call <ADDR> */
5639 return NULL;
5640 } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5641 /* call *[r12+disp32] */
5642 if (IS_REX (code [2]))
5643 rex = code [2];
5644 reg = AMD64_RSP;
5645 disp = *(gint8*)(code + 6);
5646 } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5647 /* call *%reg */
5648 return NULL;
5649 } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5650 /* call *[reg+disp8] */
5651 if (IS_REX (code [3]))
5652 rex = code [3];
5653 reg = amd64_modrm_rm (code [5]);
5654 disp = *(gint8*)(code + 6);
5655 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5656 }
5657 else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5658 /*
5659 * This is a interface call: should check the above code can't catch it earlier
5660 * 8b 40 30 mov 0x30(%eax),%eax
5661 * ff 10 call *(%eax)
5662 */
5663 if (IS_REX (code [4]))
5664 rex = code [4];
5665 reg = amd64_modrm_rm (code [6]);
5666 disp = 0;
5667 }
5668 else
5669 g_assert_not_reached ();
5670
5671 reg += amd64_rex_b (rex);
5672
5673 /* R11 is clobbered by the trampoline code */
5674 g_assert (reg != AMD64_R11);
5675
5676 *displacement = disp;
5677 return regs [reg];
5678 }
5679
5680 gpointer*
5681 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5682 {
5683 gpointer vt;
5684 int displacement;
5685 vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5686 if (!vt)
5687 return NULL;
5688 return (gpointer*)((char*)vt + displacement);
5689 }
5690
5691 int
5692 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5693 {
5694 int this_reg = AMD64_ARG_REG1;
5695
5696 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5697 CallInfo *cinfo;
5698
5699 if (!gsctx && code)
5700 gsctx = mono_get_generic_context_from_code (code);
5701
5702 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5703
5704 if (cinfo->ret.storage != ArgValuetypeInReg)
5705 this_reg = AMD64_ARG_REG2;
5706 g_free (cinfo);
5707 }
5708
5709 return this_reg;
5710 }
5711
5712 gpointer
5713 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5714 {
5715 return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5716 }
5717
5718 #define MAX_ARCH_DELEGATE_PARAMS 10
5719
5720 gpointer
5721 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5722 {
5723 guint8 *code, *start;
5724 int i;
5725
5726 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5727 return NULL;
5728
5729 /* FIXME: Support more cases */
5730 if (MONO_TYPE_ISSTRUCT (sig->ret))
5731 return NULL;
5732
5733 if (has_target) {
5734 static guint8* cached = NULL;
5735
5736 if (cached)
5737 return cached;
5738
5739 start = code = mono_global_codeman_reserve (64);
5740
5741 /* Replace the this argument with the target */
5742 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5743 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5744 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5745
5746 g_assert ((code - start) < 64);
5747
5748 mono_debug_add_delegate_trampoline (start, code - start);
5749
5750 mono_memory_barrier ();
5751
5752 cached = start;
5753 } else {
5754 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5755 for (i = 0; i < sig->param_count; ++i)
5756 if (!mono_is_regsize_var (sig->params [i]))
5757 return NULL;
5758 if (sig->param_count > 4)
5759 return NULL;
5760
5761 code = cache [sig->param_count];
5762 if (code)
5763 return code;
5764
5765 start = code = mono_global_codeman_reserve (64);
5766
5767 if (sig->param_count == 0) {
5768 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5769 } else {
5770 /* We have to shift the arguments left */
5771 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5772 for (i = 0; i < sig->param_count; ++i) {
5773 #ifdef PLATFORM_WIN32
5774 if (i < 3)
5775 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5776 else
5777 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5778 #else
5779 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5780 #endif
5781 }
5782
5783 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5784 }
5785 g_assert ((code - start) < 64);
5786
5787 mono_debug_add_delegate_trampoline (start, code - start);
5788
5789 mono_memory_barrier ();
5790
5791 cache [sig->param_count] = start;
5792 }
5793
5794 return start;
5795 }
5796
5797 /*
5798 * Support for fast access to the thread-local lmf structure using the GS
5799 * segment register on NPTL + kernel 2.6.x.
5800 */
5801
5802 static gboolean tls_offset_inited = FALSE;
5803
5804 void
5805 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5806 {
5807 if (!tls_offset_inited) {
5808 #ifdef PLATFORM_WIN32
5809 /*
5810 * We need to init this multiple times, since when we are first called, the key might not
5811 * be initialized yet.
5812 */
5813 appdomain_tls_offset = mono_domain_get_tls_key ();
5814 lmf_tls_offset = mono_get_jit_tls_key ();
5815 thread_tls_offset = mono_thread_get_tls_key ();
5816 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5817
5818 /* Only 64 tls entries can be accessed using inline code */
5819 if (appdomain_tls_offset >= 64)
5820 appdomain_tls_offset = -1;
5821 if (lmf_tls_offset >= 64)
5822 lmf_tls_offset = -1;
5823 if (thread_tls_offset >= 64)
5824 thread_tls_offset = -1;
5825 #else
5826 tls_offset_inited = TRUE;
5827 #ifdef MONO_XEN_OPT
5828 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5829 #endif
5830 appdomain_tls_offset = mono_domain_get_tls_offset ();
5831 lmf_tls_offset = mono_get_lmf_tls_offset ();
5832 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5833 thread_tls_offset = mono_thread_get_tls_offset ();
5834 #endif
5835 }
5836 }
5837
5838 void
5839 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5840 {
5841 }
5842
5843 #ifdef MONO_ARCH_HAVE_IMT
5844
5845 #define CMP_SIZE (6 + 1)
5846 #define CMP_REG_REG_SIZE (4 + 1)
5847 #define BR_SMALL_SIZE 2
5848 #define BR_LARGE_SIZE 6
5849 #define MOV_REG_IMM_SIZE 10
5850 #define MOV_REG_IMM_32BIT_SIZE 6
5851 #define JUMP_REG_SIZE (2 + 1)
5852
5853 static int
5854 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5855 {
5856 int i, distance = 0;
5857 for (i = start; i < target; ++i)
5858 distance += imt_entries [i]->chunk_size;
5859 return distance;
5860 }
5861
5862 /*
5863 * LOCKING: called with the domain lock held
5864 */
5865 gpointer
5866 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5867 gpointer fail_tramp)
5868 {
5869 int i;
5870 int size = 0;
5871 guint8 *code, *start;
5872 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5873
5874 for (i = 0; i < count; ++i) {
5875 MonoIMTCheckItem *item = imt_entries [i];
5876 if (item->is_equals) {
5877 if (item->check_target_idx) {
5878 if (!item->compare_done) {
5879 if (amd64_is_imm32 (item->key))
5880 item->chunk_size += CMP_SIZE;
5881 else
5882 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5883 }
5884 if (item->has_target_code) {
5885 item->chunk_size += MOV_REG_IMM_SIZE;
5886 } else {
5887 if (vtable_is_32bit)
5888 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5889 else
5890 item->chunk_size += MOV_REG_IMM_SIZE;
5891 }
5892 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5893 } else {
5894 if (fail_tramp) {
5895 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5896 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5897 } else {
5898 if (vtable_is_32bit)
5899 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5900 else
5901 item->chunk_size += MOV_REG_IMM_SIZE;
5902 item->chunk_size += JUMP_REG_SIZE;
5903 /* with assert below:
5904 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5905 */
5906 }
5907 }
5908 } else {
5909 if (amd64_is_imm32 (item->key))
5910 item->chunk_size += CMP_SIZE;
5911 else
5912 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5913 item->chunk_size += BR_LARGE_SIZE;
5914 imt_entries [item->check_target_idx]->compare_done = TRUE;
5915 }
5916 size += item->chunk_size;
5917 }
5918 if (fail_tramp)
5919 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5920 else
5921 code = mono_domain_code_reserve (domain, size);
5922 start = code;
5923 for (i = 0; i < count; ++i) {
5924 MonoIMTCheckItem *item = imt_entries [i];
5925 item->code_target = code;
5926 if (item->is_equals) {
5927 if (item->check_target_idx) {
5928 if (!item->compare_done) {
5929 if (amd64_is_imm32 (item->key))
5930 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5931 else {
5932 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5933 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5934 }
5935 }
5936 item->jmp_code = code;
5937 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5938 /* See the comment below about R10 */
5939 if (item->has_target_code) {
5940 amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5941 amd64_jump_reg (code, AMD64_R10);
5942 } else {
5943 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5944 amd64_jump_membase (code, AMD64_R10, 0);
5945 }
5946 } else {
5947 if (fail_tramp) {
5948 if (amd64_is_imm32 (item->key))
5949 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5950 else {
5951 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5952 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5953 }
5954 item->jmp_code = code;
5955 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5956 if (item->has_target_code) {
5957 amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5958 amd64_jump_reg (code, AMD64_R10);
5959 } else {
5960 g_assert (vtable);
5961 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5962 amd64_jump_membase (code, AMD64_R10, 0);
5963 }
5964 amd64_patch (item->jmp_code, code);
5965 amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5966 amd64_jump_reg (code, AMD64_R10);
5967 item->jmp_code = NULL;
5968
5969 } else {
5970 /* enable the commented code to assert on wrong method */
5971 #if 0
5972 if (amd64_is_imm32 (item->key))
5973 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5974 else {
5975 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5976 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5977 }
5978 item->jmp_code = code;
5979 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5980 /* See the comment below about R10 */
5981 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5982 amd64_jump_membase (code, AMD64_R10, 0);
5983 amd64_patch (item->jmp_code, code);
5984 amd64_breakpoint (code);
5985 item->jmp_code = NULL;
5986 #else
5987 /* We're using R10 here because R11
5988 needs to be preserved. R10 needs
5989 to be preserved for calls which
5990 require a runtime generic context,
5991 but interface calls don't. */
5992 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5993 amd64_jump_membase (code, AMD64_R10, 0);
5994 #endif
5995 }
5996 }
5997 } else {
5998 if (amd64_is_imm32 (item->key))
5999 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6000 else {
6001 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6002 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6003 }
6004 item->jmp_code = code;
6005 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6006 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6007 else
6008 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6009 }
6010 g_assert (code - item->code_target <= item->chunk_size);
6011 }
6012 /* patch the branches to get to the target items */
6013 for (i = 0; i < count; ++i) {
6014 MonoIMTCheckItem *item = imt_entries [i];
6015 if (item->jmp_code) {
6016 if (item->check_target_idx) {
6017 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6018 }
6019 }
6020 }
6021
6022 if (!fail_tramp)
6023 mono_stats.imt_thunks_size += code - start;
6024 g_assert (code - start <= size);
6025
6026 return start;
6027 }
6028
6029 MonoMethod*
6030 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6031 {
6032 return regs [MONO_ARCH_IMT_REG];
6033 }
6034
6035 MonoObject*
6036 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6037 {
6038 return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6039 }
6040
6041 void
6042 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6043 {
6044 /* Done by the implementation of the CALL_MEMBASE opcodes */
6045 }
6046 #endif
6047
6048 MonoVTable*
6049 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6050 {
6051 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6052 }
6053
6054 MonoInst*
6055 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6056 {
6057 MonoInst *ins = NULL;
6058 int opcode = 0;
6059
6060 if (cmethod->klass == mono_defaults.math_class) {
6061 if (strcmp (cmethod->name, "Sin") == 0) {
6062 opcode = OP_SIN;
6063 } else if (strcmp (cmethod->name, "Cos") == 0) {
6064 opcode = OP_COS;
6065 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6066 opcode = OP_SQRT;
6067 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6068 opcode = OP_ABS;
6069 }
6070
6071 if (opcode) {
6072 MONO_INST_NEW (cfg, ins, opcode);
6073 ins->type = STACK_R8;
6074 ins->dreg = mono_alloc_freg (cfg);
6075 ins->sreg1 = args [0]->dreg;
6076 MONO_ADD_INS (cfg->cbb, ins);
6077 }
6078
6079 opcode = 0;
6080 if (cfg->opt & MONO_OPT_CMOV) {
6081 if (strcmp (cmethod->name, "Min") == 0) {
6082 if (fsig->params [0]->type == MONO_TYPE_I4)
6083 opcode = OP_IMIN;
6084 if (fsig->params [0]->type == MONO_TYPE_U4)
6085 opcode = OP_IMIN_UN;
6086 else if (fsig->params [0]->type == MONO_TYPE_I8)
6087 opcode = OP_LMIN;
6088 else if (fsig->params [0]->type == MONO_TYPE_U8)
6089 opcode = OP_LMIN_UN;
6090 } else if (strcmp (cmethod->name, "Max") == 0) {
6091 if (fsig->params [0]->type == MONO_TYPE_I4)
6092 opcode = OP_IMAX;
6093 if (fsig->params [0]->type == MONO_TYPE_U4)
6094 opcode = OP_IMAX_UN;
6095 else if (fsig->params [0]->type == MONO_TYPE_I8)
6096 opcode = OP_LMAX;
6097 else if (fsig->params [0]->type == MONO_TYPE_U8)
6098 opcode = OP_LMAX_UN;
6099 }
6100 }
6101
6102 if (opcode) {
6103 MONO_INST_NEW (cfg, ins, opcode);
6104 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6105 ins->dreg = mono_alloc_ireg (cfg);
6106 ins->sreg1 = args [0]->dreg;
6107 ins->sreg2 = args [1]->dreg;
6108 MONO_ADD_INS (cfg->cbb, ins);
6109 }
6110
6111 #if 0
6112 /* OP_FREM is not IEEE compatible */
6113 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6114 MONO_INST_NEW (cfg, ins, OP_FREM);
6115 ins->inst_i0 = args [0];
6116 ins->inst_i1 = args [1];
6117 }
6118 #endif
6119 }
6120
6121 /*
6122 * Can't implement CompareExchange methods this way since they have
6123 * three arguments.
6124 */
6125
6126 return ins;
6127 }
6128
6129 gboolean
6130 mono_arch_print_tree (MonoInst *tree, int arity)
6131 {
6132 return 0;
6133 }
6134
6135 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6136 {
6137 MonoInst* ins;
6138
6139 if (appdomain_tls_offset == -1)
6140 return NULL;
6141
6142 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6143 ins->inst_offset = appdomain_tls_offset;
6144 return ins;
6145 }
6146
6147 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6148 {
6149 MonoInst* ins;
6150
6151 if (thread_tls_offset == -1)
6152 return NULL;
6153
6154 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6155 ins->inst_offset = thread_tls_offset;
6156 return ins;
6157 }
6158
6159 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6160
6161 gpointer
6162 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6163 {
6164 switch (reg) {
6165 case AMD64_RCX: return (gpointer)ctx->rcx;
6166 case AMD64_RDX: return (gpointer)ctx->rdx;
6167 case AMD64_RBX: return (gpointer)ctx->rbx;
6168 case AMD64_RBP: return (gpointer)ctx->rbp;
6169 case AMD64_RSP: return (gpointer)ctx->rsp;
6170 default:
6171 if (reg < 8)
6172 return _CTX_REG (ctx, rax, reg);
6173 else if (reg >= 12)
6174 return _CTX_REG (ctx, r12, reg - 12);
6175 else
6176 g_assert_not_reached ();
6177 }
6178 }
Mono Debugger - Cloned from the original SVN repository at mono-cvs.ximian.com