| blob | 5a8f4cf8189e152f60a23d9751f746fd272e57fc |
1 # Alpha-class cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
5 #
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
9 #
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
13 #
14 # i integer register
15 # b base register (used in address references)
16 # f floating point register
17 # a alpha_at register
18 #
19 # d EDX register
20 # l long reg (forced eax:edx)
21 # s ECX register
22 # c register which can be used as a byte register (RAX..RDX)
23 #
24 # len:number describe the maximun length in bytes of the instruction
25 # number is a positive integer. If the length is not specified
26 # it defaults to zero. But lengths are only checked if the given opcode
27 # is encountered during compilation. Some opcodes, like CONV_U4 are
28 # transformed into other opcodes in the brg files, so they do not show up
29 # during code generation.
30 #
31 # cost:number describe how many cycles are needed to complete the instruction (unused)
32 #
33 # clob:spec describe if the instruction clobbers registers or has special needs
34 #
35 # c clobbers caller-save registers
36 # 1 clobbers the first source register
37 # a EAX is clobbered
38 # d EDX is clobbered
39 # x both the source operands are clobbered (xchg)
40 # m sets an XMM reg
41 #
42 # flags:spec describe if the instruction uses or sets the flags (unused)
43 #
44 # s sets the flags
45 # u uses the flags
46 # m uses and modifies the flags
47 #
48 # res:spec describe what units are used in the processor (unused)
49 #
50 # delay: describe delay slots (unused)
51 #
52 # the required specifiers are: len, clob (if registers are clobbered), the registers
53 # specifiers if the registers are actually used, flags (when scheduling is implemented).
54 #
55 # See the code in mini-x86.c for more details on how the specifiers are used.
56 #
57 relaxed_nop: len:4
58 break: len:4
59 jmp: len:48
60 br: len:4
61 beq: len:4
62 bge: len:4
63 bgt: len:4
64 ble: len:4
65 blt: len:4
66 bne.un: len:4
67 bge.un: len:4
68 bgt.un: len:4
69 ble.un: len:4
70 blt.un: len:4
71 label: len:0
72 add: dest:i src1:i src2:i len:4
73 sub: dest:i src1:i src2:i len:4
74 mul: dest:i src1:i src2:i len:4
75 div: dest:a src1:a src2:i len:16 clob:d
76 div.un: dest:a src1:a src2:i len:16 clob:d
77 rem: dest:d src1:a src2:i len:16 clob:a
78 rem.un: dest:d src1:a src2:i len:16 clob:a
79 and: dest:i src1:i src2:i len:4
80 or: dest:i src1:i src2:i len:4
81 xor: dest:i src1:i src2:i len:4
82 shl: dest:i src1:i src2:i len:4
83 shr: dest:i src1:i src2:i len:4
84 shr.un: dest:i src1:i src2:i len:8
85 neg: dest:i src1:i len:4
86 not: dest:i src1:i len:4
87 conv.i1: dest:i src1:i len:12
88 conv.i2: dest:i src1:i len:12
89 conv.i4: dest:i src1:i len:4
90 conv.i8: dest:i src1:i len:4
91 conv.r4: dest:f src1:i len:24
92 conv.r8: dest:f src1:i len:24
93 conv.u4: dest:i src1:i len:4
94 conv.u8: dest:i src1:i len:4
95 conv.r.un: dest:f src1:i len:8
96 throw: src1:i len:20
97 rethrow: src1:i len:20
98 conv.ovf.i4.un: dest:i src1:i len:16
99 conv.ovf.u4.un:
100 conv.ovf.u4: dest:i src1:i len:15
101 ckfinite: dest:f src1:f len:44
102 conv.u2: dest:i src1:i len:4
103 conv.u1: dest:i src1:i len:4
104 conv.i: dest:i src1:i len:4
105 mul.ovf: dest:i src1:i src2:i clob:1 len:10
106 # this opcode is handled specially in the code generator
107 mul.ovf.un: dest:i src1:i src2:i len:18
108 conv.u: dest:i src1:i len:4
109 ceq: dest:c len:8
110 cgt: dest:c len:8
111 cgt.un: dest:c len:8
112 clt: dest:c len:8
113 clt.un: dest:c len:8
114 localloc: dest:i src1:i src2:i len:40 clob:1
115 compare: src1:i src2:i len:4
116 lcompare: src1:i src2:i len:4
117 icompare: src1:i src2:i len:4
118 compare_imm: src1:i len:4
119 icompare_imm: src1:i len:4
120 fcompare: src1:f src2:f len:4
122 alpha_cmp_eq: src1:i src2:i len:4
123 alpha_cmp_imm_eq: src1:i len:4
124 alpha_cmp_ule: src1:i src2:i len:4
125 alpha_cmp_imm_ule: src1:i len:4
126 alpha_cmp_le: src1:i src2:i len:4
127 alpha_cmp_imm_le: src1:i len:4
128 alpha_cmp_lt: src1:i src2:i len:4
129 alpha_cmp_imm_lt: src1:i len:4
130 alpha_cmp_ult: src1:i src2:i len:4
131 alpha_cmp_imm_ult: src1:i len:4
133 alpha_cmpt_un: src1:f src2:f len:4
134 alpha_cmpt_un_su: src1:f src2:f len:4
135 alpha_cmpt_eq: src1:f src2:f len:4
136 alpha_cmpt_eq_su: src1:f src2:f len:4
137 alpha_cmpt_lt: src1:f src2:f len:4
138 alpha_cmpt_lt_su: src1:f src2:f len:4
139 alpha_cmpt_le: src1:f src2:f len:4
140 alpha_cmpt_le_su: src1:f src2:f len:4
142 oparglist: src1:b len:11
143 setlret: dest:i src1:i src2:i len:4
144 checkthis: src1:b len:4
145 call: dest:a clob:c len:64
146 voidcall: clob:c len:64
147 voidcall_reg: src1:i clob:c len:64
148 voidcall_membase: src1:b clob:c len:64
149 fcall: dest:f len:64 clob:c
150 fcall_reg: dest:f src1:i len:64 clob:c
151 fcall_membase: dest:f src1:b len:64 clob:c
152 lcall: dest:a len:64 clob:c
153 lcall_reg: dest:a src1:i len:64 clob:c
154 lcall_membase: dest:a src1:b len:64 clob:c
155 vcall: len:64 clob:c
156 vcall_reg: src1:i len:64 clob:c
157 vcall_membase: src1:b len:64 clob:c
158 call_reg: dest:a src1:i len:64 clob:c
159 call_membase: dest:a src1:b len:64 clob:c
160 iconst: dest:i len:40
161 i8const: dest:i len:40
162 r4const: dest:f len:40
163 r8const: dest:f len:40
164 store_membase_imm: dest:b len:4
165 store_membase_reg: dest:b src1:i len:4
166 storei8_membase_reg: dest:b src1:i len:4
167 storei1_membase_imm: dest:b len:4
168 storei1_membase_reg: dest:b src1:c len:24
169 storei2_membase_imm: dest:b len:4
170 storei2_membase_reg: dest:b src1:i len:44
171 storei4_membase_imm: dest:b len:4
172 storei4_membase_reg: dest:b src1:i len:4
173 storei8_membase_imm: dest:b len:4
174 storer4_membase_reg: dest:b src1:f len:4
175 storer8_membase_reg: dest:b src1:f len:4
176 load_membase: dest:i src1:b len:4
177 loadi1_membase: dest:c src1:b len:16
178 loadu1_membase: dest:c src1:b len:12
179 loadi2_membase: dest:i src1:b len:28
180 loadu2_membase: dest:i src1:b len:24
181 loadi4_membase: dest:i src1:b len:4
182 loadu4_membase: dest:i src1:b len:8
183 loadi8_membase: dest:i src1:b len:4
184 loadr4_membase: dest:f src1:b len:4
185 loadr8_membase: dest:f src1:b len:4
186 loadr8_spill_membase: src1:b len:4
187 loadu4_mem: dest:i len:4
188 # amd64_loadi8_memindex: dest:i src1:i src2:i len:10
189 move: dest:i src1:i len:4
190 add_imm: dest:i src1:i len:4
191 sub_imm: dest:i src1:i len:4
192 mul_imm: dest:i src1:i len:11
193 # there is no actual support for division or reminder by immediate
194 # we simulate them, though (but we need to change the burg rules
195 # to allocate a symbolic reg for src2)
196 div_imm: dest:a src1:i src2:i len:16 clob:d
197 div_un_imm: dest:a src1:i src2:i len:16 clob:d
198 rem_imm: dest:d src1:i src2:i len:16 clob:a
199 rem_un_imm: dest:d src1:i src2:i len:16 clob:a
200 and_imm: dest:i src1:i len:4
201 or_imm: dest:i src1:i len:4
202 xor_imm: dest:i src1:i len:4
203 shl_imm: dest:i src1:i len:4
204 shr_imm: dest:i src1:i len:8
205 shr_un_imm: dest:i src1:i len:8
206 cond_exc_eq: len:8
207 cond_exc_ne_un: len:8
208 cond_exc_lt: len:8
209 cond_exc_lt_un: len:8
210 cond_exc_gt: len:28
211 cond_exc_gt_un: len:28
212 cond_exc_ge: len:8
213 cond_exc_ge_un: len:8
214 cond_exc_le: len:8
215 cond_exc_le_un: len:8
216 cond_exc_ov: len:8
217 cond_exc_no: len:8
218 cond_exc_c: len:8
219 cond_exc_nc: len:8
220 cond_exc_iov: len:8
221 cond_exc_ic: len:8
222 long_mul: dest:i src1:i src2:i clob:1 len:4
223 long_mul_imm: dest:i src1:i clob:1 len:12
224 long_div: dest:a src1:a src2:i len:16 clob:d
225 long_div_un: dest:a src1:a src2:i len:16 clob:d
226 long_rem: dest:d src1:a src2:i len:16 clob:a
227 long_rem_un: dest:d src1:a src2:i len:16 clob:a
228 long_shl: dest:i src1:i src2:i len:4
229 long_shr: dest:i src1:i src2:i len:4
230 long_shr_un: dest:i src1:i src2:i len:4
231 long_conv_to_r4: dest:f src1:i len:24
232 long_conv_to_r8: dest:f src1:i len:24
233 long_conv_to_ovf_i: dest:i src1:i src2:i len:40
234 long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
235 long_mul_ovf_un: dest:i src1:i src2:i len:22
236 long_conv_to_r_un: dest:f src1:i src2:i len:48
237 long_shr_imm: dest:i src1:i len:4
238 long_shr_un_imm: dest:i src1:i len:4
239 long_shl_imm: dest:i src1:i len:4
240 float_beq: len:4
241 float_bne_un: len:12
242 float_blt: len:4
243 float_blt_un: len:12
244 float_bgt: len:4
245 float_bgt_un: len:12
246 float_bge: len:4
247 float_bge_un: len:12
248 float_ble: len:4
249 float_ble_un: len:12
250 float_add: dest:f src1:f src2:f len:8
251 float_sub: dest:f src1:f src2:f len:8
252 float_mul: dest:f src1:f src2:f len:5
253 float_div: dest:f src1:f src2:f len:8
254 float_div_un: dest:f src1:f src2:f len:8
255 float_rem: dest:f src1:f src2:f len:19
256 float_rem_un: dest:f src1:f src2:f len:19
257 float_neg: dest:f src1:f len:23
258 float_not: dest:f src1:f len:3
259 float_conv_to_i1: dest:i src1:f len:49
260 float_conv_to_i2: dest:i src1:f len:49
261 float_conv_to_i4: dest:i src1:f len:49
262 float_conv_to_i8: dest:i src1:f len:49
263 float_conv_to_u4: dest:i src1:f len:49
264 float_conv_to_u8: dest:i src1:f len:49
265 float_conv_to_u2: dest:i src1:f len:49
266 float_conv_to_u1: dest:i src1:f len:49
267 float_conv_to_i: dest:i src1:f len:49
268 float_conv_to_ovf_i: dest:a src1:f len:40
269 float_conv_to_ovd_u: dest:a src1:f len:40
270 float_conv_to_r4: dest:f src1:f len:8
271 float_conv_to_r8: dest:f src1:f len:8
272 float_mul_ovf:
273 float_ceq: dest:i src1:f src2:f len:35
274 float_cgt: dest:i src1:f src2:f len:35
275 float_cgt_un: dest:i src1:f src2:f len:48
276 float_clt: dest:i src1:f src2:f len:35
277 float_clt_un: dest:i src1:f src2:f len:42
278 float_ceq_membase: dest:i src1:f src2:b len:35
279 float_cgt_membase: dest:i src1:f src2:b len:35
280 float_cgt_un_membase: dest:i src1:f src2:b len:48
281 float_clt_membase: dest:i src1:f src2:b len:35
282 float_clt_un_membase: dest:i src1:f src2:b len:42
283 float_conv_to_u: dest:i src1:f len:46
284 fmove: dest:f src1:f len:8
285 call_handler: len:4
286 start_handler: len:96
287 endfinally: len:96
288 endfilter: src1:i len:96
289 aot_const: dest:i len:10
290 # x86_test_null: src1:i len:5
291 # x86_compare_membase_reg: src1:b src2:i len:9
292 # x86_compare_membase_imm: src1:b len:13
293 # x86_compare_reg_membase: src1:i src2:b len:8
294 # x86_inc_reg: dest:i src1:i clob:1 len:3
295 # x86_inc_membase: src1:b len:8
296 # x86_dec_reg: dest:i src1:i clob:1 len:3
297 # x86_dec_membase: src1:b len:8
298 # x86_add_membase_imm: src1:b len:13
299 # x86_sub_membase_imm: src1:b len:13
300 # x86_push: src1:i len:3
301 # x86_push_imm: len:6
302 # x86_push_membase: src1:b len:8
303 # x86_push_obj: src1:b len:40
304 # x86_lea: dest:i src1:i src2:i len:8
305 # x86_lea_membase: dest:i src1:i len:11
306 # x86_xchg: src1:i src2:i clob:x len:2
307 # x86_fpop: src1:f len:3
308 # x86_fp_load_i8: dest:f src1:b len:8
309 # x86_fp_load_i4: dest:f src1:b len:8
310 # x86_seteq_membase: src1:b len:9
311 # x86_add_membase: dest:i src1:i src2:b clob:1 len:13
312 # x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
313 # x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
314 tls_get: dest:i len:13
315 # amd64_test_null: src1:i len:5
316 # amd64_icompare_membase_reg: src1:b src2:i len:8
317 # amd64_icompare_membase_imm: src1:b len:13
318 # amd64_icompare_reg_membase: src1:i src2:b len:8
319 # amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
320 # amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
321 atomic_add_i4: src1:b src2:i dest:i len:32
322 atomic_add_new_i4: src1:b src2:i dest:i len:32
323 atomic_exchange_i4: src1:b src2:i dest:i len:32
324 atomic_add_i8: src1:b src2:i dest:i len:32
325 atomic_add_new_i8: src1:b src2:i dest:i len:32
326 atomic_exchange_i8: src1:b src2:i dest:i len:32
327 memory_barrier: len:16
328 alpha_trapb: len:4
329 adc: dest:i src1:i src2:i len:3 clob:1
330 addcc: dest:i src1:i src2:i len:28
331 subcc: dest:i src1:i src2:i len:28
332 adc_imm: dest:i src1:i len:8 clob:1
333 sbb: dest:i src1:i src2:i len:3 clob:1
334 sbb_imm: dest:i src1:i len:8 clob:1
335 br_reg: src1:i len:4
336 sin: dest:f src1:f len:32
337 cos: dest:f src1:f len:32
338 abs: dest:f src1:f len:4
339 tan: dest:f src1:f len:59
340 atan: dest:f src1:f len:9
341 sqrt: dest:f src1:f len:32
342 bigmul: len:3 dest:i src1:a src2:i
343 bigmul_un: len:3 dest:i src1:a src2:i
344 sext_i1: dest:i src1:i len:8
345 sext_i2: dest:i src1:i len:8
346 sext_i4: dest:i src1:i len:8
348 # 32 bit opcodes
349 # FIXME: fix sizes
350 int_add: dest:i src1:i src2:i len:4
351 int_sub: dest:i src1:i src2:i len:4
352 int_mul: dest:i src1:i src2:i clob:1 len:64
353 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
354 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
355 int_div: dest:a src1:a src2:i clob:d len:64
356 int_div_un: dest:a src1:a src2:i clob:d len:64
357 int_rem: dest:d src1:a src2:i clob:a len:64
358 int_rem_un: dest:d src1:a src2:i clob:a len:64
359 int_and: dest:i src1:i src2:i len:4
360 int_or: dest:i src1:i src2:i len:4
361 int_xor: dest:i src1:i src2:i len:4
362 int_shl: dest:i src1:i src2:i len:8
363 int_shr: dest:i src1:i src2:i len:8
364 int_shr_un: dest:i src1:i src2:i len:8
365 int_adc: dest:i src1:i src2:i clob:1 len:64
366 int_adc_imm: dest:i src1:i clob:1 len:64
367 int_sbb: dest:i src1:i src2:i clob:1 len:64
368 int_sbb_imm: dest:i src1:i clob:1 len:64
369 int_addcc: dest:i src1:i src2:i len:28
370 int_subcc: dest:i src1:i src2:i len:28
371 int_add_imm: dest:i src1:i len:4
372 int_sub_imm: dest:i src1:i len:4
373 int_mul_imm: dest:i src1:i clob:1 len:64
374 int_div_imm: dest:a src1:i clob:d len:64
375 int_div_un_imm: dest:a src1:i clob:d len:64
376 int_rem_imm: dest:d src1:i clob:a len:64
377 int_rem_un_imm: dest:d src1:i clob:a len:64
378 int_and_imm: dest:i src1:i len:4
379 int_or_imm: dest:i src1:i len:4
380 int_xor_imm: dest:i src1:i len:4
381 int_shl_imm: dest:i src1:i len:8
382 int_shr_imm: dest:i src1:i len:8
383 int_shr_un_imm: dest:i src1:i len:8
384 int_neg: dest:i src1:i len:4
385 int_not: dest:i src1:i len:4
386 int_ceq: dest:c len:64
387 int_cgt: dest:c len:64
388 int_cgt_un: dest:c len:64
389 int_clt: dest:c len:8
390 int_clt_un: dest:c len:8
391 int_beq: len:4
392 int_bne_un: len:4
393 int_blt: len:4
394 int_blt_un: len:4
395 int_bgt: len:4
396 int_bgt_un: len:4
397 int_bge: len:4
398 int_bge_un: len:4
399 int_ble: len:4
400 int_ble_un: len:4