Lab_2/DataPaths/DataPathB_TB.vhd

   1
   2 LIBRARY ieee;
   3 USE ieee.std_logic_1164.ALL;
   4 USE work.DigEng.ALL;
   5 USE work.easyprint.ALL;
   6 USE ieee.numeric_std.ALL;
   7
   8 ENTITY DataPathB_TB IS
   9 END DataPathB_TB;
  10
  11 ARCHITECTURE behavior OF DataPathB_TB IS
  12
  13         -- Constants
  14         constant data_size : NATURAL := 16;
  15         constant num_registers : NATURAL := 32;
  16
  17         -- Component Declaration for the Unit Under Test (UUT)
  18
  19         COMPONENT DataPath_B
  20                 GENERIC(
  21                         data_size : natural;
  22                         num_registers : natural
  23                 );
  24                 PORT(
  25                         R_A : IN  std_logic_vector(log2(num_registers)-1 downto 0);
  26                         R_B : IN  std_logic_vector(log2(num_registers)-1 downto 0);
  27                         W_EN : IN  std_logic;
  28                         W_A : IN  std_logic_vector(log2(num_registers)-1 downto 0);
  29                         clk : IN  std_logic;
  30                         IMM : IN  std_logic_vector(data_size-1 downto 0);
  31                         AL : IN  std_logic_vector(3 downto 0);
  32                         SH : IN  std_logic_vector(log2(data_size)-1 downto 0);
  33                         M_A : IN  std_logic_vector(data_size-1 downto 0);
  34                         S : IN  std_logic_vector(4 downto 1);
  35                         flags : OUT  std_logic_vector(7 downto 0);
  36                         M_B : OUT  std_logic_vector(data_size-1 downto 0);
  37                         M_DA : OUT  std_logic_vector(data_size-1 downto 0);
  38                         M_in : IN  std_logic_vector(data_size-1 downto 0)
  39                 );
  40         END COMPONENT;
  41
  42
  43    --Inputs
  44    signal R_A   : std_logic_vector      (log2(num_registers)-1 downto 0) := (others => '0');
  45    signal R_B   : std_logic_vector      (log2(num_registers)-1 downto 0) := (others => '0');
  46    signal W_EN : std_logic                                                                                                              := '0';
  47    signal W_A   : std_logic_vector      (log2(num_registers)-1 downto 0) := (others => '0');
  48    signal clk   : std_logic                                                                                                             := '0';
  49    signal IMM   : std_logic_vector      (data_size-1 downto 0)                          := (others => '0');
  50    signal AL    : std_logic_vector      (3 downto 0)                                                    := (others => '0');
  51    signal SH    : std_logic_vector      (log2(data_size)-1 downto 0)            := (others => '0');
  52    signal M_A   : std_logic_vector      (data_size-1 downto 0)                          := (others => '0');
  53    signal S     : std_logic_vector      (4 downto 1)                                                    := (others => '0');
  54    signal M_in : std_logic_vector       (data_size-1 downto 0)                          := (others => '0');
  55
  56         --Outputs
  57    signal flags         : std_logic_vector      (7 downto 0);
  58    signal M_B           : std_logic_vector      (data_size-1 downto 0);
  59    signal M_DA  : std_logic_vector      (data_size-1 downto 0);
  60
  61    -- Clock period definitions
  62    constant clk_period  : time  := 10 ns;
  63    constant wait_time   : time  := clk_period;
  64
  65
  66         type TEST_VECTOR is RECORD
  67                  W_EN : std_logic;
  68                  AL : std_logic_vector(3 downto 0);
  69                  R_A : STD_LOGIC_VECTOR(log2(num_registers)-1 downto 0);
  70                  R_B : std_logic_vector(log2(num_registers)-1 downto 0);
  71                  W_A : std_logic_vector(log2(num_registers)-1 downto 0);
  72                  IMM : std_logic_vector(data_size-1 downto 0);
  73                  SH : std_logic_vector(log2(data_size)-1 downto 0) ;
  74                  M_A : std_logic_vector(data_size-1 downto 0);
  75                  S : std_logic_vector(4 downto 1);
  76                  M_in : std_logic_vector(data_size-1 downto 0);
  77
  78                  flags : std_logic_vector(7 downto 0);
  79                  M_B : std_logic_vector(data_size-1 downto 0);
  80                  M_DA : std_logic_vector(data_size-1 downto 0);
  81         end RECORD;
  82
  83
  84         type TEST_VECTOR_ARRAY is ARRAY(NATURAL RANGE <>) of TEST_VECTOR;
  85
  86         constant test_vectors : TEST_VECTOR_ARRAY := (
  87                 --W_EN,         AL,             R_A,            R_B,            W_A,            IMM,                            SH,             M_A,                            S,              M_in,                           flags,          M_B,                            M_DA
  88                 (       '1',    "1000", "00000",        "-----",        "00001",        "----------------",     "----", "----------------",     "0---", "----------------",     "01010110",     "----------------",     "----------------"      ),
  89                 (       '1',    "1010", "00000",        "-----",        "00010",        X"0005",                        "----", "----------------",     "0--1", "----------------",     "01010010",     "----------------",     "----------------"      ),
  90                 (       '1',    "1100", "00001",        "-----",        "00011",        "----------------",     "0011", "----------------",     "0---", "----------------",     "01010010",     "----------------",     "----------------"      ),
  91                 (       '0',    "0000", "00011",        "00010",        "-----",        "----------------",     "----", "----------------",     "0---", "----------------",     "01010010",     X"0005",                        X"0008"                         ),
  92                 (       '1',    "----", "-----",        "-----",        "00101",        "----------------",     "----", X"1f1f",                        "11--", X"CCCC",                        "--------",     "----------------",     X"1f1f"                         )
  93         );
  94
  95 BEGIN
  96
  97         -- Instantiate the Unit Under Test (UUT)
  98    uut: DataPath_B
  99         Generic Map(
 100                 data_size => data_size,
 101                 num_registers => num_registers
 102         )
 103         PORT MAP (
 104           R_A => R_A,
 105           R_B => R_B,
 106           W_EN => W_EN,
 107           W_A => W_A,
 108           clk => clk,
 109           IMM => IMM,
 110           AL => AL,
 111           SH => SH,
 112           M_A => M_A,
 113           S => S,
 114           flags => flags,
 115           M_B => M_B,
 116           M_DA => M_DA,
 117           M_in => M_in
 118         );
 119
 120    -- Clock process definitions
 121    clk_process :process
 122    begin
 123                 clk <= '0';
 124                 wait for clk_period/2;
 125                 clk <= '1';
 126                 wait for clk_period/2;
 127    end process;
 128
 129
 130         -- Stimulus process
 131         stim_proc: process
 132         begin
 133
 134                 -- hold reset state for 100 ns.
 135                 wait for 100 ns;
 136
 137                 -- run the test for every set of data
 138                 for i in test_vectors'range loop
 139
 140                         -- assign test inputs
 141                         R_A <= test_vectors(i).R_A;
 142                         R_B <= test_vectors(i).R_B;
 143                         W_EN <= test_vectors(i).W_EN;
 144                         W_A <= test_vectors(i).W_A;
 145                         IMM <= test_vectors(i).IMM;
 146                         AL <= test_vectors(i).AL;
 147                         SH <= test_vectors(i).SH;
 148                         M_A <= test_vectors(i).M_A;
 149                         S <= test_vectors(i).S;
 150                         M_in <= test_vectors(i).M_in;
 151
 152                         -- wait long enough for the Data path to process the inputs
 153                         wait for wait_time;
 154
 155
 156                         assert std_match(flags, test_vectors(i).flags)
 157                         report lf & " [ERR!] Test " & integer'image(i)& lf &
 158                                 " Actual flags did not equal expected flags."&
 159                                 " Actual [ " & to_bstring(flags) & " ]" &
 160                                 " Expected [ " & to_bstring(test_vectors(i).flags) & " ]"
 161                         severity error;
 162
 163                         assert std_match(test_vectors(i).M_B, M_B) -- have to use std_match when comparing meta values like '-'
 164                         report lf &" [ERR!] Test " & integer'image(i)& lf &
 165                                 " Actual value to memory did not equal expected value to memory."&
 166                                 " Actual [ " & u_tostr(M_B) & " ]" &
 167                                 " Expected [ " & u_tostr(test_vectors(i).M_B) & " ]"
 168                         severity error;
 169
 170                         assert std_match(M_DA , test_vectors(i).M_DA)
 171                         report lf &" [ERR!] Test " & integer'image(i)& lf &
 172                                 " Actual memory address did not equal expected memory address."&
 173                                 " Actual [ " & u_tostr(M_DA) & " ]" &
 174                                 " Expected [ " & u_tostr(test_vectors(i).M_DA) & " ]"
 175                         severity error;
 176
 177                         -- if there were no isses report that the test was successful
 178                         assert not (
 179                                 std_match(flags, test_vectors(i).flags) and
 180                                 std_match(M_B, test_vectors(i).M_B) and
 181                                 std_match(M_DA, test_vectors(i).M_DA))
 182                         report lf &" [ OK ] Test " & integer'image(i)& " was successful!"
 183                         severity note;
 184
 185                         wait for wait_time;
 186
 187                 end loop;
 188
 189                 wait;
 190
 191         end process;
 192
 193 END;