Lab_2/DataPaths/DataPath_D_TB.vhd

   1 --------------------------------------------------------------------------------
   2 -- Company:
   3 -- Engineer:
   4 --
   5 -- Create Date:   20:38:31 03/11/2017
   6 -- Design Name:
   7 -- Module Name:   E:/University/_Second Year/Computer Architectures/assesment/MyMicroProccessor/Lab_2/DataPaths/DataPath_D_TB.vhd
   8 -- Project Name:  DataPaths
   9 -- Target Device:
  10 -- Tool versions:
  11 -- Description:
  12 --
  13 -- VHDL Test Bench Created by ISE for module: DataPath_D
  14 --
  15 -- Dependencies:
  16 --
  17 -- Revision:
  18 -- Revision 0.01 - File Created
  19 -- Additional Comments:
  20 --
  21 -- Notes:
  22 -- This testbench has been automatically generated using types std_logic and
  23 -- std_logic_vector for the ports of the unit under test.  Xilinx recommends
  24 -- that these types always be used for the top-level I/O of a design in order
  25 -- to guarantee that the testbench will bind correctly to the post-implementation
  26 -- simulation model.
  27 --------------------------------------------------------------------------------
  28 LIBRARY ieee;
  29 USE ieee.std_logic_1164.ALL;
  30 USE work.DigEng.ALL;
  31 USE work.easyprint.ALL;
  32
  33 -- Uncomment the following library declaration if using
  34 -- arithmetic functions with Signed or Unsigned values
  35 --USE ieee.numeric_std.ALL;
  36
  37 ENTITY DataPath_D_TB IS
  38 END DataPath_D_TB;
  39
  40 ARCHITECTURE behavior OF DataPath_D_TB IS
  41
  42      -- Constants
  43         constant data_size : NATURAL := 16;
  44         constant num_registers : NATURAL := 32;
  45
  46
  47     -- Component Declaration for the Unit Under Test (UUT)
  48     COMPONENT DataPath_D
  49         GENERIC(
  50                 data_size : natural;
  51                 num_registers : natural
  52         );
  53     PORT(
  54                 clk : in  STD_LOGIC;
  55                 rst : in STD_LOGIC;
  56                 en : in STD_LOGIC;
  57
  58                 R_A : in  STD_LOGIC_VECTOR (log2(num_registers)-1 downto 0);
  59                 R_B : in  STD_LOGIC_VECTOR (log2(num_registers)-1 downto 0);
  60                 W_EN : in  STD_LOGIC;
  61                 W_A : in  STD_LOGIC_VECTOR (log2(num_registers)-1 downto 0);
  62                 IMM : in  STD_LOGIC_VECTOR (data_size-1 downto 0);
  63                 M_A : in  STD_LOGIC_VECTOR (data_size-1 downto 0);
  64                 M_in : in  STD_LOGIC_VECTOR (data_size-1 downto 0);
  65                 SEL : in  STD_LOGIC_VECTOR (7 downto 0);
  66                 AL : in  STD_LOGIC_VECTOR (3 downto 0);
  67                 SH : in  STD_LOGIC_VECTOR (log2(data_size)-1 downto 0);
  68
  69                 Flags : out  STD_LOGIC_VECTOR (7 downto 0);
  70                 M_DA : out  STD_LOGIC_VECTOR (data_size-1 downto 0);
  71                 M_out : out  STD_LOGIC_VECTOR (data_size-1 downto 0)
  72         );
  73     END COMPONENT;
  74
  75
  76    --Inputs
  77    signal clk : std_logic := '0';
  78    signal rst : std_logic := '1';
  79    signal en : std_logic :=  '0';
  80
  81    signal R_A : std_logic_vector(log2(num_registers)-1 downto 0) := (others => '0');
  82    signal R_B : std_logic_vector(log2(num_registers)-1 downto 0) := (others => '0');
  83    signal W_EN : std_logic := '0';
  84    signal W_A : std_logic_vector(log2(num_registers)-1 downto 0) := (others => '0');
  85    signal IMM : std_logic_vector(data_size-1 downto 0) := (others => '0');
  86    signal M_A : std_logic_vector(data_size-1 downto 0) := (others => '0');
  87    signal M_in : std_logic_vector(data_size-1 downto 0) := (others => '0');
  88    signal SEL : std_logic_vector(7 downto 0) := (others => '0');
  89    signal AL : std_logic_vector(3 downto 0) := (others => '0');
  90    signal SH : std_logic_vector(log2(data_size)-1 downto 0) := (others => '0');
  91
  92         --Outputs
  93    signal Flags : std_logic_vector(7 downto 0);
  94    signal M_DA : std_logic_vector(data_size-1 downto 0);
  95    signal M_out : std_logic_vector(data_size-1 downto 0);
  96
  97    -- Clock period definitions
  98    constant clk_period : time := 10 ns;
  99
 100         -- Test data definitions
 101         type TEST_VECTOR is RECORD
 102                  R_A    : STD_LOGIC_VECTOR(log2(num_registers)-1 downto 0);
 103                  R_B    : std_logic_vector(log2(num_registers)-1 downto 0);
 104
 105                  W_EN   : std_logic;
 106                  W_A    : std_logic_vector(log2(num_registers)-1 downto 0);
 107
 108                  IMM    : std_logic_vector(data_size-1 downto 0);
 109                  M_A    : std_logic_vector(data_size-1 downto 0);
 110                  M_in   : std_logic_vector(data_size-1 downto 0);
 111                  SEL    : std_logic_vector(7 downto 0);
 112                  AL     : std_logic_vector(3 downto 0);
 113                  SH     : std_logic_vector(log2(data_size)-1 downto 0) ;
 114
 115         end RECORD;
 116         type TEST_VECTOR_ARRAY is ARRAY(NATURAL RANGE <>) of TEST_VECTOR;
 117
 118         -- Test Data
 119         constant test_vectors : TEST_VECTOR_ARRAY := (
 120         --R_A,          R_B,            W_EN,   W_A,            IMM,                            M_A,                            M_in,                           SEL,            AL,             SH
 121         ( "00000",      "-----",        '0',    "-----",        "----------------",     "----------------",     "----------------",     "0-------",     "----", "----" ),
 122         ( "00000",      "-----",        '0',    "-----",        "----------------",     "----------------",     "----------------",     "0---01--",     "1000", "----" ),
 123         ( "-----",      "-----",        '0',    "-----",                           X"0005", "----------------", "----------------", "----0110", "1010", "----" ),
 124         ( "-----",      "-----",        '1',    "00001",        "----------------", "----------------", "----------------", "--1-----", "----", "----" ),
 125         ( "-----",  "-----",    '1',    "00010",        "----------------", "----------------", "----------------", "-11-11--", "1100", "0011" ),
 126         ( "-----",      "-----",        '0',    "-----",        "----------------",     "----------------", "----------------", "--1-11--", "0000", "----" ),
 127         ( "-----",      "-----",        '0',    "-----",        "----------------", "----------------", "----------------", "---0----", "----", "----" ),
 128         ( "-----",      "-----",        '0',    "-----",        "----------------", X"1F1F",                    X"CCCC",                        "---1----", "----", "----" ),
 129         ( "-----",      "-----",        '1',    "00101",        "----------------", "----------------", "----------------", "--0-----", "----", "----" )
 130
 131         );
 132
 133 BEGIN
 134
 135         -- Instantiate the Unit Under Test (UUT)
 136    uut: DataPath_D
 137         Generic Map(
 138                 data_size => data_size,
 139                 num_registers => num_registers
 140         )
 141    PORT MAP (
 142           clk => clk,
 143           R_A => R_A,
 144           R_B => R_B,
 145           W_EN => W_EN,
 146           W_A => W_A,
 147           IMM => IMM,
 148           M_A => M_A,
 149           M_in => M_in,
 150           SEL => SEL,
 151           AL => AL,
 152           SH => SH,
 153           Flags => Flags,
 154           M_DA => M_DA,
 155           M_out => M_out,
 156                   rst => rst,
 157                   en => en
 158         );
 159
 160    -- Clock process definitions
 161    clk_process :process
 162    begin
 163                 clk <= '0';
 164                 wait for clk_period/2;
 165                 clk <= '1';
 166                 wait for clk_period/2;
 167    end process;
 168
 169
 170      -- Stimulus process
 171    stim_proc: process
 172    begin
 173
 174                 -- hold reset state for 100 ns.
 175                 wait for 100 ns;
 176
 177                 rst <= '0';
 178                 en <= '1';
 179                 wait for 2*clk_period;
 180
 181                 -- run the test for every set of data
 182                 for i in test_vectors'range loop
 183
 184                         --wait for clk_period/2;
 185                         wait until rising_edge(clk);
 186
 187                         -- assign test inputs
 188                         R_A <= test_vectors(i).R_A;
 189                         R_B <= test_vectors(i).R_B;
 190
 191                         W_EN <= test_vectors(i).W_EN;
 192                         W_A <= test_vectors(i).W_A;
 193
 194                         IMM <= test_vectors(i).IMM;
 195                         M_A <= test_vectors(i).M_A;
 196                         M_in <= test_vectors(i).M_in;
 197
 198                         SEL <= test_vectors(i).SEL;
 199                         AL <= test_vectors(i).AL;
 200                         SH <= test_vectors(i).SH;
 201
 202                         --wait for clk_period/2;
 203                         wait until falling_edge(clk);
 204
 205                 end loop;
 206
 207                 -- End of test
 208                 wait;
 209         end process;
 210
 211
 212 END;