Lab_2/DataPaths/register.vhd

   1 ----------------------------------------------------------------------------------
   2 -- Company:
   3 -- Engineer:
   4 --
   5 -- Create Date:    15:01:49 03/09/2017
   6 -- Design Name:
   7 -- Module Name:    register - Behavioral
   8 -- Project Name:
   9 -- Target Devices:
  10 -- Tool versions:
  11 -- Description:
  12 --
  13 -- Dependencies:
  14 --
  15 -- Revision:
  16 -- Revision 0.01 - File Created
  17 -- Additional Comments:
  18 --
  19 ----------------------------------------------------------------------------------
  20 library IEEE;
  21 use IEEE.STD_LOGIC_1164.ALL;
  22
  23 -- Uncomment the following library declaration if using
  24 -- arithmetic functions with Signed or Unsigned values
  25 --use IEEE.NUMERIC_STD.ALL;
  26
  27 -- Uncomment the following library declaration if instantiating
  28 -- any Xilinx primitives in this code.
  29 --library UNISIM;
  30 --use UNISIM.VComponents.all;
  31
  32 entity register is
  33     Port ( clk : in  STD_LOGIC;
  34            data_in : in  STD_LOGIC_VECTOR (3 downto 0);
  35            data_out : out  STD_LOGIC_VECTOR (3 downto 0));
  36 end register;
  37
  38 architecture Behavioral of register is
  39
  40 begin
  41
  42
  43 end Behavioral;
  44