Lab_1/ParameterizableRegisterBank/DigEng.vhd

   1 ----------------------------------------------------
   2 -- PACKAGE FOR DIGITAL ENGINEERING LABS
   3 --
   4 -- To use:
   5 --
   6 -- - Download file
   7 -- - Use "Add copy" to add to Xilinx project
   8 -- - Add "use work.DigEng.all" on top of entity
   9 --
  10 ----------------------------------------------------
  11
  12 package DigEng is
  13
  14 function log2 (x : natural ) return natural;
  15 function size (x : natural ) return natural;
  16
  17 end DigEng;
  18
  19 package body DigEng is
  20
  21 ----------------------------------------------------
  22 -- LOG BASE 2 FUNCTION
  23 -- returns the ceiling of log base 2 of a (non-zero) integer
  24 -- (1->0; 2->1; 3->2; 4->2; 5->3 ...)
  25 --
  26 -- This function is NOT SYNTHESIZABLE
  27 -- should be used for indices, not circuit description
  28 --
  29 -- Examples:
  30 -- - signal A : STD_LOGIC_VECTOR(log2(data_size)-1 downto 0);
  31 --
  32 ----------------------------------------------------
  33 function log2 ( x : natural ) return natural is
  34         variable temp : natural := x ;
  35         variable n : natural := 0 ;
  36     begin
  37         while temp > 1 loop
  38             temp := temp / 2 ;
  39             n := n + 1 ;
  40         end loop ;
  41            if (x > 2**n) then
  42                 n := n + 1;
  43            end if;
  44         return n ;
  45 end function log2;
  46
  47 ----------------------------------------------------
  48 -- SIZE FUNCTION
  49 -- returns the size of a vector that can encode a (non-zero) integer
  50 -- (1->1; 2->2; 3->2; 4->3; 5->3 ...)
  51 --
  52 -- This function is NOT SYNTHESIZABLE
  53 -- should be used for indices, not circuit description
  54 --
  55 -- Examples:
  56 -- - signal A : STD_LOGIC_VECTOR(size(n)-1 downto 0);
  57 --
  58 ----------------------------------------------------
  59 function size ( x : natural ) return natural is
  60         variable temp : natural := x ;
  61         variable n : natural := 0 ;
  62     begin
  63         while temp >= 1 loop
  64             temp := temp / 2 ;
  65             n := n + 1 ;
  66         end loop ;
  67         return n ;
  68 end function size;
  69
  70 end DigEng;