Lab_1/ParameterizableRegisterBank/Param_Registers_TB.vhd

   1 ----------------------------------------------------------------------------------
   2 --
   3 -- Uni                  :       University of York
   4 -- Course               :       Electronic Engineering
   5 -- Module               :       Computer Architectures
   6 -- Engineers    :       Y3839090 & Y3840426
   7 --
   8 -- Create Date  :       23:08:04 02/23/2017
   9 -- Design Name  :       Param_Registers_TB - TestBench
  10 -- Description  :       A 16 bit 8 register dual read single write register array.
  11 --
  12 ----------------------------------------------------------------------------------
  13 LIBRARY ieee;
  14 USE ieee.std_logic_1164.ALL;
  15 USE work.DigEng.ALL;
  16
  17 ENTITY Param_Registers_TB IS
  18 END Param_Registers_TB;
  19
  20 ARCHITECTURE behavior OF Param_Registers_TB IS
  21
  22
  23         -- Constants
  24         constant num_reg : natural := 8;
  25         constant data_size : natural := 16;
  26
  27         -- Component Declaration for the Unit Under Test (UUT)
  28         COMPONENT Pram_Registers
  29                 GENERIC(
  30                         num_reg : natural;
  31                         data_size : natural
  32                 );
  33                 PORT(
  34                         addr_A : IN  std_logic_vector(log2(num_reg)-1 downto 0);
  35                         addr_B : IN  std_logic_vector(log2(num_reg)-1 downto 0);
  36                         addr_C : IN  std_logic_vector(log2(num_reg)-1 downto 0); -- Address to write to
  37                         data_in : IN  std_logic_vector(data_size-1 downto 0); -- Data to write
  38                         wr_en : IN  std_logic;
  39                         clk : IN  std_logic;
  40                         A_out : OUT  std_logic_vector(data_size-1 downto 0);
  41                         B_out : OUT  std_logic_vector(data_size-1 downto 0)
  42                 );
  43     END COMPONENT;
  44
  45
  46    --Inputs
  47    signal addr_A : std_logic_vector(log2(num_reg)-1 downto 0) := (others => '0');
  48    signal addr_B : std_logic_vector(log2(num_reg)-1 downto 0) := (others => '0');
  49    signal addr_C : std_logic_vector(log2(num_reg)-1 downto 0) := (others => '0');
  50         signal data_in : std_logic_vector(data_size-1 downto 0) := (others => '0');
  51         signal wr_en : std_logic := '0';
  52    signal clk : std_logic := '0';
  53
  54         --Outputs
  55    signal A_out : std_logic_vector(data_size-1 downto 0);
  56    signal B_out : std_logic_vector(data_size-1 downto 0);
  57
  58    -- Clock period definitions
  59    constant clk_period : time := 10 ns;
  60
  61         type TEST_VECTOR is RECORD
  62                 wr_en   : std_logic; -- Write enable
  63                 addr_A  : std_logic_vector(log2(num_reg)-1 downto 0); -- A address to read from
  64       addr_B  : std_logic_vector(log2(num_reg)-1 downto 0); -- B address to read from
  65       addr_C  : std_logic_vector(log2(num_reg)-1 downto 0); -- C address to write to
  66       data_in : std_logic_vector(data_size-1 downto 0); -- Data to write at addr_C
  67                 A_out   : std_logic_vector(data_size-1 downto 0); -- Expected data to be read from addr_A
  68       B_out   : std_logic_vector(data_size-1 downto 0); -- Expected data to be read from addr_B
  69         end RECORD;
  70
  71         type TEST_VECTOR_ARRAY is ARRAY(NATURAL range <>) of TEST_VECTOR;
  72
  73         constant test_vectors : TEST_VECTOR_ARRAY :=
  74         (
  75         -- wr_en,     addr_A,    addr_B,    addr_C,    data_in,      A_out,        B_out
  76                 ('0',      "000",      "000",      "000",      X"0000",      X"0000",      X"0000"),
  77                 ('1',      "000",      "000",      "001",      X"FFFF",      X"0000",      X"0000"),
  78                 ('1',      "000",      "000",      "010",      X"1111",      X"0000",      X"0000"),
  79                 ('0',      "001",      "010",      "000",      X"0000",      X"FFFF",      X"1111"),
  80                 ('1',      "000",      "000",      "111",      X"0011",      X"0000",      X"0000"),
  81                 ('1',      "111",      "111",      "110",      X"8800",      X"0011",      X"0011"),
  82                 ('1',      "111",      "110",      "000",      X"AAAA",      X"0011",      X"8800"),
  83                 ('0',      "000",      "000",      "000",      X"0000",      X"0000",      X"0000"),
  84
  85                 ('1',      "000",      "001",      "010",      X"1111",      X"0000",      X"FFFF"),
  86                 ('1',      "001",      "010",      "011",      X"2222",      X"FFFF",      X"1111"),
  87                 ('1',      "010",      "011",      "100",      X"3333",      X"1111",      X"2222"),
  88                 ('1',      "011",      "100",      "101",      X"4444",      X"2222",      X"3333"),
  89                 ('1',      "100",      "101",      "110",      X"5555",      X"3333",      X"4444"),
  90                 ('1',      "101",      "110",      "111",      X"6666",      X"4444",      X"5555"),
  91                 ('0',      "110",      "111",      "000",      X"0000",      X"5555",      X"6666")
  92
  93
  94         );
  95
  96 BEGIN
  97
  98         -- Instantiate the Unit Under Test (UUT)
  99         uut: Pram_Registers
 100         GENERIC MAP(
 101                 num_reg => num_reg,
 102                 data_size => data_size
 103         )
 104         PORT MAP (
 105                 addr_A => addr_A,
 106                 addr_B => addr_B,
 107                 addr_C => addr_C,
 108                 wr_en => wr_en,
 109                 clk => clk,
 110                 data_in => data_in,
 111                 A_out => A_out,
 112                 B_out => B_out
 113         );
 114
 115    -- Clock process definitions
 116    clk_process :process
 117    begin
 118                 clk <= '0';
 119                 wait for clk_period/2;
 120                 clk <= '1';
 121                 wait for clk_period/2;
 122    end process;
 123
 124
 125    -- Stimulus process
 126    stim_proc: process
 127    begin
 128
 129                 -- hold reset state for 100 ns.
 130                 wait for 100 ns;
 131
 132                 -- Loop over all of our test data sets
 133                 for i in test_vectors'range loop
 134
 135                         -- assign test inputs
 136                         wr_en <= test_vectors(i).wr_en;
 137                         addr_A <= test_vectors(i).addr_A;
 138                         addr_B <= test_vectors(i).addr_B;
 139                         addr_C <= test_vectors(i).addr_C;
 140                         data_in <= test_vectors(i).data_in;
 141
 142
 143                         -- wait for a clock cycle
 144                         wait for clk_period;
 145
 146
 147                         -- check that output A is the same as the expected
 148                         assert A_out = test_vectors(i).A_out
 149                         report " [ERR!] Test " & integer'image(i) & " : A output is not what was expected!"
 150                         severity error;
 151
 152                         -- check that output A is the same as the expected
 153                         assert B_out = test_vectors(i).B_out
 154                         report " [ERR!] Test " & integer'image(i) & " : B output is not what was expected!"
 155                         severity error;
 156
 157                         -- check that output A is the same as the expected
 158                         assert (B_out /= test_vectors(i).B_out or A_out /= test_vectors(i).A_out)
 159                         report " [ OK ] Test " & integer'image(i) & " passed!"
 160                         severity note;
 161
 162                         wait for clk_period;
 163
 164                 end loop;
 165
 166    wait;
 167    end process;
 168
 169 END;