Lab_1/ParameterizableRegisterBank/triestate_buffer.vhd

   1 ----------------------------------------------------------------------------------
   2 --
   3 -- Uni                  :       University of York
   4 -- Course               :       Electronic Engineering
   5 -- Module               :       Computer Architectures
   6 -- Engineers    :       Y3839090 & Y3840426
   7 --
   8 -- Create Date  :       21:02:48 02/23/2017
   9 -- Design Name  :       triestate_buffer - Behavioral
  10 -- Description  :       A parameteriable tristate buffer array.
  11 --
  12 ----------------------------------------------------------------------------------
  13 library IEEE;
  14 use IEEE.STD_LOGIC_1164.ALL;
  15
  16 entity triestate_buffer is
  17         Generic
  18         (
  19                 data_size : natural := 8 -- number of trie state buffers
  20         );
  21         Port (
  22                 data_in : in  STD_LOGIC_VECTOR(data_size-1 downto 0); -- data input
  23                 en : in  STD_LOGIC; -- tristate enable
  24                 data_out : out  STD_LOGIC_VECTOR(data_size-1 downto 0) -- data out
  25         );
  26 end triestate_buffer;
  27
  28 architecture Behavioral of triestate_buffer is
  29 begin
  30
  31         -- Tristate buffer implimentation from lab script
  32         DATA_OUT <=
  33                 DATA_IN when (En = '1') else
  34                 (others => 'Z'); -- Z = high-impedance
  35
  36 end Behavioral;
  37