Public Git Hosting - mymicroprocessor.git/commit

commit	8b0f8567dacc76f44c4ff9703bb9c0539bd74dbc
author	milesdig <mil@norb.it>
	Mon, 22 May 2017 10:28:47 +0000 (22 11:28 +0100)
committer	milesdig <mil@norb.it>
	Mon, 22 May 2017 10:28:47 +0000 (22 11:28 +0100)
tree	8b84a39b98e3358c5725d80fe7d9ef9b54a52536	tree \| snapshot (tar.gz zip)
parent	653b2f88089407e4a714783985a9bc1c54490c64	commit \| diff

Doesn't work but times up

59 files changed:

Project/Project/ALU_param.vhi	[deleted file]	blob \| blame \| history
Project/Project/ClockDivider.vhd	[deleted file]	blob \| blame \| history
Project/Project/ClockDivider.vhi	[deleted file]	blob \| blame \| history
Project/Project/ClockDividerColors.wcfg	[deleted file]	blob \| blame \| history
Project/Project/ClockDividerTB.vhd	[deleted file]	blob \| blame \| history
Project/Project/ControlFSM.spl	[deleted file]	blob \| blame \| history
Project/Project/ControlFSM.vhd		diff \| blob \| blame \| history
Project/Project/ControlFSM.vhi	[deleted file]	blob \| blame \| history
Project/Project/ControlFSM_TB.vhd		diff \| blob \| blame \| history
Project/Project/ControlUnit.vhd		diff \| blob \| blame \| history
Project/Project/ControlUnit.vhi	[deleted file]	blob \| blame \| history
Project/Project/DataPath_C.sym	[new file with mode: 0644]	blob
Project/Project/DataPath_C.vhi	[deleted file]	blob \| blame \| history
Project/Project/Decoder.vhd		diff \| blob \| blame \| history
Project/Project/Decoder_Block.vhi	[deleted file]	blob \| blame \| history
Project/Project/Decoder_TB.vhd		diff \| blob \| blame \| history
Project/Project/DualPortMemory.vhd		diff \| blob \| blame \| history
Project/Project/DualPortMemory.vhi	[deleted file]	blob \| blame \| history
Project/Project/DualPortMemoryTB.vhd		diff \| blob \| blame \| history
Project/Project/MMU.vhd		diff \| blob \| blame \| history
Project/Project/MMU.vhi	[deleted file]	blob \| blame \| history
Project/Project/MMU_TB.vhd		diff \| blob \| blame \| history
Project/Project/OutputReg.vhd		diff \| blob \| blame \| history
Project/Project/OutputReg.vhi	[deleted file]	blob \| blame \| history
Project/Project/OutputRegTB.vhd		diff \| blob \| blame \| history
Project/Project/Proccessor.vhd		diff \| blob \| blame \| history
Project/Project/Processor.ucf	[new file with mode: 0644]	blob
Project/Project/Processor.vhi	[deleted file]	blob \| blame \| history
Project/Project/ProcessorColors.wcfg		diff \| blob \| blame \| history
Project/Project/ProcessorTB.vhd		diff \| blob \| blame \| history
Project/Project/ProcessorTB_isim_beh1.wdb	[new file with mode: 0644]	blob
Project/Project/Project.xise		diff \| blob \| blame \| history
Project/Project/Sequencer.vhd		diff \| blob \| blame \| history
Project/Project/Sequencer.vhi	[deleted file]	blob \| blame \| history
Project/Project/SequencerTB.vhd		diff \| blob \| blame \| history
Project/Project/colors.wcfg		diff \| blob \| blame \| history
Project/Project/hello.png	[new file with mode: 0644]	blob
Project/Project/pa.fromHdl.tcl	[new file with mode: 0644]	blob
Project/Project/par_usage_statistics.html	[new file with mode: 0644]	blob
Project/Project/register.vhd		diff \| blob \| blame \| history
Project/SynthStuff/Processor.ucf	[new file with mode: 0644]	blob
Project/SynthStuff/SynthReport.txt	[new file with mode: 0644]	blob
Project/SynthStuff/Warnings.txt	[new file with mode: 0644]	blob
Project/TestBenches/ControlFSM/All.PNG	[new file with mode: 0644]	blob
Project/TestBenches/ControlFSM/log.txt	[new file with mode: 0644]	blob
Project/TestBenches/Decoder/All.PNG	[new file with mode: 0644]	blob
Project/TestBenches/Decoder/log.txt	[new file with mode: 0644]	blob
Project/TestBenches/DualPort/All.PNG	[new file with mode: 0644]	blob
Project/TestBenches/DualPort/log.txt	[new file with mode: 0644]	blob
Project/TestBenches/MMU/All.PNG	[new file with mode: 0644]	blob
Project/TestBenches/MMU/log.txt	[new file with mode: 0644]	blob
Project/TestBenches/OutputReg/All.PNG	[new file with mode: 0644]	blob
Project/TestBenches/OutputReg/log.txt	[new file with mode: 0644]	blob
Project/TestBenches/Proccessor/SimpleAdd.PNG	[new file with mode: 0644]	blob
Project/TestBenches/Proccessor/SimpleBranch.PNG	[new file with mode: 0644]	blob
Project/TestBenches/Proccessor/SimpleBranchDataPath.PNG	[new file with mode: 0644]	blob
Project/TestBenches/Proccessor/full.PNG	[new file with mode: 0644]	blob
Project/TestBenches/Sequencer/All.PNG	[new file with mode: 0644]	blob
Project/TestBenches/Sequencer/log.txt	[new file with mode: 0644]	blob

Computer Architectures project to design a 16/32 bit microprocessor in VHDL

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