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2017-05-22	milesdig	Got branch working	commit \| commitdiff \| tree
2017-05-21	milesdig	Going Insane	commit \| commitdiff \| tree
2017-05-08	milesdig	Submitting this	commit \| commitdiff \| tree
2017-05-08	milesdig	Update pdf	commit \| commitdiff \| tree
2017-05-08	milesdig	Nearly there	commit \| commitdiff \| tree
2017-05-08	milesdig	Finishing up	commit \| commitdiff \| tree
2017-05-04	milesdig	Back to work on this, after control	commit \| commitdiff \| tree
2017-04-27	milesdig	Add asm	commit \| commitdiff \| tree
2017-04-27	milesdig	Update report	commit \| commitdiff \| tree
2017-04-27	milesdig	Done full associative	commit \| commitdiff \| tree
2017-04-27	milesdig	Starting sequencer testing	commit \| commitdiff \| tree
2017-04-27	milesdig	Control Signals Table Done	commit \| commitdiff \| tree
2017-04-26	milesdig	Did control signals for Arithmetics	commit \| commitdiff \| tree
2017-04-26	milesdig	Added suggested opcodes	commit \| commitdiff \| tree
2017-04-26	milesdig	Added suggested instruction coding	commit \| commitdiff \| tree
2017-04-26	milesdig	Sequencer	commit \| commitdiff \| tree
2017-04-26	milesdig	Started on the project and homework 2	commit \| commitdiff \| tree
2017-04-26	milesdig	I've got no idea how to track this caching	commit \| commitdiff \| tree
2017-04-26	milesdig	Started HomeWork 2	commit \| commitdiff \| tree
2017-04-26	milesdig	DONE TIME TO SLEEP	commit \| commitdiff \| tree
2017-04-26	milesdig	Simulation screen shots	commit \| commitdiff \| tree
2017-04-26	milesdig	Update README.md	commit \| commitdiff \| tree
2017-04-26	milesdig	Some more comments	commit \| commitdiff \| tree
2017-04-26	milesdig	Grabbed Simulation log files	commit \| commitdiff \| tree
2017-04-26	milesdig	Update readme to mention tom	commit \| commitdiff \| tree
2017-04-26	milesdig	Grabed HDL syth report and schematics	commit \| commitdiff \| tree
2017-04-26	milesdig	That last error was a typo in the test ... :'(	commit \| commitdiff \| tree
2017-04-26	milesdig	Down to one error	commit \| commitdiff \| tree
2017-04-26	milesdig	Got it down to 2/8 tests failing for DP D	commit \| commitdiff \| tree
2017-04-26	milesdig	Figured out outputs for Arch D	commit \| commitdiff \| tree
2017-04-26	milesdig	Done for today	commit \| commitdiff \| tree
2017-04-26	milesdig	B and C working git status!	commit \| commitdiff \| tree
2017-04-26	milesdig	Realised regbank is broken	commit \| commitdiff \| tree
2017-04-26	milesdig	Giving up on this for now, Going to get DP_D working	commit \| commitdiff \| tree
2017-04-26	milesdig	Working towards fixing tests	commit \| commitdiff \| tree
2017-04-26	milesdig	Fixed simulation not being synced to clock correctly	commit \| commitdiff \| tree
2017-04-26	milesdig	More TESTINGgit add *	commit \| commitdiff \| tree
2017-04-26	milesdig	Found test control signals	commit \| commitdiff \| tree
2017-04-26	milesdig	Testbench for DP_B done, working on DP_C	commit \| commitdiff \| tree
2017-04-26	milesdig	Done most of DataPath D	commit \| commitdiff \| tree
2017-04-26	milesdig	Started work on datapath D	commit \| commitdiff \| tree
2017-04-26	milesdig	Some commenting	commit \| commitdiff \| tree
2017-04-26	milesdig	Finished seting up DataPathC Testbench. Just need to...	commit \| commitdiff \| tree
2017-04-26	milesdig	Set up testbench for DataPath C, need to add test data	commit \| commitdiff \| tree
2017-04-26	milesdig	Made DataPath_C. Time for test bench	commit \| commitdiff \| tree
2017-04-26	milesdig	Testbench now set up. Need to add more tests	commit \| commitdiff \| tree
2017-04-26	milesdig	Submitted Home work 1	commit \| commitdiff \| tree
2017-04-26	milesdig	update	commit \| commitdiff \| tree
2017-04-26	milesdig	Ready to print homework 1	commit \| commitdiff \| tree
2017-04-26	milesdig	Addd report	commit \| commitdiff \| tree
2017-04-26	milesdig	update	commit \| commitdiff \| tree
2017-04-26	milesdig	More work on the homework	commit \| commitdiff \| tree
2017-04-26	milesdig	Done a lab session, got DataPath B done and started...	commit \| commitdiff \| tree
2017-04-26	milesdig	Started Lab_2 Data paths	commit \| commitdiff \| tree
2017-04-26	milesdig	Giving up for tonight, need to ask some questions	commit \| commitdiff \| tree
2017-04-26	milesdig	update	commit \| commitdiff \| tree
2017-04-26	milesdig	Renamed folder	commit \| commitdiff \| tree
2017-04-26	milesdig	Did some work, now need foodgit add git add !	commit \| commitdiff \| tree
2017-04-26	milesdig	Finished Instruction set	commit \| commitdiff \| tree
2017-04-26	milesdig	Added report 1 to repo	commit \| commitdiff \| tree
2017-04-26	milesdig	Last few changes before subbmission and screen shots	commit \| commitdiff \| tree
2017-04-26	milesdig	Cleaned up ALU code and added failing test	commit \| commitdiff \| tree
2017-04-26	milesdig	finished up Regs lab ready for submistion	commit \| commitdiff \| tree
2017-02-24	milesdig	Last few changes before subbmission and screen shots	commit \| commitdiff \| tree
2017-02-24	milesdig	Cleaned up ALU code and added failing test	commit \| commitdiff \| tree
2017-02-24	milesdig	Lab One all working	commit \| commitdiff \| tree
2017-02-23	milesdig	Committer: Zak West <zraw500@its.york.ac.uk>	commit \| commitdiff \| tree
2017-02-22	milesdig	Added 'xor' , 'not' and 'sl' tests. Fixed issue with...	commit \| commitdiff \| tree
2017-02-22	milesdig	Better error reporting and tests for 'and' and 'or'	commit \| commitdiff \| tree
2017-02-19	milesdig	Merge pull request #5 from zwrawr/zwrawr-lab1-add-testbench	commit \| commitdiff \| tree
2017-02-18	milesdig	Fixed overflow flag and started test bench	commit \| commitdiff \| tree
2017-02-18	milesdig	Added some commenting	commit \| commitdiff \| tree
2017-02-17	milesdig	Merge pull request #4 from zwrawr/zwrawr-update-lab-one	commit \| commitdiff \| tree
2017-02-17	milesdig	Did some more work on lab one	commit \| commitdiff \| tree
2017-02-17	milesdig	Merge pull request #3 from zwrawr/zwrawr-start-lab-one	commit \| commitdiff \| tree
2017-02-16	milesdig	\# Added lab one folder and Xilinx ise project	commit \| commitdiff \| tree
2017-02-15	milesdig	Merge pull request #2 from zwrawr/zwrawr-restructure	commit \| commitdiff \| tree
2017-02-15	milesdig	Restructures folders	commit \| commitdiff \| tree
2017-02-15	milesdig	Merge pull request #1 from zwrawr/zwrawr-add-instruction-set	commit \| commitdiff \| tree
2017-02-15	milesdig	Stared on the instruction set	commit \| commitdiff \| tree
2017-02-15	milesdig	Initial commit	commit \| commitdiff \| tree

Computer Architectures project to design a 16/32 bit microprocessor in VHDL

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