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Set OSABI field back to 0 (SysV), to avoid interoperability problems
[nacl-binutils.git] / gas / config / tc-m68k.c
blob65c166d24f8110796652d3d46db0073f7306b06a
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
181 0
182 };
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
185 0
186 };
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
189 0
190 };
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
193 0
194 };
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
197 0
198 };
199 static const enum m68k_register mcf52223_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52235_ctrl[] = {
204 VBR, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf5225_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5235_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5249_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
217 0
218 };
219 static const enum m68k_register mcf5250_ctrl[] = {
220 VBR,
221 0
222 };
223 static const enum m68k_register mcf5253_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
225 0
226 };
227 static const enum m68k_register mcf5271_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
229 0
230 };
231 static const enum m68k_register mcf5272_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
233 0
234 };
235 static const enum m68k_register mcf5275_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
237 0
238 };
239 static const enum m68k_register mcf5282_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5307_ctrl[] = {
244 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
245 0
246 };
247 static const enum m68k_register mcf5329_ctrl[] = {
248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
249 0
250 };
251 static const enum m68k_register mcf5373_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcfv4e_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
258 MBAR, SECMBAR,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
264 /* Legacy names */
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
269 0
270 };
271 static const enum m68k_register mcf54455_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
273 VBR, PC, RAMBAR1, MBAR,
274 /* Legacy names */
275 TC /* ASID */, BUSCR /* MMUBAR */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
278 0
279 };
280 static const enum m68k_register mcf5475_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
283 /* Legacy names */
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
287 0
288 };
289 static const enum m68k_register mcf5485_ctrl[] = {
290 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
291 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
292 /* Legacy names */
293 TC /* ASID */, BUSCR /* MMUBAR */,
294 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
295 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
296 0
297 };
298 static const enum m68k_register fido_ctrl[] = {
299 SFC, DFC, USP, VBR, CAC, MBB,
300 0
301 };
302 #define cpu32_ctrl m68010_ctrl
303
304 static const enum m68k_register *control_regs;
305
306 /* Internal form of a 68020 instruction. */
307 struct m68k_it
308 {
309 const char *error;
310 const char *args; /* List of opcode info. */
311 int numargs;
312
313 int numo; /* Number of shorts in opcode. */
314 short opcode[11];
315
316 struct m68k_op operands[6];
317
318 int nexp; /* Number of exprs in use. */
319 struct m68k_exp exprs[4];
320
321 int nfrag; /* Number of frags we have to produce. */
322 struct
323 {
324 int fragoff; /* Where in the current opcode the frag ends. */
325 symbolS *fadd;
326 offsetT foff;
327 int fragty;
328 }
329 fragb[4];
330
331 int nrel; /* Num of reloc strucs in use. */
332 struct
333 {
334 int n;
335 expressionS exp;
336 char wid;
337 char pcrel;
338 /* In a pc relative address the difference between the address
339 of the offset and the address that the offset is relative
340 to. This depends on the addressing mode. Basically this
341 is the value to put in the offset field to address the
342 first byte of the offset, without regarding the special
343 significance of some values (in the branch instruction, for
344 example). */
345 int pcrel_fix;
346 #ifdef OBJ_ELF
347 /* Whether this expression needs special pic relocation, and if
348 so, which. */
349 enum pic_relocation pic_reloc;
350 #endif
351 }
352 reloc[5]; /* Five is enough??? */
353 };
354
355 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
356 #define float_of_arch(x) ((x) & mfloat)
357 #define mmu_of_arch(x) ((x) & mmmu)
358 #define arch_coldfire_p(x) ((x) & mcfisa_a)
359 #define arch_coldfire_fpu(x) ((x) & cfloat)
360
361 /* Macros for determining if cpu supports a specific addressing mode. */
362 #define HAVE_LONG_DISP(x) \
363 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
364 #define HAVE_LONG_CALL(x) \
365 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
366 #define HAVE_LONG_COND(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368 #define HAVE_LONG_BRANCH(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
370
371 static struct m68k_it the_ins; /* The instruction being assembled. */
372
373 #define op(ex) ((ex)->exp.X_op)
374 #define adds(ex) ((ex)->exp.X_add_symbol)
375 #define subs(ex) ((ex)->exp.X_op_symbol)
376 #define offs(ex) ((ex)->exp.X_add_number)
377
378 /* Macros for adding things to the m68k_it struct. */
379 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
380
381 /* Like addword, but goes BEFORE general operands. */
382
383 static void
384 insop (int w, const struct m68k_incant *opcode)
385 {
386 int z;
387 for (z = the_ins.numo; z > opcode->m_codenum; --z)
388 the_ins.opcode[z] = the_ins.opcode[z - 1];
389 for (z = 0; z < the_ins.nrel; z++)
390 the_ins.reloc[z].n += 2;
391 for (z = 0; z < the_ins.nfrag; z++)
392 the_ins.fragb[z].fragoff++;
393 the_ins.opcode[opcode->m_codenum] = w;
394 the_ins.numo++;
395 }
396
397 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
398 Blecch. */
399 static void
400 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
401 {
402 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
403 ? the_ins.numo * 2 - 1
404 : (width == 'b'
405 ? the_ins.numo * 2 + 1
406 : the_ins.numo * 2));
407 the_ins.reloc[the_ins.nrel].exp = exp->exp;
408 the_ins.reloc[the_ins.nrel].wid = width;
409 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
410 #ifdef OBJ_ELF
411 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
412 #endif
413 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
414 }
415
416 /* Cause an extra frag to be generated here, inserting up to 10 bytes
417 (that value is chosen in the frag_var call in md_assemble). TYPE
418 is the subtype of the frag to be generated; its primary type is
419 rs_machine_dependent.
420
421 The TYPE parameter is also used by md_convert_frag_1 and
422 md_estimate_size_before_relax. The appropriate type of fixup will
423 be emitted by md_convert_frag_1.
424
425 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
426 static void
427 add_frag (symbolS *add, offsetT off, int type)
428 {
429 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
430 the_ins.fragb[the_ins.nfrag].fadd = add;
431 the_ins.fragb[the_ins.nfrag].foff = off;
432 the_ins.fragb[the_ins.nfrag++].fragty = type;
433 }
434
435 #define isvar(ex) \
436 (op (ex) != O_constant && op (ex) != O_big)
437
438 static char *crack_operand (char *str, struct m68k_op *opP);
439 static int get_num (struct m68k_exp *exp, int ok);
440 static int reverse_16_bits (int in);
441 static int reverse_8_bits (int in);
442 static void install_gen_operand (int mode, int val);
443 static void install_operand (int mode, int val);
444 static void s_bss (int);
445 static void s_data1 (int);
446 static void s_data2 (int);
447 static void s_even (int);
448 static void s_proc (int);
449 static void s_chip (int);
450 static void s_fopt (int);
451 static void s_opt (int);
452 static void s_reg (int);
453 static void s_restore (int);
454 static void s_save (int);
455 static void s_mri_if (int);
456 static void s_mri_else (int);
457 static void s_mri_endi (int);
458 static void s_mri_break (int);
459 static void s_mri_next (int);
460 static void s_mri_for (int);
461 static void s_mri_endf (int);
462 static void s_mri_repeat (int);
463 static void s_mri_until (int);
464 static void s_mri_while (int);
465 static void s_mri_endw (int);
466 static void s_m68k_cpu (int);
467 static void s_m68k_arch (int);
468
469 struct m68k_cpu
470 {
471 unsigned long arch; /* Architecture features. */
472 const enum m68k_register *control_regs; /* Control regs on chip */
473 const char *name; /* Name */
474 int alias; /* Alias for a cannonical name. If 1, then
475 succeeds canonical name, if -1 then
476 succeeds canonical name, if <-1 ||>1 this is a
477 deprecated name, and the next/previous name
478 should be used. */
479 };
480
481 /* We hold flags for features explicitly enabled and explicitly
482 disabled. */
483 static int current_architecture;
484 static int not_current_architecture;
485 static const struct m68k_cpu *selected_arch;
486 static const struct m68k_cpu *selected_cpu;
487 static int initialized;
488
489 /* Architecture models. */
490 static const struct m68k_cpu m68k_archs[] =
491 {
492 {m68000, m68000_ctrl, "68000", 0},
493 {m68010, m68010_ctrl, "68010", 0},
494 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
495 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
496 {m68040, m68040_ctrl, "68040", 0},
497 {m68060, m68060_ctrl, "68060", 0},
498 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
499 {fido_a, fido_ctrl, "fidoa", 0},
500 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
501 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
502 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
503 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
504 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
505 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
506 {0,0,NULL, 0}
507 };
508
509 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
510 for either. */
511 static const struct m68k_cpu m68k_extensions[] =
512 {
513 {m68851, NULL, "68851", -1},
514 {m68881, NULL, "68881", -1},
515 {m68881, NULL, "68882", -1},
516
517 {cfloat|m68881, NULL, "float", 0},
518
519 {mcfhwdiv, NULL, "div", 1},
520 {mcfusp, NULL, "usp", 1},
521 {mcfmac, NULL, "mac", 1},
522 {mcfemac, NULL, "emac", 1},
523
524 {0,NULL,NULL, 0}
525 };
526
527 /* Processor list */
528 static const struct m68k_cpu m68k_cpus[] =
529 {
530 {m68000, m68000_ctrl, "68000", 0},
531 {m68000, m68000_ctrl, "68ec000", 1},
532 {m68000, m68000_ctrl, "68hc000", 1},
533 {m68000, m68000_ctrl, "68hc001", 1},
534 {m68000, m68000_ctrl, "68008", 1},
535 {m68000, m68000_ctrl, "68302", 1},
536 {m68000, m68000_ctrl, "68306", 1},
537 {m68000, m68000_ctrl, "68307", 1},
538 {m68000, m68000_ctrl, "68322", 1},
539 {m68000, m68000_ctrl, "68356", 1},
540 {m68010, m68010_ctrl, "68010", 0},
541 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
542 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
543 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
544 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
545 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
546 {m68040, m68040_ctrl, "68040", 0},
547 {m68040, m68040_ctrl, "68ec040", 1},
548 {m68060, m68060_ctrl, "68060", 0},
549 {m68060, m68060_ctrl, "68ec060", 1},
550
551 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
552 {cpu32|m68881, cpu32_ctrl, "68330", 1},
553 {cpu32|m68881, cpu32_ctrl, "68331", 1},
554 {cpu32|m68881, cpu32_ctrl, "68332", 1},
555 {cpu32|m68881, cpu32_ctrl, "68333", 1},
556 {cpu32|m68881, cpu32_ctrl, "68334", 1},
557 {cpu32|m68881, cpu32_ctrl, "68336", 1},
558 {cpu32|m68881, cpu32_ctrl, "68340", 1},
559 {cpu32|m68881, cpu32_ctrl, "68341", 1},
560 {cpu32|m68881, cpu32_ctrl, "68349", 1},
561 {cpu32|m68881, cpu32_ctrl, "68360", 1},
562
563 {mcfisa_a, mcf_ctrl, "5200", 0},
564 {mcfisa_a, mcf_ctrl, "5202", 1},
565 {mcfisa_a, mcf_ctrl, "5204", 1},
566 {mcfisa_a, mcf5206_ctrl, "5206", 1},
567
568 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
569
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
572
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
574 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
579
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
583
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
586
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
591
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
594
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
600
601 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
602 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
603 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
604
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
607
608 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
612
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
617
618 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
619
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
628
629 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
630
631 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
632 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
633 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
634 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
635 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
636 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
637
638 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
639 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
640 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
641 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
642 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
643 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
645
646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
647 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
648 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
649 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
651 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
652 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
653
654 {fido_a, fido_ctrl, "fidoa", 0},
655 {fido_a, fido_ctrl, "fido", 1},
656
657 {0,NULL,NULL, 0}
658 };
659
660 static const struct m68k_cpu *m68k_lookup_cpu
661 (const char *, const struct m68k_cpu *, int, int *);
662 static int m68k_set_arch (const char *, int, int);
663 static int m68k_set_cpu (const char *, int, int);
664 static int m68k_set_extension (const char *, int, int);
665 static void m68k_init_arch (void);
666
667 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
668 architecture and we have a lot of relaxation modes. */
669
670 /* Macros used in the relaxation code. */
671 #define TAB(x,y) (((x) << 2) + (y))
672 #define TABTYPE(x) ((x) >> 2)
673
674 /* Relaxation states. */
675 #define BYTE 0
676 #define SHORT 1
677 #define LONG 2
678 #define SZ_UNDEF 3
679
680 /* Here are all the relaxation modes we support. First we can relax ordinary
681 branches. On 68020 and higher and on CPU32 all branch instructions take
682 three forms, so on these CPUs all branches always remain as such. When we
683 have to expand to the LONG form on a 68000, though, we substitute an
684 absolute jump instead. This is a direct replacement for unconditional
685 branches and a branch over a jump for conditional branches. However, if the
686 user requires PIC and disables this with --pcrel, we can only relax between
687 BYTE and SHORT forms, punting if that isn't enough. This gives us four
688 different relaxation modes for branches: */
689
690 #define BRANCHBWL 0 /* Branch byte, word, or long. */
691 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
692 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
693 #define BRANCHBW 3 /* Branch byte or word. */
694
695 /* We also relax coprocessor branches and DBcc's. All CPUs that support
696 coprocessor branches support them in word and long forms, so we have only
697 one relaxation mode for them. DBcc's are word only on all CPUs. We can
698 relax them to the LONG form with a branch-around sequence. This sequence
699 can use a long branch (if available) or an absolute jump (if acceptable).
700 This gives us two relaxation modes. If long branches are not available and
701 absolute jumps are not acceptable, we don't relax DBcc's. */
702
703 #define FBRANCH 4 /* Coprocessor branch. */
704 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
705 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
706
707 /* That's all for instruction relaxation. However, we also relax PC-relative
708 operands. Specifically, we have three operand relaxation modes. On the
709 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
710 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
711 two. Also PC+displacement+index operands in their simple form (with a non-
712 suppressed index without memory indirection) are supported on all CPUs, but
713 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
714 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
715 form of the PC+displacement+index operand. Finally, some absolute operands
716 can be relaxed down to 16-bit PC-relative. */
717
718 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
719 #define PCINDEX 8 /* PC + displacement + index. */
720 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
721
722 /* Note that calls to frag_var need to specify the maximum expansion
723 needed; this is currently 10 bytes for DBCC. */
724
725 /* The fields are:
726 How far Forward this mode will reach:
727 How far Backward this mode will reach:
728 How many bytes this mode will add to the size of the frag
729 Which mode to go to if the offset won't fit in this one
730
731 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
732 relax_typeS md_relax_table[] =
733 {
734 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
735 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
736 { 0, 0, 4, 0 },
737 { 1, 1, 0, 0 },
738
739 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
740 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
741 { 0, 0, 4, 0 },
742 { 1, 1, 0, 0 },
743
744 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
745 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
746 { 0, 0, 6, 0 },
747 { 1, 1, 0, 0 },
748
749 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
750 { 0, 0, 2, 0 },
751 { 1, 1, 0, 0 },
752 { 1, 1, 0, 0 },
753
754 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
755 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
756 { 0, 0, 4, 0 },
757 { 1, 1, 0, 0 },
758
759 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
760 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
761 { 0, 0, 10, 0 },
762 { 1, 1, 0, 0 },
763
764 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
765 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
766 { 0, 0, 10, 0 },
767 { 1, 1, 0, 0 },
768
769 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
771 { 0, 0, 6, 0 },
772 { 1, 1, 0, 0 },
773
774 { 125, -130, 0, TAB (PCINDEX, SHORT) },
775 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
776 { 0, 0, 4, 0 },
777 { 1, 1, 0, 0 },
778
779 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
781 { 0, 0, 4, 0 },
782 { 1, 1, 0, 0 },
783 };
784
785 /* These are the machine dependent pseudo-ops. These are included so
786 the assembler can work on the output from the SUN C compiler, which
787 generates these. */
788
789 /* This table describes all the machine specific pseudo-ops the assembler
790 has to support. The fields are:
791 pseudo-op name without dot
792 function to call to execute this pseudo-op
793 Integer arg to pass to the function. */
794 const pseudo_typeS md_pseudo_table[] =
795 {
796 {"data1", s_data1, 0},
797 {"data2", s_data2, 0},
798 {"bss", s_bss, 0},
799 {"even", s_even, 0},
800 {"skip", s_space, 0},
801 {"proc", s_proc, 0},
802 #if defined (TE_SUN3) || defined (OBJ_ELF)
803 {"align", s_align_bytes, 0},
804 #endif
805 #ifdef OBJ_ELF
806 {"swbeg", s_ignore, 0},
807 #endif
808 {"extend", float_cons, 'x'},
809 {"ldouble", float_cons, 'x'},
810
811 {"arch", s_m68k_arch, 0},
812 {"cpu", s_m68k_cpu, 0},
813
814 /* The following pseudo-ops are supported for MRI compatibility. */
815 {"chip", s_chip, 0},
816 {"comline", s_space, 1},
817 {"fopt", s_fopt, 0},
818 {"mask2", s_ignore, 0},
819 {"opt", s_opt, 0},
820 {"reg", s_reg, 0},
821 {"restore", s_restore, 0},
822 {"save", s_save, 0},
823
824 {"if", s_mri_if, 0},
825 {"if.b", s_mri_if, 'b'},
826 {"if.w", s_mri_if, 'w'},
827 {"if.l", s_mri_if, 'l'},
828 {"else", s_mri_else, 0},
829 {"else.s", s_mri_else, 's'},
830 {"else.l", s_mri_else, 'l'},
831 {"endi", s_mri_endi, 0},
832 {"break", s_mri_break, 0},
833 {"break.s", s_mri_break, 's'},
834 {"break.l", s_mri_break, 'l'},
835 {"next", s_mri_next, 0},
836 {"next.s", s_mri_next, 's'},
837 {"next.l", s_mri_next, 'l'},
838 {"for", s_mri_for, 0},
839 {"for.b", s_mri_for, 'b'},
840 {"for.w", s_mri_for, 'w'},
841 {"for.l", s_mri_for, 'l'},
842 {"endf", s_mri_endf, 0},
843 {"repeat", s_mri_repeat, 0},
844 {"until", s_mri_until, 0},
845 {"until.b", s_mri_until, 'b'},
846 {"until.w", s_mri_until, 'w'},
847 {"until.l", s_mri_until, 'l'},
848 {"while", s_mri_while, 0},
849 {"while.b", s_mri_while, 'b'},
850 {"while.w", s_mri_while, 'w'},
851 {"while.l", s_mri_while, 'l'},
852 {"endw", s_mri_endw, 0},
853
854 {0, 0, 0}
855 };
856
857 /* The mote pseudo ops are put into the opcode table, since they
858 don't start with a . they look like opcodes to gas. */
859
860 const pseudo_typeS mote_pseudo_table[] =
861 {
862
863 {"dcl", cons, 4},
864 {"dc", cons, 2},
865 {"dcw", cons, 2},
866 {"dcb", cons, 1},
867
868 {"dsl", s_space, 4},
869 {"ds", s_space, 2},
870 {"dsw", s_space, 2},
871 {"dsb", s_space, 1},
872
873 {"xdef", s_globl, 0},
874 #ifdef OBJ_ELF
875 {"align", s_align_bytes, 0},
876 #else
877 {"align", s_align_ptwo, 0},
878 #endif
879 #ifdef M68KCOFF
880 {"sect", obj_coff_section, 0},
881 {"section", obj_coff_section, 0},
882 #endif
883 {0, 0, 0}
884 };
885
886 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
887 gives identical results to a 32-bit host. */
888 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
889 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
890
891 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
892 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
893 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
894 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
895
896 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
897 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
898 #define islong(x) (1)
899
900 static char notend_table[256];
901 static char alt_notend_table[256];
902 #define notend(s) \
903 (! (notend_table[(unsigned char) *s] \
904 || (*s == ':' \
905 && alt_notend_table[(unsigned char) s[1]])))
906
907 #ifdef OBJ_ELF
908
909 /* Return zero if the reference to SYMBOL from within the same segment may
910 be relaxed. */
911
912 /* On an ELF system, we can't relax an externally visible symbol,
913 because it may be overridden by a shared library. However, if
914 TARGET_OS is "elf", then we presume that we are assembling for an
915 embedded system, in which case we don't have to worry about shared
916 libraries, and we can relax any external sym. */
917
918 #define relaxable_symbol(symbol) \
919 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
920 || S_IS_WEAK (symbol)))
921
922 /* Compute the relocation code for a fixup of SIZE bytes, using pc
923 relative relocation if PCREL is non-zero. PIC says whether a special
924 pic relocation was requested. */
925
926 static bfd_reloc_code_real_type
927 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
928 {
929 switch (pic)
930 {
931 case pic_got_pcrel:
932 switch (size)
933 {
934 case 1:
935 return BFD_RELOC_8_GOT_PCREL;
936 case 2:
937 return BFD_RELOC_16_GOT_PCREL;
938 case 4:
939 return BFD_RELOC_32_GOT_PCREL;
940 }
941 break;
942
943 case pic_got_off:
944 switch (size)
945 {
946 case 1:
947 return BFD_RELOC_8_GOTOFF;
948 case 2:
949 return BFD_RELOC_16_GOTOFF;
950 case 4:
951 return BFD_RELOC_32_GOTOFF;
952 }
953 break;
954
955 case pic_plt_pcrel:
956 switch (size)
957 {
958 case 1:
959 return BFD_RELOC_8_PLT_PCREL;
960 case 2:
961 return BFD_RELOC_16_PLT_PCREL;
962 case 4:
963 return BFD_RELOC_32_PLT_PCREL;
964 }
965 break;
966
967 case pic_plt_off:
968 switch (size)
969 {
970 case 1:
971 return BFD_RELOC_8_PLTOFF;
972 case 2:
973 return BFD_RELOC_16_PLTOFF;
974 case 4:
975 return BFD_RELOC_32_PLTOFF;
976 }
977 break;
978
979 case pic_none:
980 if (pcrel)
981 {
982 switch (size)
983 {
984 case 1:
985 return BFD_RELOC_8_PCREL;
986 case 2:
987 return BFD_RELOC_16_PCREL;
988 case 4:
989 return BFD_RELOC_32_PCREL;
990 }
991 }
992 else
993 {
994 switch (size)
995 {
996 case 1:
997 return BFD_RELOC_8;
998 case 2:
999 return BFD_RELOC_16;
1000 case 4:
1001 return BFD_RELOC_32;
1002 }
1003 }
1004 }
1005
1006 if (pcrel)
1007 {
1008 if (pic == pic_none)
1009 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1010 else
1011 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1012 }
1013 else
1014 {
1015 if (pic == pic_none)
1016 as_bad (_("Can not do %d byte relocation"), size);
1017 else
1018 as_bad (_("Can not do %d byte pic relocation"), size);
1019 }
1020
1021 return BFD_RELOC_NONE;
1022 }
1023
1024 /* Here we decide which fixups can be adjusted to make them relative
1025 to the beginning of the section instead of the symbol. Basically
1026 we need to make sure that the dynamic relocations are done
1027 correctly, so in some cases we force the original symbol to be
1028 used. */
1029 int
1030 tc_m68k_fix_adjustable (fixS *fixP)
1031 {
1032 /* Adjust_reloc_syms doesn't know about the GOT. */
1033 switch (fixP->fx_r_type)
1034 {
1035 case BFD_RELOC_8_GOT_PCREL:
1036 case BFD_RELOC_16_GOT_PCREL:
1037 case BFD_RELOC_32_GOT_PCREL:
1038 case BFD_RELOC_8_GOTOFF:
1039 case BFD_RELOC_16_GOTOFF:
1040 case BFD_RELOC_32_GOTOFF:
1041 case BFD_RELOC_8_PLT_PCREL:
1042 case BFD_RELOC_16_PLT_PCREL:
1043 case BFD_RELOC_32_PLT_PCREL:
1044 case BFD_RELOC_8_PLTOFF:
1045 case BFD_RELOC_16_PLTOFF:
1046 case BFD_RELOC_32_PLTOFF:
1047 return 0;
1048
1049 case BFD_RELOC_VTABLE_INHERIT:
1050 case BFD_RELOC_VTABLE_ENTRY:
1051 return 0;
1052
1053 default:
1054 return 1;
1055 }
1056 }
1057
1058 #else /* !OBJ_ELF */
1059
1060 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1061
1062 /* PR gas/3041 Weak symbols are not relaxable
1063 because they must be treated as extern. */
1064 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1065
1066 #endif /* OBJ_ELF */
1067
1068 arelent *
1069 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1070 {
1071 arelent *reloc;
1072 bfd_reloc_code_real_type code;
1073
1074 /* If the tcbit is set, then this was a fixup of a negative value
1075 that was never resolved. We do not have a reloc to handle this,
1076 so just return. We assume that other code will have detected this
1077 situation and produced a helpful error message, so we just tell the
1078 user that the reloc cannot be produced. */
1079 if (fixp->fx_tcbit)
1080 {
1081 if (fixp->fx_addsy)
1082 as_bad_where (fixp->fx_file, fixp->fx_line,
1083 _("Unable to produce reloc against symbol '%s'"),
1084 S_GET_NAME (fixp->fx_addsy));
1085 return NULL;
1086 }
1087
1088 if (fixp->fx_r_type != BFD_RELOC_NONE)
1089 {
1090 code = fixp->fx_r_type;
1091
1092 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1093 that fixup_segment converted a non-PC relative reloc into a
1094 PC relative reloc. In such a case, we need to convert the
1095 reloc code. */
1096 if (fixp->fx_pcrel)
1097 {
1098 switch (code)
1099 {
1100 case BFD_RELOC_8:
1101 code = BFD_RELOC_8_PCREL;
1102 break;
1103 case BFD_RELOC_16:
1104 code = BFD_RELOC_16_PCREL;
1105 break;
1106 case BFD_RELOC_32:
1107 code = BFD_RELOC_32_PCREL;
1108 break;
1109 case BFD_RELOC_8_PCREL:
1110 case BFD_RELOC_16_PCREL:
1111 case BFD_RELOC_32_PCREL:
1112 case BFD_RELOC_8_GOT_PCREL:
1113 case BFD_RELOC_16_GOT_PCREL:
1114 case BFD_RELOC_32_GOT_PCREL:
1115 case BFD_RELOC_8_GOTOFF:
1116 case BFD_RELOC_16_GOTOFF:
1117 case BFD_RELOC_32_GOTOFF:
1118 case BFD_RELOC_8_PLT_PCREL:
1119 case BFD_RELOC_16_PLT_PCREL:
1120 case BFD_RELOC_32_PLT_PCREL:
1121 case BFD_RELOC_8_PLTOFF:
1122 case BFD_RELOC_16_PLTOFF:
1123 case BFD_RELOC_32_PLTOFF:
1124 break;
1125 default:
1126 as_bad_where (fixp->fx_file, fixp->fx_line,
1127 _("Cannot make %s relocation PC relative"),
1128 bfd_get_reloc_code_name (code));
1129 }
1130 }
1131 }
1132 else
1133 {
1134 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1135 switch (F (fixp->fx_size, fixp->fx_pcrel))
1136 {
1137 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1138 MAP (1, 0, BFD_RELOC_8);
1139 MAP (2, 0, BFD_RELOC_16);
1140 MAP (4, 0, BFD_RELOC_32);
1141 MAP (1, 1, BFD_RELOC_8_PCREL);
1142 MAP (2, 1, BFD_RELOC_16_PCREL);
1143 MAP (4, 1, BFD_RELOC_32_PCREL);
1144 default:
1145 abort ();
1146 }
1147 }
1148 #undef F
1149 #undef MAP
1150
1151 reloc = (arelent *) xmalloc (sizeof (arelent));
1152 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1153 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1154 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1155 #ifndef OBJ_ELF
1156 if (fixp->fx_pcrel)
1157 reloc->addend = fixp->fx_addnumber;
1158 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1159 && fixp->fx_addsy
1160 && S_IS_WEAK (fixp->fx_addsy)
1161 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1162 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1163 to put the symbol offset into frags referencing a weak symbol. */
1164 reloc->addend = fixp->fx_addnumber
1165 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1166 else
1167 reloc->addend = 0;
1168 #else
1169 if (!fixp->fx_pcrel)
1170 reloc->addend = fixp->fx_addnumber;
1171 else
1172 reloc->addend = (section->vma
1173 /* Explicit sign extension in case char is
1174 unsigned. */
1175 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1176 + fixp->fx_addnumber
1177 + md_pcrel_from (fixp));
1178 #endif
1179
1180 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1181 assert (reloc->howto != 0);
1182
1183 return reloc;
1184 }
1185
1186 /* Handle of the OPCODE hash table. NULL means any use before
1187 m68k_ip_begin() will crash. */
1188 static struct hash_control *op_hash;
1189 \f
1190 /* Assemble an m68k instruction. */
1191
1192 static void
1193 m68k_ip (char *instring)
1194 {
1195 register char *p;
1196 register struct m68k_op *opP;
1197 register const struct m68k_incant *opcode;
1198 register const char *s;
1199 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1200 char *pdot, *pdotmove;
1201 enum m68k_size siz1, siz2;
1202 char c;
1203 int losing;
1204 int opsfound;
1205 struct m68k_op operands_backup[6];
1206 LITTLENUM_TYPE words[6];
1207 LITTLENUM_TYPE *wordp;
1208 unsigned long ok_arch = 0;
1209
1210 if (*instring == ' ')
1211 instring++; /* Skip leading whitespace. */
1212
1213 /* Scan up to end of operation-code, which MUST end in end-of-string
1214 or exactly 1 space. */
1215 pdot = 0;
1216 for (p = instring; *p != '\0'; p++)
1217 {
1218 if (*p == ' ')
1219 break;
1220 if (*p == '.')
1221 pdot = p;
1222 }
1223
1224 if (p == instring)
1225 {
1226 the_ins.error = _("No operator");
1227 return;
1228 }
1229
1230 /* p now points to the end of the opcode name, probably whitespace.
1231 Make sure the name is null terminated by clobbering the
1232 whitespace, look it up in the hash table, then fix it back.
1233 Remove a dot, first, since the opcode tables have none. */
1234 if (pdot != NULL)
1235 {
1236 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1237 *pdotmove = pdotmove[1];
1238 p--;
1239 }
1240
1241 c = *p;
1242 *p = '\0';
1243 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1244 *p = c;
1245
1246 if (pdot != NULL)
1247 {
1248 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1249 *pdotmove = pdotmove[-1];
1250 *pdot = '.';
1251 ++p;
1252 }
1253
1254 if (opcode == NULL)
1255 {
1256 the_ins.error = _("Unknown operator");
1257 return;
1258 }
1259
1260 /* Found a legitimate opcode, start matching operands. */
1261 while (*p == ' ')
1262 ++p;
1263
1264 if (opcode->m_operands == 0)
1265 {
1266 char *old = input_line_pointer;
1267 *old = '\n';
1268 input_line_pointer = p;
1269 /* Ahh - it's a motorola style psuedo op. */
1270 mote_pseudo_table[opcode->m_opnum].poc_handler
1271 (mote_pseudo_table[opcode->m_opnum].poc_val);
1272 input_line_pointer = old;
1273 *old = 0;
1274
1275 return;
1276 }
1277
1278 if (flag_mri && opcode->m_opnum == 0)
1279 {
1280 /* In MRI mode, random garbage is allowed after an instruction
1281 which accepts no operands. */
1282 the_ins.args = opcode->m_operands;
1283 the_ins.numargs = opcode->m_opnum;
1284 the_ins.numo = opcode->m_codenum;
1285 the_ins.opcode[0] = getone (opcode);
1286 the_ins.opcode[1] = gettwo (opcode);
1287 return;
1288 }
1289
1290 for (opP = &the_ins.operands[0]; *p; opP++)
1291 {
1292 p = crack_operand (p, opP);
1293
1294 if (opP->error)
1295 {
1296 the_ins.error = opP->error;
1297 return;
1298 }
1299 }
1300
1301 opsfound = opP - &the_ins.operands[0];
1302
1303 /* This ugly hack is to support the floating pt opcodes in their
1304 standard form. Essentially, we fake a first enty of type COP#1 */
1305 if (opcode->m_operands[0] == 'I')
1306 {
1307 int n;
1308
1309 for (n = opsfound; n > 0; --n)
1310 the_ins.operands[n] = the_ins.operands[n - 1];
1311
1312 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1313 the_ins.operands[0].mode = CONTROL;
1314 the_ins.operands[0].reg = m68k_float_copnum;
1315 opsfound++;
1316 }
1317
1318 /* We've got the operands. Find an opcode that'll accept them. */
1319 for (losing = 0;;)
1320 {
1321 /* If we didn't get the right number of ops, or we have no
1322 common model with this pattern then reject this pattern. */
1323
1324 ok_arch |= opcode->m_arch;
1325 if (opsfound != opcode->m_opnum
1326 || ((opcode->m_arch & current_architecture) == 0))
1327 ++losing;
1328 else
1329 {
1330 int i;
1331
1332 /* Make a copy of the operands of this insn so that
1333 we can modify them safely, should we want to. */
1334 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1335 for (i = 0; i < opsfound; i++)
1336 operands_backup[i] = the_ins.operands[i];
1337
1338 for (s = opcode->m_operands, opP = &operands_backup[0];
1339 *s && !losing;
1340 s += 2, opP++)
1341 {
1342 /* Warning: this switch is huge! */
1343 /* I've tried to organize the cases into this order:
1344 non-alpha first, then alpha by letter. Lower-case
1345 goes directly before uppercase counterpart. */
1346 /* Code with multiple case ...: gets sorted by the lowest
1347 case ... it belongs to. I hope this makes sense. */
1348 switch (*s)
1349 {
1350 case '!':
1351 switch (opP->mode)
1352 {
1353 case IMMED:
1354 case DREG:
1355 case AREG:
1356 case FPREG:
1357 case CONTROL:
1358 case AINC:
1359 case ADEC:
1360 case REGLST:
1361 losing++;
1362 break;
1363 default:
1364 break;
1365 }
1366 break;
1367
1368 case '<':
1369 switch (opP->mode)
1370 {
1371 case DREG:
1372 case AREG:
1373 case FPREG:
1374 case CONTROL:
1375 case IMMED:
1376 case ADEC:
1377 case REGLST:
1378 losing++;
1379 break;
1380 default:
1381 break;
1382 }
1383 break;
1384
1385 case '>':
1386 switch (opP->mode)
1387 {
1388 case DREG:
1389 case AREG:
1390 case FPREG:
1391 case CONTROL:
1392 case IMMED:
1393 case AINC:
1394 case REGLST:
1395 losing++;
1396 break;
1397 case ABSL:
1398 break;
1399 default:
1400 if (opP->reg == PC
1401 || opP->reg == ZPC)
1402 losing++;
1403 break;
1404 }
1405 break;
1406
1407 case 'm':
1408 switch (opP->mode)
1409 {
1410 case DREG:
1411 case AREG:
1412 case AINDR:
1413 case AINC:
1414 case ADEC:
1415 break;
1416 default:
1417 losing++;
1418 }
1419 break;
1420
1421 case 'n':
1422 switch (opP->mode)
1423 {
1424 case DISP:
1425 break;
1426 default:
1427 losing++;
1428 }
1429 break;
1430
1431 case 'o':
1432 switch (opP->mode)
1433 {
1434 case BASE:
1435 case ABSL:
1436 case IMMED:
1437 break;
1438 default:
1439 losing++;
1440 }
1441 break;
1442
1443 case 'p':
1444 switch (opP->mode)
1445 {
1446 case DREG:
1447 case AREG:
1448 case AINDR:
1449 case AINC:
1450 case ADEC:
1451 break;
1452 case DISP:
1453 if (opP->reg == PC || opP->reg == ZPC)
1454 losing++;
1455 break;
1456 default:
1457 losing++;
1458 }
1459 break;
1460
1461 case 'q':
1462 switch (opP->mode)
1463 {
1464 case DREG:
1465 case AINDR:
1466 case AINC:
1467 case ADEC:
1468 break;
1469 case DISP:
1470 if (opP->reg == PC || opP->reg == ZPC)
1471 losing++;
1472 break;
1473 default:
1474 losing++;
1475 break;
1476 }
1477 break;
1478
1479 case 'v':
1480 switch (opP->mode)
1481 {
1482 case DREG:
1483 case AINDR:
1484 case AINC:
1485 case ADEC:
1486 case ABSL:
1487 break;
1488 case DISP:
1489 if (opP->reg == PC || opP->reg == ZPC)
1490 losing++;
1491 break;
1492 default:
1493 losing++;
1494 break;
1495 }
1496 break;
1497
1498 case '#':
1499 if (opP->mode != IMMED)
1500 losing++;
1501 else if (s[1] == 'b'
1502 && ! isvar (&opP->disp)
1503 && (opP->disp.exp.X_op != O_constant
1504 || ! isbyte (opP->disp.exp.X_add_number)))
1505 losing++;
1506 else if (s[1] == 'B'
1507 && ! isvar (&opP->disp)
1508 && (opP->disp.exp.X_op != O_constant
1509 || ! issbyte (opP->disp.exp.X_add_number)))
1510 losing++;
1511 else if (s[1] == 'w'
1512 && ! isvar (&opP->disp)
1513 && (opP->disp.exp.X_op != O_constant
1514 || ! isword (opP->disp.exp.X_add_number)))
1515 losing++;
1516 else if (s[1] == 'W'
1517 && ! isvar (&opP->disp)
1518 && (opP->disp.exp.X_op != O_constant
1519 || ! issword (opP->disp.exp.X_add_number)))
1520 losing++;
1521 break;
1522
1523 case '^':
1524 case 'T':
1525 if (opP->mode != IMMED)
1526 losing++;
1527 break;
1528
1529 case '$':
1530 if (opP->mode == AREG
1531 || opP->mode == CONTROL
1532 || opP->mode == FPREG
1533 || opP->mode == IMMED
1534 || opP->mode == REGLST
1535 || (opP->mode != ABSL
1536 && (opP->reg == PC
1537 || opP->reg == ZPC)))
1538 losing++;
1539 break;
1540
1541 case '%':
1542 if (opP->mode == CONTROL
1543 || opP->mode == FPREG
1544 || opP->mode == REGLST
1545 || opP->mode == IMMED
1546 || (opP->mode != ABSL
1547 && (opP->reg == PC
1548 || opP->reg == ZPC)))
1549 losing++;
1550 break;
1551
1552 case '&':
1553 switch (opP->mode)
1554 {
1555 case DREG:
1556 case AREG:
1557 case FPREG:
1558 case CONTROL:
1559 case IMMED:
1560 case AINC:
1561 case ADEC:
1562 case REGLST:
1563 losing++;
1564 break;
1565 case ABSL:
1566 break;
1567 default:
1568 if (opP->reg == PC
1569 || opP->reg == ZPC)
1570 losing++;
1571 break;
1572 }
1573 break;
1574
1575 case '*':
1576 if (opP->mode == CONTROL
1577 || opP->mode == FPREG
1578 || opP->mode == REGLST)
1579 losing++;
1580 break;
1581
1582 case '+':
1583 if (opP->mode != AINC)
1584 losing++;
1585 break;
1586
1587 case '-':
1588 if (opP->mode != ADEC)
1589 losing++;
1590 break;
1591
1592 case '/':
1593 switch (opP->mode)
1594 {
1595 case AREG:
1596 case CONTROL:
1597 case FPREG:
1598 case AINC:
1599 case ADEC:
1600 case IMMED:
1601 case REGLST:
1602 losing++;
1603 break;
1604 default:
1605 break;
1606 }
1607 break;
1608
1609 case ';':
1610 switch (opP->mode)
1611 {
1612 case AREG:
1613 case CONTROL:
1614 case FPREG:
1615 case REGLST:
1616 losing++;
1617 break;
1618 default:
1619 break;
1620 }
1621 break;
1622
1623 case '?':
1624 switch (opP->mode)
1625 {
1626 case AREG:
1627 case CONTROL:
1628 case FPREG:
1629 case AINC:
1630 case ADEC:
1631 case IMMED:
1632 case REGLST:
1633 losing++;
1634 break;
1635 case ABSL:
1636 break;
1637 default:
1638 if (opP->reg == PC || opP->reg == ZPC)
1639 losing++;
1640 break;
1641 }
1642 break;
1643
1644 case '@':
1645 switch (opP->mode)
1646 {
1647 case AREG:
1648 case CONTROL:
1649 case FPREG:
1650 case IMMED:
1651 case REGLST:
1652 losing++;
1653 break;
1654 default:
1655 break;
1656 }
1657 break;
1658
1659 case '~': /* For now! (JF FOO is this right?) */
1660 switch (opP->mode)
1661 {
1662 case DREG:
1663 case AREG:
1664 case CONTROL:
1665 case FPREG:
1666 case IMMED:
1667 case REGLST:
1668 losing++;
1669 break;
1670 case ABSL:
1671 break;
1672 default:
1673 if (opP->reg == PC
1674 || opP->reg == ZPC)
1675 losing++;
1676 break;
1677 }
1678 break;
1679
1680 case '3':
1681 if (opP->mode != CONTROL
1682 || (opP->reg != TT0 && opP->reg != TT1))
1683 losing++;
1684 break;
1685
1686 case 'A':
1687 if (opP->mode != AREG)
1688 losing++;
1689 break;
1690
1691 case 'a':
1692 if (opP->mode != AINDR)
1693 ++losing;
1694 break;
1695
1696 case '4':
1697 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1698 && (opP->mode != DISP
1699 || opP->reg < ADDR0
1700 || opP->reg > ADDR7))
1701 ++losing;
1702 break;
1703
1704 case 'B': /* FOO */
1705 if (opP->mode != ABSL
1706 || (flag_long_jumps
1707 && strncmp (instring, "jbsr", 4) == 0))
1708 losing++;
1709 break;
1710
1711 case 'b':
1712 switch (opP->mode)
1713 {
1714 case IMMED:
1715 case ABSL:
1716 case AREG:
1717 case FPREG:
1718 case CONTROL:
1719 case POST:
1720 case PRE:
1721 case REGLST:
1722 losing++;
1723 break;
1724 default:
1725 break;
1726 }
1727 break;
1728
1729 case 'C':
1730 if (opP->mode != CONTROL || opP->reg != CCR)
1731 losing++;
1732 break;
1733
1734 case 'd':
1735 if (opP->mode != DISP
1736 || opP->reg < ADDR0
1737 || opP->reg > ADDR7)
1738 losing++;
1739 break;
1740
1741 case 'D':
1742 if (opP->mode != DREG)
1743 losing++;
1744 break;
1745
1746 case 'E':
1747 if (opP->reg != ACC)
1748 losing++;
1749 break;
1750
1751 case 'e':
1752 if (opP->reg != ACC && opP->reg != ACC1
1753 && opP->reg != ACC2 && opP->reg != ACC3)
1754 losing++;
1755 break;
1756
1757 case 'F':
1758 if (opP->mode != FPREG)
1759 losing++;
1760 break;
1761
1762 case 'G':
1763 if (opP->reg != MACSR)
1764 losing++;
1765 break;
1766
1767 case 'g':
1768 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1769 losing++;
1770 break;
1771
1772 case 'H':
1773 if (opP->reg != MASK)
1774 losing++;
1775 break;
1776
1777 case 'I':
1778 if (opP->mode != CONTROL
1779 || opP->reg < COP0
1780 || opP->reg > COP7)
1781 losing++;
1782 break;
1783
1784 case 'i':
1785 if (opP->mode != LSH && opP->mode != RSH)
1786 losing++;
1787 break;
1788
1789 case 'J':
1790 if (opP->mode != CONTROL
1791 || opP->reg < USP
1792 || opP->reg > last_movec_reg
1793 || !control_regs)
1794 losing++;
1795 else
1796 {
1797 const enum m68k_register *rp;
1798
1799 for (rp = control_regs; *rp; rp++)
1800 {
1801 if (*rp == opP->reg)
1802 break;
1803 /* In most CPUs RAMBAR refers to control reg
1804 c05 (RAMBAR1), but a few CPUs have it
1805 refer to c04 (RAMBAR0). */
1806 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1807 {
1808 opP->reg = RAMBAR_ALT;
1809 break;
1810 }
1811 }
1812 if (*rp == 0)
1813 losing++;
1814 }
1815 break;
1816
1817 case 'k':
1818 if (opP->mode != IMMED)
1819 losing++;
1820 break;
1821
1822 case 'l':
1823 case 'L':
1824 if (opP->mode == DREG
1825 || opP->mode == AREG
1826 || opP->mode == FPREG)
1827 {
1828 if (s[1] == '8')
1829 losing++;
1830 else
1831 {
1832 switch (opP->mode)
1833 {
1834 case DREG:
1835 opP->mask = 1 << (opP->reg - DATA0);
1836 break;
1837 case AREG:
1838 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1839 break;
1840 case FPREG:
1841 opP->mask = 1 << (opP->reg - FP0 + 16);
1842 break;
1843 default:
1844 abort ();
1845 }
1846 opP->mode = REGLST;
1847 }
1848 }
1849 else if (opP->mode == CONTROL)
1850 {
1851 if (s[1] != '8')
1852 losing++;
1853 else
1854 {
1855 switch (opP->reg)
1856 {
1857 case FPI:
1858 opP->mask = 1 << 24;
1859 break;
1860 case FPS:
1861 opP->mask = 1 << 25;
1862 break;
1863 case FPC:
1864 opP->mask = 1 << 26;
1865 break;
1866 default:
1867 losing++;
1868 break;
1869 }
1870 opP->mode = REGLST;
1871 }
1872 }
1873 else if (opP->mode != REGLST)
1874 losing++;
1875 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1876 losing++;
1877 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1878 losing++;
1879 break;
1880
1881 case 'M':
1882 if (opP->mode != IMMED)
1883 losing++;
1884 else if (opP->disp.exp.X_op != O_constant
1885 || ! issbyte (opP->disp.exp.X_add_number))
1886 losing++;
1887 else if (! m68k_quick
1888 && instring[3] != 'q'
1889 && instring[4] != 'q')
1890 losing++;
1891 break;
1892
1893 case 'O':
1894 if (opP->mode != DREG
1895 && opP->mode != IMMED
1896 && opP->mode != ABSL)
1897 losing++;
1898 break;
1899
1900 case 'Q':
1901 if (opP->mode != IMMED)
1902 losing++;
1903 else if (opP->disp.exp.X_op != O_constant
1904 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1905 losing++;
1906 else if (! m68k_quick
1907 && (strncmp (instring, "add", 3) == 0
1908 || strncmp (instring, "sub", 3) == 0)
1909 && instring[3] != 'q')
1910 losing++;
1911 break;
1912
1913 case 'R':
1914 if (opP->mode != DREG && opP->mode != AREG)
1915 losing++;
1916 break;
1917
1918 case 'r':
1919 if (opP->mode != AINDR
1920 && (opP->mode != BASE
1921 || (opP->reg != 0
1922 && opP->reg != ZADDR0)
1923 || opP->disp.exp.X_op != O_absent
1924 || ((opP->index.reg < DATA0
1925 || opP->index.reg > DATA7)
1926 && (opP->index.reg < ADDR0
1927 || opP->index.reg > ADDR7))
1928 || opP->index.size != SIZE_UNSPEC
1929 || opP->index.scale != 1))
1930 losing++;
1931 break;
1932
1933 case 's':
1934 if (opP->mode != CONTROL
1935 || ! (opP->reg == FPI
1936 || opP->reg == FPS
1937 || opP->reg == FPC))
1938 losing++;
1939 break;
1940
1941 case 'S':
1942 if (opP->mode != CONTROL || opP->reg != SR)
1943 losing++;
1944 break;
1945
1946 case 't':
1947 if (opP->mode != IMMED)
1948 losing++;
1949 else if (opP->disp.exp.X_op != O_constant
1950 || TRUNC (opP->disp.exp.X_add_number) > 7)
1951 losing++;
1952 break;
1953
1954 case 'U':
1955 if (opP->mode != CONTROL || opP->reg != USP)
1956 losing++;
1957 break;
1958
1959 case 'x':
1960 if (opP->mode != IMMED)
1961 losing++;
1962 else if (opP->disp.exp.X_op != O_constant
1963 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1964 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1965 losing++;
1966 break;
1967
1968 case 'j':
1969 if (opP->mode != IMMED)
1970 losing++;
1971 else if (opP->disp.exp.X_op != O_constant
1972 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1973 losing++;
1974 break;
1975
1976 case 'K':
1977 if (opP->mode != IMMED)
1978 losing++;
1979 else if (opP->disp.exp.X_op != O_constant
1980 || TRUNC (opP->disp.exp.X_add_number) > 511)
1981 losing++;
1982 break;
1983
1984 /* JF these are out of order. We could put them
1985 in order if we were willing to put up with
1986 bunches of #ifdef m68851s in the code.
1987
1988 Don't forget that you need these operands
1989 to use 68030 MMU instructions. */
1990 #ifndef NO_68851
1991 /* Memory addressing mode used by pflushr. */
1992 case '|':
1993 if (opP->mode == CONTROL
1994 || opP->mode == FPREG
1995 || opP->mode == DREG
1996 || opP->mode == AREG
1997 || opP->mode == REGLST)
1998 losing++;
1999 /* We should accept immediate operands, but they
2000 supposedly have to be quad word, and we don't
2001 handle that. I would like to see what a Motorola
2002 assembler does before doing something here. */
2003 if (opP->mode == IMMED)
2004 losing++;
2005 break;
2006
2007 case 'f':
2008 if (opP->mode != CONTROL
2009 || (opP->reg != SFC && opP->reg != DFC))
2010 losing++;
2011 break;
2012
2013 case '0':
2014 if (opP->mode != CONTROL || opP->reg != TC)
2015 losing++;
2016 break;
2017
2018 case '1':
2019 if (opP->mode != CONTROL || opP->reg != AC)
2020 losing++;
2021 break;
2022
2023 case '2':
2024 if (opP->mode != CONTROL
2025 || (opP->reg != CAL
2026 && opP->reg != VAL
2027 && opP->reg != SCC))
2028 losing++;
2029 break;
2030
2031 case 'V':
2032 if (opP->mode != CONTROL
2033 || opP->reg != VAL)
2034 losing++;
2035 break;
2036
2037 case 'W':
2038 if (opP->mode != CONTROL
2039 || (opP->reg != DRP
2040 && opP->reg != SRP
2041 && opP->reg != CRP))
2042 losing++;
2043 break;
2044
2045 case 'w':
2046 switch (opP->mode)
2047 {
2048 case IMMED:
2049 case ABSL:
2050 case AREG:
2051 case DREG:
2052 case FPREG:
2053 case CONTROL:
2054 case POST:
2055 case PRE:
2056 case REGLST:
2057 losing++;
2058 break;
2059 default:
2060 break;
2061 }
2062 break;
2063
2064 case 'X':
2065 if (opP->mode != CONTROL
2066 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2067 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2068 losing++;
2069 break;
2070
2071 case 'Y':
2072 if (opP->mode != CONTROL || opP->reg != PSR)
2073 losing++;
2074 break;
2075
2076 case 'Z':
2077 if (opP->mode != CONTROL || opP->reg != PCSR)
2078 losing++;
2079 break;
2080 #endif
2081 case 'c':
2082 if (opP->mode != CONTROL
2083 || (opP->reg != NC
2084 && opP->reg != IC
2085 && opP->reg != DC
2086 && opP->reg != BC))
2087 losing++;
2088 break;
2089
2090 case '_':
2091 if (opP->mode != ABSL)
2092 ++losing;
2093 break;
2094
2095 case 'u':
2096 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2097 losing++;
2098 /* FIXME: kludge instead of fixing parser:
2099 upper/lower registers are *not* CONTROL
2100 registers, but ordinary ones. */
2101 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2102 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2103 opP->mode = DREG;
2104 else
2105 opP->mode = AREG;
2106 break;
2107
2108 case 'y':
2109 if (!(opP->mode == AINDR
2110 || (opP->mode == DISP
2111 && !(opP->reg == PC || opP->reg == ZPC))))
2112 losing++;
2113 break;
2114
2115 case 'z':
2116 if (!(opP->mode == AINDR || opP->mode == DISP))
2117 losing++;
2118 break;
2119
2120 default:
2121 abort ();
2122 }
2123
2124 if (losing)
2125 break;
2126 }
2127
2128 /* Since we have found the correct instruction, copy
2129 in the modifications that we may have made. */
2130 if (!losing)
2131 for (i = 0; i < opsfound; i++)
2132 the_ins.operands[i] = operands_backup[i];
2133 }
2134
2135 if (!losing)
2136 break;
2137
2138 opcode = opcode->m_next;
2139
2140 if (!opcode)
2141 {
2142 if (ok_arch
2143 && !(ok_arch & current_architecture))
2144 {
2145 const struct m68k_cpu *cpu;
2146 int any = 0;
2147 size_t space = 400;
2148 char *buf = xmalloc (space + 1);
2149 size_t len;
2150 int paren = 1;
2151
2152 the_ins.error = buf;
2153 /* Make sure there's a NUL at the end of the buffer -- strncpy
2154 won't write one when it runs out of buffer */
2155 buf[space] = 0;
2156 #define APPEND(STRING) \
2157 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2158
2159 APPEND (_("invalid instruction for this architecture; needs "));
2160 switch (ok_arch)
2161 {
2162 case mcfisa_a:
2163 APPEND (_("ColdFire ISA_A"));
2164 break;
2165 case mcfhwdiv:
2166 APPEND (_("ColdFire hardware divide"));
2167 break;
2168 case mcfisa_aa:
2169 APPEND (_("ColdFire ISA_A+"));
2170 break;
2171 case mcfisa_b:
2172 APPEND (_("ColdFire ISA_B"));
2173 break;
2174 case cfloat:
2175 APPEND (_("ColdFire fpu"));
2176 break;
2177 case mfloat:
2178 APPEND (_("M68K fpu"));
2179 break;
2180 case mmmu:
2181 APPEND (_("M68K mmu"));
2182 break;
2183 case m68020up:
2184 APPEND (_("68020 or higher"));
2185 break;
2186 case m68000up:
2187 APPEND (_("68000 or higher"));
2188 break;
2189 case m68010up:
2190 APPEND (_("68010 or higher"));
2191 break;
2192 default:
2193 paren = 0;
2194 }
2195 if (paren)
2196 APPEND (" (");
2197
2198 for (cpu = m68k_cpus; cpu->name; cpu++)
2199 if (!cpu->alias && (cpu->arch & ok_arch))
2200 {
2201 const struct m68k_cpu *alias;
2202 int seen_master = 0;
2203
2204 if (any)
2205 APPEND (", ");
2206 any = 0;
2207 APPEND (cpu->name);
2208 for (alias = cpu; alias != m68k_cpus; alias--)
2209 if (alias[-1].alias >= 0)
2210 break;
2211 for (; !seen_master || alias->alias > 0; alias++)
2212 {
2213 if (!alias->alias)
2214 seen_master = 1;
2215 else
2216 {
2217 if (any)
2218 APPEND (", ");
2219 else
2220 APPEND (" [");
2221 APPEND (alias->name);
2222 any = 1;
2223 }
2224 }
2225 if (any)
2226 APPEND ("]");
2227 any = 1;
2228 }
2229 if (paren)
2230 APPEND (")");
2231 #undef APPEND
2232 if (!space)
2233 {
2234 /* we ran out of space, so replace the end of the list
2235 with ellipsis. */
2236 buf -= 4;
2237 while (*buf != ' ')
2238 buf--;
2239 strcpy (buf, " ...");
2240 }
2241 }
2242 else
2243 the_ins.error = _("operands mismatch");
2244 return;
2245 }
2246
2247 losing = 0;
2248 }
2249
2250 /* Now assemble it. */
2251 the_ins.args = opcode->m_operands;
2252 the_ins.numargs = opcode->m_opnum;
2253 the_ins.numo = opcode->m_codenum;
2254 the_ins.opcode[0] = getone (opcode);
2255 the_ins.opcode[1] = gettwo (opcode);
2256
2257 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2258 {
2259 int have_disp = 0;
2260
2261 /* This switch is a doozy.
2262 Watch the first step; its a big one! */
2263 switch (s[0])
2264 {
2265
2266 case '*':
2267 case '~':
2268 case '%':
2269 case ';':
2270 case '@':
2271 case '!':
2272 case '&':
2273 case '$':
2274 case '?':
2275 case '/':
2276 case '<':
2277 case '>':
2278 case 'b':
2279 case 'm':
2280 case 'n':
2281 case 'o':
2282 case 'p':
2283 case 'q':
2284 case 'v':
2285 case 'w':
2286 case 'y':
2287 case 'z':
2288 case '4':
2289 #ifndef NO_68851
2290 case '|':
2291 #endif
2292 switch (opP->mode)
2293 {
2294 case IMMED:
2295 tmpreg = 0x3c; /* 7.4 */
2296 if (strchr ("bwl", s[1]))
2297 nextword = get_num (&opP->disp, 90);
2298 else
2299 nextword = get_num (&opP->disp, 0);
2300 if (isvar (&opP->disp))
2301 add_fix (s[1], &opP->disp, 0, 0);
2302 switch (s[1])
2303 {
2304 case 'b':
2305 if (!isbyte (nextword))
2306 opP->error = _("operand out of range");
2307 addword (nextword);
2308 baseo = 0;
2309 break;
2310 case 'w':
2311 if (!isword (nextword))
2312 opP->error = _("operand out of range");
2313 addword (nextword);
2314 baseo = 0;
2315 break;
2316 case 'W':
2317 if (!issword (nextword))
2318 opP->error = _("operand out of range");
2319 addword (nextword);
2320 baseo = 0;
2321 break;
2322 case 'l':
2323 addword (nextword >> 16);
2324 addword (nextword);
2325 baseo = 0;
2326 break;
2327
2328 case 'f':
2329 baseo = 2;
2330 outro = 8;
2331 break;
2332 case 'F':
2333 baseo = 4;
2334 outro = 11;
2335 break;
2336 case 'x':
2337 baseo = 6;
2338 outro = 15;
2339 break;
2340 case 'p':
2341 baseo = 6;
2342 outro = -1;
2343 break;
2344 default:
2345 abort ();
2346 }
2347 if (!baseo)
2348 break;
2349
2350 /* We gotta put out some float. */
2351 if (op (&opP->disp) != O_big)
2352 {
2353 valueT val;
2354 int gencnt;
2355
2356 /* Can other cases happen here? */
2357 if (op (&opP->disp) != O_constant)
2358 abort ();
2359
2360 val = (valueT) offs (&opP->disp);
2361 gencnt = 0;
2362 do
2363 {
2364 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2365 val >>= LITTLENUM_NUMBER_OF_BITS;
2366 ++gencnt;
2367 }
2368 while (val != 0);
2369 offs (&opP->disp) = gencnt;
2370 }
2371 if (offs (&opP->disp) > 0)
2372 {
2373 if (offs (&opP->disp) > baseo)
2374 {
2375 as_warn (_("Bignum too big for %c format; truncated"),
2376 s[1]);
2377 offs (&opP->disp) = baseo;
2378 }
2379 baseo -= offs (&opP->disp);
2380 while (baseo--)
2381 addword (0);
2382 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2383 offs (&opP->disp)--;
2384 --wordp)
2385 addword (*wordp);
2386 break;
2387 }
2388 gen_to_words (words, baseo, (long) outro);
2389 for (wordp = words; baseo--; wordp++)
2390 addword (*wordp);
2391 break;
2392 case DREG:
2393 tmpreg = opP->reg - DATA; /* 0.dreg */
2394 break;
2395 case AREG:
2396 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2397 break;
2398 case AINDR:
2399 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2400 break;
2401 case ADEC:
2402 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2403 break;
2404 case AINC:
2405 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2406 break;
2407 case DISP:
2408
2409 nextword = get_num (&opP->disp, 90);
2410
2411 /* Convert mode 5 addressing with a zero offset into
2412 mode 2 addressing to reduce the instruction size by a
2413 word. */
2414 if (! isvar (&opP->disp)
2415 && (nextword == 0)
2416 && (opP->disp.size == SIZE_UNSPEC)
2417 && (opP->reg >= ADDR0)
2418 && (opP->reg <= ADDR7))
2419 {
2420 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2421 break;
2422 }
2423
2424 if (opP->reg == PC
2425 && ! isvar (&opP->disp)
2426 && m68k_abspcadd)
2427 {
2428 opP->disp.exp.X_op = O_symbol;
2429 opP->disp.exp.X_add_symbol =
2430 section_symbol (absolute_section);
2431 }
2432
2433 /* Force into index mode. Hope this works. */
2434
2435 /* We do the first bit for 32-bit displacements, and the
2436 second bit for 16 bit ones. It is possible that we
2437 should make the default be WORD instead of LONG, but
2438 I think that'd break GCC, so we put up with a little
2439 inefficiency for the sake of working output. */
2440
2441 if (!issword (nextword)
2442 || (isvar (&opP->disp)
2443 && ((opP->disp.size == SIZE_UNSPEC
2444 && flag_short_refs == 0
2445 && cpu_of_arch (current_architecture) >= m68020
2446 && ! arch_coldfire_p (current_architecture))
2447 || opP->disp.size == SIZE_LONG)))
2448 {
2449 if (cpu_of_arch (current_architecture) < m68020
2450 || arch_coldfire_p (current_architecture))
2451 opP->error =
2452 _("displacement too large for this architecture; needs 68020 or higher");
2453 if (opP->reg == PC)
2454 tmpreg = 0x3B; /* 7.3 */
2455 else
2456 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2457 if (isvar (&opP->disp))
2458 {
2459 if (opP->reg == PC)
2460 {
2461 if (opP->disp.size == SIZE_LONG
2462 #ifdef OBJ_ELF
2463 /* If the displacement needs pic
2464 relocation it cannot be relaxed. */
2465 || opP->disp.pic_reloc != pic_none
2466 #endif
2467 )
2468 {
2469 addword (0x0170);
2470 add_fix ('l', &opP->disp, 1, 2);
2471 }
2472 else
2473 {
2474 add_frag (adds (&opP->disp),
2475 SEXT (offs (&opP->disp)),
2476 TAB (PCREL1632, SZ_UNDEF));
2477 break;
2478 }
2479 }
2480 else
2481 {
2482 addword (0x0170);
2483 add_fix ('l', &opP->disp, 0, 0);
2484 }
2485 }
2486 else
2487 addword (0x0170);
2488 addword (nextword >> 16);
2489 }
2490 else
2491 {
2492 if (opP->reg == PC)
2493 tmpreg = 0x3A; /* 7.2 */
2494 else
2495 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2496
2497 if (isvar (&opP->disp))
2498 {
2499 if (opP->reg == PC)
2500 {
2501 add_fix ('w', &opP->disp, 1, 0);
2502 }
2503 else
2504 add_fix ('w', &opP->disp, 0, 0);
2505 }
2506 }
2507 addword (nextword);
2508 break;
2509
2510 case POST:
2511 case PRE:
2512 case BASE:
2513 nextword = 0;
2514 baseo = get_num (&opP->disp, 90);
2515 if (opP->mode == POST || opP->mode == PRE)
2516 outro = get_num (&opP->odisp, 90);
2517 /* Figure out the `addressing mode'.
2518 Also turn on the BASE_DISABLE bit, if needed. */
2519 if (opP->reg == PC || opP->reg == ZPC)
2520 {
2521 tmpreg = 0x3b; /* 7.3 */
2522 if (opP->reg == ZPC)
2523 nextword |= 0x80;
2524 }
2525 else if (opP->reg == 0)
2526 {
2527 nextword |= 0x80;
2528 tmpreg = 0x30; /* 6.garbage */
2529 }
2530 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2531 {
2532 nextword |= 0x80;
2533 tmpreg = 0x30 + opP->reg - ZADDR0;
2534 }
2535 else
2536 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2537
2538 siz1 = opP->disp.size;
2539 if (opP->mode == POST || opP->mode == PRE)
2540 siz2 = opP->odisp.size;
2541 else
2542 siz2 = SIZE_UNSPEC;
2543
2544 /* Index register stuff. */
2545 if (opP->index.reg != 0
2546 && opP->index.reg >= DATA
2547 && opP->index.reg <= ADDR7)
2548 {
2549 nextword |= (opP->index.reg - DATA) << 12;
2550
2551 if (opP->index.size == SIZE_LONG
2552 || (opP->index.size == SIZE_UNSPEC
2553 && m68k_index_width_default == SIZE_LONG))
2554 nextword |= 0x800;
2555
2556 if ((opP->index.scale != 1
2557 && cpu_of_arch (current_architecture) < m68020)
2558 || (opP->index.scale == 8
2559 && (arch_coldfire_p (current_architecture)
2560 && !arch_coldfire_fpu (current_architecture))))
2561 {
2562 opP->error =
2563 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2564 }
2565
2566 if (arch_coldfire_p (current_architecture)
2567 && opP->index.size == SIZE_WORD)
2568 opP->error = _("invalid index size for coldfire");
2569
2570 switch (opP->index.scale)
2571 {
2572 case 1:
2573 break;
2574 case 2:
2575 nextword |= 0x200;
2576 break;
2577 case 4:
2578 nextword |= 0x400;
2579 break;
2580 case 8:
2581 nextword |= 0x600;
2582 break;
2583 default:
2584 abort ();
2585 }
2586 /* IF its simple,
2587 GET US OUT OF HERE! */
2588
2589 /* Must be INDEX, with an index register. Address
2590 register cannot be ZERO-PC, and either :b was
2591 forced, or we know it will fit. For a 68000 or
2592 68010, force this mode anyways, because the
2593 larger modes aren't supported. */
2594 if (opP->mode == BASE
2595 && ((opP->reg >= ADDR0
2596 && opP->reg <= ADDR7)
2597 || opP->reg == PC))
2598 {
2599 if (siz1 == SIZE_BYTE
2600 || cpu_of_arch (current_architecture) < m68020
2601 || arch_coldfire_p (current_architecture)
2602 || (siz1 == SIZE_UNSPEC
2603 && ! isvar (&opP->disp)
2604 && issbyte (baseo)))
2605 {
2606 nextword += baseo & 0xff;
2607 addword (nextword);
2608 if (isvar (&opP->disp))
2609 {
2610 /* Do a byte relocation. If it doesn't
2611 fit (possible on m68000) let the
2612 fixup processing complain later. */
2613 if (opP->reg == PC)
2614 add_fix ('B', &opP->disp, 1, 1);
2615 else
2616 add_fix ('B', &opP->disp, 0, 0);
2617 }
2618 else if (siz1 != SIZE_BYTE)
2619 {
2620 if (siz1 != SIZE_UNSPEC)
2621 as_warn (_("Forcing byte displacement"));
2622 if (! issbyte (baseo))
2623 opP->error = _("byte displacement out of range");
2624 }
2625
2626 break;
2627 }
2628 else if (siz1 == SIZE_UNSPEC
2629 && opP->reg == PC
2630 && isvar (&opP->disp)
2631 && subs (&opP->disp) == NULL
2632 #ifdef OBJ_ELF
2633 /* If the displacement needs pic
2634 relocation it cannot be relaxed. */
2635 && opP->disp.pic_reloc == pic_none
2636 #endif
2637 )
2638 {
2639 /* The code in md_convert_frag_1 needs to be
2640 able to adjust nextword. Call frag_grow
2641 to ensure that we have enough space in
2642 the frag obstack to make all the bytes
2643 contiguous. */
2644 frag_grow (14);
2645 nextword += baseo & 0xff;
2646 addword (nextword);
2647 add_frag (adds (&opP->disp),
2648 SEXT (offs (&opP->disp)),
2649 TAB (PCINDEX, SZ_UNDEF));
2650
2651 break;
2652 }
2653 }
2654 }
2655 else
2656 {
2657 nextword |= 0x40; /* No index reg. */
2658 if (opP->index.reg >= ZDATA0
2659 && opP->index.reg <= ZDATA7)
2660 nextword |= (opP->index.reg - ZDATA0) << 12;
2661 else if (opP->index.reg >= ZADDR0
2662 || opP->index.reg <= ZADDR7)
2663 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2664 }
2665
2666 /* It isn't simple. */
2667
2668 if (cpu_of_arch (current_architecture) < m68020
2669 || arch_coldfire_p (current_architecture))
2670 opP->error =
2671 _("invalid operand mode for this architecture; needs 68020 or higher");
2672
2673 nextword |= 0x100;
2674 /* If the guy specified a width, we assume that it is
2675 wide enough. Maybe it isn't. If so, we lose. */
2676 switch (siz1)
2677 {
2678 case SIZE_UNSPEC:
2679 if (isvar (&opP->disp)
2680 ? m68k_rel32
2681 : ! issword (baseo))
2682 {
2683 siz1 = SIZE_LONG;
2684 nextword |= 0x30;
2685 }
2686 else if (! isvar (&opP->disp) && baseo == 0)
2687 nextword |= 0x10;
2688 else
2689 {
2690 nextword |= 0x20;
2691 siz1 = SIZE_WORD;
2692 }
2693 break;
2694 case SIZE_BYTE:
2695 as_warn (_(":b not permitted; defaulting to :w"));
2696 /* Fall through. */
2697 case SIZE_WORD:
2698 nextword |= 0x20;
2699 break;
2700 case SIZE_LONG:
2701 nextword |= 0x30;
2702 break;
2703 }
2704
2705 /* Figure out inner displacement stuff. */
2706 if (opP->mode == POST || opP->mode == PRE)
2707 {
2708 if (cpu_of_arch (current_architecture) & cpu32)
2709 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2710 switch (siz2)
2711 {
2712 case SIZE_UNSPEC:
2713 if (isvar (&opP->odisp)
2714 ? m68k_rel32
2715 : ! issword (outro))
2716 {
2717 siz2 = SIZE_LONG;
2718 nextword |= 0x3;
2719 }
2720 else if (! isvar (&opP->odisp) && outro == 0)
2721 nextword |= 0x1;
2722 else
2723 {
2724 nextword |= 0x2;
2725 siz2 = SIZE_WORD;
2726 }
2727 break;
2728 case 1:
2729 as_warn (_(":b not permitted; defaulting to :w"));
2730 /* Fall through. */
2731 case 2:
2732 nextword |= 0x2;
2733 break;
2734 case 3:
2735 nextword |= 0x3;
2736 break;
2737 }
2738 if (opP->mode == POST
2739 && (nextword & 0x40) == 0)
2740 nextword |= 0x04;
2741 }
2742 addword (nextword);
2743
2744 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2745 {
2746 if (opP->reg == PC || opP->reg == ZPC)
2747 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2748 else
2749 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2750 }
2751 if (siz1 == SIZE_LONG)
2752 addword (baseo >> 16);
2753 if (siz1 != SIZE_UNSPEC)
2754 addword (baseo);
2755
2756 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2757 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2758 if (siz2 == SIZE_LONG)
2759 addword (outro >> 16);
2760 if (siz2 != SIZE_UNSPEC)
2761 addword (outro);
2762
2763 break;
2764
2765 case ABSL:
2766 nextword = get_num (&opP->disp, 90);
2767 switch (opP->disp.size)
2768 {
2769 default:
2770 abort ();
2771 case SIZE_UNSPEC:
2772 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2773 {
2774 tmpreg = 0x38; /* 7.0 */
2775 addword (nextword);
2776 break;
2777 }
2778 if (isvar (&opP->disp)
2779 && !subs (&opP->disp)
2780 && adds (&opP->disp)
2781 #ifdef OBJ_ELF
2782 /* If the displacement needs pic relocation it
2783 cannot be relaxed. */
2784 && opP->disp.pic_reloc == pic_none
2785 #endif
2786 && !flag_long_jumps
2787 && !strchr ("~%&$?", s[0]))
2788 {
2789 tmpreg = 0x3A; /* 7.2 */
2790 add_frag (adds (&opP->disp),
2791 SEXT (offs (&opP->disp)),
2792 TAB (ABSTOPCREL, SZ_UNDEF));
2793 break;
2794 }
2795 /* Fall through into long. */
2796 case SIZE_LONG:
2797 if (isvar (&opP->disp))
2798 add_fix ('l', &opP->disp, 0, 0);
2799
2800 tmpreg = 0x39;/* 7.1 mode */
2801 addword (nextword >> 16);
2802 addword (nextword);
2803 break;
2804
2805 case SIZE_BYTE:
2806 as_bad (_("unsupported byte value; use a different suffix"));
2807 /* Fall through. */
2808
2809 case SIZE_WORD:
2810 if (isvar (&opP->disp))
2811 add_fix ('w', &opP->disp, 0, 0);
2812
2813 tmpreg = 0x38;/* 7.0 mode */
2814 addword (nextword);
2815 break;
2816 }
2817 break;
2818 case CONTROL:
2819 case FPREG:
2820 default:
2821 as_bad (_("unknown/incorrect operand"));
2822 /* abort (); */
2823 }
2824
2825 /* If s[0] is '4', then this is for the mac instructions
2826 that can have a trailing_ampersand set. If so, set 0x100
2827 bit on tmpreg so install_gen_operand can check for it and
2828 set the appropriate bit (word2, bit 5). */
2829 if (s[0] == '4')
2830 {
2831 if (opP->trailing_ampersand)
2832 tmpreg |= 0x100;
2833 }
2834 install_gen_operand (s[1], tmpreg);
2835 break;
2836
2837 case '#':
2838 case '^':
2839 switch (s[1])
2840 { /* JF: I hate floating point! */
2841 case 'j':
2842 tmpreg = 70;
2843 break;
2844 case '8':
2845 tmpreg = 20;
2846 break;
2847 case 'C':
2848 tmpreg = 50;
2849 break;
2850 case '3':
2851 default:
2852 tmpreg = 90;
2853 break;
2854 }
2855 tmpreg = get_num (&opP->disp, tmpreg);
2856 if (isvar (&opP->disp))
2857 add_fix (s[1], &opP->disp, 0, 0);
2858 switch (s[1])
2859 {
2860 case 'b': /* Danger: These do no check for
2861 certain types of overflow.
2862 user beware! */
2863 if (!isbyte (tmpreg))
2864 opP->error = _("out of range");
2865 insop (tmpreg, opcode);
2866 if (isvar (&opP->disp))
2867 the_ins.reloc[the_ins.nrel - 1].n =
2868 (opcode->m_codenum) * 2 + 1;
2869 break;
2870 case 'B':
2871 if (!issbyte (tmpreg))
2872 opP->error = _("out of range");
2873 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2874 if (isvar (&opP->disp))
2875 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2876 break;
2877 case 'w':
2878 if (!isword (tmpreg))
2879 opP->error = _("out of range");
2880 insop (tmpreg, opcode);
2881 if (isvar (&opP->disp))
2882 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2883 break;
2884 case 'W':
2885 if (!issword (tmpreg))
2886 opP->error = _("out of range");
2887 insop (tmpreg, opcode);
2888 if (isvar (&opP->disp))
2889 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2890 break;
2891 case 'l':
2892 /* Because of the way insop works, we put these two out
2893 backwards. */
2894 insop (tmpreg, opcode);
2895 insop (tmpreg >> 16, opcode);
2896 if (isvar (&opP->disp))
2897 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2898 break;
2899 case '3':
2900 tmpreg &= 0xFF;
2901 case '8':
2902 case 'C':
2903 case 'j':
2904 install_operand (s[1], tmpreg);
2905 break;
2906 default:
2907 abort ();
2908 }
2909 break;
2910
2911 case '+':
2912 case '-':
2913 case 'A':
2914 case 'a':
2915 install_operand (s[1], opP->reg - ADDR);
2916 break;
2917
2918 case 'B':
2919 tmpreg = get_num (&opP->disp, 90);
2920
2921 switch (s[1])
2922 {
2923 case 'B':
2924 add_fix ('B', &opP->disp, 1, -1);
2925 break;
2926 case 'W':
2927 add_fix ('w', &opP->disp, 1, 0);
2928 addword (0);
2929 break;
2930 case 'L':
2931 long_branch:
2932 the_ins.opcode[0] |= 0xff;
2933 add_fix ('l', &opP->disp, 1, 0);
2934 addword (0);
2935 addword (0);
2936 break;
2937 case 'g': /* Conditional branch */
2938 have_disp = HAVE_LONG_CALL (current_architecture);
2939 goto var_branch;
2940
2941 case 'b': /* Unconditional branch */
2942 have_disp = HAVE_LONG_BRANCH (current_architecture);
2943 goto var_branch;
2944
2945 case 's': /* Unconditional subroutine */
2946 have_disp = HAVE_LONG_CALL (current_architecture);
2947
2948 var_branch:
2949 if (subs (&opP->disp) /* We can't relax it. */
2950 #ifdef OBJ_ELF
2951 /* If the displacement needs pic relocation it cannot be
2952 relaxed. */
2953 || opP->disp.pic_reloc != pic_none
2954 #endif
2955 || 0)
2956 {
2957 if (!have_disp)
2958 as_warn (_("Can't use long branches on this architecture"));
2959 goto long_branch;
2960 }
2961
2962 /* This could either be a symbol, or an absolute
2963 address. If it's an absolute address, turn it into
2964 an absolute jump right here and keep it out of the
2965 relaxer. */
2966 if (adds (&opP->disp) == 0)
2967 {
2968 if (the_ins.opcode[0] == 0x6000) /* jbra */
2969 the_ins.opcode[0] = 0x4EF9;
2970 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2971 the_ins.opcode[0] = 0x4EB9;
2972 else /* jCC */
2973 {
2974 the_ins.opcode[0] ^= 0x0100;
2975 the_ins.opcode[0] |= 0x0006;
2976 addword (0x4EF9);
2977 }
2978 add_fix ('l', &opP->disp, 0, 0);
2979 addword (0);
2980 addword (0);
2981 break;
2982 }
2983
2984 /* Now we know it's going into the relaxer. Now figure
2985 out which mode. We try in this order of preference:
2986 long branch, absolute jump, byte/word branches only. */
2987 if (have_disp)
2988 add_frag (adds (&opP->disp),
2989 SEXT (offs (&opP->disp)),
2990 TAB (BRANCHBWL, SZ_UNDEF));
2991 else if (! flag_keep_pcrel)
2992 {
2993 if ((the_ins.opcode[0] == 0x6000)
2994 || (the_ins.opcode[0] == 0x6100))
2995 add_frag (adds (&opP->disp),
2996 SEXT (offs (&opP->disp)),
2997 TAB (BRABSJUNC, SZ_UNDEF));
2998 else
2999 add_frag (adds (&opP->disp),
3000 SEXT (offs (&opP->disp)),
3001 TAB (BRABSJCOND, SZ_UNDEF));
3002 }
3003 else
3004 add_frag (adds (&opP->disp),
3005 SEXT (offs (&opP->disp)),
3006 TAB (BRANCHBW, SZ_UNDEF));
3007 break;
3008 case 'w':
3009 if (isvar (&opP->disp))
3010 {
3011 /* Check for DBcc instructions. We can relax them,
3012 but only if we have long branches and/or absolute
3013 jumps. */
3014 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3015 && (HAVE_LONG_BRANCH (current_architecture)
3016 || ! flag_keep_pcrel))
3017 {
3018 if (HAVE_LONG_BRANCH (current_architecture))
3019 add_frag (adds (&opP->disp),
3020 SEXT (offs (&opP->disp)),
3021 TAB (DBCCLBR, SZ_UNDEF));
3022 else
3023 add_frag (adds (&opP->disp),
3024 SEXT (offs (&opP->disp)),
3025 TAB (DBCCABSJ, SZ_UNDEF));
3026 break;
3027 }
3028 add_fix ('w', &opP->disp, 1, 0);
3029 }
3030 addword (0);
3031 break;
3032 case 'C': /* Fixed size LONG coproc branches. */
3033 add_fix ('l', &opP->disp, 1, 0);
3034 addword (0);
3035 addword (0);
3036 break;
3037 case 'c': /* Var size Coprocesssor branches. */
3038 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3039 {
3040 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3041 add_fix ('l', &opP->disp, 1, 0);
3042 addword (0);
3043 addword (0);
3044 }
3045 else
3046 add_frag (adds (&opP->disp),
3047 SEXT (offs (&opP->disp)),
3048 TAB (FBRANCH, SZ_UNDEF));
3049 break;
3050 default:
3051 abort ();
3052 }
3053 break;
3054
3055 case 'C': /* Ignore it. */
3056 break;
3057
3058 case 'd': /* JF this is a kludge. */
3059 install_operand ('s', opP->reg - ADDR);
3060 tmpreg = get_num (&opP->disp, 90);
3061 if (!issword (tmpreg))
3062 {
3063 as_warn (_("Expression out of range, using 0"));
3064 tmpreg = 0;
3065 }
3066 addword (tmpreg);
3067 break;
3068
3069 case 'D':
3070 install_operand (s[1], opP->reg - DATA);
3071 break;
3072
3073 case 'e': /* EMAC ACCx, reg/reg. */
3074 install_operand (s[1], opP->reg - ACC);
3075 break;
3076
3077 case 'E': /* Ignore it. */
3078 break;
3079
3080 case 'F':
3081 install_operand (s[1], opP->reg - FP0);
3082 break;
3083
3084 case 'g': /* EMAC ACCEXTx. */
3085 install_operand (s[1], opP->reg - ACCEXT01);
3086 break;
3087
3088 case 'G': /* Ignore it. */
3089 case 'H':
3090 break;
3091
3092 case 'I':
3093 tmpreg = opP->reg - COP0;
3094 install_operand (s[1], tmpreg);
3095 break;
3096
3097 case 'i': /* MAC/EMAC scale factor. */
3098 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3099 break;
3100
3101 case 'J': /* JF foo. */
3102 switch (opP->reg)
3103 {
3104 case SFC:
3105 tmpreg = 0x000;
3106 break;
3107 case DFC:
3108 tmpreg = 0x001;
3109 break;
3110 case CACR:
3111 tmpreg = 0x002;
3112 break;
3113 case TC:
3114 case ASID:
3115 tmpreg = 0x003;
3116 break;
3117 case ACR0:
3118 case ITT0:
3119 tmpreg = 0x004;
3120 break;
3121 case ACR1:
3122 case ITT1:
3123 tmpreg = 0x005;
3124 break;
3125 case ACR2:
3126 case DTT0:
3127 tmpreg = 0x006;
3128 break;
3129 case ACR3:
3130 case DTT1:
3131 tmpreg = 0x007;
3132 break;
3133 case BUSCR:
3134 case MMUBAR:
3135 tmpreg = 0x008;
3136 break;
3137
3138 case USP:
3139 tmpreg = 0x800;
3140 break;
3141 case VBR:
3142 tmpreg = 0x801;
3143 break;
3144 case CAAR:
3145 tmpreg = 0x802;
3146 break;
3147 case MSP:
3148 tmpreg = 0x803;
3149 break;
3150 case ISP:
3151 tmpreg = 0x804;
3152 break;
3153 case MMUSR:
3154 tmpreg = 0x805;
3155 break;
3156 case URP:
3157 tmpreg = 0x806;
3158 break;
3159 case SRP:
3160 tmpreg = 0x807;
3161 break;
3162 case PCR:
3163 tmpreg = 0x808;
3164 break;
3165 case ROMBAR:
3166 case ROMBAR0:
3167 tmpreg = 0xC00;
3168 break;
3169 case ROMBAR1:
3170 tmpreg = 0xC01;
3171 break;
3172 case FLASHBAR:
3173 case RAMBAR0:
3174 case RAMBAR_ALT:
3175 tmpreg = 0xC04;
3176 break;
3177 case RAMBAR:
3178 case RAMBAR1:
3179 tmpreg = 0xC05;
3180 break;
3181 case MPCR:
3182 tmpreg = 0xC0C;
3183 break;
3184 case EDRAMBAR:
3185 tmpreg = 0xC0D;
3186 break;
3187 case MBAR0:
3188 case MBAR2:
3189 case SECMBAR:
3190 tmpreg = 0xC0E;
3191 break;
3192 case MBAR1:
3193 case MBAR:
3194 tmpreg = 0xC0F;
3195 break;
3196 case PCR1U0:
3197 tmpreg = 0xD02;
3198 break;
3199 case PCR1L0:
3200 tmpreg = 0xD03;
3201 break;
3202 case PCR2U0:
3203 tmpreg = 0xD04;
3204 break;
3205 case PCR2L0:
3206 tmpreg = 0xD05;
3207 break;
3208 case PCR3U0:
3209 tmpreg = 0xD06;
3210 break;
3211 case PCR3L0:
3212 tmpreg = 0xD07;
3213 break;
3214 case PCR1L1:
3215 tmpreg = 0xD0A;
3216 break;
3217 case PCR1U1:
3218 tmpreg = 0xD0B;
3219 break;
3220 case PCR2L1:
3221 tmpreg = 0xD0C;
3222 break;
3223 case PCR2U1:
3224 tmpreg = 0xD0D;
3225 break;
3226 case PCR3L1:
3227 tmpreg = 0xD0E;
3228 break;
3229 case PCR3U1:
3230 tmpreg = 0xD0F;
3231 break;
3232 case CAC:
3233 tmpreg = 0xFFE;
3234 break;
3235 case MBB:
3236 tmpreg = 0xFFF;
3237 break;
3238 default:
3239 abort ();
3240 }
3241 install_operand (s[1], tmpreg);
3242 break;
3243
3244 case 'k':
3245 tmpreg = get_num (&opP->disp, 55);
3246 install_operand (s[1], tmpreg & 0x7f);
3247 break;
3248
3249 case 'l':
3250 tmpreg = opP->mask;
3251 if (s[1] == 'w')
3252 {
3253 if (tmpreg & 0x7FF0000)
3254 as_bad (_("Floating point register in register list"));
3255 insop (reverse_16_bits (tmpreg), opcode);
3256 }
3257 else
3258 {
3259 if (tmpreg & 0x700FFFF)
3260 as_bad (_("Wrong register in floating-point reglist"));
3261 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3262 }
3263 break;
3264
3265 case 'L':
3266 tmpreg = opP->mask;
3267 if (s[1] == 'w')
3268 {
3269 if (tmpreg & 0x7FF0000)
3270 as_bad (_("Floating point register in register list"));
3271 insop (tmpreg, opcode);
3272 }
3273 else if (s[1] == '8')
3274 {
3275 if (tmpreg & 0x0FFFFFF)
3276 as_bad (_("incorrect register in reglist"));
3277 install_operand (s[1], tmpreg >> 24);
3278 }
3279 else
3280 {
3281 if (tmpreg & 0x700FFFF)
3282 as_bad (_("wrong register in floating-point reglist"));
3283 else
3284 install_operand (s[1], tmpreg >> 16);
3285 }
3286 break;
3287
3288 case 'M':
3289 install_operand (s[1], get_num (&opP->disp, 60));
3290 break;
3291
3292 case 'O':
3293 tmpreg = ((opP->mode == DREG)
3294 ? 0x20 + (int) (opP->reg - DATA)
3295 : (get_num (&opP->disp, 40) & 0x1F));
3296 install_operand (s[1], tmpreg);
3297 break;
3298
3299 case 'Q':
3300 tmpreg = get_num (&opP->disp, 10);
3301 if (tmpreg == 8)
3302 tmpreg = 0;
3303 install_operand (s[1], tmpreg);
3304 break;
3305
3306 case 'R':
3307 /* This depends on the fact that ADDR registers are eight
3308 more than their corresponding DATA regs, so the result
3309 will have the ADDR_REG bit set. */
3310 install_operand (s[1], opP->reg - DATA);
3311 break;
3312
3313 case 'r':
3314 if (opP->mode == AINDR)
3315 install_operand (s[1], opP->reg - DATA);
3316 else
3317 install_operand (s[1], opP->index.reg - DATA);
3318 break;
3319
3320 case 's':
3321 if (opP->reg == FPI)
3322 tmpreg = 0x1;
3323 else if (opP->reg == FPS)
3324 tmpreg = 0x2;
3325 else if (opP->reg == FPC)
3326 tmpreg = 0x4;
3327 else
3328 abort ();
3329 install_operand (s[1], tmpreg);
3330 break;
3331
3332 case 'S': /* Ignore it. */
3333 break;
3334
3335 case 'T':
3336 install_operand (s[1], get_num (&opP->disp, 30));
3337 break;
3338
3339 case 'U': /* Ignore it. */
3340 break;
3341
3342 case 'c':
3343 switch (opP->reg)
3344 {
3345 case NC:
3346 tmpreg = 0;
3347 break;
3348 case DC:
3349 tmpreg = 1;
3350 break;
3351 case IC:
3352 tmpreg = 2;
3353 break;
3354 case BC:
3355 tmpreg = 3;
3356 break;
3357 default:
3358 as_fatal (_("failed sanity check"));
3359 } /* switch on cache token. */
3360 install_operand (s[1], tmpreg);
3361 break;
3362 #ifndef NO_68851
3363 /* JF: These are out of order, I fear. */
3364 case 'f':
3365 switch (opP->reg)
3366 {
3367 case SFC:
3368 tmpreg = 0;
3369 break;
3370 case DFC:
3371 tmpreg = 1;
3372 break;
3373 default:
3374 abort ();
3375 }
3376 install_operand (s[1], tmpreg);
3377 break;
3378
3379 case '0':
3380 case '1':
3381 case '2':
3382 switch (opP->reg)
3383 {
3384 case TC:
3385 tmpreg = 0;
3386 break;
3387 case CAL:
3388 tmpreg = 4;
3389 break;
3390 case VAL:
3391 tmpreg = 5;
3392 break;
3393 case SCC:
3394 tmpreg = 6;
3395 break;
3396 case AC:
3397 tmpreg = 7;
3398 break;
3399 default:
3400 abort ();
3401 }
3402 install_operand (s[1], tmpreg);
3403 break;
3404
3405 case 'V':
3406 if (opP->reg == VAL)
3407 break;
3408 abort ();
3409
3410 case 'W':
3411 switch (opP->reg)
3412 {
3413 case DRP:
3414 tmpreg = 1;
3415 break;
3416 case SRP:
3417 tmpreg = 2;
3418 break;
3419 case CRP:
3420 tmpreg = 3;
3421 break;
3422 default:
3423 abort ();
3424 }
3425 install_operand (s[1], tmpreg);
3426 break;
3427
3428 case 'X':
3429 switch (opP->reg)
3430 {
3431 case BAD:
3432 case BAD + 1:
3433 case BAD + 2:
3434 case BAD + 3:
3435 case BAD + 4:
3436 case BAD + 5:
3437 case BAD + 6:
3438 case BAD + 7:
3439 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3440 break;
3441
3442 case BAC:
3443 case BAC + 1:
3444 case BAC + 2:
3445 case BAC + 3:
3446 case BAC + 4:
3447 case BAC + 5:
3448 case BAC + 6:
3449 case BAC + 7:
3450 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3451 break;
3452
3453 default:
3454 abort ();
3455 }
3456 install_operand (s[1], tmpreg);
3457 break;
3458 case 'Y':
3459 know (opP->reg == PSR);
3460 break;
3461 case 'Z':
3462 know (opP->reg == PCSR);
3463 break;
3464 #endif /* m68851 */
3465 case '3':
3466 switch (opP->reg)
3467 {
3468 case TT0:
3469 tmpreg = 2;
3470 break;
3471 case TT1:
3472 tmpreg = 3;
3473 break;
3474 default:
3475 abort ();
3476 }
3477 install_operand (s[1], tmpreg);
3478 break;
3479 case 't':
3480 tmpreg = get_num (&opP->disp, 20);
3481 install_operand (s[1], tmpreg);
3482 break;
3483 case '_': /* used only for move16 absolute 32-bit address. */
3484 if (isvar (&opP->disp))
3485 add_fix ('l', &opP->disp, 0, 0);
3486 tmpreg = get_num (&opP->disp, 90);
3487 addword (tmpreg >> 16);
3488 addword (tmpreg & 0xFFFF);
3489 break;
3490 case 'u':
3491 install_operand (s[1], opP->reg - DATA0L);
3492 opP->reg -= (DATA0L);
3493 opP->reg &= 0x0F; /* remove upper/lower bit. */
3494 break;
3495 case 'x':
3496 tmpreg = get_num (&opP->disp, 80);
3497 if (tmpreg == -1)
3498 tmpreg = 0;
3499 install_operand (s[1], tmpreg);
3500 break;
3501 case 'j':
3502 tmpreg = get_num (&opP->disp, 10);
3503 install_operand (s[1], tmpreg - 1);
3504 break;
3505 case 'K':
3506 tmpreg = get_num (&opP->disp, 65);
3507 install_operand (s[1], tmpreg);
3508 break;
3509 default:
3510 abort ();
3511 }
3512 }
3513
3514 /* By the time whe get here (FINALLY) the_ins contains the complete
3515 instruction, ready to be emitted. . . */
3516 }
3517
3518 static int
3519 reverse_16_bits (int in)
3520 {
3521 int out = 0;
3522 int n;
3523
3524 static int mask[16] =
3525 {
3526 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3527 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3528 };
3529 for (n = 0; n < 16; n++)
3530 {
3531 if (in & mask[n])
3532 out |= mask[15 - n];
3533 }
3534 return out;
3535 } /* reverse_16_bits() */
3536
3537 static int
3538 reverse_8_bits (int in)
3539 {
3540 int out = 0;
3541 int n;
3542
3543 static int mask[8] =
3544 {
3545 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3546 };
3547
3548 for (n = 0; n < 8; n++)
3549 {
3550 if (in & mask[n])
3551 out |= mask[7 - n];
3552 }
3553 return out;
3554 } /* reverse_8_bits() */
3555
3556 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3557 (that value is chosen in the frag_var call in md_assemble). TYPE
3558 is the subtype of the frag to be generated; its primary type is
3559 rs_machine_dependent.
3560
3561 The TYPE parameter is also used by md_convert_frag_1 and
3562 md_estimate_size_before_relax. The appropriate type of fixup will
3563 be emitted by md_convert_frag_1.
3564
3565 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3566 static void
3567 install_operand (int mode, int val)
3568 {
3569 switch (mode)
3570 {
3571 case 's':
3572 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3573 break;
3574 case 'd':
3575 the_ins.opcode[0] |= val << 9;
3576 break;
3577 case 'E':
3578 the_ins.opcode[1] |= val << 9;
3579 break;
3580 case '1':
3581 the_ins.opcode[1] |= val << 12;
3582 break;
3583 case '2':
3584 the_ins.opcode[1] |= val << 6;
3585 break;
3586 case '3':
3587 the_ins.opcode[1] |= val;
3588 break;
3589 case '4':
3590 the_ins.opcode[2] |= val << 12;
3591 break;
3592 case '5':
3593 the_ins.opcode[2] |= val << 6;
3594 break;
3595 case '6':
3596 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3597 three words long! */
3598 the_ins.numo++;
3599 the_ins.opcode[2] |= val;
3600 break;
3601 case '7':
3602 the_ins.opcode[1] |= val << 7;
3603 break;
3604 case '8':
3605 the_ins.opcode[1] |= val << 10;
3606 break;
3607 #ifndef NO_68851
3608 case '9':
3609 the_ins.opcode[1] |= val << 5;
3610 break;
3611 #endif
3612
3613 case 't':
3614 the_ins.opcode[1] |= (val << 10) | (val << 7);
3615 break;
3616 case 'D':
3617 the_ins.opcode[1] |= (val << 12) | val;
3618 break;
3619 case 'g':
3620 the_ins.opcode[0] |= val = 0xff;
3621 break;
3622 case 'i':
3623 the_ins.opcode[0] |= val << 9;
3624 break;
3625 case 'C':
3626 the_ins.opcode[1] |= val;
3627 break;
3628 case 'j':
3629 the_ins.opcode[1] |= val;
3630 the_ins.numo++; /* What a hack. */
3631 break;
3632 case 'k':
3633 the_ins.opcode[1] |= val << 4;
3634 break;
3635 case 'b':
3636 case 'w':
3637 case 'W':
3638 case 'l':
3639 break;
3640 case 'e':
3641 the_ins.opcode[0] |= (val << 6);
3642 break;
3643 case 'L':
3644 the_ins.opcode[1] = (val >> 16);
3645 the_ins.opcode[2] = val & 0xffff;
3646 break;
3647 case 'm':
3648 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3649 the_ins.opcode[0] |= ((val & 0x7) << 9);
3650 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3651 break;
3652 case 'n': /* MAC/EMAC Rx on !load. */
3653 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3654 the_ins.opcode[0] |= ((val & 0x7) << 9);
3655 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3656 break;
3657 case 'o': /* MAC/EMAC Rx on load. */
3658 the_ins.opcode[1] |= val << 12;
3659 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3660 break;
3661 case 'M': /* MAC/EMAC Ry on !load. */
3662 the_ins.opcode[0] |= (val & 0xF);
3663 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3664 break;
3665 case 'N': /* MAC/EMAC Ry on load. */
3666 the_ins.opcode[1] |= (val & 0xF);
3667 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3668 break;
3669 case 'h':
3670 the_ins.opcode[1] |= ((val != 1) << 10);
3671 break;
3672 case 'F':
3673 the_ins.opcode[0] |= ((val & 0x3) << 9);
3674 break;
3675 case 'f':
3676 the_ins.opcode[0] |= ((val & 0x3) << 0);
3677 break;
3678 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3679 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3680 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3681 break;
3682 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3683 the_ins.opcode[0] |= ((val & 0x1) << 7);
3684 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3685 break;
3686 case 'I':
3687 the_ins.opcode[1] |= ((val & 0x3) << 9);
3688 break;
3689 case ']':
3690 the_ins.opcode[0] |= (val & 0x1) <<10;
3691 break;
3692 case 'c':
3693 default:
3694 as_fatal (_("failed sanity check."));
3695 }
3696 }
3697
3698 static void
3699 install_gen_operand (int mode, int val)
3700 {
3701 switch (mode)
3702 {
3703 case '/': /* Special for mask loads for mac/msac insns with
3704 possible mask; trailing_ampersend set in bit 8. */
3705 the_ins.opcode[0] |= (val & 0x3f);
3706 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3707 break;
3708 case 's':
3709 the_ins.opcode[0] |= val;
3710 break;
3711 case 'd':
3712 /* This is a kludge!!! */
3713 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3714 break;
3715 case 'b':
3716 case 'w':
3717 case 'l':
3718 case 'f':
3719 case 'F':
3720 case 'x':
3721 case 'p':
3722 the_ins.opcode[0] |= val;
3723 break;
3724 /* more stuff goes here. */
3725 default:
3726 as_fatal (_("failed sanity check."));
3727 }
3728 }
3729
3730 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3731 then deal with the bitfield hack. */
3732
3733 static char *
3734 crack_operand (char *str, struct m68k_op *opP)
3735 {
3736 register int parens;
3737 register int c;
3738 register char *beg_str;
3739 int inquote = 0;
3740
3741 if (!str)
3742 {
3743 return str;
3744 }
3745 beg_str = str;
3746 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3747 {
3748 if (! inquote)
3749 {
3750 if (*str == '(')
3751 parens++;
3752 else if (*str == ')')
3753 {
3754 if (!parens)
3755 { /* ERROR. */
3756 opP->error = _("Extra )");
3757 return str;
3758 }
3759 --parens;
3760 }
3761 }
3762 if (flag_mri && *str == '\'')
3763 inquote = ! inquote;
3764 }
3765 if (!*str && parens)
3766 { /* ERROR. */
3767 opP->error = _("Missing )");
3768 return str;
3769 }
3770 c = *str;
3771 *str = '\0';
3772 if (m68k_ip_op (beg_str, opP) != 0)
3773 {
3774 *str = c;
3775 return str;
3776 }
3777 *str = c;
3778 if (c == '}')
3779 c = *++str; /* JF bitfield hack. */
3780 if (c)
3781 {
3782 c = *++str;
3783 if (!c)
3784 as_bad (_("Missing operand"));
3785 }
3786
3787 /* Detect MRI REG symbols and convert them to REGLSTs. */
3788 if (opP->mode == CONTROL && (int)opP->reg < 0)
3789 {
3790 opP->mode = REGLST;
3791 opP->mask = ~(int)opP->reg;
3792 opP->reg = 0;
3793 }
3794
3795 return str;
3796 }
3797
3798 /* This is the guts of the machine-dependent assembler. STR points to a
3799 machine dependent instruction. This function is supposed to emit
3800 the frags/bytes it assembles to.
3801 */
3802
3803 static void
3804 insert_reg (const char *regname, int regnum)
3805 {
3806 char buf[100];
3807 int i;
3808
3809 #ifdef REGISTER_PREFIX
3810 if (!flag_reg_prefix_optional)
3811 {
3812 buf[0] = REGISTER_PREFIX;
3813 strcpy (buf + 1, regname);
3814 regname = buf;
3815 }
3816 #endif
3817
3818 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3819 &zero_address_frag));
3820
3821 for (i = 0; regname[i]; i++)
3822 buf[i] = TOUPPER (regname[i]);
3823 buf[i] = '\0';
3824
3825 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3826 &zero_address_frag));
3827 }
3828
3829 struct init_entry
3830 {
3831 const char *name;
3832 int number;
3833 };
3834
3835 static const struct init_entry init_table[] =
3836 {
3837 { "d0", DATA0 },
3838 { "d1", DATA1 },
3839 { "d2", DATA2 },
3840 { "d3", DATA3 },
3841 { "d4", DATA4 },
3842 { "d5", DATA5 },
3843 { "d6", DATA6 },
3844 { "d7", DATA7 },
3845 { "a0", ADDR0 },
3846 { "a1", ADDR1 },
3847 { "a2", ADDR2 },
3848 { "a3", ADDR3 },
3849 { "a4", ADDR4 },
3850 { "a5", ADDR5 },
3851 { "a6", ADDR6 },
3852 { "fp", ADDR6 },
3853 { "a7", ADDR7 },
3854 { "sp", ADDR7 },
3855 { "ssp", ADDR7 },
3856 { "fp0", FP0 },
3857 { "fp1", FP1 },
3858 { "fp2", FP2 },
3859 { "fp3", FP3 },
3860 { "fp4", FP4 },
3861 { "fp5", FP5 },
3862 { "fp6", FP6 },
3863 { "fp7", FP7 },
3864 { "fpi", FPI },
3865 { "fpiar", FPI },
3866 { "fpc", FPI },
3867 { "fps", FPS },
3868 { "fpsr", FPS },
3869 { "fpc", FPC },
3870 { "fpcr", FPC },
3871 { "control", FPC },
3872 { "status", FPS },
3873 { "iaddr", FPI },
3874
3875 { "cop0", COP0 },
3876 { "cop1", COP1 },
3877 { "cop2", COP2 },
3878 { "cop3", COP3 },
3879 { "cop4", COP4 },
3880 { "cop5", COP5 },
3881 { "cop6", COP6 },
3882 { "cop7", COP7 },
3883 { "pc", PC },
3884 { "zpc", ZPC },
3885 { "sr", SR },
3886
3887 { "ccr", CCR },
3888 { "cc", CCR },
3889
3890 { "acc", ACC },
3891 { "acc0", ACC },
3892 { "acc1", ACC1 },
3893 { "acc2", ACC2 },
3894 { "acc3", ACC3 },
3895 { "accext01", ACCEXT01 },
3896 { "accext23", ACCEXT23 },
3897 { "macsr", MACSR },
3898 { "mask", MASK },
3899
3900 /* Control registers. */
3901 { "sfc", SFC }, /* Source Function Code. */
3902 { "sfcr", SFC },
3903 { "dfc", DFC }, /* Destination Function Code. */
3904 { "dfcr", DFC },
3905 { "cacr", CACR }, /* Cache Control Register. */
3906 { "caar", CAAR }, /* Cache Address Register. */
3907
3908 { "usp", USP }, /* User Stack Pointer. */
3909 { "vbr", VBR }, /* Vector Base Register. */
3910 { "msp", MSP }, /* Master Stack Pointer. */
3911 { "isp", ISP }, /* Interrupt Stack Pointer. */
3912
3913 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3914 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3915 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3916 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3917
3918 /* 68ec040 versions of same */
3919 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3920 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3921 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3922 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3923
3924 /* Coldfire versions of same. The ColdFire programmer's reference
3925 manual indicated that the order is 2,3,0,1, but Ken Rose
3926 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3927 { "acr0", ACR0 }, /* Access Control Unit 0. */
3928 { "acr1", ACR1 }, /* Access Control Unit 1. */
3929 { "acr2", ACR2 }, /* Access Control Unit 2. */
3930 { "acr3", ACR3 }, /* Access Control Unit 3. */
3931
3932 { "tc", TC }, /* MMU Translation Control Register. */
3933 { "tcr", TC },
3934 { "asid", ASID },
3935
3936 { "mmusr", MMUSR }, /* MMU Status Register. */
3937 { "srp", SRP }, /* User Root Pointer. */
3938 { "urp", URP }, /* Supervisor Root Pointer. */
3939
3940 { "buscr", BUSCR },
3941 { "mmubar", MMUBAR },
3942 { "pcr", PCR },
3943
3944 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3945 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3946 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3947 { "mbar", MBAR }, /* Module Base Address Register. */
3948
3949 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3950 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3951 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3952 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3953 { "mpcr", MPCR }, /* mcfv4e registers. */
3954 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3955 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3956 { "asid", TC }, /* mcfv4e registers. */
3957 { "mmubar", BUSCR }, /* mcfv4e registers. */
3958 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3959 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3960 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3961 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3962 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3963 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3964 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3965 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3966 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3967 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3968 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3969 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3970
3971 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3972 { "rambar", RAMBAR }, /* mcf528x registers. */
3973
3974 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3975
3976 { "cac", CAC }, /* fido registers. */
3977 { "mbb", MBB }, /* fido registers. */
3978 /* End of control registers. */
3979
3980 { "ac", AC },
3981 { "bc", BC },
3982 { "cal", CAL },
3983 { "crp", CRP },
3984 { "drp", DRP },
3985 { "pcsr", PCSR },
3986 { "psr", PSR },
3987 { "scc", SCC },
3988 { "val", VAL },
3989 { "bad0", BAD0 },
3990 { "bad1", BAD1 },
3991 { "bad2", BAD2 },
3992 { "bad3", BAD3 },
3993 { "bad4", BAD4 },
3994 { "bad5", BAD5 },
3995 { "bad6", BAD6 },
3996 { "bad7", BAD7 },
3997 { "bac0", BAC0 },
3998 { "bac1", BAC1 },
3999 { "bac2", BAC2 },
4000 { "bac3", BAC3 },
4001 { "bac4", BAC4 },
4002 { "bac5", BAC5 },
4003 { "bac6", BAC6 },
4004 { "bac7", BAC7 },
4005
4006 { "ic", IC },
4007 { "dc", DC },
4008 { "nc", NC },
4009
4010 { "tt0", TT0 },
4011 { "tt1", TT1 },
4012 /* 68ec030 versions of same. */
4013 { "ac0", TT0 },
4014 { "ac1", TT1 },
4015 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4016 { "acusr", PSR },
4017
4018 /* Suppressed data and address registers. */
4019 { "zd0", ZDATA0 },
4020 { "zd1", ZDATA1 },
4021 { "zd2", ZDATA2 },
4022 { "zd3", ZDATA3 },
4023 { "zd4", ZDATA4 },
4024 { "zd5", ZDATA5 },
4025 { "zd6", ZDATA6 },
4026 { "zd7", ZDATA7 },
4027 { "za0", ZADDR0 },
4028 { "za1", ZADDR1 },
4029 { "za2", ZADDR2 },
4030 { "za3", ZADDR3 },
4031 { "za4", ZADDR4 },
4032 { "za5", ZADDR5 },
4033 { "za6", ZADDR6 },
4034 { "za7", ZADDR7 },
4035
4036 /* Upper and lower data and address registers, used by macw and msacw. */
4037 { "d0l", DATA0L },
4038 { "d1l", DATA1L },
4039 { "d2l", DATA2L },
4040 { "d3l", DATA3L },
4041 { "d4l", DATA4L },
4042 { "d5l", DATA5L },
4043 { "d6l", DATA6L },
4044 { "d7l", DATA7L },
4045
4046 { "a0l", ADDR0L },
4047 { "a1l", ADDR1L },
4048 { "a2l", ADDR2L },
4049 { "a3l", ADDR3L },
4050 { "a4l", ADDR4L },
4051 { "a5l", ADDR5L },
4052 { "a6l", ADDR6L },
4053 { "a7l", ADDR7L },
4054
4055 { "d0u", DATA0U },
4056 { "d1u", DATA1U },
4057 { "d2u", DATA2U },
4058 { "d3u", DATA3U },
4059 { "d4u", DATA4U },
4060 { "d5u", DATA5U },
4061 { "d6u", DATA6U },
4062 { "d7u", DATA7U },
4063
4064 { "a0u", ADDR0U },
4065 { "a1u", ADDR1U },
4066 { "a2u", ADDR2U },
4067 { "a3u", ADDR3U },
4068 { "a4u", ADDR4U },
4069 { "a5u", ADDR5U },
4070 { "a6u", ADDR6U },
4071 { "a7u", ADDR7U },
4072
4073 { 0, 0 }
4074 };
4075
4076 static void
4077 init_regtable (void)
4078 {
4079 int i;
4080 for (i = 0; init_table[i].name; i++)
4081 insert_reg (init_table[i].name, init_table[i].number);
4082 }
4083
4084 void
4085 md_assemble (char *str)
4086 {
4087 const char *er;
4088 short *fromP;
4089 char *toP = NULL;
4090 int m, n = 0;
4091 char *to_beg_P;
4092 int shorts_this_frag;
4093 fixS *fixP;
4094
4095 if (!selected_cpu && !selected_arch)
4096 {
4097 /* We've not selected an architecture yet. Set the default
4098 now. We do this lazily so that an initial .cpu or .arch directive
4099 can specify. */
4100 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4101 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4102 }
4103 if (!initialized)
4104 m68k_init_arch ();
4105
4106 /* In MRI mode, the instruction and operands are separated by a
4107 space. Anything following the operands is a comment. The label
4108 has already been removed. */
4109 if (flag_mri)
4110 {
4111 char *s;
4112 int fields = 0;
4113 int infield = 0;
4114 int inquote = 0;
4115
4116 for (s = str; *s != '\0'; s++)
4117 {
4118 if ((*s == ' ' || *s == '\t') && ! inquote)
4119 {
4120 if (infield)
4121 {
4122 ++fields;
4123 if (fields >= 2)
4124 {
4125 *s = '\0';
4126 break;
4127 }
4128 infield = 0;
4129 }
4130 }
4131 else
4132 {
4133 if (! infield)
4134 infield = 1;
4135 if (*s == '\'')
4136 inquote = ! inquote;
4137 }
4138 }
4139 }
4140
4141 memset (&the_ins, '\0', sizeof (the_ins));
4142 m68k_ip (str);
4143 er = the_ins.error;
4144 if (!er)
4145 {
4146 for (n = 0; n < the_ins.numargs; n++)
4147 if (the_ins.operands[n].error)
4148 {
4149 er = the_ins.operands[n].error;
4150 break;
4151 }
4152 }
4153 if (er)
4154 {
4155 as_bad (_("%s -- statement `%s' ignored"), er, str);
4156 return;
4157 }
4158
4159 /* If there is a current label, record that it marks an instruction. */
4160 if (current_label != NULL)
4161 {
4162 current_label->text = 1;
4163 current_label = NULL;
4164 }
4165
4166 #ifdef OBJ_ELF
4167 /* Tie dwarf2 debug info to the address at the start of the insn. */
4168 dwarf2_emit_insn (0);
4169 #endif
4170
4171 if (the_ins.nfrag == 0)
4172 {
4173 /* No frag hacking involved; just put it out. */
4174 toP = frag_more (2 * the_ins.numo);
4175 fromP = &the_ins.opcode[0];
4176 for (m = the_ins.numo; m; --m)
4177 {
4178 md_number_to_chars (toP, (long) (*fromP), 2);
4179 toP += 2;
4180 fromP++;
4181 }
4182 /* Put out symbol-dependent info. */
4183 for (m = 0; m < the_ins.nrel; m++)
4184 {
4185 switch (the_ins.reloc[m].wid)
4186 {
4187 case 'B':
4188 n = 1;
4189 break;
4190 case 'b':
4191 n = 1;
4192 break;
4193 case '3':
4194 n = 1;
4195 break;
4196 case 'w':
4197 case 'W':
4198 n = 2;
4199 break;
4200 case 'l':
4201 n = 4;
4202 break;
4203 default:
4204 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4205 the_ins.reloc[m].wid);
4206 }
4207
4208 fixP = fix_new_exp (frag_now,
4209 ((toP - frag_now->fr_literal)
4210 - the_ins.numo * 2 + the_ins.reloc[m].n),
4211 n,
4212 &the_ins.reloc[m].exp,
4213 the_ins.reloc[m].pcrel,
4214 get_reloc_code (n, the_ins.reloc[m].pcrel,
4215 the_ins.reloc[m].pic_reloc));
4216 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4217 if (the_ins.reloc[m].wid == 'B')
4218 fixP->fx_signed = 1;
4219 }
4220 return;
4221 }
4222
4223 /* There's some frag hacking. */
4224 {
4225 /* Calculate the max frag size. */
4226 int wid;
4227
4228 wid = 2 * the_ins.fragb[0].fragoff;
4229 for (n = 1; n < the_ins.nfrag; n++)
4230 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4231 /* frag_var part. */
4232 wid += 10;
4233 /* Make sure the whole insn fits in one chunk, in particular that
4234 the var part is attached, as we access one byte before the
4235 variable frag for byte branches. */
4236 frag_grow (wid);
4237 }
4238
4239 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4240 {
4241 int wid;
4242
4243 if (n == 0)
4244 wid = 2 * the_ins.fragb[n].fragoff;
4245 else
4246 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4247 toP = frag_more (wid);
4248 to_beg_P = toP;
4249 shorts_this_frag = 0;
4250 for (m = wid / 2; m; --m)
4251 {
4252 md_number_to_chars (toP, (long) (*fromP), 2);
4253 toP += 2;
4254 fromP++;
4255 shorts_this_frag++;
4256 }
4257 for (m = 0; m < the_ins.nrel; m++)
4258 {
4259 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4260 {
4261 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4262 break;
4263 }
4264 wid = the_ins.reloc[m].wid;
4265 if (wid == 0)
4266 continue;
4267 the_ins.reloc[m].wid = 0;
4268 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4269
4270 fixP = fix_new_exp (frag_now,
4271 ((toP - frag_now->fr_literal)
4272 - the_ins.numo * 2 + the_ins.reloc[m].n),
4273 wid,
4274 &the_ins.reloc[m].exp,
4275 the_ins.reloc[m].pcrel,
4276 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4277 the_ins.reloc[m].pic_reloc));
4278 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4279 }
4280 (void) frag_var (rs_machine_dependent, 10, 0,
4281 (relax_substateT) (the_ins.fragb[n].fragty),
4282 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4283 }
4284 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4285 shorts_this_frag = 0;
4286 if (n)
4287 {
4288 toP = frag_more (n * 2);
4289 while (n--)
4290 {
4291 md_number_to_chars (toP, (long) (*fromP), 2);
4292 toP += 2;
4293 fromP++;
4294 shorts_this_frag++;
4295 }
4296 }
4297 for (m = 0; m < the_ins.nrel; m++)
4298 {
4299 int wid;
4300
4301 wid = the_ins.reloc[m].wid;
4302 if (wid == 0)
4303 continue;
4304 the_ins.reloc[m].wid = 0;
4305 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4306
4307 fixP = fix_new_exp (frag_now,
4308 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4309 - shorts_this_frag * 2),
4310 wid,
4311 &the_ins.reloc[m].exp,
4312 the_ins.reloc[m].pcrel,
4313 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4314 the_ins.reloc[m].pic_reloc));
4315 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4316 }
4317 }
4318
4319 /* Comparison function used by qsort to rank the opcode entries by name. */
4320
4321 static int
4322 m68k_compare_opcode (const void * v1, const void * v2)
4323 {
4324 struct m68k_opcode * op1, * op2;
4325 int ret;
4326
4327 if (v1 == v2)
4328 return 0;
4329
4330 op1 = *(struct m68k_opcode **) v1;
4331 op2 = *(struct m68k_opcode **) v2;
4332
4333 /* Compare the two names. If different, return the comparison.
4334 If the same, return the order they are in the opcode table. */
4335 ret = strcmp (op1->name, op2->name);
4336 if (ret)
4337 return ret;
4338 if (op1 < op2)
4339 return -1;
4340 return 1;
4341 }
4342
4343 void
4344 md_begin (void)
4345 {
4346 const struct m68k_opcode *ins;
4347 struct m68k_incant *hack, *slak;
4348 const char *retval = 0; /* Empty string, or error msg text. */
4349 int i;
4350
4351 /* Set up hash tables with 68000 instructions.
4352 similar to what the vax assembler does. */
4353 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4354 a copy of it at runtime, adding in the information we want but isn't
4355 there. I think it'd be better to have an awk script hack the table
4356 at compile time. Or even just xstr the table and use it as-is. But
4357 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4358 names. */
4359
4360 if (flag_mri)
4361 {
4362 flag_reg_prefix_optional = 1;
4363 m68k_abspcadd = 1;
4364 if (! m68k_rel32_from_cmdline)
4365 m68k_rel32 = 0;
4366 }
4367
4368 /* First sort the opcode table into alphabetical order to seperate
4369 the order that the assembler wants to see the opcodes from the
4370 order that the disassembler wants to see them. */
4371 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4372 if (!m68k_sorted_opcodes)
4373 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4374 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4375
4376 for (i = m68k_numopcodes; i--;)
4377 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4378
4379 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4380 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4381
4382 op_hash = hash_new ();
4383
4384 obstack_begin (&robyn, 4000);
4385 for (i = 0; i < m68k_numopcodes; i++)
4386 {
4387 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4388 do
4389 {
4390 ins = m68k_sorted_opcodes[i];
4391
4392 /* We must enter all insns into the table, because .arch and
4393 .cpu directives can change things. */
4394 slak->m_operands = ins->args;
4395 slak->m_arch = ins->arch;
4396 slak->m_opcode = ins->opcode;
4397
4398 /* In most cases we can determine the number of opcode words
4399 by checking the second word of the mask. Unfortunately
4400 some instructions have 2 opcode words, but no fixed bits
4401 in the second word. A leading dot in the operands
4402 string also indicates 2 opcodes. */
4403 if (*slak->m_operands == '.')
4404 {
4405 slak->m_operands++;
4406 slak->m_codenum = 2;
4407 }
4408 else if (ins->match & 0xffffL)
4409 slak->m_codenum = 2;
4410 else
4411 slak->m_codenum = 1;
4412 slak->m_opnum = strlen (slak->m_operands) / 2;
4413
4414 if (i + 1 != m68k_numopcodes
4415 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4416 {
4417 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4418 i++;
4419 }
4420 else
4421 slak->m_next = 0;
4422 slak = slak->m_next;
4423 }
4424 while (slak);
4425
4426 retval = hash_insert (op_hash, ins->name, (char *) hack);
4427 if (retval)
4428 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4429 }
4430
4431 for (i = 0; i < m68k_numaliases; i++)
4432 {
4433 const char *name = m68k_opcode_aliases[i].primary;
4434 const char *alias = m68k_opcode_aliases[i].alias;
4435 PTR val = hash_find (op_hash, name);
4436
4437 if (!val)
4438 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4439 retval = hash_insert (op_hash, alias, val);
4440 if (retval)
4441 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4442 }
4443
4444 /* In MRI mode, all unsized branches are variable sized. Normally,
4445 they are word sized. */
4446 if (flag_mri)
4447 {
4448 static struct m68k_opcode_alias mri_aliases[] =
4449 {
4450 { "bhi", "jhi", },
4451 { "bls", "jls", },
4452 { "bcc", "jcc", },
4453 { "bcs", "jcs", },
4454 { "bne", "jne", },
4455 { "beq", "jeq", },
4456 { "bvc", "jvc", },
4457 { "bvs", "jvs", },
4458 { "bpl", "jpl", },
4459 { "bmi", "jmi", },
4460 { "bge", "jge", },
4461 { "blt", "jlt", },
4462 { "bgt", "jgt", },
4463 { "ble", "jle", },
4464 { "bra", "jra", },
4465 { "bsr", "jbsr", },
4466 };
4467
4468 for (i = 0;
4469 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4470 i++)
4471 {
4472 const char *name = mri_aliases[i].primary;
4473 const char *alias = mri_aliases[i].alias;
4474 PTR val = hash_find (op_hash, name);
4475
4476 if (!val)
4477 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4478 retval = hash_jam (op_hash, alias, val);
4479 if (retval)
4480 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4481 }
4482 }
4483
4484 for (i = 0; i < (int) sizeof (notend_table); i++)
4485 {
4486 notend_table[i] = 0;
4487 alt_notend_table[i] = 0;
4488 }
4489
4490 notend_table[','] = 1;
4491 notend_table['{'] = 1;
4492 notend_table['}'] = 1;
4493 alt_notend_table['a'] = 1;
4494 alt_notend_table['A'] = 1;
4495 alt_notend_table['d'] = 1;
4496 alt_notend_table['D'] = 1;
4497 alt_notend_table['#'] = 1;
4498 alt_notend_table['&'] = 1;
4499 alt_notend_table['f'] = 1;
4500 alt_notend_table['F'] = 1;
4501 #ifdef REGISTER_PREFIX
4502 alt_notend_table[REGISTER_PREFIX] = 1;
4503 #endif
4504
4505 /* We need to put '(' in alt_notend_table to handle
4506 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4507 alt_notend_table['('] = 1;
4508
4509 /* We need to put '@' in alt_notend_table to handle
4510 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4511 alt_notend_table['@'] = 1;
4512
4513 /* We need to put digits in alt_notend_table to handle
4514 bfextu %d0{24:1},%d0 */
4515 alt_notend_table['0'] = 1;
4516 alt_notend_table['1'] = 1;
4517 alt_notend_table['2'] = 1;
4518 alt_notend_table['3'] = 1;
4519 alt_notend_table['4'] = 1;
4520 alt_notend_table['5'] = 1;
4521 alt_notend_table['6'] = 1;
4522 alt_notend_table['7'] = 1;
4523 alt_notend_table['8'] = 1;
4524 alt_notend_table['9'] = 1;
4525
4526 #ifndef MIT_SYNTAX_ONLY
4527 /* Insert pseudo ops, these have to go into the opcode table since
4528 gas expects pseudo ops to start with a dot. */
4529 {
4530 int n = 0;
4531
4532 while (mote_pseudo_table[n].poc_name)
4533 {
4534 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4535 hash_insert (op_hash,
4536 mote_pseudo_table[n].poc_name, (char *) hack);
4537 hack->m_operands = 0;
4538 hack->m_opnum = n;
4539 n++;
4540 }
4541 }
4542 #endif
4543
4544 init_regtable ();
4545
4546 #ifdef OBJ_ELF
4547 record_alignment (text_section, 2);
4548 record_alignment (data_section, 2);
4549 record_alignment (bss_section, 2);
4550 #endif
4551 }
4552
4553 \f
4554 /* This is called when a label is defined. */
4555
4556 void
4557 m68k_frob_label (symbolS *sym)
4558 {
4559 struct label_line *n;
4560
4561 n = (struct label_line *) xmalloc (sizeof *n);
4562 n->next = labels;
4563 n->label = sym;
4564 as_where (&n->file, &n->line);
4565 n->text = 0;
4566 labels = n;
4567 current_label = n;
4568
4569 #ifdef OBJ_ELF
4570 dwarf2_emit_label (sym);
4571 #endif
4572 }
4573
4574 /* This is called when a value that is not an instruction is emitted. */
4575
4576 void
4577 m68k_flush_pending_output (void)
4578 {
4579 current_label = NULL;
4580 }
4581
4582 /* This is called at the end of the assembly, when the final value of
4583 the label is known. We warn if this is a text symbol aligned at an
4584 odd location. */
4585
4586 void
4587 m68k_frob_symbol (symbolS *sym)
4588 {
4589 if (S_GET_SEGMENT (sym) == reg_section
4590 && (int) S_GET_VALUE (sym) < 0)
4591 {
4592 S_SET_SEGMENT (sym, absolute_section);
4593 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4594 }
4595 else if ((S_GET_VALUE (sym) & 1) != 0)
4596 {
4597 struct label_line *l;
4598
4599 for (l = labels; l != NULL; l = l->next)
4600 {
4601 if (l->label == sym)
4602 {
4603 if (l->text)
4604 as_warn_where (l->file, l->line,
4605 _("text label `%s' aligned to odd boundary"),
4606 S_GET_NAME (sym));
4607 break;
4608 }
4609 }
4610 }
4611 }
4612 \f
4613 /* This is called if we go in or out of MRI mode because of the .mri
4614 pseudo-op. */
4615
4616 void
4617 m68k_mri_mode_change (int on)
4618 {
4619 if (on)
4620 {
4621 if (! flag_reg_prefix_optional)
4622 {
4623 flag_reg_prefix_optional = 1;
4624 #ifdef REGISTER_PREFIX
4625 init_regtable ();
4626 #endif
4627 }
4628 m68k_abspcadd = 1;
4629 if (! m68k_rel32_from_cmdline)
4630 m68k_rel32 = 0;
4631 }
4632 else
4633 {
4634 if (! reg_prefix_optional_seen)
4635 {
4636 #ifdef REGISTER_PREFIX_OPTIONAL
4637 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4638 #else
4639 flag_reg_prefix_optional = 0;
4640 #endif
4641 #ifdef REGISTER_PREFIX
4642 init_regtable ();
4643 #endif
4644 }
4645 m68k_abspcadd = 0;
4646 if (! m68k_rel32_from_cmdline)
4647 m68k_rel32 = 1;
4648 }
4649 }
4650
4651 /* Equal to MAX_PRECISION in atof-ieee.c. */
4652 #define MAX_LITTLENUMS 6
4653
4654 /* Turn a string in input_line_pointer into a floating point constant
4655 of type TYPE, and store the appropriate bytes in *LITP. The number
4656 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4657 returned, or NULL on OK. */
4658
4659 char *
4660 md_atof (int type, char *litP, int *sizeP)
4661 {
4662 int prec;
4663 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4664 LITTLENUM_TYPE *wordP;
4665 char *t;
4666
4667 switch (type)
4668 {
4669 case 'f':
4670 case 'F':
4671 case 's':
4672 case 'S':
4673 prec = 2;
4674 break;
4675
4676 case 'd':
4677 case 'D':
4678 case 'r':
4679 case 'R':
4680 prec = 4;
4681 break;
4682
4683 case 'x':
4684 case 'X':
4685 prec = 6;
4686 break;
4687
4688 case 'p':
4689 case 'P':
4690 prec = 6;
4691 break;
4692
4693 default:
4694 *sizeP = 0;
4695 return _("Bad call to MD_ATOF()");
4696 }
4697 t = atof_ieee (input_line_pointer, type, words);
4698 if (t)
4699 input_line_pointer = t;
4700
4701 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4702 for (wordP = words; prec--;)
4703 {
4704 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4705 litP += sizeof (LITTLENUM_TYPE);
4706 }
4707 return 0;
4708 }
4709
4710 void
4711 md_number_to_chars (char *buf, valueT val, int n)
4712 {
4713 number_to_chars_bigendian (buf, val, n);
4714 }
4715
4716 void
4717 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4718 {
4719 offsetT val = *valP;
4720 addressT upper_limit;
4721 offsetT lower_limit;
4722
4723 /* This is unnecessary but it convinces the native rs6000 compiler
4724 to generate the code we want. */
4725 char *buf = fixP->fx_frag->fr_literal;
4726 buf += fixP->fx_where;
4727 /* End ibm compiler workaround. */
4728
4729 val = SEXT (val);
4730
4731 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4732 fixP->fx_done = 1;
4733
4734 #ifdef OBJ_ELF
4735 if (fixP->fx_addsy)
4736 {
4737 memset (buf, 0, fixP->fx_size);
4738 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4739
4740 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4741 && !S_IS_DEFINED (fixP->fx_addsy)
4742 && !S_IS_WEAK (fixP->fx_addsy))
4743 S_SET_WEAK (fixP->fx_addsy);
4744 return;
4745 }
4746 #elif defined(OBJ_AOUT)
4747 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4748 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4749 {
4750 memset (buf, 0, fixP->fx_size);
4751 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4752 return;
4753 }
4754 #endif
4755
4756 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4757 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4758 return;
4759
4760 switch (fixP->fx_size)
4761 {
4762 /* The cast to offsetT below are necessary to make code
4763 correct for machines where ints are smaller than offsetT. */
4764 case 1:
4765 *buf++ = val;
4766 upper_limit = 0x7f;
4767 lower_limit = - (offsetT) 0x80;
4768 break;
4769 case 2:
4770 *buf++ = (val >> 8);
4771 *buf++ = val;
4772 upper_limit = 0x7fff;
4773 lower_limit = - (offsetT) 0x8000;
4774 break;
4775 case 4:
4776 *buf++ = (val >> 24);
4777 *buf++ = (val >> 16);
4778 *buf++ = (val >> 8);
4779 *buf++ = val;
4780 upper_limit = 0x7fffffff;
4781 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4782 break;
4783 default:
4784 BAD_CASE (fixP->fx_size);
4785 }
4786
4787 /* Fix up a negative reloc. */
4788 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4789 {
4790 fixP->fx_addsy = fixP->fx_subsy;
4791 fixP->fx_subsy = NULL;
4792 fixP->fx_tcbit = 1;
4793 }
4794
4795 /* For non-pc-relative values, it's conceivable we might get something
4796 like "0xff" for a byte field. So extend the upper part of the range
4797 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4798 so that we can do any range checking at all. */
4799 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4800 upper_limit = upper_limit * 2 + 1;
4801
4802 if ((addressT) val > upper_limit
4803 && (val > 0 || val < lower_limit))
4804 as_bad_where (fixP->fx_file, fixP->fx_line,
4805 _("value %ld out of range"), (long)val);
4806
4807 /* A one byte PC-relative reloc means a short branch. We can't use
4808 a short branch with a value of 0 or -1, because those indicate
4809 different opcodes (branches with longer offsets). fixup_segment
4810 in write.c may have clobbered fx_pcrel, so we need to examine the
4811 reloc type. */
4812 if ((fixP->fx_pcrel
4813 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4814 && fixP->fx_size == 1
4815 && (fixP->fx_addsy == NULL
4816 || S_IS_DEFINED (fixP->fx_addsy))
4817 && (val == 0 || val == -1))
4818 as_bad_where (fixP->fx_file, fixP->fx_line,
4819 _("invalid byte branch offset"));
4820 }
4821
4822 /* *fragP has been relaxed to its final size, and now needs to have
4823 the bytes inside it modified to conform to the new size There is UGLY
4824 MAGIC here. ..
4825 */
4826 static void
4827 md_convert_frag_1 (fragS *fragP)
4828 {
4829 long disp;
4830 fixS *fixP = NULL;
4831
4832 /* Address in object code of the displacement. */
4833 register int object_address = fragP->fr_fix + fragP->fr_address;
4834
4835 /* Address in gas core of the place to store the displacement. */
4836 /* This convinces the native rs6000 compiler to generate the code we
4837 want. */
4838 register char *buffer_address = fragP->fr_literal;
4839 buffer_address += fragP->fr_fix;
4840 /* End ibm compiler workaround. */
4841
4842 /* The displacement of the address, from current location. */
4843 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4844 disp = (disp + fragP->fr_offset) - object_address;
4845
4846 switch (fragP->fr_subtype)
4847 {
4848 case TAB (BRANCHBWL, BYTE):
4849 case TAB (BRABSJUNC, BYTE):
4850 case TAB (BRABSJCOND, BYTE):
4851 case TAB (BRANCHBW, BYTE):
4852 know (issbyte (disp));
4853 if (disp == 0)
4854 as_bad_where (fragP->fr_file, fragP->fr_line,
4855 _("short branch with zero offset: use :w"));
4856 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4857 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4858 fixP->fx_pcrel_adjust = -1;
4859 break;
4860 case TAB (BRANCHBWL, SHORT):
4861 case TAB (BRABSJUNC, SHORT):
4862 case TAB (BRABSJCOND, SHORT):
4863 case TAB (BRANCHBW, SHORT):
4864 fragP->fr_opcode[1] = 0x00;
4865 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4866 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4867 fragP->fr_fix += 2;
4868 break;
4869 case TAB (BRANCHBWL, LONG):
4870 fragP->fr_opcode[1] = (char) 0xFF;
4871 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4872 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4873 fragP->fr_fix += 4;
4874 break;
4875 case TAB (BRABSJUNC, LONG):
4876 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4877 {
4878 if (flag_keep_pcrel)
4879 as_bad_where (fragP->fr_file, fragP->fr_line,
4880 _("Conversion of PC relative BSR to absolute JSR"));
4881 fragP->fr_opcode[0] = 0x4E;
4882 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4883 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4884 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4885 fragP->fr_fix += 4;
4886 }
4887 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4888 {
4889 if (flag_keep_pcrel)
4890 as_bad_where (fragP->fr_file, fragP->fr_line,
4891 _("Conversion of PC relative branch to absolute jump"));
4892 fragP->fr_opcode[0] = 0x4E;
4893 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4894 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4895 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4896 fragP->fr_fix += 4;
4897 }
4898 else
4899 {
4900 /* This cannot happen, because jbsr and jbra are the only two
4901 unconditional branches. */
4902 abort ();
4903 }
4904 break;
4905 case TAB (BRABSJCOND, LONG):
4906 if (flag_keep_pcrel)
4907 as_bad_where (fragP->fr_file, fragP->fr_line,
4908 _("Conversion of PC relative conditional branch to absolute jump"));
4909
4910 /* Only Bcc 68000 instructions can come here
4911 Change bcc into b!cc/jmp absl long. */
4912 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4913 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4914
4915 /* JF: these used to be fr_opcode[2,3], but they may be in a
4916 different frag, in which case referring to them is a no-no.
4917 Only fr_opcode[0,1] are guaranteed to work. */
4918 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4919 *buffer_address++ = (char) 0xf9;
4920 fragP->fr_fix += 2; /* Account for jmp instruction. */
4921 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4922 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4923 fragP->fr_fix += 4;
4924 break;
4925 case TAB (FBRANCH, SHORT):
4926 know ((fragP->fr_opcode[1] & 0x40) == 0);
4927 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4928 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4929 fragP->fr_fix += 2;
4930 break;
4931 case TAB (FBRANCH, LONG):
4932 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4933 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4934 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4935 fragP->fr_fix += 4;
4936 break;
4937 case TAB (DBCCLBR, SHORT):
4938 case TAB (DBCCABSJ, SHORT):
4939 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4940 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4941 fragP->fr_fix += 2;
4942 break;
4943 case TAB (DBCCLBR, LONG):
4944 /* Only DBcc instructions can come here.
4945 Change dbcc into dbcc/bral.
4946 JF: these used to be fr_opcode[2-7], but that's wrong. */
4947 if (flag_keep_pcrel)
4948 as_bad_where (fragP->fr_file, fragP->fr_line,
4949 _("Conversion of DBcc to absolute jump"));
4950
4951 *buffer_address++ = 0x00; /* Branch offset = 4. */
4952 *buffer_address++ = 0x04;
4953 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4954 *buffer_address++ = 0x06;
4955 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4956 *buffer_address++ = (char) 0xff;
4957
4958 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4959 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4960 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4961 fragP->fr_fix += 4;
4962 break;
4963 case TAB (DBCCABSJ, LONG):
4964 /* Only DBcc instructions can come here.
4965 Change dbcc into dbcc/jmp.
4966 JF: these used to be fr_opcode[2-7], but that's wrong. */
4967 if (flag_keep_pcrel)
4968 as_bad_where (fragP->fr_file, fragP->fr_line,
4969 _("Conversion of PC relative conditional branch to absolute jump"));
4970
4971 *buffer_address++ = 0x00; /* Branch offset = 4. */
4972 *buffer_address++ = 0x04;
4973 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4974 *buffer_address++ = 0x06;
4975 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4976 *buffer_address++ = (char) 0xf9;
4977
4978 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4979 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4980 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4981 fragP->fr_fix += 4;
4982 break;
4983 case TAB (PCREL1632, SHORT):
4984 fragP->fr_opcode[1] &= ~0x3F;
4985 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4986 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4987 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4988 fragP->fr_fix += 2;
4989 break;
4990 case TAB (PCREL1632, LONG):
4991 /* Already set to mode 7.3; this indicates: PC indirect with
4992 suppressed index, 32-bit displacement. */
4993 *buffer_address++ = 0x01;
4994 *buffer_address++ = 0x70;
4995 fragP->fr_fix += 2;
4996 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4997 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4998 fixP->fx_pcrel_adjust = 2;
4999 fragP->fr_fix += 4;
5000 break;
5001 case TAB (PCINDEX, BYTE):
5002 assert (fragP->fr_fix >= 2);
5003 buffer_address[-2] &= ~1;
5004 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5005 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5006 fixP->fx_pcrel_adjust = 1;
5007 break;
5008 case TAB (PCINDEX, SHORT):
5009 assert (fragP->fr_fix >= 2);
5010 buffer_address[-2] |= 0x1;
5011 buffer_address[-1] = 0x20;
5012 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5013 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5014 fixP->fx_pcrel_adjust = 2;
5015 fragP->fr_fix += 2;
5016 break;
5017 case TAB (PCINDEX, LONG):
5018 assert (fragP->fr_fix >= 2);
5019 buffer_address[-2] |= 0x1;
5020 buffer_address[-1] = 0x30;
5021 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5022 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5023 fixP->fx_pcrel_adjust = 2;
5024 fragP->fr_fix += 4;
5025 break;
5026 case TAB (ABSTOPCREL, SHORT):
5027 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5028 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5029 fragP->fr_fix += 2;
5030 break;
5031 case TAB (ABSTOPCREL, LONG):
5032 if (flag_keep_pcrel)
5033 as_fatal (_("Conversion of PC relative displacement to absolute"));
5034 /* The thing to do here is force it to ABSOLUTE LONG, since
5035 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5036 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5037 abort ();
5038 fragP->fr_opcode[1] &= ~0x3F;
5039 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5040 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5041 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5042 fragP->fr_fix += 4;
5043 break;
5044 }
5045 if (fixP)
5046 {
5047 fixP->fx_file = fragP->fr_file;
5048 fixP->fx_line = fragP->fr_line;
5049 }
5050 }
5051
5052 void
5053 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5054 segT sec ATTRIBUTE_UNUSED,
5055 fragS *fragP)
5056 {
5057 md_convert_frag_1 (fragP);
5058 }
5059
5060 /* Force truly undefined symbols to their maximum size, and generally set up
5061 the frag list to be relaxed
5062 */
5063 int
5064 md_estimate_size_before_relax (fragS *fragP, segT segment)
5065 {
5066 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5067 switch (fragP->fr_subtype)
5068 {
5069 case TAB (BRANCHBWL, SZ_UNDEF):
5070 case TAB (BRABSJUNC, SZ_UNDEF):
5071 case TAB (BRABSJCOND, SZ_UNDEF):
5072 {
5073 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5074 && relaxable_symbol (fragP->fr_symbol))
5075 {
5076 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5077 }
5078 else if (flag_short_refs)
5079 {
5080 /* Symbol is undefined and we want short ref. */
5081 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5082 }
5083 else
5084 {
5085 /* Symbol is still undefined. Make it LONG. */
5086 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5087 }
5088 break;
5089 }
5090
5091 case TAB (BRANCHBW, SZ_UNDEF):
5092 {
5093 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5094 && relaxable_symbol (fragP->fr_symbol))
5095 {
5096 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5097 }
5098 else
5099 {
5100 /* Symbol is undefined and we don't have long branches. */
5101 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5102 }
5103 break;
5104 }
5105
5106 case TAB (FBRANCH, SZ_UNDEF):
5107 case TAB (DBCCLBR, SZ_UNDEF):
5108 case TAB (DBCCABSJ, SZ_UNDEF):
5109 case TAB (PCREL1632, SZ_UNDEF):
5110 {
5111 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5112 && relaxable_symbol (fragP->fr_symbol))
5113 || flag_short_refs)
5114 {
5115 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5116 }
5117 else
5118 {
5119 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5120 }
5121 break;
5122 }
5123
5124 case TAB (PCINDEX, SZ_UNDEF):
5125 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5126 && relaxable_symbol (fragP->fr_symbol)))
5127 {
5128 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5129 }
5130 else
5131 {
5132 fragP->fr_subtype = TAB (PCINDEX, LONG);
5133 }
5134 break;
5135
5136 case TAB (ABSTOPCREL, SZ_UNDEF):
5137 {
5138 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5139 && relaxable_symbol (fragP->fr_symbol)))
5140 {
5141 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5142 }
5143 else
5144 {
5145 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5146 }
5147 break;
5148 }
5149
5150 default:
5151 break;
5152 }
5153
5154 /* Now that SZ_UNDEF are taken care of, check others. */
5155 switch (fragP->fr_subtype)
5156 {
5157 case TAB (BRANCHBWL, BYTE):
5158 case TAB (BRABSJUNC, BYTE):
5159 case TAB (BRABSJCOND, BYTE):
5160 case TAB (BRANCHBW, BYTE):
5161 /* We can't do a short jump to the next instruction, so in that
5162 case we force word mode. If the symbol is at the start of a
5163 frag, and it is the next frag with any data in it (usually
5164 this is just the next frag, but assembler listings may
5165 introduce empty frags), we must use word mode. */
5166 if (fragP->fr_symbol)
5167 {
5168 fragS *sym_frag;
5169
5170 sym_frag = symbol_get_frag (fragP->fr_symbol);
5171 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5172 {
5173 fragS *l;
5174
5175 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5176 if (l->fr_fix != 0)
5177 break;
5178 if (l == sym_frag)
5179 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5180 }
5181 }
5182 break;
5183 default:
5184 break;
5185 }
5186 return md_relax_table[fragP->fr_subtype].rlx_length;
5187 }
5188
5189 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5190 /* the bit-field entries in the relocation_info struct plays hell
5191 with the byte-order problems of cross-assembly. So as a hack,
5192 I added this mach. dependent ri twiddler. Ugly, but it gets
5193 you there. -KWK */
5194 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5195 are symbolnum, most sig. byte first. Last byte is broken up with
5196 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5197 nibble as nuthin. (on Sun 3 at least) */
5198 /* Translate the internal relocation information into target-specific
5199 format. */
5200 #ifdef comment
5201 void
5202 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5203 {
5204 /* This is easy. */
5205 md_number_to_chars (the_bytes, ri->r_address, 4);
5206 /* Now the fun stuff. */
5207 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5208 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5209 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5210 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5211 | ((ri->r_length << 5) & 0x60)
5212 | ((ri->r_extern << 4) & 0x10));
5213 }
5214
5215 #endif
5216
5217 #endif /* OBJ_AOUT or OBJ_BOUT */
5218
5219 #ifndef WORKING_DOT_WORD
5220 int md_short_jump_size = 4;
5221 int md_long_jump_size = 6;
5222
5223 void
5224 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5225 fragS *frag ATTRIBUTE_UNUSED,
5226 symbolS *to_symbol ATTRIBUTE_UNUSED)
5227 {
5228 valueT offset;
5229
5230 offset = to_addr - (from_addr + 2);
5231
5232 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5233 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5234 }
5235
5236 void
5237 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5238 fragS *frag, symbolS *to_symbol)
5239 {
5240 valueT offset;
5241
5242 if (!HAVE_LONG_BRANCH (current_architecture))
5243 {
5244 if (flag_keep_pcrel)
5245 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5246 offset = to_addr - S_GET_VALUE (to_symbol);
5247 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5248 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5249 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5250 0, NO_RELOC);
5251 }
5252 else
5253 {
5254 offset = to_addr - (from_addr + 2);
5255 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5256 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5257 }
5258 }
5259
5260 #endif
5261
5262 /* Different values of OK tell what its OK to return. Things that
5263 aren't OK are an error (what a shock, no?)
5264
5265 0: Everything is OK
5266 10: Absolute 1:8 only
5267 20: Absolute 0:7 only
5268 30: absolute 0:15 only
5269 40: Absolute 0:31 only
5270 50: absolute 0:127 only
5271 55: absolute -64:63 only
5272 60: absolute -128:127 only
5273 65: absolute 0:511 only
5274 70: absolute 0:4095 only
5275 80: absolute -1, 1:7 only
5276 90: No bignums. */
5277
5278 static int
5279 get_num (struct m68k_exp *exp, int ok)
5280 {
5281 if (exp->exp.X_op == O_absent)
5282 {
5283 /* Do the same thing the VAX asm does. */
5284 op (exp) = O_constant;
5285 adds (exp) = 0;
5286 subs (exp) = 0;
5287 offs (exp) = 0;
5288 if (ok == 10)
5289 {
5290 as_warn (_("expression out of range: defaulting to 1"));
5291 offs (exp) = 1;
5292 }
5293 }
5294 else if (exp->exp.X_op == O_constant)
5295 {
5296 switch (ok)
5297 {
5298 case 10:
5299 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5300 {
5301 as_warn (_("expression out of range: defaulting to 1"));
5302 offs (exp) = 1;
5303 }
5304 break;
5305 case 20:
5306 if ((valueT) TRUNC (offs (exp)) > 7)
5307 goto outrange;
5308 break;
5309 case 30:
5310 if ((valueT) TRUNC (offs (exp)) > 15)
5311 goto outrange;
5312 break;
5313 case 40:
5314 if ((valueT) TRUNC (offs (exp)) > 32)
5315 goto outrange;
5316 break;
5317 case 50:
5318 if ((valueT) TRUNC (offs (exp)) > 127)
5319 goto outrange;
5320 break;
5321 case 55:
5322 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5323 goto outrange;
5324 break;
5325 case 60:
5326 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5327 goto outrange;
5328 break;
5329 case 65:
5330 if ((valueT) TRUNC (offs (exp)) > 511)
5331 goto outrange;
5332 break;
5333 case 70:
5334 if ((valueT) TRUNC (offs (exp)) > 4095)
5335 {
5336 outrange:
5337 as_warn (_("expression out of range: defaulting to 0"));
5338 offs (exp) = 0;
5339 }
5340 break;
5341 case 80:
5342 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5343 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5344 {
5345 as_warn (_("expression out of range: defaulting to 1"));
5346 offs (exp) = 1;
5347 }
5348 break;
5349 default:
5350 break;
5351 }
5352 }
5353 else if (exp->exp.X_op == O_big)
5354 {
5355 if (offs (exp) <= 0 /* flonum. */
5356 && (ok == 90 /* no bignums */
5357 || (ok > 10 /* Small-int ranges including 0 ok. */
5358 /* If we have a flonum zero, a zero integer should
5359 do as well (e.g., in moveq). */
5360 && generic_floating_point_number.exponent == 0
5361 && generic_floating_point_number.low[0] == 0)))
5362 {
5363 /* HACK! Turn it into a long. */
5364 LITTLENUM_TYPE words[6];
5365
5366 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5367 op (exp) = O_constant;
5368 adds (exp) = 0;
5369 subs (exp) = 0;
5370 offs (exp) = words[1] | (words[0] << 16);
5371 }
5372 else if (ok != 0)
5373 {
5374 op (exp) = O_constant;
5375 adds (exp) = 0;
5376 subs (exp) = 0;
5377 offs (exp) = (ok == 10) ? 1 : 0;
5378 as_warn (_("Can't deal with expression; defaulting to %ld"),
5379 (long) offs (exp));
5380 }
5381 }
5382 else
5383 {
5384 if (ok >= 10 && ok <= 80)
5385 {
5386 op (exp) = O_constant;
5387 adds (exp) = 0;
5388 subs (exp) = 0;
5389 offs (exp) = (ok == 10) ? 1 : 0;
5390 as_warn (_("Can't deal with expression; defaulting to %ld"),
5391 (long) offs (exp));
5392 }
5393 }
5394
5395 if (exp->size != SIZE_UNSPEC)
5396 {
5397 switch (exp->size)
5398 {
5399 case SIZE_UNSPEC:
5400 case SIZE_LONG:
5401 break;
5402 case SIZE_BYTE:
5403 if (!isbyte (offs (exp)))
5404 as_warn (_("expression doesn't fit in BYTE"));
5405 break;
5406 case SIZE_WORD:
5407 if (!isword (offs (exp)))
5408 as_warn (_("expression doesn't fit in WORD"));
5409 break;
5410 }
5411 }
5412
5413 return offs (exp);
5414 }
5415
5416 /* These are the back-ends for the various machine dependent pseudo-ops. */
5417
5418 static void
5419 s_data1 (int ignore ATTRIBUTE_UNUSED)
5420 {
5421 subseg_set (data_section, 1);
5422 demand_empty_rest_of_line ();
5423 }
5424
5425 static void
5426 s_data2 (int ignore ATTRIBUTE_UNUSED)
5427 {
5428 subseg_set (data_section, 2);
5429 demand_empty_rest_of_line ();
5430 }
5431
5432 static void
5433 s_bss (int ignore ATTRIBUTE_UNUSED)
5434 {
5435 /* We don't support putting frags in the BSS segment, we fake it
5436 by marking in_bss, then looking at s_skip for clues. */
5437
5438 subseg_set (bss_section, 0);
5439 demand_empty_rest_of_line ();
5440 }
5441
5442 static void
5443 s_even (int ignore ATTRIBUTE_UNUSED)
5444 {
5445 register int temp;
5446 register long temp_fill;
5447
5448 temp = 1; /* JF should be 2? */
5449 temp_fill = get_absolute_expression ();
5450 if (!need_pass_2) /* Never make frag if expect extra pass. */
5451 frag_align (temp, (int) temp_fill, 0);
5452 demand_empty_rest_of_line ();
5453 record_alignment (now_seg, temp);
5454 }
5455
5456 static void
5457 s_proc (int ignore ATTRIBUTE_UNUSED)
5458 {
5459 demand_empty_rest_of_line ();
5460 }
5461 \f
5462 /* Pseudo-ops handled for MRI compatibility. */
5463
5464 /* This function returns non-zero if the argument is a conditional
5465 pseudo-op. This is called when checking whether a pending
5466 alignment is needed. */
5467
5468 int
5469 m68k_conditional_pseudoop (pseudo_typeS *pop)
5470 {
5471 return (pop->poc_handler == s_mri_if
5472 || pop->poc_handler == s_mri_else);
5473 }
5474
5475 /* Handle an MRI style chip specification. */
5476
5477 static void
5478 mri_chip (void)
5479 {
5480 char *s;
5481 char c;
5482 int i;
5483
5484 s = input_line_pointer;
5485 /* We can't use get_symbol_end since the processor names are not proper
5486 symbols. */
5487 while (is_part_of_name (c = *input_line_pointer++))
5488 ;
5489 *--input_line_pointer = 0;
5490 for (i = 0; m68k_cpus[i].name; i++)
5491 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5492 break;
5493 if (!m68k_cpus[i].name)
5494 {
5495 as_bad (_("%s: unrecognized processor name"), s);
5496 *input_line_pointer = c;
5497 ignore_rest_of_line ();
5498 return;
5499 }
5500 *input_line_pointer = c;
5501
5502 if (*input_line_pointer == '/')
5503 current_architecture = 0;
5504 else
5505 current_architecture &= m68881 | m68851;
5506 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5507 control_regs = m68k_cpus[i].control_regs;
5508
5509 while (*input_line_pointer == '/')
5510 {
5511 ++input_line_pointer;
5512 s = input_line_pointer;
5513 /* We can't use get_symbol_end since the processor names are not
5514 proper symbols. */
5515 while (is_part_of_name (c = *input_line_pointer++))
5516 ;
5517 *--input_line_pointer = 0;
5518 if (strcmp (s, "68881") == 0)
5519 current_architecture |= m68881;
5520 else if (strcmp (s, "68851") == 0)
5521 current_architecture |= m68851;
5522 *input_line_pointer = c;
5523 }
5524 }
5525
5526 /* The MRI CHIP pseudo-op. */
5527
5528 static void
5529 s_chip (int ignore ATTRIBUTE_UNUSED)
5530 {
5531 char *stop = NULL;
5532 char stopc;
5533
5534 if (flag_mri)
5535 stop = mri_comment_field (&stopc);
5536 mri_chip ();
5537 if (flag_mri)
5538 mri_comment_end (stop, stopc);
5539 demand_empty_rest_of_line ();
5540 }
5541
5542 /* The MRI FOPT pseudo-op. */
5543
5544 static void
5545 s_fopt (int ignore ATTRIBUTE_UNUSED)
5546 {
5547 SKIP_WHITESPACE ();
5548
5549 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5550 {
5551 int temp;
5552
5553 input_line_pointer += 3;
5554 temp = get_absolute_expression ();
5555 if (temp < 0 || temp > 7)
5556 as_bad (_("bad coprocessor id"));
5557 else
5558 m68k_float_copnum = COP0 + temp;
5559 }
5560 else
5561 {
5562 as_bad (_("unrecognized fopt option"));
5563 ignore_rest_of_line ();
5564 return;
5565 }
5566
5567 demand_empty_rest_of_line ();
5568 }
5569
5570 /* The structure used to handle the MRI OPT pseudo-op. */
5571
5572 struct opt_action
5573 {
5574 /* The name of the option. */
5575 const char *name;
5576
5577 /* If this is not NULL, just call this function. The first argument
5578 is the ARG field of this structure, the second argument is
5579 whether the option was negated. */
5580 void (*pfn) (int arg, int on);
5581
5582 /* If this is not NULL, and the PFN field is NULL, set the variable
5583 this points to. Set it to the ARG field if the option was not
5584 negated, and the NOTARG field otherwise. */
5585 int *pvar;
5586
5587 /* The value to pass to PFN or to assign to *PVAR. */
5588 int arg;
5589
5590 /* The value to assign to *PVAR if the option is negated. If PFN is
5591 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5592 the option may not be negated. */
5593 int notarg;
5594 };
5595
5596 /* The table used to handle the MRI OPT pseudo-op. */
5597
5598 static void skip_to_comma (int, int);
5599 static void opt_nest (int, int);
5600 static void opt_chip (int, int);
5601 static void opt_list (int, int);
5602 static void opt_list_symbols (int, int);
5603
5604 static const struct opt_action opt_table[] =
5605 {
5606 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5607
5608 /* We do relaxing, so there is little use for these options. */
5609 { "b", 0, 0, 0, 0 },
5610 { "brs", 0, 0, 0, 0 },
5611 { "brb", 0, 0, 0, 0 },
5612 { "brl", 0, 0, 0, 0 },
5613 { "brw", 0, 0, 0, 0 },
5614
5615 { "c", 0, 0, 0, 0 },
5616 { "cex", 0, 0, 0, 0 },
5617 { "case", 0, &symbols_case_sensitive, 1, 0 },
5618 { "cl", 0, 0, 0, 0 },
5619 { "cre", 0, 0, 0, 0 },
5620 { "d", 0, &flag_keep_locals, 1, 0 },
5621 { "e", 0, 0, 0, 0 },
5622 { "f", 0, &flag_short_refs, 1, 0 },
5623 { "frs", 0, &flag_short_refs, 1, 0 },
5624 { "frl", 0, &flag_short_refs, 0, 1 },
5625 { "g", 0, 0, 0, 0 },
5626 { "i", 0, 0, 0, 0 },
5627 { "m", 0, 0, 0, 0 },
5628 { "mex", 0, 0, 0, 0 },
5629 { "mc", 0, 0, 0, 0 },
5630 { "md", 0, 0, 0, 0 },
5631 { "nest", opt_nest, 0, 0, 0 },
5632 { "next", skip_to_comma, 0, 0, 0 },
5633 { "o", 0, 0, 0, 0 },
5634 { "old", 0, 0, 0, 0 },
5635 { "op", skip_to_comma, 0, 0, 0 },
5636 { "pco", 0, 0, 0, 0 },
5637 { "p", opt_chip, 0, 0, 0 },
5638 { "pcr", 0, 0, 0, 0 },
5639 { "pcs", 0, 0, 0, 0 },
5640 { "r", 0, 0, 0, 0 },
5641 { "quick", 0, &m68k_quick, 1, 0 },
5642 { "rel32", 0, &m68k_rel32, 1, 0 },
5643 { "s", opt_list, 0, 0, 0 },
5644 { "t", opt_list_symbols, 0, 0, 0 },
5645 { "w", 0, &flag_no_warnings, 0, 1 },
5646 { "x", 0, 0, 0, 0 }
5647 };
5648
5649 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5650
5651 /* The MRI OPT pseudo-op. */
5652
5653 static void
5654 s_opt (int ignore ATTRIBUTE_UNUSED)
5655 {
5656 do
5657 {
5658 int t;
5659 char *s;
5660 char c;
5661 int i;
5662 const struct opt_action *o;
5663
5664 SKIP_WHITESPACE ();
5665
5666 t = 1;
5667 if (*input_line_pointer == '-')
5668 {
5669 ++input_line_pointer;
5670 t = 0;
5671 }
5672 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5673 {
5674 input_line_pointer += 2;
5675 t = 0;
5676 }
5677
5678 s = input_line_pointer;
5679 c = get_symbol_end ();
5680
5681 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5682 {
5683 if (strcasecmp (s, o->name) == 0)
5684 {
5685 if (o->pfn)
5686 {
5687 /* Restore input_line_pointer now in case the option
5688 takes arguments. */
5689 *input_line_pointer = c;
5690 (*o->pfn) (o->arg, t);
5691 }
5692 else if (o->pvar != NULL)
5693 {
5694 if (! t && o->arg == o->notarg)
5695 as_bad (_("option `%s' may not be negated"), s);
5696 *input_line_pointer = c;
5697 *o->pvar = t ? o->arg : o->notarg;
5698 }
5699 else
5700 *input_line_pointer = c;
5701 break;
5702 }
5703 }
5704 if (i >= OPTCOUNT)
5705 {
5706 as_bad (_("option `%s' not recognized"), s);
5707 *input_line_pointer = c;
5708 }
5709 }
5710 while (*input_line_pointer++ == ',');
5711
5712 /* Move back to terminating character. */
5713 --input_line_pointer;
5714 demand_empty_rest_of_line ();
5715 }
5716
5717 /* Skip ahead to a comma. This is used for OPT options which we do
5718 not support and which take arguments. */
5719
5720 static void
5721 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5722 {
5723 while (*input_line_pointer != ','
5724 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5725 ++input_line_pointer;
5726 }
5727
5728 /* Handle the OPT NEST=depth option. */
5729
5730 static void
5731 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5732 {
5733 if (*input_line_pointer != '=')
5734 {
5735 as_bad (_("bad format of OPT NEST=depth"));
5736 return;
5737 }
5738
5739 ++input_line_pointer;
5740 max_macro_nest = get_absolute_expression ();
5741 }
5742
5743 /* Handle the OPT P=chip option. */
5744
5745 static void
5746 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5747 {
5748 if (*input_line_pointer != '=')
5749 {
5750 /* This is just OPT P, which we do not support. */
5751 return;
5752 }
5753
5754 ++input_line_pointer;
5755 mri_chip ();
5756 }
5757
5758 /* Handle the OPT S option. */
5759
5760 static void
5761 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5762 {
5763 listing_list (on);
5764 }
5765
5766 /* Handle the OPT T option. */
5767
5768 static void
5769 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5770 {
5771 if (on)
5772 listing |= LISTING_SYMBOLS;
5773 else
5774 listing &= ~LISTING_SYMBOLS;
5775 }
5776
5777 /* Handle the MRI REG pseudo-op. */
5778
5779 static void
5780 s_reg (int ignore ATTRIBUTE_UNUSED)
5781 {
5782 char *s;
5783 int c;
5784 struct m68k_op rop;
5785 int mask;
5786 char *stop = NULL;
5787 char stopc;
5788
5789 if (line_label == NULL)
5790 {
5791 as_bad (_("missing label"));
5792 ignore_rest_of_line ();
5793 return;
5794 }
5795
5796 if (flag_mri)
5797 stop = mri_comment_field (&stopc);
5798
5799 SKIP_WHITESPACE ();
5800
5801 s = input_line_pointer;
5802 while (ISALNUM (*input_line_pointer)
5803 #ifdef REGISTER_PREFIX
5804 || *input_line_pointer == REGISTER_PREFIX
5805 #endif
5806 || *input_line_pointer == '/'
5807 || *input_line_pointer == '-')
5808 ++input_line_pointer;
5809 c = *input_line_pointer;
5810 *input_line_pointer = '\0';
5811
5812 if (m68k_ip_op (s, &rop) != 0)
5813 {
5814 if (rop.error == NULL)
5815 as_bad (_("bad register list"));
5816 else
5817 as_bad (_("bad register list: %s"), rop.error);
5818 *input_line_pointer = c;
5819 ignore_rest_of_line ();
5820 return;
5821 }
5822
5823 *input_line_pointer = c;
5824
5825 if (rop.mode == REGLST)
5826 mask = rop.mask;
5827 else if (rop.mode == DREG)
5828 mask = 1 << (rop.reg - DATA0);
5829 else if (rop.mode == AREG)
5830 mask = 1 << (rop.reg - ADDR0 + 8);
5831 else if (rop.mode == FPREG)
5832 mask = 1 << (rop.reg - FP0 + 16);
5833 else if (rop.mode == CONTROL
5834 && rop.reg == FPI)
5835 mask = 1 << 24;
5836 else if (rop.mode == CONTROL
5837 && rop.reg == FPS)
5838 mask = 1 << 25;
5839 else if (rop.mode == CONTROL
5840 && rop.reg == FPC)
5841 mask = 1 << 26;
5842 else
5843 {
5844 as_bad (_("bad register list"));
5845 ignore_rest_of_line ();
5846 return;
5847 }
5848
5849 S_SET_SEGMENT (line_label, reg_section);
5850 S_SET_VALUE (line_label, ~mask);
5851 symbol_set_frag (line_label, &zero_address_frag);
5852
5853 if (flag_mri)
5854 mri_comment_end (stop, stopc);
5855
5856 demand_empty_rest_of_line ();
5857 }
5858
5859 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5860
5861 struct save_opts
5862 {
5863 struct save_opts *next;
5864 int abspcadd;
5865 int symbols_case_sensitive;
5866 int keep_locals;
5867 int short_refs;
5868 int architecture;
5869 const enum m68k_register *control_regs;
5870 int quick;
5871 int rel32;
5872 int listing;
5873 int no_warnings;
5874 /* FIXME: We don't save OPT S. */
5875 };
5876
5877 /* This variable holds the stack of saved options. */
5878
5879 static struct save_opts *save_stack;
5880
5881 /* The MRI SAVE pseudo-op. */
5882
5883 static void
5884 s_save (int ignore ATTRIBUTE_UNUSED)
5885 {
5886 struct save_opts *s;
5887
5888 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5889 s->abspcadd = m68k_abspcadd;
5890 s->symbols_case_sensitive = symbols_case_sensitive;
5891 s->keep_locals = flag_keep_locals;
5892 s->short_refs = flag_short_refs;
5893 s->architecture = current_architecture;
5894 s->control_regs = control_regs;
5895 s->quick = m68k_quick;
5896 s->rel32 = m68k_rel32;
5897 s->listing = listing;
5898 s->no_warnings = flag_no_warnings;
5899
5900 s->next = save_stack;
5901 save_stack = s;
5902
5903 demand_empty_rest_of_line ();
5904 }
5905
5906 /* The MRI RESTORE pseudo-op. */
5907
5908 static void
5909 s_restore (int ignore ATTRIBUTE_UNUSED)
5910 {
5911 struct save_opts *s;
5912
5913 if (save_stack == NULL)
5914 {
5915 as_bad (_("restore without save"));
5916 ignore_rest_of_line ();
5917 return;
5918 }
5919
5920 s = save_stack;
5921 save_stack = s->next;
5922
5923 m68k_abspcadd = s->abspcadd;
5924 symbols_case_sensitive = s->symbols_case_sensitive;
5925 flag_keep_locals = s->keep_locals;
5926 flag_short_refs = s->short_refs;
5927 current_architecture = s->architecture;
5928 control_regs = s->control_regs;
5929 m68k_quick = s->quick;
5930 m68k_rel32 = s->rel32;
5931 listing = s->listing;
5932 flag_no_warnings = s->no_warnings;
5933
5934 free (s);
5935
5936 demand_empty_rest_of_line ();
5937 }
5938
5939 /* Types of MRI structured control directives. */
5940
5941 enum mri_control_type
5942 {
5943 mri_for,
5944 mri_if,
5945 mri_repeat,
5946 mri_while
5947 };
5948
5949 /* This structure is used to stack the MRI structured control
5950 directives. */
5951
5952 struct mri_control_info
5953 {
5954 /* The directive within which this one is enclosed. */
5955 struct mri_control_info *outer;
5956
5957 /* The type of directive. */
5958 enum mri_control_type type;
5959
5960 /* Whether an ELSE has been in an IF. */
5961 int else_seen;
5962
5963 /* The add or sub statement at the end of a FOR. */
5964 char *incr;
5965
5966 /* The label of the top of a FOR or REPEAT loop. */
5967 char *top;
5968
5969 /* The label to jump to for the next iteration, or the else
5970 expression of a conditional. */
5971 char *next;
5972
5973 /* The label to jump to to break out of the loop, or the label past
5974 the end of a conditional. */
5975 char *bottom;
5976 };
5977
5978 /* The stack of MRI structured control directives. */
5979
5980 static struct mri_control_info *mri_control_stack;
5981
5982 /* The current MRI structured control directive index number, used to
5983 generate label names. */
5984
5985 static int mri_control_index;
5986
5987 /* Assemble an instruction for an MRI structured control directive. */
5988
5989 static void
5990 mri_assemble (char *str)
5991 {
5992 char *s;
5993
5994 /* md_assemble expects the opcode to be in lower case. */
5995 for (s = str; *s != ' ' && *s != '\0'; s++)
5996 *s = TOLOWER (*s);
5997
5998 md_assemble (str);
5999 }
6000
6001 /* Generate a new MRI label structured control directive label name. */
6002
6003 static char *
6004 mri_control_label (void)
6005 {
6006 char *n;
6007
6008 n = (char *) xmalloc (20);
6009 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6010 ++mri_control_index;
6011 return n;
6012 }
6013
6014 /* Create a new MRI structured control directive. */
6015
6016 static struct mri_control_info *
6017 push_mri_control (enum mri_control_type type)
6018 {
6019 struct mri_control_info *n;
6020
6021 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6022
6023 n->type = type;
6024 n->else_seen = 0;
6025 if (type == mri_if || type == mri_while)
6026 n->top = NULL;
6027 else
6028 n->top = mri_control_label ();
6029 n->next = mri_control_label ();
6030 n->bottom = mri_control_label ();
6031
6032 n->outer = mri_control_stack;
6033 mri_control_stack = n;
6034
6035 return n;
6036 }
6037
6038 /* Pop off the stack of MRI structured control directives. */
6039
6040 static void
6041 pop_mri_control (void)
6042 {
6043 struct mri_control_info *n;
6044
6045 n = mri_control_stack;
6046 mri_control_stack = n->outer;
6047 if (n->top != NULL)
6048 free (n->top);
6049 free (n->next);
6050 free (n->bottom);
6051 free (n);
6052 }
6053
6054 /* Recognize a condition code in an MRI structured control expression. */
6055
6056 static int
6057 parse_mri_condition (int *pcc)
6058 {
6059 char c1, c2;
6060
6061 know (*input_line_pointer == '<');
6062
6063 ++input_line_pointer;
6064 c1 = *input_line_pointer++;
6065 c2 = *input_line_pointer++;
6066
6067 if (*input_line_pointer != '>')
6068 {
6069 as_bad (_("syntax error in structured control directive"));
6070 return 0;
6071 }
6072
6073 ++input_line_pointer;
6074 SKIP_WHITESPACE ();
6075
6076 c1 = TOLOWER (c1);
6077 c2 = TOLOWER (c2);
6078
6079 *pcc = (c1 << 8) | c2;
6080
6081 return 1;
6082 }
6083
6084 /* Parse a single operand in an MRI structured control expression. */
6085
6086 static int
6087 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6088 char **rightstart, char **rightstop)
6089 {
6090 char *s;
6091
6092 SKIP_WHITESPACE ();
6093
6094 *pcc = -1;
6095 *leftstart = NULL;
6096 *leftstop = NULL;
6097 *rightstart = NULL;
6098 *rightstop = NULL;
6099
6100 if (*input_line_pointer == '<')
6101 {
6102 /* It's just a condition code. */
6103 return parse_mri_condition (pcc);
6104 }
6105
6106 /* Look ahead for the condition code. */
6107 for (s = input_line_pointer; *s != '\0'; ++s)
6108 {
6109 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6110 break;
6111 }
6112 if (*s == '\0')
6113 {
6114 as_bad (_("missing condition code in structured control directive"));
6115 return 0;
6116 }
6117
6118 *leftstart = input_line_pointer;
6119 *leftstop = s;
6120 if (*leftstop > *leftstart
6121 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6122 --*leftstop;
6123
6124 input_line_pointer = s;
6125 if (! parse_mri_condition (pcc))
6126 return 0;
6127
6128 /* Look ahead for AND or OR or end of line. */
6129 for (s = input_line_pointer; *s != '\0'; ++s)
6130 {
6131 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6132 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6133 ^^^ ^^ */
6134 if ((s == input_line_pointer
6135 || *(s-1) == ' '
6136 || *(s-1) == '\t')
6137 && ((strncasecmp (s, "AND", 3) == 0
6138 && (s[3] == '.' || ! is_part_of_name (s[3])))
6139 || (strncasecmp (s, "OR", 2) == 0
6140 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6141 break;
6142 }
6143
6144 *rightstart = input_line_pointer;
6145 *rightstop = s;
6146 if (*rightstop > *rightstart
6147 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6148 --*rightstop;
6149
6150 input_line_pointer = s;
6151
6152 return 1;
6153 }
6154
6155 #define MCC(b1, b2) (((b1) << 8) | (b2))
6156
6157 /* Swap the sense of a condition. This changes the condition so that
6158 it generates the same result when the operands are swapped. */
6159
6160 static int
6161 swap_mri_condition (int cc)
6162 {
6163 switch (cc)
6164 {
6165 case MCC ('h', 'i'): return MCC ('c', 's');
6166 case MCC ('l', 's'): return MCC ('c', 'c');
6167 /* <HS> is an alias for <CC>. */
6168 case MCC ('h', 's'):
6169 case MCC ('c', 'c'): return MCC ('l', 's');
6170 /* <LO> is an alias for <CS>. */
6171 case MCC ('l', 'o'):
6172 case MCC ('c', 's'): return MCC ('h', 'i');
6173 case MCC ('p', 'l'): return MCC ('m', 'i');
6174 case MCC ('m', 'i'): return MCC ('p', 'l');
6175 case MCC ('g', 'e'): return MCC ('l', 'e');
6176 case MCC ('l', 't'): return MCC ('g', 't');
6177 case MCC ('g', 't'): return MCC ('l', 't');
6178 case MCC ('l', 'e'): return MCC ('g', 'e');
6179 /* Issue a warning for conditions we can not swap. */
6180 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6181 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6182 case MCC ('v', 'c'):
6183 case MCC ('v', 's'):
6184 default :
6185 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6186 (char) (cc >> 8), (char) (cc));
6187 break;
6188 }
6189 return cc;
6190 }
6191
6192 /* Reverse the sense of a condition. */
6193
6194 static int
6195 reverse_mri_condition (int cc)
6196 {
6197 switch (cc)
6198 {
6199 case MCC ('h', 'i'): return MCC ('l', 's');
6200 case MCC ('l', 's'): return MCC ('h', 'i');
6201 /* <HS> is an alias for <CC> */
6202 case MCC ('h', 's'): return MCC ('l', 'o');
6203 case MCC ('c', 'c'): return MCC ('c', 's');
6204 /* <LO> is an alias for <CS> */
6205 case MCC ('l', 'o'): return MCC ('h', 's');
6206 case MCC ('c', 's'): return MCC ('c', 'c');
6207 case MCC ('n', 'e'): return MCC ('e', 'q');
6208 case MCC ('e', 'q'): return MCC ('n', 'e');
6209 case MCC ('v', 'c'): return MCC ('v', 's');
6210 case MCC ('v', 's'): return MCC ('v', 'c');
6211 case MCC ('p', 'l'): return MCC ('m', 'i');
6212 case MCC ('m', 'i'): return MCC ('p', 'l');
6213 case MCC ('g', 'e'): return MCC ('l', 't');
6214 case MCC ('l', 't'): return MCC ('g', 'e');
6215 case MCC ('g', 't'): return MCC ('l', 'e');
6216 case MCC ('l', 'e'): return MCC ('g', 't');
6217 }
6218 return cc;
6219 }
6220
6221 /* Build an MRI structured control expression. This generates test
6222 and branch instructions. It goes to TRUELAB if the condition is
6223 true, and to FALSELAB if the condition is false. Exactly one of
6224 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6225 is the size qualifier for the expression. EXTENT is the size to
6226 use for the branch. */
6227
6228 static void
6229 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6230 char *rightstart, char *rightstop,
6231 const char *truelab, const char *falselab,
6232 int extent)
6233 {
6234 char *buf;
6235 char *s;
6236
6237 if (leftstart != NULL)
6238 {
6239 struct m68k_op leftop, rightop;
6240 char c;
6241
6242 /* Swap the compare operands, if necessary, to produce a legal
6243 m68k compare instruction. Comparing a register operand with
6244 a non-register operand requires the register to be on the
6245 right (cmp, cmpa). Comparing an immediate value with
6246 anything requires the immediate value to be on the left
6247 (cmpi). */
6248
6249 c = *leftstop;
6250 *leftstop = '\0';
6251 (void) m68k_ip_op (leftstart, &leftop);
6252 *leftstop = c;
6253
6254 c = *rightstop;
6255 *rightstop = '\0';
6256 (void) m68k_ip_op (rightstart, &rightop);
6257 *rightstop = c;
6258
6259 if (rightop.mode == IMMED
6260 || ((leftop.mode == DREG || leftop.mode == AREG)
6261 && (rightop.mode != DREG && rightop.mode != AREG)))
6262 {
6263 char *temp;
6264
6265 /* Correct conditional handling:
6266 if #1 <lt> d0 then ;means if (1 < d0)
6267 ...
6268 endi
6269
6270 should assemble to:
6271
6272 cmp #1,d0 if we do *not* swap the operands
6273 bgt true we need the swapped condition!
6274 ble false
6275 true:
6276 ...
6277 false:
6278 */
6279 temp = leftstart;
6280 leftstart = rightstart;
6281 rightstart = temp;
6282 temp = leftstop;
6283 leftstop = rightstop;
6284 rightstop = temp;
6285 }
6286 else
6287 {
6288 cc = swap_mri_condition (cc);
6289 }
6290 }
6291
6292 if (truelab == NULL)
6293 {
6294 cc = reverse_mri_condition (cc);
6295 truelab = falselab;
6296 }
6297
6298 if (leftstart != NULL)
6299 {
6300 buf = (char *) xmalloc (20
6301 + (leftstop - leftstart)
6302 + (rightstop - rightstart));
6303 s = buf;
6304 *s++ = 'c';
6305 *s++ = 'm';
6306 *s++ = 'p';
6307 if (qual != '\0')
6308 *s++ = TOLOWER (qual);
6309 *s++ = ' ';
6310 memcpy (s, leftstart, leftstop - leftstart);
6311 s += leftstop - leftstart;
6312 *s++ = ',';
6313 memcpy (s, rightstart, rightstop - rightstart);
6314 s += rightstop - rightstart;
6315 *s = '\0';
6316 mri_assemble (buf);
6317 free (buf);
6318 }
6319
6320 buf = (char *) xmalloc (20 + strlen (truelab));
6321 s = buf;
6322 *s++ = 'b';
6323 *s++ = cc >> 8;
6324 *s++ = cc & 0xff;
6325 if (extent != '\0')
6326 *s++ = TOLOWER (extent);
6327 *s++ = ' ';
6328 strcpy (s, truelab);
6329 mri_assemble (buf);
6330 free (buf);
6331 }
6332
6333 /* Parse an MRI structured control expression. This generates test
6334 and branch instructions. STOP is where the expression ends. It
6335 goes to TRUELAB if the condition is true, and to FALSELAB if the
6336 condition is false. Exactly one of TRUELAB and FALSELAB will be
6337 NULL, meaning to fall through. QUAL is the size qualifier for the
6338 expression. EXTENT is the size to use for the branch. */
6339
6340 static void
6341 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6342 const char *falselab, int extent)
6343 {
6344 int c;
6345 int cc;
6346 char *leftstart;
6347 char *leftstop;
6348 char *rightstart;
6349 char *rightstop;
6350
6351 c = *stop;
6352 *stop = '\0';
6353
6354 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6355 &rightstart, &rightstop))
6356 {
6357 *stop = c;
6358 return;
6359 }
6360
6361 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6362 {
6363 const char *flab;
6364
6365 if (falselab != NULL)
6366 flab = falselab;
6367 else
6368 flab = mri_control_label ();
6369
6370 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6371 rightstop, (const char *) NULL, flab, extent);
6372
6373 input_line_pointer += 3;
6374 if (*input_line_pointer != '.'
6375 || input_line_pointer[1] == '\0')
6376 qual = '\0';
6377 else
6378 {
6379 qual = input_line_pointer[1];
6380 input_line_pointer += 2;
6381 }
6382
6383 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6384 &rightstart, &rightstop))
6385 {
6386 *stop = c;
6387 return;
6388 }
6389
6390 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6391 rightstop, truelab, falselab, extent);
6392
6393 if (falselab == NULL)
6394 colon (flab);
6395 }
6396 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6397 {
6398 const char *tlab;
6399
6400 if (truelab != NULL)
6401 tlab = truelab;
6402 else
6403 tlab = mri_control_label ();
6404
6405 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6406 rightstop, tlab, (const char *) NULL, extent);
6407
6408 input_line_pointer += 2;
6409 if (*input_line_pointer != '.'
6410 || input_line_pointer[1] == '\0')
6411 qual = '\0';
6412 else
6413 {
6414 qual = input_line_pointer[1];
6415 input_line_pointer += 2;
6416 }
6417
6418 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6419 &rightstart, &rightstop))
6420 {
6421 *stop = c;
6422 return;
6423 }
6424
6425 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6426 rightstop, truelab, falselab, extent);
6427
6428 if (truelab == NULL)
6429 colon (tlab);
6430 }
6431 else
6432 {
6433 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6434 rightstop, truelab, falselab, extent);
6435 }
6436
6437 *stop = c;
6438 if (input_line_pointer != stop)
6439 as_bad (_("syntax error in structured control directive"));
6440 }
6441
6442 /* Handle the MRI IF pseudo-op. This may be a structured control
6443 directive, or it may be a regular assembler conditional, depending
6444 on its operands. */
6445
6446 static void
6447 s_mri_if (int qual)
6448 {
6449 char *s;
6450 int c;
6451 struct mri_control_info *n;
6452
6453 /* A structured control directive must end with THEN with an
6454 optional qualifier. */
6455 s = input_line_pointer;
6456 /* We only accept '*' as introduction of comments if preceded by white space
6457 or at first column of a line (I think this can't actually happen here?)
6458 This is important when assembling:
6459 if d0 <ne> 12(a0,d0*2) then
6460 if d0 <ne> #CONST*20 then. */
6461 while (! (is_end_of_line[(unsigned char) *s]
6462 || (flag_mri
6463 && *s == '*'
6464 && (s == input_line_pointer
6465 || *(s-1) == ' '
6466 || *(s-1) == '\t'))))
6467 ++s;
6468 --s;
6469 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6470 --s;
6471
6472 if (s - input_line_pointer > 1
6473 && s[-1] == '.')
6474 s -= 2;
6475
6476 if (s - input_line_pointer < 3
6477 || strncasecmp (s - 3, "THEN", 4) != 0)
6478 {
6479 if (qual != '\0')
6480 {
6481 as_bad (_("missing then"));
6482 ignore_rest_of_line ();
6483 return;
6484 }
6485
6486 /* It's a conditional. */
6487 s_if (O_ne);
6488 return;
6489 }
6490
6491 /* Since this might be a conditional if, this pseudo-op will be
6492 called even if we are supported to be ignoring input. Double
6493 check now. Clobber *input_line_pointer so that ignore_input
6494 thinks that this is not a special pseudo-op. */
6495 c = *input_line_pointer;
6496 *input_line_pointer = 0;
6497 if (ignore_input ())
6498 {
6499 *input_line_pointer = c;
6500 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6501 ++input_line_pointer;
6502 demand_empty_rest_of_line ();
6503 return;
6504 }
6505 *input_line_pointer = c;
6506
6507 n = push_mri_control (mri_if);
6508
6509 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6510 n->next, s[1] == '.' ? s[2] : '\0');
6511
6512 if (s[1] == '.')
6513 input_line_pointer = s + 3;
6514 else
6515 input_line_pointer = s + 1;
6516
6517 if (flag_mri)
6518 {
6519 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6520 ++input_line_pointer;
6521 }
6522
6523 demand_empty_rest_of_line ();
6524 }
6525
6526 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6527 structured IF, associate the ELSE with the IF. Otherwise, assume
6528 it is a conditional else. */
6529
6530 static void
6531 s_mri_else (int qual)
6532 {
6533 int c;
6534 char *buf;
6535 char q[2];
6536
6537 if (qual == '\0'
6538 && (mri_control_stack == NULL
6539 || mri_control_stack->type != mri_if
6540 || mri_control_stack->else_seen))
6541 {
6542 s_else (0);
6543 return;
6544 }
6545
6546 c = *input_line_pointer;
6547 *input_line_pointer = 0;
6548 if (ignore_input ())
6549 {
6550 *input_line_pointer = c;
6551 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6552 ++input_line_pointer;
6553 demand_empty_rest_of_line ();
6554 return;
6555 }
6556 *input_line_pointer = c;
6557
6558 if (mri_control_stack == NULL
6559 || mri_control_stack->type != mri_if
6560 || mri_control_stack->else_seen)
6561 {
6562 as_bad (_("else without matching if"));
6563 ignore_rest_of_line ();
6564 return;
6565 }
6566
6567 mri_control_stack->else_seen = 1;
6568
6569 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6570 q[0] = TOLOWER (qual);
6571 q[1] = '\0';
6572 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6573 mri_assemble (buf);
6574 free (buf);
6575
6576 colon (mri_control_stack->next);
6577
6578 if (flag_mri)
6579 {
6580 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6581 ++input_line_pointer;
6582 }
6583
6584 demand_empty_rest_of_line ();
6585 }
6586
6587 /* Handle the MRI ENDI pseudo-op. */
6588
6589 static void
6590 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6591 {
6592 if (mri_control_stack == NULL
6593 || mri_control_stack->type != mri_if)
6594 {
6595 as_bad (_("endi without matching if"));
6596 ignore_rest_of_line ();
6597 return;
6598 }
6599
6600 /* ignore_input will not return true for ENDI, so we don't need to
6601 worry about checking it again here. */
6602
6603 if (! mri_control_stack->else_seen)
6604 colon (mri_control_stack->next);
6605 colon (mri_control_stack->bottom);
6606
6607 pop_mri_control ();
6608
6609 if (flag_mri)
6610 {
6611 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6612 ++input_line_pointer;
6613 }
6614
6615 demand_empty_rest_of_line ();
6616 }
6617
6618 /* Handle the MRI BREAK pseudo-op. */
6619
6620 static void
6621 s_mri_break (int extent)
6622 {
6623 struct mri_control_info *n;
6624 char *buf;
6625 char ex[2];
6626
6627 n = mri_control_stack;
6628 while (n != NULL
6629 && n->type != mri_for
6630 && n->type != mri_repeat
6631 && n->type != mri_while)
6632 n = n->outer;
6633 if (n == NULL)
6634 {
6635 as_bad (_("break outside of structured loop"));
6636 ignore_rest_of_line ();
6637 return;
6638 }
6639
6640 buf = (char *) xmalloc (20 + strlen (n->bottom));
6641 ex[0] = TOLOWER (extent);
6642 ex[1] = '\0';
6643 sprintf (buf, "bra%s %s", ex, n->bottom);
6644 mri_assemble (buf);
6645 free (buf);
6646
6647 if (flag_mri)
6648 {
6649 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6650 ++input_line_pointer;
6651 }
6652
6653 demand_empty_rest_of_line ();
6654 }
6655
6656 /* Handle the MRI NEXT pseudo-op. */
6657
6658 static void
6659 s_mri_next (int extent)
6660 {
6661 struct mri_control_info *n;
6662 char *buf;
6663 char ex[2];
6664
6665 n = mri_control_stack;
6666 while (n != NULL
6667 && n->type != mri_for
6668 && n->type != mri_repeat
6669 && n->type != mri_while)
6670 n = n->outer;
6671 if (n == NULL)
6672 {
6673 as_bad (_("next outside of structured loop"));
6674 ignore_rest_of_line ();
6675 return;
6676 }
6677
6678 buf = (char *) xmalloc (20 + strlen (n->next));
6679 ex[0] = TOLOWER (extent);
6680 ex[1] = '\0';
6681 sprintf (buf, "bra%s %s", ex, n->next);
6682 mri_assemble (buf);
6683 free (buf);
6684
6685 if (flag_mri)
6686 {
6687 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6688 ++input_line_pointer;
6689 }
6690
6691 demand_empty_rest_of_line ();
6692 }
6693
6694 /* Handle the MRI FOR pseudo-op. */
6695
6696 static void
6697 s_mri_for (int qual)
6698 {
6699 const char *varstart, *varstop;
6700 const char *initstart, *initstop;
6701 const char *endstart, *endstop;
6702 const char *bystart, *bystop;
6703 int up;
6704 int by;
6705 int extent;
6706 struct mri_control_info *n;
6707 char *buf;
6708 char *s;
6709 char ex[2];
6710
6711 /* The syntax is
6712 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6713 */
6714
6715 SKIP_WHITESPACE ();
6716 varstart = input_line_pointer;
6717
6718 /* Look for the '='. */
6719 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6720 && *input_line_pointer != '=')
6721 ++input_line_pointer;
6722 if (*input_line_pointer != '=')
6723 {
6724 as_bad (_("missing ="));
6725 ignore_rest_of_line ();
6726 return;
6727 }
6728
6729 varstop = input_line_pointer;
6730 if (varstop > varstart
6731 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6732 --varstop;
6733
6734 ++input_line_pointer;
6735
6736 initstart = input_line_pointer;
6737
6738 /* Look for TO or DOWNTO. */
6739 up = 1;
6740 initstop = NULL;
6741 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6742 {
6743 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6744 && ! is_part_of_name (input_line_pointer[2]))
6745 {
6746 initstop = input_line_pointer;
6747 input_line_pointer += 2;
6748 break;
6749 }
6750 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6751 && ! is_part_of_name (input_line_pointer[6]))
6752 {
6753 initstop = input_line_pointer;
6754 up = 0;
6755 input_line_pointer += 6;
6756 break;
6757 }
6758 ++input_line_pointer;
6759 }
6760 if (initstop == NULL)
6761 {
6762 as_bad (_("missing to or downto"));
6763 ignore_rest_of_line ();
6764 return;
6765 }
6766 if (initstop > initstart
6767 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6768 --initstop;
6769
6770 SKIP_WHITESPACE ();
6771 endstart = input_line_pointer;
6772
6773 /* Look for BY or DO. */
6774 by = 0;
6775 endstop = NULL;
6776 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6777 {
6778 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6779 && ! is_part_of_name (input_line_pointer[2]))
6780 {
6781 endstop = input_line_pointer;
6782 by = 1;
6783 input_line_pointer += 2;
6784 break;
6785 }
6786 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6787 && (input_line_pointer[2] == '.'
6788 || ! is_part_of_name (input_line_pointer[2])))
6789 {
6790 endstop = input_line_pointer;
6791 input_line_pointer += 2;
6792 break;
6793 }
6794 ++input_line_pointer;
6795 }
6796 if (endstop == NULL)
6797 {
6798 as_bad (_("missing do"));
6799 ignore_rest_of_line ();
6800 return;
6801 }
6802 if (endstop > endstart
6803 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6804 --endstop;
6805
6806 if (! by)
6807 {
6808 bystart = "#1";
6809 bystop = bystart + 2;
6810 }
6811 else
6812 {
6813 SKIP_WHITESPACE ();
6814 bystart = input_line_pointer;
6815
6816 /* Look for DO. */
6817 bystop = NULL;
6818 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6819 {
6820 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6821 && (input_line_pointer[2] == '.'
6822 || ! is_part_of_name (input_line_pointer[2])))
6823 {
6824 bystop = input_line_pointer;
6825 input_line_pointer += 2;
6826 break;
6827 }
6828 ++input_line_pointer;
6829 }
6830 if (bystop == NULL)
6831 {
6832 as_bad (_("missing do"));
6833 ignore_rest_of_line ();
6834 return;
6835 }
6836 if (bystop > bystart
6837 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6838 --bystop;
6839 }
6840
6841 if (*input_line_pointer != '.')
6842 extent = '\0';
6843 else
6844 {
6845 extent = input_line_pointer[1];
6846 input_line_pointer += 2;
6847 }
6848
6849 /* We have fully parsed the FOR operands. Now build the loop. */
6850 n = push_mri_control (mri_for);
6851
6852 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6853
6854 /* Move init,var. */
6855 s = buf;
6856 *s++ = 'm';
6857 *s++ = 'o';
6858 *s++ = 'v';
6859 *s++ = 'e';
6860 if (qual != '\0')
6861 *s++ = TOLOWER (qual);
6862 *s++ = ' ';
6863 memcpy (s, initstart, initstop - initstart);
6864 s += initstop - initstart;
6865 *s++ = ',';
6866 memcpy (s, varstart, varstop - varstart);
6867 s += varstop - varstart;
6868 *s = '\0';
6869 mri_assemble (buf);
6870
6871 colon (n->top);
6872
6873 /* cmp end,var. */
6874 s = buf;
6875 *s++ = 'c';
6876 *s++ = 'm';
6877 *s++ = 'p';
6878 if (qual != '\0')
6879 *s++ = TOLOWER (qual);
6880 *s++ = ' ';
6881 memcpy (s, endstart, endstop - endstart);
6882 s += endstop - endstart;
6883 *s++ = ',';
6884 memcpy (s, varstart, varstop - varstart);
6885 s += varstop - varstart;
6886 *s = '\0';
6887 mri_assemble (buf);
6888
6889 /* bcc bottom. */
6890 ex[0] = TOLOWER (extent);
6891 ex[1] = '\0';
6892 if (up)
6893 sprintf (buf, "blt%s %s", ex, n->bottom);
6894 else
6895 sprintf (buf, "bgt%s %s", ex, n->bottom);
6896 mri_assemble (buf);
6897
6898 /* Put together the add or sub instruction used by ENDF. */
6899 s = buf;
6900 if (up)
6901 strcpy (s, "add");
6902 else
6903 strcpy (s, "sub");
6904 s += 3;
6905 if (qual != '\0')
6906 *s++ = TOLOWER (qual);
6907 *s++ = ' ';
6908 memcpy (s, bystart, bystop - bystart);
6909 s += bystop - bystart;
6910 *s++ = ',';
6911 memcpy (s, varstart, varstop - varstart);
6912 s += varstop - varstart;
6913 *s = '\0';
6914 n->incr = buf;
6915
6916 if (flag_mri)
6917 {
6918 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6919 ++input_line_pointer;
6920 }
6921
6922 demand_empty_rest_of_line ();
6923 }
6924
6925 /* Handle the MRI ENDF pseudo-op. */
6926
6927 static void
6928 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6929 {
6930 if (mri_control_stack == NULL
6931 || mri_control_stack->type != mri_for)
6932 {
6933 as_bad (_("endf without for"));
6934 ignore_rest_of_line ();
6935 return;
6936 }
6937
6938 colon (mri_control_stack->next);
6939
6940 mri_assemble (mri_control_stack->incr);
6941
6942 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6943 mri_assemble (mri_control_stack->incr);
6944
6945 free (mri_control_stack->incr);
6946
6947 colon (mri_control_stack->bottom);
6948
6949 pop_mri_control ();
6950
6951 if (flag_mri)
6952 {
6953 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6954 ++input_line_pointer;
6955 }
6956
6957 demand_empty_rest_of_line ();
6958 }
6959
6960 /* Handle the MRI REPEAT pseudo-op. */
6961
6962 static void
6963 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6964 {
6965 struct mri_control_info *n;
6966
6967 n = push_mri_control (mri_repeat);
6968 colon (n->top);
6969 if (flag_mri)
6970 {
6971 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6972 ++input_line_pointer;
6973 }
6974 demand_empty_rest_of_line ();
6975 }
6976
6977 /* Handle the MRI UNTIL pseudo-op. */
6978
6979 static void
6980 s_mri_until (int qual)
6981 {
6982 char *s;
6983
6984 if (mri_control_stack == NULL
6985 || mri_control_stack->type != mri_repeat)
6986 {
6987 as_bad (_("until without repeat"));
6988 ignore_rest_of_line ();
6989 return;
6990 }
6991
6992 colon (mri_control_stack->next);
6993
6994 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6995 ;
6996
6997 parse_mri_control_expression (s, qual, (const char *) NULL,
6998 mri_control_stack->top, '\0');
6999
7000 colon (mri_control_stack->bottom);
7001
7002 input_line_pointer = s;
7003
7004 pop_mri_control ();
7005
7006 if (flag_mri)
7007 {
7008 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7009 ++input_line_pointer;
7010 }
7011
7012 demand_empty_rest_of_line ();
7013 }
7014
7015 /* Handle the MRI WHILE pseudo-op. */
7016
7017 static void
7018 s_mri_while (int qual)
7019 {
7020 char *s;
7021
7022 struct mri_control_info *n;
7023
7024 s = input_line_pointer;
7025 /* We only accept '*' as introduction of comments if preceded by white space
7026 or at first column of a line (I think this can't actually happen here?)
7027 This is important when assembling:
7028 while d0 <ne> 12(a0,d0*2) do
7029 while d0 <ne> #CONST*20 do. */
7030 while (! (is_end_of_line[(unsigned char) *s]
7031 || (flag_mri
7032 && *s == '*'
7033 && (s == input_line_pointer
7034 || *(s-1) == ' '
7035 || *(s-1) == '\t'))))
7036 s++;
7037 --s;
7038 while (*s == ' ' || *s == '\t')
7039 --s;
7040 if (s - input_line_pointer > 1
7041 && s[-1] == '.')
7042 s -= 2;
7043 if (s - input_line_pointer < 2
7044 || strncasecmp (s - 1, "DO", 2) != 0)
7045 {
7046 as_bad (_("missing do"));
7047 ignore_rest_of_line ();
7048 return;
7049 }
7050
7051 n = push_mri_control (mri_while);
7052
7053 colon (n->next);
7054
7055 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7056 s[1] == '.' ? s[2] : '\0');
7057
7058 input_line_pointer = s + 1;
7059 if (*input_line_pointer == '.')
7060 input_line_pointer += 2;
7061
7062 if (flag_mri)
7063 {
7064 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7065 ++input_line_pointer;
7066 }
7067
7068 demand_empty_rest_of_line ();
7069 }
7070
7071 /* Handle the MRI ENDW pseudo-op. */
7072
7073 static void
7074 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7075 {
7076 char *buf;
7077
7078 if (mri_control_stack == NULL
7079 || mri_control_stack->type != mri_while)
7080 {
7081 as_bad (_("endw without while"));
7082 ignore_rest_of_line ();
7083 return;
7084 }
7085
7086 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7087 sprintf (buf, "bra %s", mri_control_stack->next);
7088 mri_assemble (buf);
7089 free (buf);
7090
7091 colon (mri_control_stack->bottom);
7092
7093 pop_mri_control ();
7094
7095 if (flag_mri)
7096 {
7097 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7098 ++input_line_pointer;
7099 }
7100
7101 demand_empty_rest_of_line ();
7102 }
7103 \f
7104 /* Parse a .cpu directive. */
7105
7106 static void
7107 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7108 {
7109 char saved_char;
7110 char *name;
7111
7112 if (initialized)
7113 {
7114 as_bad (_("already assembled instructions"));
7115 ignore_rest_of_line ();
7116 return;
7117 }
7118
7119 name = input_line_pointer;
7120 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7121 input_line_pointer++;
7122 saved_char = *input_line_pointer;
7123 *input_line_pointer = 0;
7124
7125 m68k_set_cpu (name, 1, 0);
7126
7127 *input_line_pointer = saved_char;
7128 demand_empty_rest_of_line ();
7129 return;
7130 }
7131
7132 /* Parse a .arch directive. */
7133
7134 static void
7135 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7136 {
7137 char saved_char;
7138 char *name;
7139
7140 if (initialized)
7141 {
7142 as_bad (_("already assembled instructions"));
7143 ignore_rest_of_line ();
7144 return;
7145 }
7146
7147 name = input_line_pointer;
7148 while (*input_line_pointer && *input_line_pointer != ','
7149 && !ISSPACE (*input_line_pointer))
7150 input_line_pointer++;
7151 saved_char = *input_line_pointer;
7152 *input_line_pointer = 0;
7153
7154 if (m68k_set_arch (name, 1, 0))
7155 {
7156 /* Scan extensions. */
7157 do
7158 {
7159 *input_line_pointer++ = saved_char;
7160 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7161 break;
7162 name = input_line_pointer;
7163 while (*input_line_pointer && *input_line_pointer != ','
7164 && !ISSPACE (*input_line_pointer))
7165 input_line_pointer++;
7166 saved_char = *input_line_pointer;
7167 *input_line_pointer = 0;
7168 }
7169 while (m68k_set_extension (name, 1, 0));
7170 }
7171
7172 *input_line_pointer = saved_char;
7173 demand_empty_rest_of_line ();
7174 return;
7175 }
7176 \f
7177 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7178 if none is found, the caller is responsible for emitting an error
7179 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7180 cpu name, if it begins with a '6' (possibly skipping an intervening
7181 'c'. We also allow a 'c' in the same place. if NEGATED is
7182 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7183 the option is indeed negated. */
7184
7185 static const struct m68k_cpu *
7186 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7187 int allow_m, int *negated)
7188 {
7189 /* allow negated value? */
7190 if (negated)
7191 {
7192 *negated = 0;
7193
7194 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7195 {
7196 arg += 3;
7197 *negated = 1;
7198 }
7199 }
7200
7201 /* Remove 'm' or 'mc' prefix from 68k variants. */
7202 if (allow_m)
7203 {
7204 if (arg[0] == 'm')
7205 {
7206 if (arg[1] == '6')
7207 arg += 1;
7208 else if (arg[1] == 'c' && arg[2] == '6')
7209 arg += 2;
7210 }
7211 }
7212 else if (arg[0] == 'c' && arg[1] == '6')
7213 arg += 1;
7214
7215 for (; table->name; table++)
7216 if (!strcmp (arg, table->name))
7217 {
7218 if (table->alias < -1 || table->alias > 1)
7219 as_bad (_("`%s' is deprecated, use `%s'"),
7220 table->name, table[table->alias < 0 ? 1 : -1].name);
7221 return table;
7222 }
7223 return 0;
7224 }
7225
7226 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7227
7228 static int
7229 m68k_set_cpu (char const *name, int allow_m, int silent)
7230 {
7231 const struct m68k_cpu *cpu;
7232
7233 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7234
7235 if (!cpu)
7236 {
7237 if (!silent)
7238 as_bad (_("cpu `%s' unrecognized"), name);
7239 return 0;
7240 }
7241
7242 if (selected_cpu && selected_cpu != cpu)
7243 {
7244 as_bad (_("already selected `%s' processor"),
7245 selected_cpu->name);
7246 return 0;
7247 }
7248 selected_cpu = cpu;
7249 return 1;
7250 }
7251
7252 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7253
7254 static int
7255 m68k_set_arch (char const *name, int allow_m, int silent)
7256 {
7257 const struct m68k_cpu *arch;
7258
7259 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7260
7261 if (!arch)
7262 {
7263 if (!silent)
7264 as_bad (_("architecture `%s' unrecognized"), name);
7265 return 0;
7266 }
7267
7268 if (selected_arch && selected_arch != arch)
7269 {
7270 as_bad (_("already selected `%s' architecture"),
7271 selected_arch->name);
7272 return 0;
7273 }
7274
7275 selected_arch = arch;
7276 return 1;
7277 }
7278
7279 /* Set the architecture extension, issuing errors if it is
7280 unrecognized, or invalid */
7281
7282 static int
7283 m68k_set_extension (char const *name, int allow_m, int silent)
7284 {
7285 int negated;
7286 const struct m68k_cpu *ext;
7287
7288 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7289
7290 if (!ext)
7291 {
7292 if (!silent)
7293 as_bad (_("extension `%s' unrecognized"), name);
7294 return 0;
7295 }
7296
7297 if (negated)
7298 not_current_architecture |= ext->arch;
7299 else
7300 current_architecture |= ext->arch;
7301 return 1;
7302 }
7303
7304 /* md_parse_option
7305 Invocation line includes a switch not recognized by the base assembler.
7306 */
7307
7308 #ifdef OBJ_ELF
7309 const char *md_shortopts = "lSA:m:kQ:V";
7310 #else
7311 const char *md_shortopts = "lSA:m:k";
7312 #endif
7313
7314 struct option md_longopts[] = {
7315 #define OPTION_PIC (OPTION_MD_BASE)
7316 {"pic", no_argument, NULL, OPTION_PIC},
7317 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7318 {"register-prefix-optional", no_argument, NULL,
7319 OPTION_REGISTER_PREFIX_OPTIONAL},
7320 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7321 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7322 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7323 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7324 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7325 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7326 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7327 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7328 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7329 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7330 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7331 {"pcrel", no_argument, NULL, OPTION_PCREL},
7332 {NULL, no_argument, NULL, 0}
7333 };
7334 size_t md_longopts_size = sizeof (md_longopts);
7335
7336 int
7337 md_parse_option (int c, char *arg)
7338 {
7339 switch (c)
7340 {
7341 case 'l': /* -l means keep external to 2 bit offset
7342 rather than 16 bit one. */
7343 flag_short_refs = 1;
7344 break;
7345
7346 case 'S': /* -S means that jbsr's always turn into
7347 jsr's. */
7348 flag_long_jumps = 1;
7349 break;
7350
7351 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7352 branches into absolute jumps. */
7353 flag_keep_pcrel = 1;
7354 break;
7355
7356 case OPTION_PIC:
7357 case 'k':
7358 flag_want_pic = 1;
7359 break; /* -pic, Position Independent Code. */
7360
7361 case OPTION_REGISTER_PREFIX_OPTIONAL:
7362 flag_reg_prefix_optional = 1;
7363 reg_prefix_optional_seen = 1;
7364 break;
7365
7366 /* -V: SVR4 argument to print version ID. */
7367 case 'V':
7368 print_version_id ();
7369 break;
7370
7371 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7372 should be emitted or not. FIXME: Not implemented. */
7373 case 'Q':
7374 break;
7375
7376 case OPTION_BITWISE_OR:
7377 {
7378 char *n, *t;
7379 const char *s;
7380
7381 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7382 t = n;
7383 for (s = m68k_comment_chars; *s != '\0'; s++)
7384 if (*s != '|')
7385 *t++ = *s;
7386 *t = '\0';
7387 m68k_comment_chars = n;
7388 }
7389 break;
7390
7391 case OPTION_BASE_SIZE_DEFAULT_16:
7392 m68k_index_width_default = SIZE_WORD;
7393 break;
7394
7395 case OPTION_BASE_SIZE_DEFAULT_32:
7396 m68k_index_width_default = SIZE_LONG;
7397 break;
7398
7399 case OPTION_DISP_SIZE_DEFAULT_16:
7400 m68k_rel32 = 0;
7401 m68k_rel32_from_cmdline = 1;
7402 break;
7403
7404 case OPTION_DISP_SIZE_DEFAULT_32:
7405 m68k_rel32 = 1;
7406 m68k_rel32_from_cmdline = 1;
7407 break;
7408
7409 case 'A':
7410 #if WARN_DEPRECATED
7411 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7412 arg, arg));
7413 #endif
7414 /* Intentional fall-through. */
7415 case 'm':
7416 if (!strncmp (arg, "arch=", 5))
7417 m68k_set_arch (arg + 5, 1, 0);
7418 else if (!strncmp (arg, "cpu=", 4))
7419 m68k_set_cpu (arg + 4, 1, 0);
7420 else if (m68k_set_extension (arg, 0, 1))
7421 ;
7422 else if (m68k_set_arch (arg, 0, 1))
7423 ;
7424 else if (m68k_set_cpu (arg, 0, 1))
7425 ;
7426 else
7427 return 0;
7428 break;
7429
7430 default:
7431 return 0;
7432 }
7433
7434 return 1;
7435 }
7436
7437 /* Setup tables from the selected arch and/or cpu */
7438
7439 static void
7440 m68k_init_arch (void)
7441 {
7442 if (not_current_architecture & current_architecture)
7443 {
7444 as_bad (_("architecture features both enabled and disabled"));
7445 not_current_architecture &= ~current_architecture;
7446 }
7447 if (selected_arch)
7448 {
7449 current_architecture |= selected_arch->arch;
7450 control_regs = selected_arch->control_regs;
7451 }
7452 else
7453 current_architecture |= selected_cpu->arch;
7454
7455 current_architecture &= ~not_current_architecture;
7456
7457 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7458 {
7459 /* Determine which float is really meant. */
7460 if (current_architecture & (m68k_mask & ~m68881))
7461 current_architecture ^= cfloat;
7462 else
7463 current_architecture ^= m68881;
7464 }
7465
7466 if (selected_cpu)
7467 {
7468 control_regs = selected_cpu->control_regs;
7469 if (current_architecture & ~selected_cpu->arch)
7470 {
7471 as_bad (_("selected processor does not have all features of selected architecture"));
7472 current_architecture
7473 = selected_cpu->arch & ~not_current_architecture;
7474 }
7475 }
7476
7477 if ((current_architecture & m68k_mask)
7478 && (current_architecture & ~m68k_mask))
7479 {
7480 as_bad (_ ("m68k and cf features both selected"));
7481 if (current_architecture & m68k_mask)
7482 current_architecture &= m68k_mask;
7483 else
7484 current_architecture &= ~m68k_mask;
7485 }
7486
7487 /* Permit m68881 specification with all cpus; those that can't work
7488 with a coprocessor could be doing emulation. */
7489 if (current_architecture & m68851)
7490 {
7491 if (current_architecture & m68040)
7492 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7493 }
7494 /* What other incompatibilities could we check for? */
7495
7496 if (cpu_of_arch (current_architecture) < m68020
7497 || arch_coldfire_p (current_architecture))
7498 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7499
7500 initialized = 1;
7501 }
7502
7503 void
7504 md_show_usage (FILE *stream)
7505 {
7506 const char *default_cpu = TARGET_CPU;
7507 int i;
7508 unsigned int default_arch;
7509
7510 /* Get the canonical name for the default target CPU. */
7511 if (*default_cpu == 'm')
7512 default_cpu++;
7513 for (i = 0; m68k_cpus[i].name; i++)
7514 {
7515 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7516 {
7517 default_arch = m68k_cpus[i].arch;
7518 while (m68k_cpus[i].alias > 0)
7519 i--;
7520 while (m68k_cpus[i].alias < 0)
7521 i++;
7522 default_cpu = m68k_cpus[i].name;
7523 }
7524 }
7525
7526 fprintf (stream, _("\
7527 -march=<arch> set architecture\n\
7528 -mcpu=<cpu> set cpu [default %s]\n\
7529 "), default_cpu);
7530 for (i = 0; m68k_extensions[i].name; i++)
7531 fprintf (stream, _("\
7532 -m[no-]%-16s enable/disable%s architecture extension\n\
7533 "), m68k_extensions[i].name,
7534 m68k_extensions[i].alias > 0 ? " ColdFire"
7535 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7536
7537 fprintf (stream, _("\
7538 -l use 1 word for refs to undefined symbols [default 2]\n\
7539 -pic, -k generate position independent code\n\
7540 -S turn jbsr into jsr\n\
7541 --pcrel never turn PC-relative branches into absolute jumps\n\
7542 --register-prefix-optional\n\
7543 recognize register names without prefix character\n\
7544 --bitwise-or do not treat `|' as a comment character\n\
7545 --base-size-default-16 base reg without size is 16 bits\n\
7546 --base-size-default-32 base reg without size is 32 bits (default)\n\
7547 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7548 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7549 "));
7550
7551 fprintf (stream, _("Architecture variants are: "));
7552 for (i = 0; m68k_archs[i].name; i++)
7553 {
7554 if (i)
7555 fprintf (stream, " | ");
7556 fprintf (stream, m68k_archs[i].name);
7557 }
7558 fprintf (stream, "\n");
7559
7560 fprintf (stream, _("Processor variants are: "));
7561 for (i = 0; m68k_cpus[i].name; i++)
7562 {
7563 if (i)
7564 fprintf (stream, " | ");
7565 fprintf (stream, m68k_cpus[i].name);
7566 }
7567 fprintf (stream, _("\n"));
7568 }
7569 \f
7570 #ifdef TEST2
7571
7572 /* TEST2: Test md_assemble() */
7573 /* Warning, this routine probably doesn't work anymore. */
7574 int
7575 main (void)
7576 {
7577 struct m68k_it the_ins;
7578 char buf[120];
7579 char *cp;
7580 int n;
7581
7582 m68k_ip_begin ();
7583 for (;;)
7584 {
7585 if (!gets (buf) || !*buf)
7586 break;
7587 if (buf[0] == '|' || buf[1] == '.')
7588 continue;
7589 for (cp = buf; *cp; cp++)
7590 if (*cp == '\t')
7591 *cp = ' ';
7592 if (is_label (buf))
7593 continue;
7594 memset (&the_ins, '\0', sizeof (the_ins));
7595 m68k_ip (&the_ins, buf);
7596 if (the_ins.error)
7597 {
7598 printf (_("Error %s in %s\n"), the_ins.error, buf);
7599 }
7600 else
7601 {
7602 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7603 for (n = 0; n < the_ins.numo; n++)
7604 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7605 printf (" ");
7606 print_the_insn (&the_ins.opcode[0], stdout);
7607 (void) putchar ('\n');
7608 }
7609 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7610 {
7611 if (the_ins.operands[n].error)
7612 {
7613 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7614 continue;
7615 }
7616 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7617 the_ins.operands[n].reg);
7618 if (the_ins.operands[n].b_const)
7619 printf ("Constant: '%.*s', ",
7620 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7621 the_ins.operands[n].b_const);
7622 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7623 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7624 if (the_ins.operands[n].b_iadd)
7625 printf ("Iadd: '%.*s',",
7626 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7627 the_ins.operands[n].b_iadd);
7628 putchar ('\n');
7629 }
7630 }
7631 m68k_ip_end ();
7632 return 0;
7633 }
7634
7635 int
7636 is_label (char *str)
7637 {
7638 while (*str == ' ')
7639 str++;
7640 while (*str && *str != ' ')
7641 str++;
7642 if (str[-1] == ':' || str[1] == '=')
7643 return 1;
7644 return 0;
7645 }
7646
7647 #endif
7648
7649 /* Possible states for relaxation:
7650
7651 0 0 branch offset byte (bra, etc)
7652 0 1 word
7653 0 2 long
7654
7655 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7656 1 1 word
7657 1 2 long
7658
7659 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7660 2 1 word-long
7661 2 2 long-word
7662 2 3 long-long
7663
7664 */
7665
7666 /* We have no need to default values of symbols. */
7667
7668 symbolS *
7669 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7670 {
7671 return 0;
7672 }
7673
7674 /* Round up a section size to the appropriate boundary. */
7675 valueT
7676 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7677 {
7678 #ifdef OBJ_AOUT
7679 /* For a.out, force the section size to be aligned. If we don't do
7680 this, BFD will align it for us, but it will not write out the
7681 final bytes of the section. This may be a bug in BFD, but it is
7682 easier to fix it here since that is how the other a.out targets
7683 work. */
7684 int align;
7685
7686 align = bfd_get_section_alignment (stdoutput, segment);
7687 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7688 #endif
7689
7690 return size;
7691 }
7692
7693 /* Exactly what point is a PC-relative offset relative TO?
7694 On the 68k, it is relative to the address of the first extension
7695 word. The difference between the addresses of the offset and the
7696 first extension word is stored in fx_pcrel_adjust. */
7697 long
7698 md_pcrel_from (fixS *fixP)
7699 {
7700 int adjust;
7701
7702 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7703 sign extend the value here. */
7704 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7705 if (adjust == 64)
7706 adjust = -1;
7707 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7708 }
7709
7710 #ifdef OBJ_ELF
7711 void
7712 m68k_elf_final_processing (void)
7713 {
7714 unsigned flags = 0;
7715
7716 if (arch_coldfire_fpu (current_architecture))
7717 flags |= EF_M68K_CFV4E;
7718 /* Set file-specific flags if this is a cpu32 processor. */
7719 if (cpu_of_arch (current_architecture) & cpu32)
7720 flags |= EF_M68K_CPU32;
7721 else if (cpu_of_arch (current_architecture) & fido_a)
7722 flags |= EF_M68K_FIDO;
7723 else if ((cpu_of_arch (current_architecture) & m68000up)
7724 && !(cpu_of_arch (current_architecture) & m68020up))
7725 flags |= EF_M68K_M68000;
7726
7727 if (current_architecture & mcfisa_a)
7728 {
7729 static const unsigned isa_features[][2] =
7730 {
7731 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7732 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7733 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7734 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7735 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7736 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7737 {0,0},
7738 };
7739 static const unsigned mac_features[][2] =
7740 {
7741 {EF_M68K_CF_MAC, mcfmac},
7742 {EF_M68K_CF_EMAC, mcfemac},
7743 {0,0},
7744 };
7745 unsigned ix;
7746 unsigned pattern;
7747
7748 pattern = (current_architecture
7749 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7750 for (ix = 0; isa_features[ix][1]; ix++)
7751 {
7752 if (pattern == isa_features[ix][1])
7753 {
7754 flags |= isa_features[ix][0];
7755 break;
7756 }
7757 }
7758 if (!isa_features[ix][1])
7759 {
7760 cf_bad:
7761 as_warn (_("Not a defined coldfire architecture"));
7762 }
7763 else
7764 {
7765 if (current_architecture & cfloat)
7766 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7767
7768 pattern = current_architecture & (mcfmac|mcfemac);
7769 if (pattern)
7770 {
7771 for (ix = 0; mac_features[ix][1]; ix++)
7772 {
7773 if (pattern == mac_features[ix][1])
7774 {
7775 flags |= mac_features[ix][0];
7776 break;
7777 }
7778 }
7779 if (!mac_features[ix][1])
7780 goto cf_bad;
7781 }
7782 }
7783 }
7784 elf_elfheader (stdoutput)->e_flags |= flags;
7785 }
7786 #endif
7787
7788 int
7789 tc_m68k_regname_to_dw2regnum (char *regname)
7790 {
7791 unsigned int regnum;
7792 static const char *const regnames[] =
7793 {
7794 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7795 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7796 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7797 "pc"
7798 };
7799
7800 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7801 if (strcmp (regname, regnames[regnum]) == 0)
7802 return regnum;
7803
7804 return -1;
7805 }
7806
7807 void
7808 tc_m68k_frame_initial_instructions (void)
7809 {
7810 static int sp_regno = -1;
7811
7812 if (sp_regno < 0)
7813 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7814
7815 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7816 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7817 }
binutils for building for Google Native Client (NaCl)