Import binutils 2.18
[nacl-binutils.git] / gas / config / tc-cr16.c
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1 /* tc-cr16.c -- Assembler code for the CR16 CPU core.
2 Copyright 2007 Free Software Foundation, Inc.
4 Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "dwarf2dbg.h"
26 #include "opcode/cr16.h"
27 #include "elf/cr16.h"
30 /* Word is considered here as a 16-bit unsigned short int. */
31 #define WORD_SHIFT 16
33 /* Register is 2-byte size. */
34 #define REG_SIZE 2
36 /* Maximum size of a single instruction (in words). */
37 #define INSN_MAX_SIZE 3
39 /* Maximum bits which may be set in a `mask16' operand. */
40 #define MAX_REGS_IN_MASK16 8
42 /* Assign a number NUM, shifted by SHIFT bytes, into a location
43 pointed by index BYTE of array 'output_opcode'. */
44 #define CR16_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT)
46 /* Operand errors. */
47 typedef enum
49 OP_LEGAL = 0, /* Legal operand. */
50 OP_OUT_OF_RANGE, /* Operand not within permitted range. */
51 OP_NOT_EVEN /* Operand is Odd number, should be even. */
53 op_err;
55 /* Opcode mnemonics hash table. */
56 static struct hash_control *cr16_inst_hash;
57 /* CR16 registers hash table. */
58 static struct hash_control *reg_hash;
59 /* CR16 register pair hash table. */
60 static struct hash_control *regp_hash;
61 /* CR16 processor registers hash table. */
62 static struct hash_control *preg_hash;
63 /* CR16 processor registers 32 bit hash table. */
64 static struct hash_control *pregp_hash;
65 /* Current instruction we're assembling. */
66 const inst *instruction;
69 static int code_label = 0;
71 /* Global variables. */
73 /* Array to hold an instruction encoding. */
74 long output_opcode[2];
76 /* Nonzero means a relocatable symbol. */
77 int relocatable;
79 /* A copy of the original instruction (used in error messages). */
80 char ins_parse[MAX_INST_LEN];
82 /* The current processed argument number. */
83 int cur_arg_num;
85 /* Generic assembler global variables which must be defined by all targets. */
87 /* Characters which always start a comment. */
88 const char comment_chars[] = "#";
90 /* Characters which start a comment at the beginning of a line. */
91 const char line_comment_chars[] = "#";
93 /* This array holds machine specific line separator characters. */
94 const char line_separator_chars[] = ";";
96 /* Chars that can be used to separate mant from exp in floating point nums. */
97 const char EXP_CHARS[] = "eE";
99 /* Chars that mean this number is a floating point constant as in 0f12.456 */
100 const char FLT_CHARS[] = "f'";
102 /* Target-specific multicharacter options, not const-declared at usage. */
103 const char *md_shortopts = "";
104 struct option md_longopts[] =
106 {NULL, no_argument, NULL, 0}
108 size_t md_longopts_size = sizeof (md_longopts);
110 static void
111 l_cons (int nbytes)
113 int c;
114 expressionS exp;
116 #ifdef md_flush_pending_output
117 md_flush_pending_output ();
118 #endif
120 if (is_it_end_of_statement ())
122 demand_empty_rest_of_line ();
123 return;
126 #ifdef TC_ADDRESS_BYTES
127 if (nbytes == 0)
128 nbytes = TC_ADDRESS_BYTES ();
129 #endif
131 #ifdef md_cons_align
132 md_cons_align (nbytes);
133 #endif
135 c = 0;
138 unsigned int bits_available = BITS_PER_CHAR * nbytes;
139 char *hold = input_line_pointer;
141 expression (&exp);
143 if (*input_line_pointer == ':')
145 /* Bitfields. */
146 long value = 0;
148 for (;;)
150 unsigned long width;
152 if (*input_line_pointer != ':')
154 input_line_pointer = hold;
155 break;
157 if (exp.X_op == O_absent)
159 as_warn (_("using a bit field width of zero"));
160 exp.X_add_number = 0;
161 exp.X_op = O_constant;
164 if (exp.X_op != O_constant)
166 *input_line_pointer = '\0';
167 as_bad (_("field width \"%s\" too complex for a bitfield"), hold);
168 *input_line_pointer = ':';
169 demand_empty_rest_of_line ();
170 return;
173 if ((width = exp.X_add_number) >
174 (unsigned int)(BITS_PER_CHAR * nbytes))
176 as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes));
177 width = BITS_PER_CHAR * nbytes;
178 } /* Too big. */
181 if (width > bits_available)
183 /* FIXME-SOMEDAY: backing up and reparsing is wasteful. */
184 input_line_pointer = hold;
185 exp.X_add_number = value;
186 break;
189 /* Skip ':'. */
190 hold = ++input_line_pointer;
192 expression (&exp);
193 if (exp.X_op != O_constant)
195 char cache = *input_line_pointer;
197 *input_line_pointer = '\0';
198 as_bad (_("field value \"%s\" too complex for a bitfield"), hold);
199 *input_line_pointer = cache;
200 demand_empty_rest_of_line ();
201 return;
204 value |= ((~(-1 << width) & exp.X_add_number)
205 << ((BITS_PER_CHAR * nbytes) - bits_available));
207 if ((bits_available -= width) == 0
208 || is_it_end_of_statement ()
209 || *input_line_pointer != ',')
210 break;
212 hold = ++input_line_pointer;
213 expression (&exp);
216 exp.X_add_number = value;
217 exp.X_op = O_constant;
218 exp.X_unsigned = 1;
221 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
222 code_label = 1;
223 emit_expr (&exp, (unsigned int) nbytes);
224 ++c;
225 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
227 input_line_pointer +=3;
228 break;
231 while ((*input_line_pointer++ == ','));
233 /* Put terminator back into stream. */
234 input_line_pointer--;
236 demand_empty_rest_of_line ();
240 /* This table describes all the machine specific pseudo-ops
241 the assembler has to support. The fields are:
242 *** Pseudo-op name without dot.
243 *** Function to call to execute this pseudo-op.
244 *** Integer arg to pass to the function. */
246 const pseudo_typeS md_pseudo_table[] =
248 /* In CR16 machine, align is in bytes (not a ptwo boundary). */
249 {"align", s_align_bytes, 0},
250 {"long", l_cons, 4 },
251 {0, 0, 0}
254 /* CR16 relaxation table. */
255 const relax_typeS md_relax_table[] =
257 /* bCC */
258 {0xfa, -0x100, 2, 1}, /* 8 */
259 {0xfffe, -0x10000, 4, 2}, /* 16 */
260 {0xfffffe, -0x1000000, 6, 0}, /* 24 */
263 /* Return the bit size for a given operand. */
265 static int
266 get_opbits (operand_type op)
268 if (op < MAX_OPRD)
269 return cr16_optab[op].bit_size;
271 return 0;
274 /* Return the argument type of a given operand. */
276 static argtype
277 get_optype (operand_type op)
279 if (op < MAX_OPRD)
280 return cr16_optab[op].arg_type;
281 else
282 return nullargs;
285 /* Return the flags of a given operand. */
287 static int
288 get_opflags (operand_type op)
290 if (op < MAX_OPRD)
291 return cr16_optab[op].flags;
293 return 0;
296 /* Get the cc code. */
298 static int
299 get_cc (char *cc_name)
301 unsigned int i;
303 for (i = 0; i < cr16_num_cc; i++)
304 if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0)
305 return i;
307 return -1;
310 /* Get the core processor register 'reg_name'. */
312 static reg
313 get_register (char *reg_name)
315 const reg_entry *reg;
317 reg = (const reg_entry *) hash_find (reg_hash, reg_name);
319 if (reg != NULL)
320 return reg->value.reg_val;
322 return nullregister;
324 /* Get the core processor register-pair 'reg_name'. */
326 static reg
327 get_register_pair (char *reg_name)
329 const reg_entry *reg;
330 char tmp_rp[16]="\0";
332 /* Add '(' and ')' to the reg pair, if its not present. */
333 if (reg_name[0] != '(')
335 tmp_rp[0] = '(';
336 strcat (tmp_rp, reg_name);
337 strcat (tmp_rp,")");
338 reg = (const reg_entry *) hash_find (regp_hash, tmp_rp);
340 else
341 reg = (const reg_entry *) hash_find (regp_hash, reg_name);
343 if (reg != NULL)
344 return reg->value.reg_val;
346 return nullregister;
349 /* Get the index register 'reg_name'. */
351 static reg
352 get_index_register (char *reg_name)
354 const reg_entry *reg;
356 reg = (const reg_entry *) hash_find (reg_hash, reg_name);
358 if ((reg != NULL)
359 && ((reg->value.reg_val == 12) || (reg->value.reg_val == 13)))
360 return reg->value.reg_val;
362 return nullregister;
364 /* Get the core processor index register-pair 'reg_name'. */
366 static reg
367 get_index_register_pair (char *reg_name)
369 const reg_entry *reg;
371 reg = (const reg_entry *) hash_find (regp_hash, reg_name);
373 if (reg != NULL)
375 if ((reg->value.reg_val != 1) || (reg->value.reg_val != 7)
376 || (reg->value.reg_val != 9) || (reg->value.reg_val > 10))
377 return reg->value.reg_val;
379 as_bad (_("Unknown register pair - index relative mode: `%d'"), reg->value.reg_val);
382 return nullregister;
385 /* Get the processor register 'preg_name'. */
387 static preg
388 get_pregister (char *preg_name)
390 const reg_entry *preg;
392 preg = (const reg_entry *) hash_find (preg_hash, preg_name);
394 if (preg != NULL)
395 return preg->value.preg_val;
397 return nullpregister;
400 /* Get the processor register 'preg_name 32 bit'. */
402 static preg
403 get_pregisterp (char *preg_name)
405 const reg_entry *preg;
407 preg = (const reg_entry *) hash_find (pregp_hash, preg_name);
409 if (preg != NULL)
410 return preg->value.preg_val;
412 return nullpregister;
416 /* Round up a section size to the appropriate boundary. */
418 valueT
419 md_section_align (segT seg, valueT val)
421 /* Round .text section to a multiple of 2. */
422 if (seg == text_section)
423 return (val + 1) & ~1;
424 return val;
427 /* Parse an operand that is machine-specific (remove '*'). */
429 void
430 md_operand (expressionS * exp)
432 char c = *input_line_pointer;
434 switch (c)
436 case '*':
437 input_line_pointer++;
438 expression (exp);
439 break;
440 default:
441 break;
445 /* Reset global variables before parsing a new instruction. */
447 static void
448 reset_vars (char *op)
450 cur_arg_num = relocatable = 0;
451 memset (& output_opcode, '\0', sizeof (output_opcode));
453 /* Save a copy of the original OP (used in error messages). */
454 strncpy (ins_parse, op, sizeof ins_parse - 1);
455 ins_parse [sizeof ins_parse - 1] = 0;
458 /* This macro decides whether a particular reloc is an entry in a
459 switch table. It is used when relaxing, because the linker needs
460 to know about all such entries so that it can adjust them if
461 necessary. */
463 #define SWITCH_TABLE(fix) \
464 ( (fix)->fx_addsy != NULL \
465 && (fix)->fx_subsy != NULL \
466 && S_GET_SEGMENT ((fix)->fx_addsy) == \
467 S_GET_SEGMENT ((fix)->fx_subsy) \
468 && S_GET_SEGMENT (fix->fx_addsy) != undefined_section \
469 && ( (fix)->fx_r_type == BFD_RELOC_CR16_NUM8 \
470 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16 \
471 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32 \
472 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a))
474 /* See whether we need to force a relocation into the output file.
475 This is used to force out switch and PC relative relocations when
476 relaxing. */
479 cr16_force_relocation (fixS *fix)
481 /* REVISIT: Check if the "SWITCH_TABLE (fix)" should be added
482 if (generic_force_reloc (fix) || SWITCH_TABLE (fix)) */
483 if (generic_force_reloc (fix))
484 return 1;
486 return 0;
489 /* Record a fixup for a cons expression. */
491 void
492 cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp)
494 int rtype;
495 switch (len)
497 default: rtype = BFD_RELOC_NONE; break;
498 case 1: rtype = BFD_RELOC_CR16_NUM8 ; break;
499 case 2: rtype = BFD_RELOC_CR16_NUM16; break;
500 case 4:
501 if (code_label)
503 rtype = BFD_RELOC_CR16_NUM32a;
504 code_label = 0;
506 else
507 rtype = BFD_RELOC_CR16_NUM32;
508 break;
511 fix_new_exp (frag, offset, len, exp, 0, rtype);
514 /* Generate a relocation entry for a fixup. */
516 arelent *
517 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
519 arelent * reloc;
521 reloc = xmalloc (sizeof (arelent));
522 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
523 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
524 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
525 reloc->addend = fixP->fx_offset;
527 if (fixP->fx_subsy != NULL)
529 if (SWITCH_TABLE (fixP))
531 /* Keep the current difference in the addend. */
532 reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
533 - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
535 switch (fixP->fx_r_type)
537 case BFD_RELOC_CR16_NUM8:
538 fixP->fx_r_type = BFD_RELOC_CR16_NUM8;
539 break;
540 case BFD_RELOC_CR16_NUM16:
541 fixP->fx_r_type = BFD_RELOC_CR16_NUM16;
542 break;
543 case BFD_RELOC_CR16_NUM32:
544 fixP->fx_r_type = BFD_RELOC_CR16_NUM32;
545 break;
546 case BFD_RELOC_CR16_NUM32a:
547 fixP->fx_r_type = BFD_RELOC_CR16_NUM32a;
548 break;
549 default:
550 abort ();
551 break;
554 else
556 /* We only resolve difference expressions in the same section. */
557 as_bad_where (fixP->fx_file, fixP->fx_line,
558 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
559 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
560 segment_name (fixP->fx_addsy
561 ? S_GET_SEGMENT (fixP->fx_addsy)
562 : absolute_section),
563 S_GET_NAME (fixP->fx_subsy),
564 segment_name (S_GET_SEGMENT (fixP->fx_addsy)));
568 assert ((int) fixP->fx_r_type > 0);
569 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
571 if (reloc->howto == NULL)
573 as_bad_where (fixP->fx_file, fixP->fx_line,
574 _("internal error: reloc %d (`%s') not supported by object file format"),
575 fixP->fx_r_type,
576 bfd_get_reloc_code_name (fixP->fx_r_type));
577 return NULL;
579 assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
581 return reloc;
584 /* Prepare machine-dependent frags for relaxation. */
587 md_estimate_size_before_relax (fragS *fragp, asection *seg)
589 /* If symbol is undefined or located in a different section,
590 select the largest supported relocation. */
591 relax_substateT subtype;
592 relax_substateT rlx_state[] = {0, 2};
594 for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
596 if (fragp->fr_subtype == rlx_state[subtype]
597 && (!S_IS_DEFINED (fragp->fr_symbol)
598 || seg != S_GET_SEGMENT (fragp->fr_symbol)))
600 fragp->fr_subtype = rlx_state[subtype + 1];
601 break;
605 if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
606 abort ();
608 return md_relax_table[fragp->fr_subtype].rlx_length;
611 void
612 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
614 /* 'opcode' points to the start of the instruction, whether
615 we need to change the instruction's fixed encoding. */
616 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
618 subseg_change (sec, 0);
620 fix_new (fragP, fragP->fr_fix,
621 bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
622 fragP->fr_symbol, fragP->fr_offset, 1, reloc);
623 fragP->fr_var = 0;
624 fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
627 /* Process machine-dependent command line options. Called once for
628 each option on the command line that the machine-independent part of
629 GAS does not understand. */
632 md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
634 return 0;
637 /* Machine-dependent usage-output. */
639 void
640 md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
642 return;
645 /* Turn a string in input_line_pointer into a floating point constant
646 of type TYPE, and store the appropriate bytes in *LITP. The number
647 of LITTLENUMS emitted is stored in *SIZEP. An error message is
648 returned, or NULL on OK. */
650 char *
651 md_atof (int type, char *litP, int *sizeP)
653 int prec;
654 int i;
655 LITTLENUM_TYPE words[4];
656 char *t;
658 switch (type)
660 case 'f':
661 prec = 2;
662 break;
664 case 'd':
665 prec = 4;
666 break;
668 default:
669 *sizeP = 0;
670 return _("bad call to md_atof");
673 t = atof_ieee (input_line_pointer, type, words);
674 if (t)
675 input_line_pointer = t;
677 *sizeP = prec * 2;
679 if (! target_big_endian)
681 for (i = prec - 1; i >= 0; i--)
683 md_number_to_chars (litP, (valueT) words[i], 2);
684 litP += 2;
687 else
689 for (i = 0; i < prec; i++)
691 md_number_to_chars (litP, (valueT) words[i], 2);
692 litP += 2;
696 return NULL;
699 /* Apply a fixS (fixup of an instruction or data that we didn't have
700 enough info to complete immediately) to the data in a frag.
701 Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
702 relaxation of debug sections, this function is called only when
703 fixuping relocations of debug sections. */
705 void
706 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
708 valueT val = * valP;
709 char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
710 fixP->fx_offset = 0;
712 switch (fixP->fx_r_type)
714 case BFD_RELOC_CR16_NUM8:
715 bfd_put_8 (stdoutput, (unsigned char) val, buf);
716 break;
717 case BFD_RELOC_CR16_NUM16:
718 bfd_put_16 (stdoutput, val, buf);
719 break;
720 case BFD_RELOC_CR16_NUM32:
721 bfd_put_32 (stdoutput, val, buf);
722 break;
723 case BFD_RELOC_CR16_NUM32a:
724 bfd_put_32 (stdoutput, val, buf);
725 break;
726 default:
727 /* We shouldn't ever get here because linkrelax is nonzero. */
728 abort ();
729 break;
732 fixP->fx_done = 0;
734 if (fixP->fx_addsy == NULL
735 && fixP->fx_pcrel == 0)
736 fixP->fx_done = 1;
738 if (fixP->fx_pcrel == 1
739 && fixP->fx_addsy != NULL
740 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
741 fixP->fx_done = 1;
744 /* The location from which a PC relative jump should be calculated,
745 given a PC relative reloc. */
747 long
748 md_pcrel_from (fixS *fixp)
750 return fixp->fx_frag->fr_address + fixp->fx_where;
753 static void
754 initialise_reg_hash_table (struct hash_control ** hash_table,
755 const reg_entry * register_table,
756 const unsigned int num_entries)
758 const reg_entry * reg;
759 const char *hashret;
761 if ((* hash_table = hash_new ()) == NULL)
762 as_fatal (_("Virtual memory exhausted"));
764 for (reg = register_table;
765 reg < (register_table + num_entries);
766 reg++)
768 hashret = hash_insert (* hash_table, reg->name, (char *) reg);
769 if (hashret)
770 as_fatal (_("Internal Error: Can't hash %s: %s"),
771 reg->name, hashret);
775 /* This function is called once, at assembler startup time. This should
776 set up all the tables, etc that the MD part of the assembler needs. */
778 void
779 md_begin (void)
781 int i = 0;
783 /* Set up a hash table for the instructions. */
784 if ((cr16_inst_hash = hash_new ()) == NULL)
785 as_fatal (_("Virtual memory exhausted"));
787 while (cr16_instruction[i].mnemonic != NULL)
789 const char *hashret;
790 const char *mnemonic = cr16_instruction[i].mnemonic;
792 hashret = hash_insert (cr16_inst_hash, mnemonic,
793 (char *)(cr16_instruction + i));
795 if (hashret != NULL && *hashret != '\0')
796 as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction[i].mnemonic,
797 *hashret == 0 ? _("(unknown reason)") : hashret);
799 /* Insert unique names into hash table. The CR16 instruction set
800 has many identical opcode names that have different opcodes based
801 on the operands. This hash table then provides a quick index to
802 the first opcode with a particular name in the opcode table. */
805 ++i;
807 while (cr16_instruction[i].mnemonic != NULL
808 && streq (cr16_instruction[i].mnemonic, mnemonic));
811 /* Initialize reg_hash hash table. */
812 initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS);
813 /* Initialize regp_hash hash table. */
814 initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS);
815 /* Initialize preg_hash hash table. */
816 initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS);
817 /* Initialize pregp_hash hash table. */
818 initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS);
820 /* Set linkrelax here to avoid fixups in most sections. */
821 linkrelax = 1;
824 /* Process constants (immediate/absolute)
825 and labels (jump targets/Memory locations). */
827 static void
828 process_label_constant (char *str, ins * cr16_ins)
830 char *saved_input_line_pointer;
831 int symbol_with_at = 0;
832 int symbol_with_s = 0;
833 int symbol_with_m = 0;
834 int symbol_with_l = 0;
835 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */
837 saved_input_line_pointer = input_line_pointer;
838 input_line_pointer = str;
840 expression (&cr16_ins->exp);
842 switch (cr16_ins->exp.X_op)
844 case O_big:
845 case O_absent:
846 /* Missing or bad expr becomes absolute 0. */
847 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
848 str);
849 cr16_ins->exp.X_op = O_constant;
850 cr16_ins->exp.X_add_number = 0;
851 cr16_ins->exp.X_add_symbol = NULL;
852 cr16_ins->exp.X_op_symbol = NULL;
853 /* Fall through. */
855 case O_constant:
856 cur_arg->X_op = O_constant;
857 cur_arg->constant = cr16_ins->exp.X_add_number;
858 break;
860 case O_symbol:
861 case O_subtract:
862 case O_add:
863 cur_arg->X_op = O_symbol;
864 cr16_ins->rtype = BFD_RELOC_NONE;
865 relocatable = 1;
867 if (strneq (input_line_pointer, "@c", 2))
868 symbol_with_at = 1;
870 if (strneq (input_line_pointer, "@l", 2)
871 || strneq (input_line_pointer, ":l", 2))
872 symbol_with_l = 1;
874 if (strneq (input_line_pointer, "@m", 2)
875 || strneq (input_line_pointer, ":m", 2))
876 symbol_with_m = 1;
878 if (strneq (input_line_pointer, "@s", 2)
879 || strneq (input_line_pointer, ":s", 2))
880 symbol_with_s = 1;
882 switch (cur_arg->type)
884 case arg_cr:
885 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
887 if (cur_arg->size == 20)
888 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
889 else
890 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
892 break;
894 case arg_crp:
895 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
896 switch (instruction->size)
898 case 1:
899 switch (cur_arg->size)
901 case 0:
902 cr16_ins->rtype = BFD_RELOC_CR16_REGREL0;
903 break;
904 case 4:
905 if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb"))
906 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4;
907 else
908 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a;
909 break;
910 default: break;
912 break;
913 case 2:
914 cr16_ins->rtype = BFD_RELOC_CR16_REGREL16;
915 break;
916 case 3:
917 if (cur_arg->size == 20)
918 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
919 else
920 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
921 break;
922 default:
923 break;
925 break;
927 case arg_idxr:
928 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
929 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
930 break;
932 case arg_idxrp:
933 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
934 switch (instruction->size)
936 case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break;
937 case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break;
938 case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break;
939 default: break;
941 break;
943 case arg_c:
944 if (IS_INSN_MNEMONIC ("bal"))
945 cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
946 else if (IS_INSN_TYPE (BRANCH_INS))
948 if (symbol_with_s)
949 cr16_ins->rtype = BFD_RELOC_CR16_DISP8;
950 else if (symbol_with_m)
951 cr16_ins->rtype = BFD_RELOC_CR16_DISP16;
952 else
953 cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
955 else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS)
956 || IS_INSN_TYPE (CSTBIT_INS))
958 if (symbol_with_s)
959 as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str);
960 if (symbol_with_m)
961 cr16_ins->rtype = BFD_RELOC_CR16_ABS20;
962 else /* Default to (symbol_with_l) */
963 cr16_ins->rtype = BFD_RELOC_CR16_ABS24;
965 else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
966 cr16_ins->rtype = BFD_RELOC_CR16_DISP4;
967 break;
969 case arg_ic:
970 if (IS_INSN_TYPE (ARITH_INS))
972 if (symbol_with_s)
973 cr16_ins->rtype = BFD_RELOC_CR16_IMM4;
974 else if (symbol_with_m)
975 cr16_ins->rtype = BFD_RELOC_CR16_IMM20;
976 else if (symbol_with_at)
977 cr16_ins->rtype = BFD_RELOC_CR16_IMM32a;
978 else /* Default to (symbol_with_l) */
979 cr16_ins->rtype = BFD_RELOC_CR16_IMM32;
981 else if (IS_INSN_TYPE (ARITH_BYTE_INS))
983 cr16_ins->rtype = BFD_RELOC_CR16_IMM16;
985 break;
986 default:
987 break;
989 break;
991 default:
992 cur_arg->X_op = cr16_ins->exp.X_op;
993 break;
996 input_line_pointer = saved_input_line_pointer;
997 return;
1000 /* Retrieve the opcode image of a given register.
1001 If the register is illegal for the current instruction,
1002 issue an error. */
1004 static int
1005 getreg_image (reg r)
1007 const reg_entry *reg;
1008 char *reg_name;
1009 int is_procreg = 0; /* Nonzero means argument should be processor reg. */
1011 /* Check whether the register is in registers table. */
1012 if (r < MAX_REG)
1013 reg = cr16_regtab + r;
1014 else /* Register not found. */
1016 as_bad (_("Unknown register: `%d'"), r);
1017 return 0;
1020 reg_name = reg->name;
1022 /* Issue a error message when register is illegal. */
1023 #define IMAGE_ERR \
1024 as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
1025 reg_name, ins_parse); \
1026 break;
1028 switch (reg->type)
1030 case CR16_R_REGTYPE:
1031 if (! is_procreg)
1032 return reg->image;
1033 else
1034 IMAGE_ERR;
1036 case CR16_P_REGTYPE:
1037 return reg->image;
1038 break;
1040 default:
1041 IMAGE_ERR;
1044 return 0;
1047 /* Parsing different types of operands
1048 -> constants Immediate/Absolute/Relative numbers
1049 -> Labels Relocatable symbols
1050 -> (reg pair base) Register pair base
1051 -> (rbase) Register base
1052 -> disp(rbase) Register relative
1053 -> [rinx]disp(reg pair) Register index with reg pair mode
1054 -> disp(rbase,ridx,scl) Register index mode. */
1056 static void
1057 set_operand (char *operand, ins * cr16_ins)
1059 char *operandS; /* Pointer to start of sub-opearand. */
1060 char *operandE; /* Pointer to end of sub-opearand. */
1062 argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */
1064 /* Initialize pointers. */
1065 operandS = operandE = operand;
1067 switch (cur_arg->type)
1069 case arg_ic: /* Case $0x18. */
1070 operandS++;
1071 case arg_c: /* Case 0x18. */
1072 /* Set constant. */
1073 process_label_constant (operandS, cr16_ins);
1075 if (cur_arg->type != arg_ic)
1076 cur_arg->type = arg_c;
1077 break;
1079 case arg_icr: /* Case $0x18(r1). */
1080 operandS++;
1081 case arg_cr: /* Case 0x18(r1). */
1082 /* Set displacement constant. */
1083 while (*operandE != '(')
1084 operandE++;
1085 *operandE = '\0';
1086 process_label_constant (operandS, cr16_ins);
1087 operandS = operandE;
1088 case arg_rbase: /* Case (r1) or (r1,r0). */
1089 operandS++;
1090 /* Set register base. */
1091 while (*operandE != ')')
1092 operandE++;
1093 *operandE = '\0';
1094 if ((cur_arg->r = get_register (operandS)) == nullregister)
1095 as_bad (_("Illegal register `%s' in Instruction `%s'"),
1096 operandS, ins_parse);
1098 /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */
1099 if ((cur_arg->type != arg_rbase)
1100 && ((getreg_image (cur_arg->r) == 12)
1101 || (getreg_image (cur_arg->r) == 13)
1102 || (getreg_image (cur_arg->r) == 14)
1103 || (getreg_image (cur_arg->r) == 15)))
1105 cur_arg->type = arg_crp;
1106 cur_arg->rp = cur_arg->r;
1108 break;
1110 case arg_crp: /* Case 0x18(r1,r0). */
1111 /* Set displacement constant. */
1112 while (*operandE != '(')
1113 operandE++;
1114 *operandE = '\0';
1115 process_label_constant (operandS, cr16_ins);
1116 operandS = operandE;
1117 operandS++;
1118 /* Set register pair base. */
1119 while (*operandE != ')')
1120 operandE++;
1121 *operandE = '\0';
1122 if ((cur_arg->rp = get_register_pair (operandS)) == nullregister)
1123 as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
1124 operandS, ins_parse);
1125 break;
1127 case arg_idxr:
1128 /* Set register pair base. */
1129 if ((strchr (operandS,'(') != NULL))
1131 while ((*operandE != '(') && (! ISSPACE (*operandE)))
1132 operandE++;
1133 if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister)
1134 as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
1135 operandS, ins_parse);
1136 *operandE++ = '\0';
1137 cur_arg->type = arg_idxrp;
1139 else
1140 cur_arg->rp = -1;
1142 operandE = operandS;
1143 /* Set displacement constant. */
1144 while (*operandE != ']')
1145 operandE++;
1146 process_label_constant (++operandE, cr16_ins);
1147 *operandE++ = '\0';
1148 operandE = operandS;
1150 /* Set index register . */
1151 operandS = strchr (operandE,'[');
1152 if (operandS != NULL)
1153 { /* Eliminate '[', detach from rest of operand. */
1154 *operandS++ = '\0';
1156 operandE = strchr (operandS, ']');
1158 if (operandE == NULL)
1159 as_bad (_("unmatched '['"));
1160 else
1161 { /* Eliminate ']' and make sure it was the last thing
1162 in the string. */
1163 *operandE = '\0';
1164 if (*(operandE + 1) != '\0')
1165 as_bad (_("garbage after index spec ignored"));
1169 if ((cur_arg->i_r = get_index_register (operandS)) == nullregister)
1170 as_bad (_("Illegal register `%s' in Instruction `%s'"),
1171 operandS, ins_parse);
1172 *operandE = '\0';
1173 *operandS = '\0';
1174 break;
1176 default:
1177 break;
1181 /* Parse a single operand.
1182 operand - Current operand to parse.
1183 cr16_ins - Current assembled instruction. */
1185 static void
1186 parse_operand (char *operand, ins * cr16_ins)
1188 int ret_val;
1189 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */
1191 /* Initialize the type to NULL before parsing. */
1192 cur_arg->type = nullargs;
1194 /* Check whether this is a condition code . */
1195 if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1))
1197 cur_arg->type = arg_cc;
1198 cur_arg->cc = ret_val;
1199 cur_arg->X_op = O_register;
1200 return;
1203 /* Check whether this is a general processor register. */
1204 if ((ret_val = get_register (operand)) != nullregister)
1206 cur_arg->type = arg_r;
1207 cur_arg->r = ret_val;
1208 cur_arg->X_op = 0;
1209 return;
1212 /* Check whether this is a general processor register pair. */
1213 if ((operand[0] == '(')
1214 && ((ret_val = get_register_pair (operand)) != nullregister))
1216 cur_arg->type = arg_rp;
1217 cur_arg->rp = ret_val;
1218 cur_arg->X_op = O_register;
1219 return;
1222 /* Check whether the operand is a processor register.
1223 For "lprd" and "sprd" instruction, only 32 bit
1224 processor registers used. */
1225 if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd")))
1226 && ((ret_val = get_pregister (operand)) != nullpregister))
1228 cur_arg->type = arg_pr;
1229 cur_arg->pr = ret_val;
1230 cur_arg->X_op = O_register;
1231 return;
1234 /* Check whether this is a processor register - 32 bit. */
1235 if ((ret_val = get_pregisterp (operand)) != nullpregister)
1237 cur_arg->type = arg_prp;
1238 cur_arg->prp = ret_val;
1239 cur_arg->X_op = O_register;
1240 return;
1243 /* Deal with special characters. */
1244 switch (operand[0])
1246 case '$':
1247 if (strchr (operand, '(') != NULL)
1248 cur_arg->type = arg_icr;
1249 else
1250 cur_arg->type = arg_ic;
1251 goto set_params;
1252 break;
1254 case '(':
1255 cur_arg->type = arg_rbase;
1256 goto set_params;
1257 break;
1259 case '[':
1260 cur_arg->type = arg_idxr;
1261 goto set_params;
1262 break;
1264 default:
1265 break;
1268 if (strchr (operand, '(') != NULL)
1270 if (strchr (operand, ',') != NULL
1271 && (strchr (operand, ',') > strchr (operand, '(')))
1272 cur_arg->type = arg_crp;
1273 else
1274 cur_arg->type = arg_cr;
1276 else
1277 cur_arg->type = arg_c;
1279 /* Parse an operand according to its type. */
1280 set_params:
1281 cur_arg->constant = 0;
1282 set_operand (operand, cr16_ins);
1285 /* Parse the various operands. Each operand is then analyzed to fillup
1286 the fields in the cr16_ins data structure. */
1288 static void
1289 parse_operands (ins * cr16_ins, char *operands)
1291 char *operandS; /* Operands string. */
1292 char *operandH, *operandT; /* Single operand head/tail pointers. */
1293 int allocated = 0; /* Indicates a new operands string was allocated.*/
1294 char *operand[MAX_OPERANDS];/* Separating the operands. */
1295 int op_num = 0; /* Current operand number we are parsing. */
1296 int bracket_flag = 0; /* Indicates a bracket '(' was found. */
1297 int sq_bracket_flag = 0; /* Indicates a square bracket '[' was found. */
1299 /* Preprocess the list of registers, if necessary. */
1300 operandS = operandH = operandT = operands;
1302 while (*operandT != '\0')
1304 if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
1306 *operandT++ = '\0';
1307 operand[op_num++] = strdup (operandH);
1308 operandH = operandT;
1309 continue;
1312 if (*operandT == ' ')
1313 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
1315 if (*operandT == '(')
1316 bracket_flag = 1;
1317 else if (*operandT == '[')
1318 sq_bracket_flag = 1;
1320 if (*operandT == ')')
1322 if (bracket_flag)
1323 bracket_flag = 0;
1324 else
1325 as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
1327 else if (*operandT == ']')
1329 if (sq_bracket_flag)
1330 sq_bracket_flag = 0;
1331 else
1332 as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
1335 if (bracket_flag == 1 && *operandT == ')')
1336 bracket_flag = 0;
1337 else if (sq_bracket_flag == 1 && *operandT == ']')
1338 sq_bracket_flag = 0;
1340 operandT++;
1343 /* Adding the last operand. */
1344 operand[op_num++] = strdup (operandH);
1345 cr16_ins->nargs = op_num;
1347 /* Verifying correct syntax of operands (all brackets should be closed). */
1348 if (bracket_flag || sq_bracket_flag)
1349 as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
1351 /* Now we parse each operand separately. */
1352 for (op_num = 0; op_num < cr16_ins->nargs; op_num++)
1354 cur_arg_num = op_num;
1355 parse_operand (operand[op_num], cr16_ins);
1356 free (operand[op_num]);
1359 if (allocated)
1360 free (operandS);
1363 /* Get the trap index in dispatch table, given its name.
1364 This routine is used by assembling the 'excp' instruction. */
1366 static int
1367 gettrap (char *s)
1369 const trap_entry *trap;
1371 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
1372 if (strcasecmp (trap->name, s) == 0)
1373 return trap->entry;
1375 /* To make compatable with CR16 4.1 tools, the below 3-lines of
1376 * code added. Refer: Development Tracker item #123 */
1377 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
1378 if (trap->entry == (unsigned int) atoi (s))
1379 return trap->entry;
1381 as_bad (_("Unknown exception: `%s'"), s);
1382 return 0;
1385 /* Top level module where instruction parsing starts.
1386 cr16_ins - data structure holds some information.
1387 operands - holds the operands part of the whole instruction. */
1389 static void
1390 parse_insn (ins *insn, char *operands)
1392 int i;
1394 /* Handle instructions with no operands. */
1395 for (i = 0; cr16_no_op_insn[i] != NULL; i++)
1397 if (streq (cr16_no_op_insn[i], instruction->mnemonic))
1399 insn->nargs = 0;
1400 return;
1404 /* Handle 'excp' instructions. */
1405 if (IS_INSN_MNEMONIC ("excp"))
1407 insn->nargs = 1;
1408 insn->arg[0].type = arg_ic;
1409 insn->arg[0].constant = gettrap (operands);
1410 insn->arg[0].X_op = O_constant;
1411 return;
1414 if (operands != NULL)
1415 parse_operands (insn, operands);
1418 /* bCC instruction requires special handling. */
1419 static char *
1420 get_b_cc (char * op)
1422 unsigned int i;
1423 char op1[5];
1425 for (i = 1; i < strlen (op); i++)
1426 op1[i-1] = op[i];
1428 op1[i-1] = '\0';
1430 for (i = 0; i < cr16_num_cc ; i++)
1431 if (streq (op1, cr16_b_cond_tab[i]))
1432 return (char *) cr16_b_cond_tab[i];
1434 return NULL;
1437 /* bCC instruction requires special handling. */
1438 static int
1439 is_bcc_insn (char * op)
1441 if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b")
1442 || streq (op, "beq0w") || streq (op, "bnq0w")))
1443 if ((op[0] == 'b') && (get_b_cc (op) != NULL))
1444 return 1;
1445 return 0;
1448 /* Cinv instruction requires special handling. */
1450 static int
1451 check_cinv_options (char * operand)
1453 char *p = operand;
1454 int i_used = 0, u_used = 0, d_used = 0;
1456 while (*++p != ']')
1458 if (*p == ',' || *p == ' ')
1459 continue;
1461 else if (*p == 'i')
1462 i_used = 1;
1463 else if (*p == 'u')
1464 u_used = 1;
1465 else if (*p == 'd')
1466 d_used = 1;
1467 else
1468 as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
1471 return 0;
1474 /* Retrieve the opcode image of a given register pair.
1475 If the register is illegal for the current instruction,
1476 issue an error. */
1478 static int
1479 getregp_image (reg r)
1481 const reg_entry *reg;
1482 char *reg_name;
1484 /* Check whether the register is in registers table. */
1485 if (r < MAX_REG)
1486 reg = cr16_regptab + r;
1487 /* Register not found. */
1488 else
1490 as_bad (_("Unknown register pair: `%d'"), r);
1491 return 0;
1494 reg_name = reg->name;
1496 /* Issue a error message when register pair is illegal. */
1497 #define RPAIR_IMAGE_ERR \
1498 as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \
1499 reg_name, ins_parse); \
1500 break;
1502 switch (reg->type)
1504 case CR16_RP_REGTYPE:
1505 return reg->image;
1506 default:
1507 RPAIR_IMAGE_ERR;
1510 return 0;
1513 /* Retrieve the opcode image of a given index register pair.
1514 If the register is illegal for the current instruction,
1515 issue an error. */
1517 static int
1518 getidxregp_image (reg r)
1520 const reg_entry *reg;
1521 char *reg_name;
1523 /* Check whether the register is in registers table. */
1524 if (r < MAX_REG)
1525 reg = cr16_regptab + r;
1526 /* Register not found. */
1527 else
1529 as_bad (_("Unknown register pair: `%d'"), r);
1530 return 0;
1533 reg_name = reg->name;
1535 /* Issue a error message when register pair is illegal. */
1536 #define IDX_RPAIR_IMAGE_ERR \
1537 as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \
1538 reg_name, ins_parse); \
1540 if (reg->type == CR16_RP_REGTYPE)
1542 switch (reg->image)
1544 case 0: return 0; break;
1545 case 2: return 1; break;
1546 case 4: return 2; break;
1547 case 6: return 3; break;
1548 case 8: return 4; break;
1549 case 10: return 5; break;
1550 case 3: return 6; break;
1551 case 5: return 7; break;
1552 default:
1553 break;
1557 IDX_RPAIR_IMAGE_ERR;
1558 return 0;
1561 /* Retrieve the opcode image of a given processort register.
1562 If the register is illegal for the current instruction,
1563 issue an error. */
1564 static int
1565 getprocreg_image (reg r)
1567 const reg_entry *reg;
1568 char *reg_name;
1570 /* Check whether the register is in registers table. */
1571 if (r < MAX_PREG)
1572 reg = &cr16_pregtab[r - MAX_REG];
1573 /* Register not found. */
1574 else
1576 as_bad (_("Unknown processor register : `%d'"), r);
1577 return 0;
1580 reg_name = reg->name;
1582 /* Issue a error message when register pair is illegal. */
1583 #define PROCREG_IMAGE_ERR \
1584 as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \
1585 reg_name, ins_parse); \
1586 break;
1588 switch (reg->type)
1590 case CR16_P_REGTYPE:
1591 return reg->image;
1592 default:
1593 PROCREG_IMAGE_ERR;
1596 return 0;
1599 /* Retrieve the opcode image of a given processort register.
1600 If the register is illegal for the current instruction,
1601 issue an error. */
1602 static int
1603 getprocregp_image (reg r)
1605 const reg_entry *reg;
1606 char *reg_name;
1607 int pregptab_disp = 0;
1609 /* Check whether the register is in registers table. */
1610 if (r < MAX_PREG)
1612 r = r - MAX_REG;
1613 switch (r)
1615 case 4: pregptab_disp = 1; break;
1616 case 6: pregptab_disp = 2; break;
1617 case 8:
1618 case 9:
1619 case 10:
1620 pregptab_disp = 3; break;
1621 case 12:
1622 pregptab_disp = 4; break;
1623 case 14:
1624 pregptab_disp = 5; break;
1625 default: break;
1627 reg = &cr16_pregptab[r - pregptab_disp];
1629 /* Register not found. */
1630 else
1632 as_bad (_("Unknown processor register (32 bit) : `%d'"), r);
1633 return 0;
1636 reg_name = reg->name;
1638 /* Issue a error message when register pair is illegal. */
1639 #define PROCREGP_IMAGE_ERR \
1640 as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\
1641 reg_name, ins_parse); \
1642 break;
1644 switch (reg->type)
1646 case CR16_P_REGTYPE:
1647 return reg->image;
1648 default:
1649 PROCREGP_IMAGE_ERR;
1652 return 0;
1655 /* Routine used to represent integer X using NBITS bits. */
1657 static long
1658 getconstant (long x, int nbits)
1660 /* The following expression avoids overflow if
1661 'nbits' is the number of bits in 'bfd_vma'. */
1662 return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1));
1665 /* Print a constant value to 'output_opcode':
1666 ARG holds the operand's type and value.
1667 SHIFT represents the location of the operand to be print into.
1668 NBITS determines the size (in bits) of the constant. */
1670 static void
1671 print_constant (int nbits, int shift, argument *arg)
1673 unsigned long mask = 0;
1675 long constant = getconstant (arg->constant, nbits);
1677 switch (nbits)
1679 case 32:
1680 case 28:
1681 /* mask the upper part of the constant, that is, the bits
1682 going to the lowest byte of output_opcode[0].
1683 The upper part of output_opcode[1] is always filled,
1684 therefore it is always masked with 0xFFFF. */
1685 mask = (1 << (nbits - 16)) - 1;
1686 /* Divide the constant between two consecutive words :
1687 0 1 2 3
1688 +---------+---------+---------+---------+
1689 | | X X X X | x X x X | |
1690 +---------+---------+---------+---------+
1691 output_opcode[0] output_opcode[1] */
1693 CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
1694 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
1695 break;
1697 case 21:
1698 if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) nbits = 20;
1699 case 24:
1700 case 22:
1701 case 20:
1702 /* mask the upper part of the constant, that is, the bits
1703 going to the lowest byte of output_opcode[0].
1704 The upper part of output_opcode[1] is always filled,
1705 therefore it is always masked with 0xFFFF. */
1706 mask = (1 << (nbits - 16)) - 1;
1707 /* Divide the constant between two consecutive words :
1708 0 1 2 3
1709 +---------+---------+---------+---------+
1710 | | X X X X | - X - X | |
1711 +---------+---------+---------+---------+
1712 output_opcode[0] output_opcode[1] */
1714 if ((instruction->size > 2) && (shift == WORD_SHIFT))
1716 if (arg->type == arg_idxrp)
1718 CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0);
1719 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
1721 else
1723 CR16_PRINT (0, (((((constant >> WORD_SHIFT) & mask) << 8) & 0x0f00) | ((((constant >> WORD_SHIFT) & mask) >> 4) & 0xf)),0);
1724 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
1727 else
1728 CR16_PRINT (0, constant, shift);
1729 break;
1731 case 14:
1732 if (arg->type == arg_idxrp)
1734 if (instruction->size == 2)
1736 CR16_PRINT (0, ((constant)&0xf), shift); // 0-3 bits
1737 CR16_PRINT (0, ((constant>>4)&0x3), (shift+20)); // 4-5 bits
1738 CR16_PRINT (0, ((constant>>6)&0x3), (shift+14)); // 6-7 bits
1739 CR16_PRINT (0, ((constant>>8)&0x3f), (shift+8)); // 8-13 bits
1741 else
1742 CR16_PRINT (0, constant, shift);
1744 break;
1746 case 16:
1747 case 12:
1748 /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
1749 always filling the upper part of output_opcode[1]. If we mistakenly
1750 write it to output_opcode[0], the constant prefix (that is, 'match')
1751 will be overriden.
1752 0 1 2 3
1753 +---------+---------+---------+---------+
1754 | 'match' | | X X X X | |
1755 +---------+---------+---------+---------+
1756 output_opcode[0] output_opcode[1] */
1758 if ((instruction->size > 2) && (shift == WORD_SHIFT))
1759 CR16_PRINT (1, constant, WORD_SHIFT);
1760 else
1761 CR16_PRINT (0, constant, shift);
1762 break;
1764 case 8:
1765 CR16_PRINT (0, ((constant/2)&0xf), shift);
1766 CR16_PRINT (0, ((constant/2)>>4), (shift+8));
1767 break;
1769 default:
1770 CR16_PRINT (0, constant, shift);
1771 break;
1775 /* Print an operand to 'output_opcode', which later on will be
1776 printed to the object file:
1777 ARG holds the operand's type, size and value.
1778 SHIFT represents the printing location of operand.
1779 NBITS determines the size (in bits) of a constant operand. */
1781 static void
1782 print_operand (int nbits, int shift, argument *arg)
1784 switch (arg->type)
1786 case arg_cc:
1787 CR16_PRINT (0, arg->cc, shift);
1788 break;
1790 case arg_r:
1791 CR16_PRINT (0, getreg_image (arg->r), shift);
1792 break;
1794 case arg_rp:
1795 CR16_PRINT (0, getregp_image (arg->rp), shift);
1796 break;
1798 case arg_pr:
1799 CR16_PRINT (0, getprocreg_image (arg->pr), shift);
1800 break;
1802 case arg_prp:
1803 CR16_PRINT (0, getprocregp_image (arg->prp), shift);
1804 break;
1806 case arg_idxrp:
1807 /* 16 12 8 6 0
1808 +-----------------------------+
1809 | r_index | disp | rp_base |
1810 +-----------------------------+ */
1812 if (instruction->size == 3)
1814 CR16_PRINT (0, getidxregp_image (arg->rp), 0);
1815 if (getreg_image (arg->i_r) == 12)
1816 CR16_PRINT (0, 0, 3);
1817 else
1818 CR16_PRINT (0, 1, 3);
1820 else
1822 CR16_PRINT (0, getidxregp_image (arg->rp), 16);
1823 if (getreg_image (arg->i_r) == 12)
1824 CR16_PRINT (0, 0, 19);
1825 else
1826 CR16_PRINT (0, 1, 19);
1828 print_constant (nbits, shift, arg);
1829 break;
1831 case arg_idxr:
1832 if (getreg_image (arg->i_r) == 12)
1833 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
1834 || IS_INSN_MNEMONIC ("tbitb"))
1835 CR16_PRINT (0, 0, 23);
1836 else CR16_PRINT (0, 0, 24);
1837 else
1838 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
1839 || IS_INSN_MNEMONIC ("tbitb"))
1840 CR16_PRINT (0, 1, 23);
1841 else CR16_PRINT (0, 1, 24);
1843 print_constant (nbits, shift, arg);
1844 break;
1846 case arg_ic:
1847 case arg_c:
1848 print_constant (nbits, shift, arg);
1849 break;
1851 case arg_rbase:
1852 CR16_PRINT (0, getreg_image (arg->r), shift);
1853 break;
1855 case arg_cr:
1856 print_constant (nbits, shift , arg);
1857 /* Add the register argument to the output_opcode. */
1858 CR16_PRINT (0, getreg_image (arg->r), (shift+16));
1859 break;
1861 case arg_crp:
1862 print_constant (nbits, shift , arg);
1863 if (instruction->size > 1)
1864 CR16_PRINT (0, getregp_image (arg->rp), (shift + 16));
1865 else if (IS_INSN_TYPE (LD_STOR_INS) || (IS_INSN_TYPE (CSTBIT_INS)))
1867 if (instruction->size == 2)
1868 CR16_PRINT (0, getregp_image (arg->rp), (shift - 8));
1869 else if (instruction->size == 1)
1870 CR16_PRINT (0, getregp_image (arg->rp), 16);
1872 else
1873 CR16_PRINT (0, getregp_image (arg->rp), shift);
1874 break;
1876 default:
1877 break;
1881 /* Retrieve the number of operands for the current assembled instruction. */
1883 static int
1884 get_number_of_operands (void)
1886 int i;
1888 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
1890 return i;
1893 /* Verify that the number NUM can be represented in BITS bits (that is,
1894 within its permitted range), based on the instruction's FLAGS.
1895 If UPDATE is nonzero, update the value of NUM if necessary.
1896 Return OP_LEGAL upon success, actual error type upon failure. */
1898 static op_err
1899 check_range (long *num, int bits, int unsigned flags, int update)
1901 long min, max;
1902 int retval = OP_LEGAL;
1903 long value = *num;
1905 if (bits == 0 && value > 0) return OP_OUT_OF_RANGE;
1907 /* For hosts witah longs bigger than 32-bits make sure that the top
1908 bits of a 32-bit negative value read in by the parser are set,
1909 so that the correct comparisons are made. */
1910 if (value & 0x80000000)
1911 value |= (-1L << 31);
1914 /* Verify operand value is even. */
1915 if (flags & OP_EVEN)
1917 if (value % 2)
1918 return OP_NOT_EVEN;
1921 if (flags & OP_DEC)
1923 value -= 1;
1924 if (update)
1925 *num = value;
1928 if (flags & OP_SHIFT)
1930 value >>= 1;
1931 if (update)
1932 *num = value;
1934 else if (flags & OP_SHIFT_DEC)
1936 value = (value >> 1) - 1;
1937 if (update)
1938 *num = value;
1941 if (flags & OP_ABS20)
1943 if (value > 0xEFFFF)
1944 return OP_OUT_OF_RANGE;
1947 if (flags & OP_ESC)
1949 if (value == 0xB || value == 0x9)
1950 return OP_OUT_OF_RANGE;
1951 else if (value == -1)
1953 if (update)
1954 *num = 9;
1955 return retval;
1959 if (flags & OP_ESC1)
1961 if (value > 13)
1962 return OP_OUT_OF_RANGE;
1965 if (flags & OP_SIGNED)
1967 max = (1 << (bits - 1)) - 1;
1968 min = - (1 << (bits - 1));
1969 if ((value > max) || (value < min))
1970 retval = OP_OUT_OF_RANGE;
1972 else if (flags & OP_UNSIGNED)
1974 max = ((((1 << (bits - 1)) - 1) << 1) | 1);
1975 min = 0;
1976 if (((unsigned long) value > (unsigned long) max)
1977 || ((unsigned long) value < (unsigned long) min))
1978 retval = OP_OUT_OF_RANGE;
1980 else if (flags & OP_NEG)
1982 max = - 1;
1983 min = - ((1 << (bits - 1))-1);
1984 if ((value > max) || (value < min))
1985 retval = OP_OUT_OF_RANGE;
1987 return retval;
1990 /* Bunch of error checkings.
1991 The checks are made after a matching instruction was found. */
1993 static void
1994 warn_if_needed (ins *insn)
1996 /* If the post-increment address mode is used and the load/store
1997 source register is the same as rbase, the result of the
1998 instruction is undefined. */
1999 if (IS_INSN_TYPE (LD_STOR_INS_INC))
2001 /* Enough to verify that one of the arguments is a simple reg. */
2002 if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
2003 if (insn->arg[0].r == insn->arg[1].r)
2004 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn->arg[0].r);
2007 if (IS_INSN_MNEMONIC ("pop")
2008 || IS_INSN_MNEMONIC ("push")
2009 || IS_INSN_MNEMONIC ("popret"))
2011 unsigned int count = insn->arg[0].constant, reg_val;
2013 /* Check if count operand caused to save/retrive the RA twice
2014 to generate warning message. */
2015 if (insn->nargs > 2)
2017 reg_val = getreg_image (insn->arg[1].r);
2019 if ( ((reg_val == 9) && (count > 7))
2020 || ((reg_val == 10) && (count > 6))
2021 || ((reg_val == 11) && (count > 5))
2022 || ((reg_val == 12) && (count > 4))
2023 || ((reg_val == 13) && (count > 2))
2024 || ((reg_val == 14) && (count > 0)))
2025 as_warn (_("RA register is saved twice."));
2027 /* Check if the third operand is "RA" or "ra" */
2028 if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA)))
2029 as_bad (_("`%s' Illegal use of registers."), ins_parse);
2032 if (insn->nargs > 1)
2034 reg_val = getreg_image (insn->arg[1].r);
2036 /* If register is a register pair ie r12/r13/r14 in operand1, then
2037 the count constant should be validated. */
2038 if (((reg_val == 11) && (count > 7))
2039 || ((reg_val == 12) && (count > 6))
2040 || ((reg_val == 13) && (count > 4))
2041 || ((reg_val == 14) && (count > 2))
2042 || ((reg_val == 15) && (count > 0)))
2043 as_bad (_("`%s' Illegal count-register combination."), ins_parse);
2045 else
2047 /* Check if the operand is "RA" or "ra" */
2048 if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA)))
2049 as_bad (_("`%s' Illegal use of register."), ins_parse);
2053 /* Some instruction assume the stack pointer as rptr operand.
2054 Issue an error when the register to be loaded is also SP. */
2055 if (instruction->flags & NO_SP)
2057 if (getreg_image (insn->arg[1].r) == getreg_image (sp))
2058 as_bad (_("`%s' has undefined result"), ins_parse);
2061 /* If the rptr register is specified as one of the registers to be loaded,
2062 the final contents of rptr are undefined. Thus, we issue an error. */
2063 if (instruction->flags & NO_RPTR)
2065 if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
2066 as_bad (_("Same src/dest register is used (`r%d'),result is undefined"),
2067 getreg_image (insn->arg[0].r));
2071 /* In some cases, we need to adjust the instruction pointer although a
2072 match was already found. Here, we gather all these cases.
2073 Returns 1 if instruction pointer was adjusted, otherwise 0. */
2075 static int
2076 adjust_if_needed (ins *insn ATTRIBUTE_UNUSED)
2078 int ret_value = 0;
2080 if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS)))
2082 if ((instruction->operands[0].op_type == abs24)
2083 && ((insn->arg[0].constant) > 0xF00000))
2085 insn->arg[0].constant &= 0xFFFFF;
2086 instruction--;
2087 ret_value = 1;
2091 return ret_value;
2094 /* Assemble a single instruction:
2095 INSN is already parsed (that is, all operand values and types are set).
2096 For instruction to be assembled, we need to find an appropriate template in
2097 the instruction table, meeting the following conditions:
2098 1: Has the same number of operands.
2099 2: Has the same operand types.
2100 3: Each operand size is sufficient to represent the instruction's values.
2101 Returns 1 upon success, 0 upon failure. */
2103 static int
2104 assemble_insn (char *mnemonic, ins *insn)
2106 /* Type of each operand in the current template. */
2107 argtype cur_type[MAX_OPERANDS];
2108 /* Size (in bits) of each operand in the current template. */
2109 unsigned int cur_size[MAX_OPERANDS];
2110 /* Flags of each operand in the current template. */
2111 unsigned int cur_flags[MAX_OPERANDS];
2112 /* Instruction type to match. */
2113 unsigned int ins_type;
2114 /* Boolean flag to mark whether a match was found. */
2115 int match = 0;
2116 int i;
2117 /* Nonzero if an instruction with same number of operands was found. */
2118 int found_same_number_of_operands = 0;
2119 /* Nonzero if an instruction with same argument types was found. */
2120 int found_same_argument_types = 0;
2121 /* Nonzero if a constant was found within the required range. */
2122 int found_const_within_range = 0;
2123 /* Argument number of an operand with invalid type. */
2124 int invalid_optype = -1;
2125 /* Argument number of an operand with invalid constant value. */
2126 int invalid_const = -1;
2127 /* Operand error (used for issuing various constant error messages). */
2128 op_err op_error, const_err = OP_LEGAL;
2130 /* Retrieve data (based on FUNC) for each operand of a given instruction. */
2131 #define GET_CURRENT_DATA(FUNC, ARRAY) \
2132 for (i = 0; i < insn->nargs; i++) \
2133 ARRAY[i] = FUNC (instruction->operands[i].op_type)
2135 #define GET_CURRENT_TYPE GET_CURRENT_DATA (get_optype, cur_type)
2136 #define GET_CURRENT_SIZE GET_CURRENT_DATA (get_opbits, cur_size)
2137 #define GET_CURRENT_FLAGS GET_CURRENT_DATA (get_opflags, cur_flags)
2139 /* Instruction has no operands -> only copy the constant opcode. */
2140 if (insn->nargs == 0)
2142 output_opcode[0] = BIN (instruction->match, instruction->match_bits);
2143 return 1;
2146 /* In some case, same mnemonic can appear with different instruction types.
2147 For example, 'storb' is supported with 3 different types :
2148 LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
2149 We assume that when reaching this point, the instruction type was
2150 pre-determined. We need to make sure that the type stays the same
2151 during a search for matching instruction. */
2152 ins_type = CR16_INS_TYPE (instruction->flags);
2154 while (/* Check that match is still not found. */
2155 match != 1
2156 /* Check we didn't get to end of table. */
2157 && instruction->mnemonic != NULL
2158 /* Check that the actual mnemonic is still available. */
2159 && IS_INSN_MNEMONIC (mnemonic)
2160 /* Check that the instruction type wasn't changed. */
2161 && IS_INSN_TYPE (ins_type))
2163 /* Check whether number of arguments is legal. */
2164 if (get_number_of_operands () != insn->nargs)
2165 goto next_insn;
2166 found_same_number_of_operands = 1;
2168 /* Initialize arrays with data of each operand in current template. */
2169 GET_CURRENT_TYPE;
2170 GET_CURRENT_SIZE;
2171 GET_CURRENT_FLAGS;
2173 /* Check for type compatibility. */
2174 for (i = 0; i < insn->nargs; i++)
2176 if (cur_type[i] != insn->arg[i].type)
2178 if (invalid_optype == -1)
2179 invalid_optype = i + 1;
2180 goto next_insn;
2183 found_same_argument_types = 1;
2185 for (i = 0; i < insn->nargs; i++)
2187 /* If 'bal' instruction size is '2' and reg operand is not 'ra'
2188 then goto next instruction. */
2189 if (IS_INSN_MNEMONIC ("bal") && (i == 0)
2190 && (instruction->size == 2) && (insn->arg[i].rp != 14))
2191 goto next_insn;
2193 /* If 'storb' instruction with 'sp' reg and 16-bit disp of
2194 * reg-pair, leads to undifined trap, so this should use
2195 * 20-bit disp of reg-pair. */
2196 if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
2197 && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
2198 goto next_insn;
2200 /* Only check range - don't update the constant's value, since the
2201 current instruction may not be the last we try to match.
2202 The constant's value will be updated later, right before printing
2203 it to the object file. */
2204 if ((insn->arg[i].X_op == O_constant)
2205 && (op_error = check_range (&insn->arg[i].constant, cur_size[i],
2206 cur_flags[i], 0)))
2208 if (invalid_const == -1)
2210 invalid_const = i + 1;
2211 const_err = op_error;
2213 goto next_insn;
2215 /* For symbols, we make sure the relocation size (which was already
2216 determined) is sufficient. */
2217 else if ((insn->arg[i].X_op == O_symbol)
2218 && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
2219 > cur_size[i]))
2220 goto next_insn;
2222 found_const_within_range = 1;
2224 /* If we got till here -> Full match is found. */
2225 match = 1;
2226 break;
2228 /* Try again with next instruction. */
2229 next_insn:
2230 instruction++;
2233 if (!match)
2235 /* We haven't found a match - instruction can't be assembled. */
2236 if (!found_same_number_of_operands)
2237 as_bad (_("Incorrect number of operands"));
2238 else if (!found_same_argument_types)
2239 as_bad (_("Illegal type of operand (arg %d)"), invalid_optype);
2240 else if (!found_const_within_range)
2242 switch (const_err)
2244 case OP_OUT_OF_RANGE:
2245 as_bad (_("Operand out of range (arg %d)"), invalid_const);
2246 break;
2247 case OP_NOT_EVEN:
2248 as_bad (_("Operand has odd displacement (arg %d)"), invalid_const);
2249 break;
2250 default:
2251 as_bad (_("Illegal operand (arg %d)"), invalid_const);
2252 break;
2256 return 0;
2258 else
2259 /* Full match - print the encoding to output file. */
2261 /* Make further checkings (such that couldn't be made earlier).
2262 Warn the user if necessary. */
2263 warn_if_needed (insn);
2265 /* Check whether we need to adjust the instruction pointer. */
2266 if (adjust_if_needed (insn))
2267 /* If instruction pointer was adjusted, we need to update
2268 the size of the current template operands. */
2269 GET_CURRENT_SIZE;
2271 for (i = 0; i < insn->nargs; i++)
2273 int j = instruction->flags & REVERSE_MATCH ?
2274 i == 0 ? 1 :
2275 i == 1 ? 0 : i :
2278 /* This time, update constant value before printing it. */
2279 if ((insn->arg[j].X_op == O_constant)
2280 && (check_range (&insn->arg[j].constant, cur_size[j],
2281 cur_flags[j], 1) != OP_LEGAL))
2282 as_fatal (_("Illegal operand (arg %d)"), j+1);
2285 /* First, copy the instruction's opcode. */
2286 output_opcode[0] = BIN (instruction->match, instruction->match_bits);
2288 for (i = 0; i < insn->nargs; i++)
2290 /* For BAL (ra),disp17 instuction only. And also set the
2291 DISP24a relocation type. */
2292 if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0)
2294 insn->rtype = BFD_RELOC_CR16_DISP24a;
2295 continue;
2297 cur_arg_num = i;
2298 print_operand (cur_size[i], instruction->operands[i].shift,
2299 &insn->arg[i]);
2303 return 1;
2306 /* Print the instruction.
2307 Handle also cases where the instruction is relaxable/relocatable. */
2309 static void
2310 print_insn (ins *insn)
2312 unsigned int i, j, insn_size;
2313 char *this_frag;
2314 unsigned short words[4];
2315 int addr_mod;
2317 /* Arrange the insn encodings in a WORD size array. */
2318 for (i = 0, j = 0; i < 2; i++)
2320 words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
2321 words[j++] = output_opcode[i] & 0xFFFF;
2324 insn_size = instruction->size;
2325 this_frag = frag_more (insn_size * 2);
2327 /* Handle relocation. */
2328 if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
2330 reloc_howto_type *reloc_howto;
2331 int size;
2333 reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
2335 if (!reloc_howto)
2336 abort ();
2338 size = bfd_get_reloc_size (reloc_howto);
2340 if (size < 1 || size > 4)
2341 abort ();
2343 fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
2344 size, &insn->exp, reloc_howto->pc_relative,
2345 insn->rtype);
2348 /* Verify a 2-byte code alignment. */
2349 addr_mod = frag_now_fix () & 1;
2350 if (frag_now->has_code && frag_now->insn_addr != addr_mod)
2351 as_bad (_("instruction address is not a multiple of 2"));
2352 frag_now->insn_addr = addr_mod;
2353 frag_now->has_code = 1;
2355 /* Write the instruction encoding to frag. */
2356 for (i = 0; i < insn_size; i++)
2358 md_number_to_chars (this_frag, (valueT) words[i], 2);
2359 this_frag += 2;
2363 /* This is the guts of the machine-dependent assembler. OP points to a
2364 machine dependent instruction. This function is supposed to emit
2365 the frags/bytes it assembles to. */
2367 void
2368 md_assemble (char *op)
2370 ins cr16_ins;
2371 char *param, param1[32];
2372 char c;
2374 /* Reset global variables for a new instruction. */
2375 reset_vars (op);
2377 /* Strip the mnemonic. */
2378 for (param = op; *param != 0 && !ISSPACE (*param); param++)
2380 c = *param;
2381 *param++ = '\0';
2383 /* bCC instuctions and adjust the mnemonic by adding extra white spaces. */
2384 if (is_bcc_insn (op))
2386 strcpy (param1, get_b_cc (op));
2387 op = "b";
2388 strcat (param1,",");
2389 strcat (param1, param);
2390 param = (char *) &param1;
2393 /* Checking the cinv options and adjust the mnemonic by removing the
2394 extra white spaces. */
2395 if (streq ("cinv", op))
2397 /* Validate the cinv options. */
2398 check_cinv_options (param);
2399 strcat (op, param);
2402 /* MAPPING - SHIFT INSN, if imm4/imm16 positive values
2403 lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
2404 as CR16 core doesn't support lsh[b/w] right shift operaions. */
2405 if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
2406 && (param [0] == '$'))
2408 strcpy (param1, param);
2409 /* Find the instruction. */
2410 instruction = (const inst *) hash_find (cr16_inst_hash, op);
2411 parse_operands (&cr16_ins, param1);
2412 if (((&cr16_ins)->arg[0].type == arg_ic)
2413 && ((&cr16_ins)->arg[0].constant >= 0))
2415 if (streq ("lshb", op))
2416 op = "ashub";
2417 else if (streq ("lshd", op))
2418 op = "ashud";
2419 else
2420 op = "ashuw";
2424 /* Find the instruction. */
2425 instruction = (const inst *) hash_find (cr16_inst_hash, op);
2426 if (instruction == NULL)
2428 as_bad (_("Unknown opcode: `%s'"), op);
2429 return;
2432 /* Tie dwarf2 debug info to the address at the start of the insn. */
2433 dwarf2_emit_insn (0);
2435 /* Parse the instruction's operands. */
2436 parse_insn (&cr16_ins, param);
2438 /* Assemble the instruction - return upon failure. */
2439 if (assemble_insn (op, &cr16_ins) == 0)
2440 return;
2442 /* Print the instruction. */
2443 print_insn (&cr16_ins);