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Implement -MD, -MF, -MT, -MQ
[nasm/avx512.git] / assemble.c
blob245aea44998bc01c373ff481fb7436302a644f13
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \171 - placement of DREX suffix in the absence of an EA
48 * \172\ab - the register number from operand a in bits 7..4, with
49 * the 4-bit immediate from operand b in bits 3..0.
50 * \173\xab - the register number from operand a in bits 7..4, with
51 * the value b in bits 3..0.
52 * \174\a - the register number from operand a in bits 7..4, and
53 * an arbitrary value in bits 3..0 (assembled as zero.)
54 * \2ab - a ModRM, calculated on EA in operand a, with the spare
55 * field equal to digit b.
56 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
57 * is not equal to the truncated and sign-extended 32-bit
58 * operand; used for 32-bit immediates in 64-bit mode.
59 * \260..\263 - this instruction uses VEX rather than REX, with the
60 * V field taken from operand 0..3.
61 * \270 - this instruction uses VEX rather than REX, with the
62 * V field set to 1111b.
63 *
64 * VEX prefixes are followed by the sequence:
65 * \mm\wlp where mm is the M field; and wlp is:
66 * 00 0ww lpp
67 * [w0] ww = 0 for W = 0
68 * [w1] ww = 1 for W = 1
69 * [wx] ww = 2 for W don't care (always assembled as 0)
70 * [ww] ww = 3 for W used as REX.W
71 *
72 *
73 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
74 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
75 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
76 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
77 * \314 - (disassembler only) invalid with REX.B
78 * \315 - (disassembler only) invalid with REX.X
79 * \316 - (disassembler only) invalid with REX.R
80 * \317 - (disassembler only) invalid with REX.W
81 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
82 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
83 * \322 - indicates that this instruction is only valid when the
84 * operand size is the default (instruction to disassembler,
85 * generates no code in the assembler)
86 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
87 * \324 - indicates 64-bit operand size requiring REX prefix.
88 * \330 - a literal byte follows in the code stream, to be added
89 * to the condition code value of the instruction.
90 * \331 - instruction not valid with REP prefix. Hint for
91 * disassembler only; for SSE instructions.
92 * \332 - REP prefix (0xF2 byte) used as opcode extension.
93 * \333 - REP prefix (0xF3 byte) used as opcode extension.
94 * \334 - LOCK prefix used instead of REX.R
95 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
96 * \340 - reserve <operand 0> bytes of uninitialized storage.
97 * Operand 0 had better be a segmentless constant.
98 * \360 - no SSE prefix (== \364\331)
99 * \361 - 66 SSE prefix (== \366\331)
100 * \362 - F2 SSE prefix (== \364\332)
101 * \363 - F3 SSE prefix (== \364\333)
102 * \364 - operand-size prefix (0x66) not permitted
103 * \365 - address-size prefix (0x67) not permitted
104 * \366 - operand-size prefix (0x66) used as opcode extension
105 * \367 - address-size prefix (0x67) used as opcode extension
106 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
107 * 370 is used for Jcc, 371 is used for JMP.
108 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
109 * used for conditional jump over longer jump
110 */
111
112 #include "compiler.h"
113
114 #include <stdio.h>
115 #include <string.h>
116 #include <inttypes.h>
117
118 #include "nasm.h"
119 #include "nasmlib.h"
120 #include "assemble.h"
121 #include "insns.h"
122 #include "preproc.h"
123 #include "tables.h"
124
125 /* Initialized to zero by the C standard */
126 static const uint8_t const_zero_buf[256];
127
128 typedef struct {
129 int sib_present; /* is a SIB byte necessary? */
130 int bytes; /* # of bytes of offset needed */
131 int size; /* lazy - this is sib+bytes+1 */
132 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
133 } ea;
134
135 static uint32_t cpu; /* cpu level received from nasm.c */
136 static efunc errfunc;
137 static struct ofmt *outfmt;
138 static ListGen *list;
139
140 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
141 static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t);
142 static int matches(const struct itemplate *, insn *, int bits);
143 static int32_t regflag(const operand *);
144 static int32_t regval(const operand *);
145 static int rexflags(int, int32_t, int);
146 static int op_rexflags(const operand *, int);
147 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
148 static void add_asp(insn *, int);
149
150 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
151 {
152 return ins->prefixes[pos] == prefix;
153 }
154
155 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
156 {
157 if (ins->prefixes[pos])
158 errfunc(ERR_NONFATAL, "invalid %s prefix",
159 prefix_name(ins->prefixes[pos]));
160 }
161
162 static const char *size_name(int size)
163 {
164 switch (size) {
165 case 1:
166 return "byte";
167 case 2:
168 return "word";
169 case 4:
170 return "dword";
171 case 8:
172 return "qword";
173 case 10:
174 return "tword";
175 case 16:
176 return "oword";
177 case 32:
178 return "yword";
179 default:
180 return "???";
181 }
182 }
183
184 static void warn_overflow(int size, int64_t data)
185 {
186 if (size < 8) {
187 int64_t lim = ((int64_t)1 << (size*8))-1;
188
189 if (data < ~lim || data > lim)
190 errfunc(ERR_WARNING | ERR_WARN_NOV,
191 "%s data exceeds bounds", size_name(size));
192 }
193 }
194 /*
195 * This routine wrappers the real output format's output routine,
196 * in order to pass a copy of the data off to the listing file
197 * generator at the same time.
198 */
199 static void out(int64_t offset, int32_t segto, const void *data,
200 enum out_type type, uint64_t size,
201 int32_t segment, int32_t wrt)
202 {
203 static int32_t lineno = 0; /* static!!! */
204 static char *lnfname = NULL;
205 uint8_t p[8];
206
207 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
208 /*
209 * This is a non-relocated address, and we're going to
210 * convert it into RAWDATA format.
211 */
212 uint8_t *q = p;
213
214 if (size > 8) {
215 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
216 return;
217 }
218
219 WRITEADDR(q, *(int64_t *)data, size);
220 data = p;
221 type = OUT_RAWDATA;
222 }
223
224 list->output(offset, data, type, size);
225
226 /*
227 * this call to src_get determines when we call the
228 * debug-format-specific "linenum" function
229 * it updates lineno and lnfname to the current values
230 * returning 0 if "same as last time", -2 if lnfname
231 * changed, and the amount by which lineno changed,
232 * if it did. thus, these variables must be static
233 */
234
235 if (src_get(&lineno, &lnfname)) {
236 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
237 }
238
239 outfmt->output(segto, data, type, size, segment, wrt);
240 }
241
242 static int jmp_match(int32_t segment, int64_t offset, int bits,
243 insn * ins, const uint8_t *code)
244 {
245 int64_t isize;
246 uint8_t c = code[0];
247
248 if (c != 0370 && c != 0371)
249 return 0;
250 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
251 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
252 && c == 0370)
253 return 1;
254 else
255 return (pass0 == 0); /* match a forward reference */
256 }
257 isize = calcsize(segment, offset, bits, ins, code);
258 if (ins->oprs[0].segment != segment)
259 return 0;
260 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
261 if (isize >= -128L && isize <= 127L)
262 return 1; /* it is byte size */
263
264 return 0;
265 }
266
267 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
268 insn * instruction, struct ofmt *output, efunc error,
269 ListGen * listgen)
270 {
271 const struct itemplate *temp;
272 int j;
273 int size_prob;
274 int64_t insn_end;
275 int32_t itimes;
276 int64_t start = offset;
277 int64_t wsize = 0; /* size for DB etc. */
278
279 errfunc = error; /* to pass to other functions */
280 cpu = cp;
281 outfmt = output; /* likewise */
282 list = listgen; /* and again */
283
284 switch (instruction->opcode) {
285 case -1:
286 return 0;
287 case I_DB:
288 wsize = 1;
289 break;
290 case I_DW:
291 wsize = 2;
292 break;
293 case I_DD:
294 wsize = 4;
295 break;
296 case I_DQ:
297 wsize = 8;
298 break;
299 case I_DT:
300 wsize = 10;
301 break;
302 case I_DO:
303 wsize = 16;
304 break;
305 case I_DY:
306 wsize = 32;
307 break;
308 default:
309 break;
310 }
311
312 if (wsize) {
313 extop *e;
314 int32_t t = instruction->times;
315 if (t < 0)
316 errfunc(ERR_PANIC,
317 "instruction->times < 0 (%ld) in assemble()", t);
318
319 while (t--) { /* repeat TIMES times */
320 for (e = instruction->eops; e; e = e->next) {
321 if (e->type == EOT_DB_NUMBER) {
322 if (wsize == 1) {
323 if (e->segment != NO_SEG)
324 errfunc(ERR_NONFATAL,
325 "one-byte relocation attempted");
326 else {
327 uint8_t out_byte = e->offset;
328 out(offset, segment, &out_byte,
329 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
330 }
331 } else if (wsize > 8) {
332 errfunc(ERR_NONFATAL,
333 "integer supplied to a DT, DO or DY"
334 " instruction");
335 } else
336 out(offset, segment, &e->offset,
337 OUT_ADDRESS, wsize, e->segment, e->wrt);
338 offset += wsize;
339 } else if (e->type == EOT_DB_STRING) {
340 int align;
341
342 out(offset, segment, e->stringval,
343 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
344 align = e->stringlen % wsize;
345
346 if (align) {
347 align = wsize - align;
348 out(offset, segment, const_zero_buf,
349 OUT_RAWDATA, align, NO_SEG, NO_SEG);
350 }
351 offset += e->stringlen + align;
352 }
353 }
354 if (t > 0 && t == instruction->times - 1) {
355 /*
356 * Dummy call to list->output to give the offset to the
357 * listing module.
358 */
359 list->output(offset, NULL, OUT_RAWDATA, 0);
360 list->uplevel(LIST_TIMES);
361 }
362 }
363 if (instruction->times > 1)
364 list->downlevel(LIST_TIMES);
365 return offset - start;
366 }
367
368 if (instruction->opcode == I_INCBIN) {
369 static char fname[FILENAME_MAX];
370 FILE *fp;
371 int32_t len;
372 char *prefix = "", *combine;
373 char **pPrevPath = NULL;
374
375 len = FILENAME_MAX - 1;
376 if (len > instruction->eops->stringlen)
377 len = instruction->eops->stringlen;
378 strncpy(fname, instruction->eops->stringval, len);
379 fname[len] = '\0';
380
381 while (1) { /* added by alexfru: 'incbin' uses include paths */
382 combine = nasm_malloc(strlen(prefix) + len + 1);
383 strcpy(combine, prefix);
384 strcat(combine, fname);
385
386 if ((fp = fopen(combine, "rb")) != NULL) {
387 nasm_free(combine);
388 break;
389 }
390
391 nasm_free(combine);
392 pPrevPath = pp_get_include_path_ptr(pPrevPath);
393 if (pPrevPath == NULL)
394 break;
395 prefix = *pPrevPath;
396 }
397
398 if (fp == NULL)
399 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
400 fname);
401 else if (fseek(fp, 0L, SEEK_END) < 0)
402 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
403 fname);
404 else {
405 static char buf[2048];
406 int32_t t = instruction->times;
407 int32_t base = 0;
408
409 len = ftell(fp);
410 if (instruction->eops->next) {
411 base = instruction->eops->next->offset;
412 len -= base;
413 if (instruction->eops->next->next &&
414 len > instruction->eops->next->next->offset)
415 len = instruction->eops->next->next->offset;
416 }
417 /*
418 * Dummy call to list->output to give the offset to the
419 * listing module.
420 */
421 list->output(offset, NULL, OUT_RAWDATA, 0);
422 list->uplevel(LIST_INCBIN);
423 while (t--) {
424 int32_t l;
425
426 fseek(fp, base, SEEK_SET);
427 l = len;
428 while (l > 0) {
429 int32_t m =
430 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
431 fp);
432 if (!m) {
433 /*
434 * This shouldn't happen unless the file
435 * actually changes while we are reading
436 * it.
437 */
438 error(ERR_NONFATAL,
439 "`incbin': unexpected EOF while"
440 " reading file `%s'", fname);
441 t = 0; /* Try to exit cleanly */
442 break;
443 }
444 out(offset, segment, buf, OUT_RAWDATA, m,
445 NO_SEG, NO_SEG);
446 l -= m;
447 }
448 }
449 list->downlevel(LIST_INCBIN);
450 if (instruction->times > 1) {
451 /*
452 * Dummy call to list->output to give the offset to the
453 * listing module.
454 */
455 list->output(offset, NULL, OUT_RAWDATA, 0);
456 list->uplevel(LIST_TIMES);
457 list->downlevel(LIST_TIMES);
458 }
459 fclose(fp);
460 return instruction->times * len;
461 }
462 return 0; /* if we're here, there's an error */
463 }
464
465 /* Check to see if we need an address-size prefix */
466 add_asp(instruction, bits);
467
468 size_prob = false;
469
470 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
471 int m = matches(temp, instruction, bits);
472
473 if (m == 99)
474 m += jmp_match(segment, offset, bits, instruction, temp->code);
475
476 if (m == 100) { /* matches! */
477 const uint8_t *codes = temp->code;
478 int64_t insn_size = calcsize(segment, offset, bits,
479 instruction, codes);
480 itimes = instruction->times;
481 if (insn_size < 0) /* shouldn't be, on pass two */
482 error(ERR_PANIC, "errors made it through from pass one");
483 else
484 while (itimes--) {
485 for (j = 0; j < MAXPREFIX; j++) {
486 uint8_t c = 0;
487 switch (instruction->prefixes[j]) {
488 case P_LOCK:
489 c = 0xF0;
490 break;
491 case P_REPNE:
492 case P_REPNZ:
493 c = 0xF2;
494 break;
495 case P_REPE:
496 case P_REPZ:
497 case P_REP:
498 c = 0xF3;
499 break;
500 case R_CS:
501 if (bits == 64) {
502 error(ERR_WARNING,
503 "cs segment base generated, but will be ignored in 64-bit mode");
504 }
505 c = 0x2E;
506 break;
507 case R_DS:
508 if (bits == 64) {
509 error(ERR_WARNING,
510 "ds segment base generated, but will be ignored in 64-bit mode");
511 }
512 c = 0x3E;
513 break;
514 case R_ES:
515 if (bits == 64) {
516 error(ERR_WARNING,
517 "es segment base generated, but will be ignored in 64-bit mode");
518 }
519 c = 0x26;
520 break;
521 case R_FS:
522 c = 0x64;
523 break;
524 case R_GS:
525 c = 0x65;
526 break;
527 case R_SS:
528 if (bits == 64) {
529 error(ERR_WARNING,
530 "ss segment base generated, but will be ignored in 64-bit mode");
531 }
532 c = 0x36;
533 break;
534 case R_SEGR6:
535 case R_SEGR7:
536 error(ERR_NONFATAL,
537 "segr6 and segr7 cannot be used as prefixes");
538 break;
539 case P_A16:
540 if (bits == 64) {
541 error(ERR_NONFATAL,
542 "16-bit addressing is not supported "
543 "in 64-bit mode");
544 } else if (bits != 16)
545 c = 0x67;
546 break;
547 case P_A32:
548 if (bits != 32)
549 c = 0x67;
550 break;
551 case P_A64:
552 if (bits != 64) {
553 error(ERR_NONFATAL,
554 "64-bit addressing is only supported "
555 "in 64-bit mode");
556 }
557 break;
558 case P_ASP:
559 c = 0x67;
560 break;
561 case P_O16:
562 if (bits != 16)
563 c = 0x66;
564 break;
565 case P_O32:
566 if (bits == 16)
567 c = 0x66;
568 break;
569 case P_O64:
570 /* REX.W */
571 break;
572 case P_OSP:
573 c = 0x66;
574 break;
575 case P_none:
576 break;
577 default:
578 error(ERR_PANIC, "invalid instruction prefix");
579 }
580 if (c != 0) {
581 out(offset, segment, &c, OUT_RAWDATA, 1,
582 NO_SEG, NO_SEG);
583 offset++;
584 }
585 }
586 insn_end = offset + insn_size;
587 gencode(segment, offset, bits, instruction, codes,
588 insn_end);
589 offset += insn_size;
590 if (itimes > 0 && itimes == instruction->times - 1) {
591 /*
592 * Dummy call to list->output to give the offset to the
593 * listing module.
594 */
595 list->output(offset, NULL, OUT_RAWDATA, 0);
596 list->uplevel(LIST_TIMES);
597 }
598 }
599 if (instruction->times > 1)
600 list->downlevel(LIST_TIMES);
601 return offset - start;
602 } else if (m > 0 && m > size_prob) {
603 size_prob = m;
604 }
605 // temp++;
606 }
607
608 if (temp->opcode == -1) { /* didn't match any instruction */
609 switch (size_prob) {
610 case 1:
611 error(ERR_NONFATAL, "operation size not specified");
612 break;
613 case 2:
614 error(ERR_NONFATAL, "mismatch in operand sizes");
615 break;
616 case 3:
617 error(ERR_NONFATAL, "no instruction for this cpu level");
618 break;
619 case 4:
620 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
621 break;
622 default:
623 error(ERR_NONFATAL,
624 "invalid combination of opcode and operands");
625 break;
626 }
627 }
628 return 0;
629 }
630
631 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
632 insn * instruction, efunc error)
633 {
634 const struct itemplate *temp;
635
636 errfunc = error; /* to pass to other functions */
637 cpu = cp;
638
639 if (instruction->opcode == -1)
640 return 0;
641
642 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
643 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
644 instruction->opcode == I_DT || instruction->opcode == I_DO ||
645 instruction->opcode == I_DY) {
646 extop *e;
647 int32_t isize, osize, wsize = 0; /* placate gcc */
648
649 isize = 0;
650 switch (instruction->opcode) {
651 case I_DB:
652 wsize = 1;
653 break;
654 case I_DW:
655 wsize = 2;
656 break;
657 case I_DD:
658 wsize = 4;
659 break;
660 case I_DQ:
661 wsize = 8;
662 break;
663 case I_DT:
664 wsize = 10;
665 break;
666 case I_DO:
667 wsize = 16;
668 break;
669 case I_DY:
670 wsize = 32;
671 break;
672 default:
673 break;
674 }
675
676 for (e = instruction->eops; e; e = e->next) {
677 int32_t align;
678
679 osize = 0;
680 if (e->type == EOT_DB_NUMBER)
681 osize = 1;
682 else if (e->type == EOT_DB_STRING)
683 osize = e->stringlen;
684
685 align = (-osize) % wsize;
686 if (align < 0)
687 align += wsize;
688 isize += osize + align;
689 }
690 return isize * instruction->times;
691 }
692
693 if (instruction->opcode == I_INCBIN) {
694 char fname[FILENAME_MAX];
695 FILE *fp;
696 int32_t len;
697 char *prefix = "", *combine;
698 char **pPrevPath = NULL;
699
700 len = FILENAME_MAX - 1;
701 if (len > instruction->eops->stringlen)
702 len = instruction->eops->stringlen;
703 strncpy(fname, instruction->eops->stringval, len);
704 fname[len] = '\0';
705
706 /* added by alexfru: 'incbin' uses include paths */
707 while (1) {
708 combine = nasm_malloc(strlen(prefix) + len + 1);
709 strcpy(combine, prefix);
710 strcat(combine, fname);
711
712 if ((fp = fopen(combine, "rb")) != NULL) {
713 nasm_free(combine);
714 break;
715 }
716
717 nasm_free(combine);
718 pPrevPath = pp_get_include_path_ptr(pPrevPath);
719 if (pPrevPath == NULL)
720 break;
721 prefix = *pPrevPath;
722 }
723
724 if (fp == NULL)
725 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
726 fname);
727 else if (fseek(fp, 0L, SEEK_END) < 0)
728 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
729 fname);
730 else {
731 len = ftell(fp);
732 fclose(fp);
733 if (instruction->eops->next) {
734 len -= instruction->eops->next->offset;
735 if (instruction->eops->next->next &&
736 len > instruction->eops->next->next->offset) {
737 len = instruction->eops->next->next->offset;
738 }
739 }
740 return instruction->times * len;
741 }
742 return 0; /* if we're here, there's an error */
743 }
744
745 /* Check to see if we need an address-size prefix */
746 add_asp(instruction, bits);
747
748 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
749 int m = matches(temp, instruction, bits);
750 if (m == 99)
751 m += jmp_match(segment, offset, bits, instruction, temp->code);
752
753 if (m == 100) {
754 /* we've matched an instruction. */
755 int64_t isize;
756 const uint8_t *codes = temp->code;
757 int j;
758
759 isize = calcsize(segment, offset, bits, instruction, codes);
760 if (isize < 0)
761 return -1;
762 for (j = 0; j < MAXPREFIX; j++) {
763 switch (instruction->prefixes[j]) {
764 case P_A16:
765 if (bits != 16)
766 isize++;
767 break;
768 case P_A32:
769 if (bits != 32)
770 isize++;
771 break;
772 case P_O16:
773 if (bits != 16)
774 isize++;
775 break;
776 case P_O32:
777 if (bits == 16)
778 isize++;
779 break;
780 case P_A64:
781 case P_O64:
782 case P_none:
783 break;
784 default:
785 isize++;
786 break;
787 }
788 }
789 return isize * instruction->times;
790 }
791 }
792 return -1; /* didn't match any instruction */
793 }
794
795 static bool possible_sbyte(insn * ins, int op)
796 {
797 return !(ins->forw_ref && ins->oprs[op].opflags) &&
798 optimizing >= 0 &&
799 !(ins->oprs[op].type & STRICT) &&
800 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
801 }
802
803 /* check that opn[op] is a signed byte of size 16 or 32 */
804 static bool is_sbyte16(insn * ins, int op)
805 {
806 int16_t v;
807
808 if (!possible_sbyte(ins, op))
809 return false;
810
811 v = ins->oprs[op].offset;
812 return v >= -128 && v <= 127;
813 }
814
815 static bool is_sbyte32(insn * ins, int op)
816 {
817 int32_t v;
818
819 if (!possible_sbyte(ins, op))
820 return false;
821
822 v = ins->oprs[op].offset;
823 return v >= -128 && v <= 127;
824 }
825
826 /* check that opn[op] is a signed byte of size 32; warn if this is not
827 the original value when extended to 64 bits */
828 static bool is_sbyte64(insn * ins, int op)
829 {
830 int64_t v64;
831 int32_t v32;
832
833 /* dead in the water on forward reference or External */
834 if (!possible_sbyte(ins, op))
835 return false;
836
837 v64 = ins->oprs[op].offset;
838 v32 = (int32_t)v64;
839
840 warn_overflow(32, v64);
841
842 return v32 >= -128 && v32 <= 127;
843 }
844 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
845 insn * ins, const uint8_t *codes)
846 {
847 int64_t length = 0;
848 uint8_t c;
849 int rex_mask = ~0;
850 struct operand *opx;
851
852 ins->rex = 0; /* Ensure REX is reset */
853
854 if (ins->prefixes[PPS_OSIZE] == P_O64)
855 ins->rex |= REX_W;
856
857 (void)segment; /* Don't warn that this parameter is unused */
858 (void)offset; /* Don't warn that this parameter is unused */
859
860 while (*codes) {
861 c = *codes++;
862 opx = &ins->oprs[c & 3];
863 switch (c) {
864 case 01:
865 case 02:
866 case 03:
867 codes += c, length += c;
868 break;
869 case 04:
870 case 05:
871 case 06:
872 case 07:
873 length++;
874 break;
875 case 010:
876 case 011:
877 case 012:
878 case 013:
879 ins->rex |=
880 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
881 codes++, length++;
882 break;
883 case 014:
884 case 015:
885 case 016:
886 case 017:
887 length++;
888 break;
889 case 020:
890 case 021:
891 case 022:
892 case 023:
893 length++;
894 break;
895 case 024:
896 case 025:
897 case 026:
898 case 027:
899 length++;
900 break;
901 case 030:
902 case 031:
903 case 032:
904 case 033:
905 length += 2;
906 break;
907 case 034:
908 case 035:
909 case 036:
910 case 037:
911 if (opx->type & (BITS16 | BITS32 | BITS64))
912 length += (opx->type & BITS16) ? 2 : 4;
913 else
914 length += (bits == 16) ? 2 : 4;
915 break;
916 case 040:
917 case 041:
918 case 042:
919 case 043:
920 length += 4;
921 break;
922 case 044:
923 case 045:
924 case 046:
925 case 047:
926 length += ins->addr_size >> 3;
927 break;
928 case 050:
929 case 051:
930 case 052:
931 case 053:
932 length++;
933 break;
934 case 054:
935 case 055:
936 case 056:
937 case 057:
938 length += 8; /* MOV reg64/imm */
939 break;
940 case 060:
941 case 061:
942 case 062:
943 case 063:
944 length += 2;
945 break;
946 case 064:
947 case 065:
948 case 066:
949 case 067:
950 if (opx->type & (BITS16 | BITS32 | BITS64))
951 length += (opx->type & BITS16) ? 2 : 4;
952 else
953 length += (bits == 16) ? 2 : 4;
954 break;
955 case 070:
956 case 071:
957 case 072:
958 case 073:
959 length += 4;
960 break;
961 case 074:
962 case 075:
963 case 076:
964 case 077:
965 length += 2;
966 break;
967 case 0140:
968 case 0141:
969 case 0142:
970 case 0143:
971 length += is_sbyte16(ins, c & 3) ? 1 : 2;
972 break;
973 case 0144:
974 case 0145:
975 case 0146:
976 case 0147:
977 codes++;
978 length++;
979 break;
980 case 0150:
981 case 0151:
982 case 0152:
983 case 0153:
984 length += is_sbyte32(ins, c & 3) ? 1 : 4;
985 break;
986 case 0154:
987 case 0155:
988 case 0156:
989 case 0157:
990 codes++;
991 length++;
992 break;
993 case 0160:
994 case 0161:
995 case 0162:
996 case 0163:
997 length++;
998 ins->rex |= REX_D;
999 ins->drexdst = regval(opx);
1000 break;
1001 case 0164:
1002 case 0165:
1003 case 0166:
1004 case 0167:
1005 length++;
1006 ins->rex |= REX_D|REX_OC;
1007 ins->drexdst = regval(opx);
1008 break;
1009 case 0171:
1010 break;
1011 case 0172:
1012 case 0173:
1013 case 0174:
1014 codes++;
1015 length++;
1016 break;
1017 case 0250:
1018 case 0251:
1019 case 0252:
1020 case 0253:
1021 length += is_sbyte64(ins, c & 3) ? 1 : 4;
1022 break;
1023 case 0260:
1024 case 0261:
1025 case 0262:
1026 case 0263:
1027 length += 2;
1028 ins->rex |= REX_V;
1029 ins->drexdst = regval(opx);
1030 ins->vex_m = *codes++;
1031 ins->vex_wlp = *codes++;
1032 break;
1033 case 0270:
1034 length += 2;
1035 ins->rex |= REX_V;
1036 ins->drexdst = 0;
1037 ins->vex_m = *codes++;
1038 ins->vex_wlp = *codes++;
1039 break;
1040 case 0300:
1041 case 0301:
1042 case 0302:
1043 case 0303:
1044 break;
1045 case 0310:
1046 if (bits == 64)
1047 return -1;
1048 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1049 break;
1050 case 0311:
1051 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1052 break;
1053 case 0312:
1054 break;
1055 case 0313:
1056 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1057 has_prefix(ins, PPS_ASIZE, P_A32))
1058 return -1;
1059 break;
1060 case 0314:
1061 case 0315:
1062 case 0316:
1063 case 0317:
1064 break;
1065 case 0320:
1066 length += (bits != 16);
1067 break;
1068 case 0321:
1069 length += (bits == 16);
1070 break;
1071 case 0322:
1072 break;
1073 case 0323:
1074 rex_mask &= ~REX_W;
1075 break;
1076 case 0324:
1077 ins->rex |= REX_W;
1078 break;
1079 case 0330:
1080 codes++, length++;
1081 break;
1082 case 0331:
1083 break;
1084 case 0332:
1085 case 0333:
1086 length++;
1087 break;
1088 case 0334:
1089 ins->rex |= REX_L;
1090 break;
1091 case 0335:
1092 break;
1093 case 0340:
1094 if (ins->oprs[0].segment != NO_SEG)
1095 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1096 " quantity of BSS space");
1097 else
1098 length += ins->oprs[0].offset;
1099 break;
1100 case 0360:
1101 break;
1102 case 0361:
1103 case 0362:
1104 case 0363:
1105 length++;
1106 break;
1107 case 0364:
1108 case 0365:
1109 break;
1110 case 0366:
1111 case 0367:
1112 length++;
1113 break;
1114 case 0370:
1115 case 0371:
1116 case 0372:
1117 break;
1118 case 0373:
1119 length++;
1120 break;
1121 default: /* can't do it by 'case' statements */
1122 if (c >= 0100 && c <= 0277) { /* it's an EA */
1123 ea ea_data;
1124 int rfield;
1125 int32_t rflags;
1126 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1127
1128 if (c <= 0177) {
1129 /* pick rfield from operand b */
1130 rflags = regflag(&ins->oprs[c & 7]);
1131 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1132 } else {
1133 rflags = 0;
1134 rfield = c & 7;
1135 }
1136
1137 if (!process_ea
1138 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1139 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1140 errfunc(ERR_NONFATAL, "invalid effective address");
1141 return -1;
1142 } else {
1143 ins->rex |= ea_data.rex;
1144 length += ea_data.size;
1145 }
1146 } else {
1147 errfunc(ERR_PANIC, "internal instruction table corrupt"
1148 ": instruction code 0x%02X given", c);
1149 }
1150 }
1151 }
1152
1153 ins->rex &= rex_mask;
1154
1155 if (ins->rex & REX_V) {
1156 int bad32 = REX_R|REX_W|REX_X|REX_B;
1157
1158 if (ins->rex & REX_H) {
1159 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1160 return -1;
1161 }
1162 switch (ins->vex_wlp & 030) {
1163 case 000:
1164 case 020:
1165 ins->rex &= ~REX_W;
1166 break;
1167 case 010:
1168 ins->rex |= REX_W;
1169 bad32 &= ~REX_W;
1170 break;
1171 case 030:
1172 /* Follow REX_W */
1173 break;
1174 }
1175
1176 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1177 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1178 return -1;
1179 }
1180 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1181 length += 3;
1182 else
1183 length += 2;
1184 } else if (ins->rex & REX_D) {
1185 if (ins->rex & REX_H) {
1186 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1187 return -1;
1188 }
1189 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1190 ins->drexdst > 7)) {
1191 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1192 return -1;
1193 }
1194 length++;
1195 } else if (ins->rex & REX_REAL) {
1196 if (ins->rex & REX_H) {
1197 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1198 return -1;
1199 } else if (bits == 64) {
1200 length++;
1201 } else if ((ins->rex & REX_L) &&
1202 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1203 cpu >= IF_X86_64) {
1204 /* LOCK-as-REX.R */
1205 assert_no_prefix(ins, PPS_LREP);
1206 length++;
1207 } else {
1208 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1209 return -1;
1210 }
1211 }
1212
1213 return length;
1214 }
1215
1216 #define EMIT_REX() \
1217 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1218 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1219 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1220 ins->rex = 0; \
1221 offset += 1; \
1222 }
1223
1224 static void gencode(int32_t segment, int64_t offset, int bits,
1225 insn * ins, const uint8_t *codes, int64_t insn_end)
1226 {
1227 static char condval[] = { /* conditional opcodes */
1228 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1229 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1230 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1231 };
1232 uint8_t c;
1233 uint8_t bytes[4];
1234 int64_t size;
1235 int64_t data;
1236 struct operand *opx;
1237
1238 while (*codes) {
1239 c = *codes++;
1240 opx = &ins->oprs[c & 3];
1241 switch (c) {
1242 case 01:
1243 case 02:
1244 case 03:
1245 EMIT_REX();
1246 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1247 codes += c;
1248 offset += c;
1249 break;
1250
1251 case 04:
1252 case 06:
1253 switch (ins->oprs[0].basereg) {
1254 case R_CS:
1255 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1256 break;
1257 case R_DS:
1258 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1259 break;
1260 case R_ES:
1261 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1262 break;
1263 case R_SS:
1264 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1265 break;
1266 default:
1267 errfunc(ERR_PANIC,
1268 "bizarre 8086 segment register received");
1269 }
1270 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1271 offset++;
1272 break;
1273
1274 case 05:
1275 case 07:
1276 switch (ins->oprs[0].basereg) {
1277 case R_FS:
1278 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1279 break;
1280 case R_GS:
1281 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1282 break;
1283 default:
1284 errfunc(ERR_PANIC,
1285 "bizarre 386 segment register received");
1286 }
1287 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1288 offset++;
1289 break;
1290
1291 case 010:
1292 case 011:
1293 case 012:
1294 case 013:
1295 EMIT_REX();
1296 bytes[0] = *codes++ + ((regval(opx)) & 7);
1297 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1298 offset += 1;
1299 break;
1300
1301 case 014:
1302 case 015:
1303 case 016:
1304 case 017:
1305 /* XXX: warns for legitimate optimizer actions */
1306 if (opx->offset < -128 || opx->offset > 127) {
1307 errfunc(ERR_WARNING | ERR_WARN_NOV,
1308 "signed byte value exceeds bounds");
1309 }
1310
1311 if (opx->segment != NO_SEG) {
1312 data = opx->offset;
1313 out(offset, segment, &data, OUT_ADDRESS, 1,
1314 opx->segment, opx->wrt);
1315 } else {
1316 bytes[0] = opx->offset;
1317 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1318 NO_SEG);
1319 }
1320 offset += 1;
1321 break;
1322
1323 case 020:
1324 case 021:
1325 case 022:
1326 case 023:
1327 if (opx->offset < -256 || opx->offset > 255) {
1328 errfunc(ERR_WARNING | ERR_WARN_NOV,
1329 "byte value exceeds bounds");
1330 }
1331 if (opx->segment != NO_SEG) {
1332 data = opx->offset;
1333 out(offset, segment, &data, OUT_ADDRESS, 1,
1334 opx->segment, opx->wrt);
1335 } else {
1336 bytes[0] = opx->offset;
1337 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1338 NO_SEG);
1339 }
1340 offset += 1;
1341 break;
1342
1343 case 024:
1344 case 025:
1345 case 026:
1346 case 027:
1347 if (opx->offset < 0 || opx->offset > 255)
1348 errfunc(ERR_WARNING | ERR_WARN_NOV,
1349 "unsigned byte value exceeds bounds");
1350 if (opx->segment != NO_SEG) {
1351 data = opx->offset;
1352 out(offset, segment, &data, OUT_ADDRESS, 1,
1353 opx->segment, opx->wrt);
1354 } else {
1355 bytes[0] = opx->offset;
1356 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1357 NO_SEG);
1358 }
1359 offset += 1;
1360 break;
1361
1362 case 030:
1363 case 031:
1364 case 032:
1365 case 033:
1366 data = opx->offset;
1367 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1368 warn_overflow(2, data);
1369 out(offset, segment, &data, OUT_ADDRESS, 2,
1370 opx->segment, opx->wrt);
1371 offset += 2;
1372 break;
1373
1374 case 034:
1375 case 035:
1376 case 036:
1377 case 037:
1378 if (opx->type & (BITS16 | BITS32))
1379 size = (opx->type & BITS16) ? 2 : 4;
1380 else
1381 size = (bits == 16) ? 2 : 4;
1382 data = opx->offset;
1383 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1384 warn_overflow(size, data);
1385 out(offset, segment, &data, OUT_ADDRESS, size,
1386 opx->segment, opx->wrt);
1387 offset += size;
1388 break;
1389
1390 case 040:
1391 case 041:
1392 case 042:
1393 case 043:
1394 data = opx->offset;
1395 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1396 warn_overflow(4, data);
1397 out(offset, segment, &data, OUT_ADDRESS, 4,
1398 opx->segment, opx->wrt);
1399 offset += 4;
1400 break;
1401
1402 case 044:
1403 case 045:
1404 case 046:
1405 case 047:
1406 data = opx->offset;
1407 size = ins->addr_size >> 3;
1408 if (opx->segment == NO_SEG &&
1409 opx->wrt == NO_SEG)
1410 warn_overflow(size, data);
1411 out(offset, segment, &data, OUT_ADDRESS, size,
1412 opx->segment, opx->wrt);
1413 offset += size;
1414 break;
1415
1416 case 050:
1417 case 051:
1418 case 052:
1419 case 053:
1420 if (opx->segment != segment)
1421 errfunc(ERR_NONFATAL,
1422 "short relative jump outside segment");
1423 data = opx->offset - insn_end;
1424 if (data > 127 || data < -128)
1425 errfunc(ERR_NONFATAL, "short jump is out of range");
1426 bytes[0] = data;
1427 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1428 offset += 1;
1429 break;
1430
1431 case 054:
1432 case 055:
1433 case 056:
1434 case 057:
1435 data = (int64_t)opx->offset;
1436 out(offset, segment, &data, OUT_ADDRESS, 8,
1437 opx->segment, opx->wrt);
1438 offset += 8;
1439 break;
1440
1441 case 060:
1442 case 061:
1443 case 062:
1444 case 063:
1445 if (opx->segment != segment) {
1446 data = opx->offset;
1447 out(offset, segment, &data,
1448 OUT_REL2ADR, insn_end - offset,
1449 opx->segment, opx->wrt);
1450 } else {
1451 data = opx->offset - insn_end;
1452 out(offset, segment, &data,
1453 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1454 }
1455 offset += 2;
1456 break;
1457
1458 case 064:
1459 case 065:
1460 case 066:
1461 case 067:
1462 if (opx->type & (BITS16 | BITS32 | BITS64))
1463 size = (opx->type & BITS16) ? 2 : 4;
1464 else
1465 size = (bits == 16) ? 2 : 4;
1466 if (opx->segment != segment) {
1467 data = opx->offset;
1468 out(offset, segment, &data,
1469 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1470 insn_end - offset, opx->segment, opx->wrt);
1471 } else {
1472 data = opx->offset - insn_end;
1473 out(offset, segment, &data,
1474 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1475 }
1476 offset += size;
1477 break;
1478
1479 case 070:
1480 case 071:
1481 case 072:
1482 case 073:
1483 if (opx->segment != segment) {
1484 data = opx->offset;
1485 out(offset, segment, &data,
1486 OUT_REL4ADR, insn_end - offset,
1487 opx->segment, opx->wrt);
1488 } else {
1489 data = opx->offset - insn_end;
1490 out(offset, segment, &data,
1491 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1492 }
1493 offset += 4;
1494 break;
1495
1496 case 074:
1497 case 075:
1498 case 076:
1499 case 077:
1500 if (opx->segment == NO_SEG)
1501 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1502 " relocatable");
1503 data = 0;
1504 out(offset, segment, &data, OUT_ADDRESS, 2,
1505 outfmt->segbase(1 + opx->segment),
1506 opx->wrt);
1507 offset += 2;
1508 break;
1509
1510 case 0140:
1511 case 0141:
1512 case 0142:
1513 case 0143:
1514 data = opx->offset;
1515 if (is_sbyte16(ins, c & 3)) {
1516 bytes[0] = data;
1517 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1518 NO_SEG);
1519 offset++;
1520 } else {
1521 if (opx->segment == NO_SEG &&
1522 opx->wrt == NO_SEG)
1523 warn_overflow(2, data);
1524 out(offset, segment, &data, OUT_ADDRESS, 2,
1525 opx->segment, opx->wrt);
1526 offset += 2;
1527 }
1528 break;
1529
1530 case 0144:
1531 case 0145:
1532 case 0146:
1533 case 0147:
1534 EMIT_REX();
1535 bytes[0] = *codes++;
1536 if (is_sbyte16(ins, c & 3))
1537 bytes[0] |= 2; /* s-bit */
1538 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1539 offset++;
1540 break;
1541
1542 case 0150:
1543 case 0151:
1544 case 0152:
1545 case 0153:
1546 data = opx->offset;
1547 if (is_sbyte32(ins, c & 3)) {
1548 bytes[0] = data;
1549 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1550 NO_SEG);
1551 offset++;
1552 } else {
1553 out(offset, segment, &data, OUT_ADDRESS, 4,
1554 opx->segment, opx->wrt);
1555 offset += 4;
1556 }
1557 break;
1558
1559 case 0154:
1560 case 0155:
1561 case 0156:
1562 case 0157:
1563 EMIT_REX();
1564 bytes[0] = *codes++;
1565 if (is_sbyte32(ins, c & 3))
1566 bytes[0] |= 2; /* s-bit */
1567 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1568 offset++;
1569 break;
1570
1571 case 0160:
1572 case 0161:
1573 case 0162:
1574 case 0163:
1575 case 0164:
1576 case 0165:
1577 case 0166:
1578 case 0167:
1579 break;
1580
1581 case 0171:
1582 bytes[0] =
1583 (ins->drexdst << 4) |
1584 (ins->rex & REX_OC ? 0x08 : 0) |
1585 (ins->rex & (REX_R|REX_X|REX_B));
1586 ins->rex = 0;
1587 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1588 offset++;
1589 break;
1590
1591 case 0172:
1592 c = *codes++;
1593 opx = &ins->oprs[c >> 3];
1594 bytes[0] = nasm_regvals[opx->basereg] << 4;
1595 opx = &ins->oprs[c & 7];
1596 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1597 errfunc(ERR_NONFATAL,
1598 "non-absolute expression not permitted as argument %d",
1599 c & 7);
1600 } else {
1601 if (opx->offset & ~15) {
1602 errfunc(ERR_WARNING | ERR_WARN_NOV,
1603 "four-bit argument exceeds bounds");
1604 }
1605 bytes[0] |= opx->offset & 15;
1606 }
1607 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1608 offset++;
1609 break;
1610
1611 case 0173:
1612 c = *codes++;
1613 opx = &ins->oprs[c >> 4];
1614 bytes[0] = nasm_regvals[opx->basereg] << 4;
1615 bytes[0] |= c & 15;
1616 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1617 offset++;
1618 break;
1619
1620 case 0174:
1621 c = *codes++;
1622 opx = &ins->oprs[c];
1623 bytes[0] = nasm_regvals[opx->basereg] << 4;
1624 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1625 offset++;
1626 break;
1627
1628 case 0250:
1629 case 0251:
1630 case 0252:
1631 case 0253:
1632 data = opx->offset;
1633 /* is_sbyte32() is right here, we have already warned */
1634 if (is_sbyte32(ins, c & 3)) {
1635 bytes[0] = data;
1636 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1637 NO_SEG);
1638 offset++;
1639 } else {
1640 out(offset, segment, &data, OUT_ADDRESS, 4,
1641 opx->segment, opx->wrt);
1642 offset += 4;
1643 }
1644 break;
1645
1646 case 0260:
1647 case 0261:
1648 case 0262:
1649 case 0263:
1650 case 0270:
1651 codes += 2;
1652 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1653 bytes[0] = 0xc4;
1654 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1655 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1656 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1657 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1658 offset += 3;
1659 } else {
1660 bytes[0] = 0xc5;
1661 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1662 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1663 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1664 offset += 2;
1665 }
1666 break;
1667
1668 case 0300:
1669 case 0301:
1670 case 0302:
1671 case 0303:
1672 break;
1673
1674 case 0310:
1675 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1676 *bytes = 0x67;
1677 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1678 offset += 1;
1679 } else
1680 offset += 0;
1681 break;
1682
1683 case 0311:
1684 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1685 *bytes = 0x67;
1686 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1687 offset += 1;
1688 } else
1689 offset += 0;
1690 break;
1691
1692 case 0312:
1693 break;
1694
1695 case 0313:
1696 ins->rex = 0;
1697 break;
1698
1699 case 0314:
1700 case 0315:
1701 case 0316:
1702 case 0317:
1703 break;
1704
1705 case 0320:
1706 if (bits != 16) {
1707 *bytes = 0x66;
1708 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1709 offset += 1;
1710 } else
1711 offset += 0;
1712 break;
1713
1714 case 0321:
1715 if (bits == 16) {
1716 *bytes = 0x66;
1717 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1718 offset += 1;
1719 } else
1720 offset += 0;
1721 break;
1722
1723 case 0322:
1724 case 0323:
1725 break;
1726
1727 case 0324:
1728 ins->rex |= REX_W;
1729 break;
1730
1731 case 0330:
1732 *bytes = *codes++ ^ condval[ins->condition];
1733 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1734 offset += 1;
1735 break;
1736
1737 case 0331:
1738 break;
1739
1740 case 0332:
1741 case 0333:
1742 *bytes = c - 0332 + 0xF2;
1743 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1744 offset += 1;
1745 break;
1746
1747 case 0334:
1748 if (ins->rex & REX_R) {
1749 *bytes = 0xF0;
1750 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1751 offset += 1;
1752 }
1753 ins->rex &= ~(REX_L|REX_R);
1754 break;
1755
1756 case 0335:
1757 break;
1758
1759 case 0340:
1760 if (ins->oprs[0].segment != NO_SEG)
1761 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1762 else {
1763 int64_t size = ins->oprs[0].offset;
1764 if (size > 0)
1765 out(offset, segment, NULL,
1766 OUT_RESERVE, size, NO_SEG, NO_SEG);
1767 offset += size;
1768 }
1769 break;
1770
1771 case 0360:
1772 break;
1773
1774 case 0361:
1775 bytes[0] = 0x66;
1776 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1777 offset += 1;
1778 break;
1779
1780 case 0362:
1781 case 0363:
1782 bytes[0] = c - 0362 + 0xf2;
1783 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1784 offset += 1;
1785 break;
1786
1787 case 0364:
1788 case 0365:
1789 break;
1790
1791 case 0366:
1792 case 0367:
1793 *bytes = c - 0366 + 0x66;
1794 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1795 offset += 1;
1796 break;
1797
1798 case 0370:
1799 case 0371:
1800 case 0372:
1801 break;
1802
1803 case 0373:
1804 *bytes = bits == 16 ? 3 : 5;
1805 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1806 offset += 1;
1807 break;
1808
1809 default: /* can't do it by 'case' statements */
1810 if (c >= 0100 && c <= 0277) { /* it's an EA */
1811 ea ea_data;
1812 int rfield;
1813 int32_t rflags;
1814 uint8_t *p;
1815 int32_t s;
1816
1817 if (c <= 0177) {
1818 /* pick rfield from operand b */
1819 rflags = regflag(&ins->oprs[c & 7]);
1820 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1821 } else {
1822 /* rfield is constant */
1823 rflags = 0;
1824 rfield = c & 7;
1825 }
1826
1827 if (!process_ea
1828 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1829 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1830 errfunc(ERR_NONFATAL, "invalid effective address");
1831 }
1832
1833
1834 p = bytes;
1835 *p++ = ea_data.modrm;
1836 if (ea_data.sib_present)
1837 *p++ = ea_data.sib;
1838
1839 /* DREX suffixes come between the SIB and the displacement */
1840 if (ins->rex & REX_D) {
1841 *p++ =
1842 (ins->drexdst << 4) |
1843 (ins->rex & REX_OC ? 0x08 : 0) |
1844 (ins->rex & (REX_R|REX_X|REX_B));
1845 ins->rex = 0;
1846 }
1847
1848 s = p - bytes;
1849 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1850
1851 switch (ea_data.bytes) {
1852 case 0:
1853 break;
1854 case 1:
1855 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1856 data = ins->oprs[(c >> 3) & 7].offset;
1857 out(offset, segment, &data, OUT_ADDRESS, 1,
1858 ins->oprs[(c >> 3) & 7].segment,
1859 ins->oprs[(c >> 3) & 7].wrt);
1860 } else {
1861 *bytes = ins->oprs[(c >> 3) & 7].offset;
1862 out(offset, segment, bytes, OUT_RAWDATA, 1,
1863 NO_SEG, NO_SEG);
1864 }
1865 s++;
1866 break;
1867 case 8:
1868 case 2:
1869 case 4:
1870 data = ins->oprs[(c >> 3) & 7].offset;
1871 warn_overflow(ea_data.bytes, data);
1872 out(offset, segment, &data,
1873 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1874 ea_data.bytes,
1875 ins->oprs[(c >> 3) & 7].segment,
1876 ins->oprs[(c >> 3) & 7].wrt);
1877 s += ea_data.bytes;
1878 break;
1879 }
1880 offset += s;
1881 } else {
1882 errfunc(ERR_PANIC, "internal instruction table corrupt"
1883 ": instruction code 0x%02X given", c);
1884 }
1885 }
1886 }
1887 }
1888
1889 static int32_t regflag(const operand * o)
1890 {
1891 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1892 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1893 }
1894 return nasm_reg_flags[o->basereg];
1895 }
1896
1897 static int32_t regval(const operand * o)
1898 {
1899 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1900 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1901 }
1902 return nasm_regvals[o->basereg];
1903 }
1904
1905 static int op_rexflags(const operand * o, int mask)
1906 {
1907 int32_t flags;
1908 int val;
1909
1910 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1911 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1912 }
1913
1914 flags = nasm_reg_flags[o->basereg];
1915 val = nasm_regvals[o->basereg];
1916
1917 return rexflags(val, flags, mask);
1918 }
1919
1920 static int rexflags(int val, int32_t flags, int mask)
1921 {
1922 int rex = 0;
1923
1924 if (val >= 8)
1925 rex |= REX_B|REX_X|REX_R;
1926 if (flags & BITS64)
1927 rex |= REX_W;
1928 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1929 rex |= REX_H;
1930 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1931 rex |= REX_P;
1932
1933 return rex & mask;
1934 }
1935
1936 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1937 {
1938 int i, size[MAX_OPERANDS], asize, oprs, ret;
1939
1940 ret = 100;
1941
1942 /*
1943 * Check the opcode
1944 */
1945 if (itemp->opcode != instruction->opcode)
1946 return 0;
1947
1948 /*
1949 * Count the operands
1950 */
1951 if (itemp->operands != instruction->operands)
1952 return 0;
1953
1954 /*
1955 * Check that no spurious colons or TOs are present
1956 */
1957 for (i = 0; i < itemp->operands; i++)
1958 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1959 return 0;
1960
1961 /*
1962 * Process size flags
1963 */
1964 if (itemp->flags & IF_ARMASK) {
1965 memset(size, 0, sizeof size);
1966
1967 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1968
1969 switch (itemp->flags & IF_SMASK) {
1970 case IF_SB:
1971 size[i] = BITS8;
1972 break;
1973 case IF_SW:
1974 size[i] = BITS16;
1975 break;
1976 case IF_SD:
1977 size[i] = BITS32;
1978 break;
1979 case IF_SQ:
1980 size[i] = BITS64;
1981 break;
1982 case IF_SO:
1983 size[i] = BITS128;
1984 break;
1985 case IF_SY:
1986 size[i] = BITS256;
1987 break;
1988 case IF_SZ:
1989 switch (bits) {
1990 case 16:
1991 size[i] = BITS16;
1992 break;
1993 case 32:
1994 size[i] = BITS32;
1995 break;
1996 case 64:
1997 size[i] = BITS64;
1998 break;
1999 }
2000 break;
2001 default:
2002 break;
2003 }
2004 } else {
2005 asize = 0;
2006 switch (itemp->flags & IF_SMASK) {
2007 case IF_SB:
2008 asize = BITS8;
2009 break;
2010 case IF_SW:
2011 asize = BITS16;
2012 break;
2013 case IF_SD:
2014 asize = BITS32;
2015 break;
2016 case IF_SQ:
2017 asize = BITS64;
2018 break;
2019 case IF_SO:
2020 asize = BITS128;
2021 break;
2022 case IF_SY:
2023 asize = BITS256;
2024 break;
2025 case IF_SZ:
2026 switch (bits) {
2027 case 16:
2028 asize = BITS16;
2029 break;
2030 case 32:
2031 asize = BITS32;
2032 break;
2033 case 64:
2034 asize = BITS64;
2035 break;
2036 }
2037 break;
2038 default:
2039 break;
2040 }
2041 for (i = 0; i < MAX_OPERANDS; i++)
2042 size[i] = asize;
2043 }
2044
2045 /*
2046 * Check that the operand flags all match up
2047 */
2048 for (i = 0; i < itemp->operands; i++) {
2049 int32_t type = instruction->oprs[i].type;
2050 if (!(type & SIZE_MASK))
2051 type |= size[i];
2052
2053 if (itemp->opd[i] & SAME_AS) {
2054 int j = itemp->opd[i] & ~SAME_AS;
2055 if (type != instruction->oprs[j].type ||
2056 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2057 return 0;
2058 } else if (itemp->opd[i] & ~type ||
2059 ((itemp->opd[i] & SIZE_MASK) &&
2060 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2061 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2062 (type & SIZE_MASK))
2063 return 0;
2064 else
2065 return 1;
2066 }
2067 }
2068
2069 /*
2070 * Check operand sizes
2071 */
2072 if (itemp->flags & (IF_SM | IF_SM2)) {
2073 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2074 asize = 0;
2075 for (i = 0; i < oprs; i++) {
2076 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2077 int j;
2078 for (j = 0; j < oprs; j++)
2079 size[j] = asize;
2080 break;
2081 }
2082 }
2083 } else {
2084 oprs = itemp->operands;
2085 }
2086
2087 for (i = 0; i < itemp->operands; i++) {
2088 if (!(itemp->opd[i] & SIZE_MASK) &&
2089 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2090 return 2;
2091 }
2092
2093 /*
2094 * Check template is okay at the set cpu level
2095 */
2096 if (((itemp->flags & IF_PLEVEL) > cpu))
2097 return 3;
2098
2099 /*
2100 * Check if instruction is available in long mode
2101 */
2102 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2103 return 4;
2104
2105 /*
2106 * Check if special handling needed for Jumps
2107 */
2108 if ((uint8_t)(itemp->code[0]) >= 0370)
2109 return 99;
2110
2111 return ret;
2112 }
2113
2114 static ea *process_ea(operand * input, ea * output, int bits,
2115 int addrbits, int rfield, int32_t rflags, int forw_ref)
2116 {
2117 output->rip = false;
2118
2119 /* REX flags for the rfield operand */
2120 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2121
2122 if (!(REGISTER & ~input->type)) { /* register direct */
2123 int i;
2124 int32_t f;
2125
2126 if (input->basereg < EXPR_REG_START /* Verify as Register */
2127 || input->basereg >= REG_ENUM_LIMIT)
2128 return NULL;
2129 f = regflag(input);
2130 i = nasm_regvals[input->basereg];
2131
2132 if (REG_EA & ~f)
2133 return NULL; /* Invalid EA register */
2134
2135 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2136
2137 output->sib_present = false; /* no SIB necessary */
2138 output->bytes = 0; /* no offset necessary either */
2139 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2140 } else { /* it's a memory reference */
2141 if (input->basereg == -1
2142 && (input->indexreg == -1 || input->scale == 0)) {
2143 /* it's a pure offset */
2144 if (bits == 64 && (~input->type & IP_REL)) {
2145 int scale, index, base;
2146 output->sib_present = true;
2147 scale = 0;
2148 index = 4;
2149 base = 5;
2150 output->sib = (scale << 6) | (index << 3) | base;
2151 output->bytes = 4;
2152 output->modrm = 4 | ((rfield & 7) << 3);
2153 output->rip = false;
2154 } else {
2155 output->sib_present = false;
2156 output->bytes = (addrbits != 16 ? 4 : 2);
2157 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2158 output->rip = bits == 64;
2159 }
2160 } else { /* it's an indirection */
2161 int i = input->indexreg, b = input->basereg, s = input->scale;
2162 int32_t o = input->offset, seg = input->segment;
2163 int hb = input->hintbase, ht = input->hinttype;
2164 int t;
2165 int it, bt;
2166 int32_t ix, bx; /* register flags */
2167
2168 if (s == 0)
2169 i = -1; /* make this easy, at least */
2170
2171 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2172 it = nasm_regvals[i];
2173 ix = nasm_reg_flags[i];
2174 } else {
2175 it = -1;
2176 ix = 0;
2177 }
2178
2179 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2180 bt = nasm_regvals[b];
2181 bx = nasm_reg_flags[b];
2182 } else {
2183 bt = -1;
2184 bx = 0;
2185 }
2186
2187 /* check for a 32/64-bit memory reference... */
2188 if ((ix|bx) & (BITS32|BITS64)) {
2189 /* it must be a 32/64-bit memory reference. Firstly we have
2190 * to check that all registers involved are type E/Rxx. */
2191 int32_t sok = BITS32|BITS64;
2192
2193 if (it != -1) {
2194 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2195 sok &= ix;
2196 else
2197 return NULL;
2198 }
2199
2200 if (bt != -1) {
2201 if (REG_GPR & ~bx)
2202 return NULL; /* Invalid register */
2203 if (~sok & bx & SIZE_MASK)
2204 return NULL; /* Invalid size */
2205 sok &= bx;
2206 }
2207
2208 /* While we're here, ensure the user didn't specify
2209 WORD or QWORD. */
2210 if (input->disp_size == 16 || input->disp_size == 64)
2211 return NULL;
2212
2213 if (addrbits == 16 ||
2214 (addrbits == 32 && !(sok & BITS32)) ||
2215 (addrbits == 64 && !(sok & BITS64)))
2216 return NULL;
2217
2218 /* now reorganize base/index */
2219 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2220 ((hb == b && ht == EAH_NOTBASE)
2221 || (hb == i && ht == EAH_MAKEBASE))) {
2222 /* swap if hints say so */
2223 t = bt, bt = it, it = t;
2224 t = bx, bx = ix, ix = t;
2225 }
2226 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2227 bt = -1, bx = 0, s++;
2228 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2229 /* make single reg base, unless hint */
2230 bt = it, bx = ix, it = -1, ix = 0;
2231 }
2232 if (((s == 2 && it != REG_NUM_ESP
2233 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2234 || s == 5 || s == 9) && bt == -1)
2235 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2236 if (it == -1 && (bt & 7) != REG_NUM_ESP
2237 && (input->eaflags & EAF_TIMESTWO))
2238 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2239 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2240 if (s == 1 && it == REG_NUM_ESP) {
2241 /* swap ESP into base if scale is 1 */
2242 t = it, it = bt, bt = t;
2243 t = ix, ix = bx, bx = t;
2244 }
2245 if (it == REG_NUM_ESP
2246 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2247 return NULL; /* wrong, for various reasons */
2248
2249 output->rex |= rexflags(it, ix, REX_X);
2250 output->rex |= rexflags(bt, bx, REX_B);
2251
2252 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2253 /* no SIB needed */
2254 int mod, rm;
2255
2256 if (bt == -1) {
2257 rm = 5;
2258 mod = 0;
2259 } else {
2260 rm = (bt & 7);
2261 if (rm != REG_NUM_EBP && o == 0 &&
2262 seg == NO_SEG && !forw_ref &&
2263 !(input->eaflags &
2264 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2265 mod = 0;
2266 else if (input->eaflags & EAF_BYTEOFFS ||
2267 (o >= -128 && o <= 127 && seg == NO_SEG
2268 && !forw_ref
2269 && !(input->eaflags & EAF_WORDOFFS)))
2270 mod = 1;
2271 else
2272 mod = 2;
2273 }
2274
2275 output->sib_present = false;
2276 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2277 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2278 } else {
2279 /* we need a SIB */
2280 int mod, scale, index, base;
2281
2282 if (it == -1)
2283 index = 4, s = 1;
2284 else
2285 index = (it & 7);
2286
2287 switch (s) {
2288 case 1:
2289 scale = 0;
2290 break;
2291 case 2:
2292 scale = 1;
2293 break;
2294 case 4:
2295 scale = 2;
2296 break;
2297 case 8:
2298 scale = 3;
2299 break;
2300 default: /* then what the smeg is it? */
2301 return NULL; /* panic */
2302 }
2303
2304 if (bt == -1) {
2305 base = 5;
2306 mod = 0;
2307 } else {
2308 base = (bt & 7);
2309 if (base != REG_NUM_EBP && o == 0 &&
2310 seg == NO_SEG && !forw_ref &&
2311 !(input->eaflags &
2312 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2313 mod = 0;
2314 else if (input->eaflags & EAF_BYTEOFFS ||
2315 (o >= -128 && o <= 127 && seg == NO_SEG
2316 && !forw_ref
2317 && !(input->eaflags & EAF_WORDOFFS)))
2318 mod = 1;
2319 else
2320 mod = 2;
2321 }
2322
2323 output->sib_present = true;
2324 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2325 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2326 output->sib = (scale << 6) | (index << 3) | base;
2327 }
2328 } else { /* it's 16-bit */
2329 int mod, rm;
2330
2331 /* check for 64-bit long mode */
2332 if (addrbits == 64)
2333 return NULL;
2334
2335 /* check all registers are BX, BP, SI or DI */
2336 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2337 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2338 && i != R_SI && i != R_DI))
2339 return NULL;
2340
2341 /* ensure the user didn't specify DWORD/QWORD */
2342 if (input->disp_size == 32 || input->disp_size == 64)
2343 return NULL;
2344
2345 if (s != 1 && i != -1)
2346 return NULL; /* no can do, in 16-bit EA */
2347 if (b == -1 && i != -1) {
2348 int tmp = b;
2349 b = i;
2350 i = tmp;
2351 } /* swap */
2352 if ((b == R_SI || b == R_DI) && i != -1) {
2353 int tmp = b;
2354 b = i;
2355 i = tmp;
2356 }
2357 /* have BX/BP as base, SI/DI index */
2358 if (b == i)
2359 return NULL; /* shouldn't ever happen, in theory */
2360 if (i != -1 && b != -1 &&
2361 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2362 return NULL; /* invalid combinations */
2363 if (b == -1) /* pure offset: handled above */
2364 return NULL; /* so if it gets to here, panic! */
2365
2366 rm = -1;
2367 if (i != -1)
2368 switch (i * 256 + b) {
2369 case R_SI * 256 + R_BX:
2370 rm = 0;
2371 break;
2372 case R_DI * 256 + R_BX:
2373 rm = 1;
2374 break;
2375 case R_SI * 256 + R_BP:
2376 rm = 2;
2377 break;
2378 case R_DI * 256 + R_BP:
2379 rm = 3;
2380 break;
2381 } else
2382 switch (b) {
2383 case R_SI:
2384 rm = 4;
2385 break;
2386 case R_DI:
2387 rm = 5;
2388 break;
2389 case R_BP:
2390 rm = 6;
2391 break;
2392 case R_BX:
2393 rm = 7;
2394 break;
2395 }
2396 if (rm == -1) /* can't happen, in theory */
2397 return NULL; /* so panic if it does */
2398
2399 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2400 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2401 mod = 0;
2402 else if (input->eaflags & EAF_BYTEOFFS ||
2403 (o >= -128 && o <= 127 && seg == NO_SEG
2404 && !forw_ref
2405 && !(input->eaflags & EAF_WORDOFFS)))
2406 mod = 1;
2407 else
2408 mod = 2;
2409
2410 output->sib_present = false; /* no SIB - it's 16-bit */
2411 output->bytes = mod; /* bytes of offset needed */
2412 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2413 }
2414 }
2415 }
2416
2417 output->size = 1 + output->sib_present + output->bytes;
2418 return output;
2419 }
2420
2421 static void add_asp(insn *ins, int addrbits)
2422 {
2423 int j, valid;
2424 int defdisp;
2425
2426 valid = (addrbits == 64) ? 64|32 : 32|16;
2427
2428 switch (ins->prefixes[PPS_ASIZE]) {
2429 case P_A16:
2430 valid &= 16;
2431 break;
2432 case P_A32:
2433 valid &= 32;
2434 break;
2435 case P_A64:
2436 valid &= 64;
2437 break;
2438 case P_ASP:
2439 valid &= (addrbits == 32) ? 16 : 32;
2440 break;
2441 default:
2442 break;
2443 }
2444
2445 for (j = 0; j < ins->operands; j++) {
2446 if (!(MEMORY & ~ins->oprs[j].type)) {
2447 int32_t i, b;
2448
2449 /* Verify as Register */
2450 if (ins->oprs[j].indexreg < EXPR_REG_START
2451 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2452 i = 0;
2453 else
2454 i = nasm_reg_flags[ins->oprs[j].indexreg];
2455
2456 /* Verify as Register */
2457 if (ins->oprs[j].basereg < EXPR_REG_START
2458 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2459 b = 0;
2460 else
2461 b = nasm_reg_flags[ins->oprs[j].basereg];
2462
2463 if (ins->oprs[j].scale == 0)
2464 i = 0;
2465
2466 if (!i && !b) {
2467 int ds = ins->oprs[j].disp_size;
2468 if ((addrbits != 64 && ds > 8) ||
2469 (addrbits == 64 && ds == 16))
2470 valid &= ds;
2471 } else {
2472 if (!(REG16 & ~b))
2473 valid &= 16;
2474 if (!(REG32 & ~b))
2475 valid &= 32;
2476 if (!(REG64 & ~b))
2477 valid &= 64;
2478
2479 if (!(REG16 & ~i))
2480 valid &= 16;
2481 if (!(REG32 & ~i))
2482 valid &= 32;
2483 if (!(REG64 & ~i))
2484 valid &= 64;
2485 }
2486 }
2487 }
2488
2489 if (valid & addrbits) {
2490 ins->addr_size = addrbits;
2491 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2492 /* Add an address size prefix */
2493 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2494 ins->prefixes[PPS_ASIZE] = pref;
2495 ins->addr_size = (addrbits == 32) ? 16 : 32;
2496 } else {
2497 /* Impossible... */
2498 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2499 ins->addr_size = addrbits; /* Error recovery */
2500 }
2501
2502 defdisp = ins->addr_size == 16 ? 16 : 32;
2503
2504 for (j = 0; j < ins->operands; j++) {
2505 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2506 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2507 != ins->addr_size) {
2508 /* mem_offs sizes must match the address size; if not,
2509 strip the MEM_OFFS bit and match only EA instructions */
2510 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2511 }
2512 }
2513 }
Adding AVX-512 features