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MPX: Add MPX instructions
[nasm/avx512.git] / assemble.c
blob5a1602ee0533aca05fc8afdc8cc1fdabf33864ea
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
170 */
171
172 #include "compiler.h"
173
174 #include <stdio.h>
175 #include <string.h>
176 #include <inttypes.h>
177
178 #include "nasm.h"
179 #include "nasmlib.h"
180 #include "assemble.h"
181 #include "insns.h"
182 #include "tables.h"
183
184 enum match_result {
185 /*
186 * Matching errors. These should be sorted so that more specific
187 * errors come later in the sequence.
188 */
189 MERR_INVALOP,
190 MERR_OPSIZEMISSING,
191 MERR_OPSIZEMISMATCH,
192 MERR_BADCPU,
193 MERR_BADMODE,
194 MERR_BADHLE,
195 MERR_ENCMISMATCH,
196 /*
197 * Matching success; the conditional ones first
198 */
199 MOK_JUMP, /* Matching OK but needs jmp_match() */
200 MOK_GOOD /* Matching unconditionally OK */
201 };
202
203 typedef struct {
204 enum ea_type type; /* what kind of EA is this? */
205 int sib_present; /* is a SIB byte necessary? */
206 int bytes; /* # of bytes of offset needed */
207 int size; /* lazy - this is sib+bytes+1 */
208 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
209 int8_t disp8; /* compressed displacement for EVEX */
210 } ea;
211
212 #define GEN_SIB(scale, index, base) \
213 (((scale) << 6) | ((index) << 3) | ((base)))
214
215 #define GEN_MODRM(mod, reg, rm) \
216 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
217
218 static iflags_t cpu; /* cpu level received from nasm.c */
219 static efunc errfunc;
220 static struct ofmt *outfmt;
221 static ListGen *list;
222
223 static int64_t calcsize(int32_t, int64_t, int, insn *,
224 const struct itemplate *);
225 static void gencode(int32_t segment, int64_t offset, int bits,
226 insn * ins, const struct itemplate *temp,
227 int64_t insn_end);
228 static enum match_result find_match(const struct itemplate **tempp,
229 insn *instruction,
230 int32_t segment, int64_t offset, int bits);
231 static enum match_result matches(const struct itemplate *, insn *, int bits);
232 static opflags_t regflag(const operand *);
233 static int32_t regval(const operand *);
234 static int rexflags(int, opflags_t, int);
235 static int op_rexflags(const operand *, int);
236 static int op_evexflags(const operand *, int, uint8_t);
237 static void add_asp(insn *, int);
238
239 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
240
241 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
242 {
243 return ins->prefixes[pos] == prefix;
244 }
245
246 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
247 {
248 if (ins->prefixes[pos])
249 errfunc(ERR_NONFATAL, "invalid %s prefix",
250 prefix_name(ins->prefixes[pos]));
251 }
252
253 static const char *size_name(int size)
254 {
255 switch (size) {
256 case 1:
257 return "byte";
258 case 2:
259 return "word";
260 case 4:
261 return "dword";
262 case 8:
263 return "qword";
264 case 10:
265 return "tword";
266 case 16:
267 return "oword";
268 case 32:
269 return "yword";
270 case 64:
271 return "zword";
272 default:
273 return "???";
274 }
275 }
276
277 static void warn_overflow(int pass, int size)
278 {
279 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
280 "%s data exceeds bounds", size_name(size));
281 }
282
283 static void warn_overflow_const(int64_t data, int size)
284 {
285 if (overflow_general(data, size))
286 warn_overflow(ERR_PASS1, size);
287 }
288
289 static void warn_overflow_opd(const struct operand *o, int size)
290 {
291 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
292 if (overflow_general(o->offset, size))
293 warn_overflow(ERR_PASS2, size);
294 }
295 }
296
297 /*
298 * This routine wrappers the real output format's output routine,
299 * in order to pass a copy of the data off to the listing file
300 * generator at the same time.
301 */
302 static void out(int64_t offset, int32_t segto, const void *data,
303 enum out_type type, uint64_t size,
304 int32_t segment, int32_t wrt)
305 {
306 static int32_t lineno = 0; /* static!!! */
307 static char *lnfname = NULL;
308 uint8_t p[8];
309
310 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
311 /*
312 * This is a non-relocated address, and we're going to
313 * convert it into RAWDATA format.
314 */
315 uint8_t *q = p;
316
317 if (size > 8) {
318 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
319 return;
320 }
321
322 WRITEADDR(q, *(int64_t *)data, size);
323 data = p;
324 type = OUT_RAWDATA;
325 }
326
327 list->output(offset, data, type, size);
328
329 /*
330 * this call to src_get determines when we call the
331 * debug-format-specific "linenum" function
332 * it updates lineno and lnfname to the current values
333 * returning 0 if "same as last time", -2 if lnfname
334 * changed, and the amount by which lineno changed,
335 * if it did. thus, these variables must be static
336 */
337
338 if (src_get(&lineno, &lnfname))
339 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
340
341 outfmt->output(segto, data, type, size, segment, wrt);
342 }
343
344 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
345 {
346 if (opx->segment != NO_SEG) {
347 uint64_t data = opx->offset;
348 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
349 } else {
350 uint8_t byte = opx->offset;
351 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
352 }
353 }
354
355 static bool jmp_match(int32_t segment, int64_t offset, int bits,
356 insn * ins, const struct itemplate *temp)
357 {
358 int64_t isize;
359 const uint8_t *code = temp->code;
360 uint8_t c = code[0];
361
362 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
363 return false;
364 if (!optimizing)
365 return false;
366 if (optimizing < 0 && c == 0371)
367 return false;
368
369 isize = calcsize(segment, offset, bits, ins, temp);
370
371 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
372 /* Be optimistic in pass 1 */
373 return true;
374
375 if (ins->oprs[0].segment != segment)
376 return false;
377
378 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
379 return (isize >= -128 && isize <= 127); /* is it byte size? */
380 }
381
382 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
383 insn * instruction, struct ofmt *output, efunc error,
384 ListGen * listgen)
385 {
386 const struct itemplate *temp;
387 int j;
388 enum match_result m;
389 int64_t insn_end;
390 int32_t itimes;
391 int64_t start = offset;
392 int64_t wsize; /* size for DB etc. */
393
394 errfunc = error; /* to pass to other functions */
395 cpu = cp;
396 outfmt = output; /* likewise */
397 list = listgen; /* and again */
398
399 wsize = idata_bytes(instruction->opcode);
400 if (wsize == -1)
401 return 0;
402
403 if (wsize) {
404 extop *e;
405 int32_t t = instruction->times;
406 if (t < 0)
407 errfunc(ERR_PANIC,
408 "instruction->times < 0 (%ld) in assemble()", t);
409
410 while (t--) { /* repeat TIMES times */
411 list_for_each(e, instruction->eops) {
412 if (e->type == EOT_DB_NUMBER) {
413 if (wsize > 8) {
414 errfunc(ERR_NONFATAL,
415 "integer supplied to a DT, DO or DY"
416 " instruction");
417 } else {
418 out(offset, segment, &e->offset,
419 OUT_ADDRESS, wsize, e->segment, e->wrt);
420 offset += wsize;
421 }
422 } else if (e->type == EOT_DB_STRING ||
423 e->type == EOT_DB_STRING_FREE) {
424 int align;
425
426 out(offset, segment, e->stringval,
427 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
428 align = e->stringlen % wsize;
429
430 if (align) {
431 align = wsize - align;
432 out(offset, segment, zero_buffer,
433 OUT_RAWDATA, align, NO_SEG, NO_SEG);
434 }
435 offset += e->stringlen + align;
436 }
437 }
438 if (t > 0 && t == instruction->times - 1) {
439 /*
440 * Dummy call to list->output to give the offset to the
441 * listing module.
442 */
443 list->output(offset, NULL, OUT_RAWDATA, 0);
444 list->uplevel(LIST_TIMES);
445 }
446 }
447 if (instruction->times > 1)
448 list->downlevel(LIST_TIMES);
449 return offset - start;
450 }
451
452 if (instruction->opcode == I_INCBIN) {
453 const char *fname = instruction->eops->stringval;
454 FILE *fp;
455
456 fp = fopen(fname, "rb");
457 if (!fp) {
458 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
459 fname);
460 } else if (fseek(fp, 0L, SEEK_END) < 0) {
461 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
462 fname);
463 fclose(fp);
464 } else {
465 static char buf[4096];
466 size_t t = instruction->times;
467 size_t base = 0;
468 size_t len;
469
470 len = ftell(fp);
471 if (instruction->eops->next) {
472 base = instruction->eops->next->offset;
473 len -= base;
474 if (instruction->eops->next->next &&
475 len > (size_t)instruction->eops->next->next->offset)
476 len = (size_t)instruction->eops->next->next->offset;
477 }
478 /*
479 * Dummy call to list->output to give the offset to the
480 * listing module.
481 */
482 list->output(offset, NULL, OUT_RAWDATA, 0);
483 list->uplevel(LIST_INCBIN);
484 while (t--) {
485 size_t l;
486
487 fseek(fp, base, SEEK_SET);
488 l = len;
489 while (l > 0) {
490 int32_t m;
491 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
492 if (!m) {
493 /*
494 * This shouldn't happen unless the file
495 * actually changes while we are reading
496 * it.
497 */
498 error(ERR_NONFATAL,
499 "`incbin': unexpected EOF while"
500 " reading file `%s'", fname);
501 t = 0; /* Try to exit cleanly */
502 break;
503 }
504 out(offset, segment, buf, OUT_RAWDATA, m,
505 NO_SEG, NO_SEG);
506 l -= m;
507 }
508 }
509 list->downlevel(LIST_INCBIN);
510 if (instruction->times > 1) {
511 /*
512 * Dummy call to list->output to give the offset to the
513 * listing module.
514 */
515 list->output(offset, NULL, OUT_RAWDATA, 0);
516 list->uplevel(LIST_TIMES);
517 list->downlevel(LIST_TIMES);
518 }
519 fclose(fp);
520 return instruction->times * len;
521 }
522 return 0; /* if we're here, there's an error */
523 }
524
525 /* Check to see if we need an address-size prefix */
526 add_asp(instruction, bits);
527
528 m = find_match(&temp, instruction, segment, offset, bits);
529
530 if (m == MOK_GOOD) {
531 /* Matches! */
532 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
533 itimes = instruction->times;
534 if (insn_size < 0) /* shouldn't be, on pass two */
535 error(ERR_PANIC, "errors made it through from pass one");
536 else
537 while (itimes--) {
538 for (j = 0; j < MAXPREFIX; j++) {
539 uint8_t c = 0;
540 switch (instruction->prefixes[j]) {
541 case P_WAIT:
542 c = 0x9B;
543 break;
544 case P_LOCK:
545 c = 0xF0;
546 break;
547 case P_REPNE:
548 case P_REPNZ:
549 case P_XACQUIRE:
550 c = 0xF2;
551 break;
552 case P_REPE:
553 case P_REPZ:
554 case P_REP:
555 case P_XRELEASE:
556 c = 0xF3;
557 break;
558 case R_CS:
559 if (bits == 64) {
560 error(ERR_WARNING | ERR_PASS2,
561 "cs segment base generated, but will be ignored in 64-bit mode");
562 }
563 c = 0x2E;
564 break;
565 case R_DS:
566 if (bits == 64) {
567 error(ERR_WARNING | ERR_PASS2,
568 "ds segment base generated, but will be ignored in 64-bit mode");
569 }
570 c = 0x3E;
571 break;
572 case R_ES:
573 if (bits == 64) {
574 error(ERR_WARNING | ERR_PASS2,
575 "es segment base generated, but will be ignored in 64-bit mode");
576 }
577 c = 0x26;
578 break;
579 case R_FS:
580 c = 0x64;
581 break;
582 case R_GS:
583 c = 0x65;
584 break;
585 case R_SS:
586 if (bits == 64) {
587 error(ERR_WARNING | ERR_PASS2,
588 "ss segment base generated, but will be ignored in 64-bit mode");
589 }
590 c = 0x36;
591 break;
592 case R_SEGR6:
593 case R_SEGR7:
594 error(ERR_NONFATAL,
595 "segr6 and segr7 cannot be used as prefixes");
596 break;
597 case P_A16:
598 if (bits == 64) {
599 error(ERR_NONFATAL,
600 "16-bit addressing is not supported "
601 "in 64-bit mode");
602 } else if (bits != 16)
603 c = 0x67;
604 break;
605 case P_A32:
606 if (bits != 32)
607 c = 0x67;
608 break;
609 case P_A64:
610 if (bits != 64) {
611 error(ERR_NONFATAL,
612 "64-bit addressing is only supported "
613 "in 64-bit mode");
614 }
615 break;
616 case P_ASP:
617 c = 0x67;
618 break;
619 case P_O16:
620 if (bits != 16)
621 c = 0x66;
622 break;
623 case P_O32:
624 if (bits == 16)
625 c = 0x66;
626 break;
627 case P_O64:
628 /* REX.W */
629 break;
630 case P_OSP:
631 c = 0x66;
632 break;
633 case P_none:
634 break;
635 default:
636 error(ERR_PANIC, "invalid instruction prefix");
637 }
638 if (c != 0) {
639 out(offset, segment, &c, OUT_RAWDATA, 1,
640 NO_SEG, NO_SEG);
641 offset++;
642 }
643 }
644 insn_end = offset + insn_size;
645 gencode(segment, offset, bits, instruction,
646 temp, insn_end);
647 offset += insn_size;
648 if (itimes > 0 && itimes == instruction->times - 1) {
649 /*
650 * Dummy call to list->output to give the offset to the
651 * listing module.
652 */
653 list->output(offset, NULL, OUT_RAWDATA, 0);
654 list->uplevel(LIST_TIMES);
655 }
656 }
657 if (instruction->times > 1)
658 list->downlevel(LIST_TIMES);
659 return offset - start;
660 } else {
661 /* No match */
662 switch (m) {
663 case MERR_OPSIZEMISSING:
664 error(ERR_NONFATAL, "operation size not specified");
665 break;
666 case MERR_OPSIZEMISMATCH:
667 error(ERR_NONFATAL, "mismatch in operand sizes");
668 break;
669 case MERR_BADCPU:
670 error(ERR_NONFATAL, "no instruction for this cpu level");
671 break;
672 case MERR_BADMODE:
673 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
674 bits);
675 break;
676 default:
677 error(ERR_NONFATAL,
678 "invalid combination of opcode and operands");
679 break;
680 }
681 }
682 return 0;
683 }
684
685 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
686 insn * instruction, efunc error)
687 {
688 const struct itemplate *temp;
689 enum match_result m;
690
691 errfunc = error; /* to pass to other functions */
692 cpu = cp;
693
694 if (instruction->opcode == I_none)
695 return 0;
696
697 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
698 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
699 instruction->opcode == I_DT || instruction->opcode == I_DO ||
700 instruction->opcode == I_DY) {
701 extop *e;
702 int32_t isize, osize, wsize;
703
704 isize = 0;
705 wsize = idata_bytes(instruction->opcode);
706
707 list_for_each(e, instruction->eops) {
708 int32_t align;
709
710 osize = 0;
711 if (e->type == EOT_DB_NUMBER) {
712 osize = 1;
713 warn_overflow_const(e->offset, wsize);
714 } else if (e->type == EOT_DB_STRING ||
715 e->type == EOT_DB_STRING_FREE)
716 osize = e->stringlen;
717
718 align = (-osize) % wsize;
719 if (align < 0)
720 align += wsize;
721 isize += osize + align;
722 }
723 return isize * instruction->times;
724 }
725
726 if (instruction->opcode == I_INCBIN) {
727 const char *fname = instruction->eops->stringval;
728 FILE *fp;
729 int64_t val = 0;
730 size_t len;
731
732 fp = fopen(fname, "rb");
733 if (!fp)
734 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
735 fname);
736 else if (fseek(fp, 0L, SEEK_END) < 0)
737 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
738 fname);
739 else {
740 len = ftell(fp);
741 if (instruction->eops->next) {
742 len -= instruction->eops->next->offset;
743 if (instruction->eops->next->next &&
744 len > (size_t)instruction->eops->next->next->offset) {
745 len = (size_t)instruction->eops->next->next->offset;
746 }
747 }
748 val = instruction->times * len;
749 }
750 if (fp)
751 fclose(fp);
752 return val;
753 }
754
755 /* Check to see if we need an address-size prefix */
756 add_asp(instruction, bits);
757
758 m = find_match(&temp, instruction, segment, offset, bits);
759 if (m == MOK_GOOD) {
760 /* we've matched an instruction. */
761 int64_t isize;
762 int j;
763
764 isize = calcsize(segment, offset, bits, instruction, temp);
765 if (isize < 0)
766 return -1;
767 for (j = 0; j < MAXPREFIX; j++) {
768 switch (instruction->prefixes[j]) {
769 case P_A16:
770 if (bits != 16)
771 isize++;
772 break;
773 case P_A32:
774 if (bits != 32)
775 isize++;
776 break;
777 case P_O16:
778 if (bits != 16)
779 isize++;
780 break;
781 case P_O32:
782 if (bits == 16)
783 isize++;
784 break;
785 case P_A64:
786 case P_O64:
787 case P_none:
788 break;
789 default:
790 isize++;
791 break;
792 }
793 }
794 return isize * instruction->times;
795 } else {
796 return -1; /* didn't match any instruction */
797 }
798 }
799
800 static void bad_hle_warn(const insn * ins, uint8_t hleok)
801 {
802 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
803 enum whatwarn { w_none, w_lock, w_inval } ww;
804 static const enum whatwarn warn[2][4] =
805 {
806 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
807 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
808 };
809 unsigned int n;
810
811 n = (unsigned int)rep_pfx - P_XACQUIRE;
812 if (n > 1)
813 return; /* Not XACQUIRE/XRELEASE */
814
815 ww = warn[n][hleok];
816 if (!is_class(MEMORY, ins->oprs[0].type))
817 ww = w_inval; /* HLE requires operand 0 to be memory */
818
819 switch (ww) {
820 case w_none:
821 break;
822
823 case w_lock:
824 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
825 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
826 "%s with this instruction requires lock",
827 prefix_name(rep_pfx));
828 }
829 break;
830
831 case w_inval:
832 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
833 "%s invalid with this instruction",
834 prefix_name(rep_pfx));
835 break;
836 }
837 }
838
839 /* Common construct */
840 #define case3(x) case (x): case (x)+1: case (x)+2
841 #define case4(x) case3(x): case (x)+3
842
843 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
844 insn * ins, const struct itemplate *temp)
845 {
846 const uint8_t *codes = temp->code;
847 int64_t length = 0;
848 uint8_t c;
849 int rex_mask = ~0;
850 int op1, op2;
851 struct operand *opx;
852 uint8_t opex = 0;
853 enum ea_type eat;
854 uint8_t hleok = 0;
855 bool lockcheck = true;
856 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
857
858 ins->rex = 0; /* Ensure REX is reset */
859 eat = EA_SCALAR; /* Expect a scalar EA */
860 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
861
862 if (ins->prefixes[PPS_OSIZE] == P_O64)
863 ins->rex |= REX_W;
864
865 (void)segment; /* Don't warn that this parameter is unused */
866 (void)offset; /* Don't warn that this parameter is unused */
867
868 while (*codes) {
869 c = *codes++;
870 op1 = (c & 3) + ((opex & 1) << 2);
871 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
872 opx = &ins->oprs[op1];
873 opex = 0; /* For the next iteration */
874
875 switch (c) {
876 case4(01):
877 codes += c, length += c;
878 break;
879
880 case3(05):
881 opex = c;
882 break;
883
884 case4(010):
885 ins->rex |=
886 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
887 codes++, length++;
888 break;
889
890 case4(014):
891 /* this is an index reg of MIB operand */
892 mib_index = opx->basereg;
893 break;
894
895 case4(020):
896 case4(024):
897 length++;
898 break;
899
900 case4(030):
901 length += 2;
902 break;
903
904 case4(034):
905 if (opx->type & (BITS16 | BITS32 | BITS64))
906 length += (opx->type & BITS16) ? 2 : 4;
907 else
908 length += (bits == 16) ? 2 : 4;
909 break;
910
911 case4(040):
912 length += 4;
913 break;
914
915 case4(044):
916 length += ins->addr_size >> 3;
917 break;
918
919 case4(050):
920 length++;
921 break;
922
923 case4(054):
924 length += 8; /* MOV reg64/imm */
925 break;
926
927 case4(060):
928 length += 2;
929 break;
930
931 case4(064):
932 if (opx->type & (BITS16 | BITS32 | BITS64))
933 length += (opx->type & BITS16) ? 2 : 4;
934 else
935 length += (bits == 16) ? 2 : 4;
936 break;
937
938 case4(070):
939 length += 4;
940 break;
941
942 case4(074):
943 length += 2;
944 break;
945
946 case 0172:
947 case 0173:
948 codes++;
949 length++;
950 break;
951
952 case4(0174):
953 length++;
954 break;
955
956 case4(0240):
957 ins->rex |= REX_EV;
958 ins->vexreg = regval(opx);
959 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
960 ins->vex_cm = *codes++;
961 ins->vex_wlp = *codes++;
962 ins->evex_tuple = (*codes++ - 0300);
963 break;
964
965 case 0250:
966 ins->rex |= REX_EV;
967 ins->vexreg = 0;
968 ins->vex_cm = *codes++;
969 ins->vex_wlp = *codes++;
970 ins->evex_tuple = (*codes++ - 0300);
971 break;
972
973 case4(0254):
974 length += 4;
975 break;
976
977 case4(0260):
978 ins->rex |= REX_V;
979 ins->vexreg = regval(opx);
980 ins->vex_cm = *codes++;
981 ins->vex_wlp = *codes++;
982 break;
983
984 case 0270:
985 ins->rex |= REX_V;
986 ins->vexreg = 0;
987 ins->vex_cm = *codes++;
988 ins->vex_wlp = *codes++;
989 break;
990
991 case3(0271):
992 hleok = c & 3;
993 break;
994
995 case4(0274):
996 length++;
997 break;
998
999 case4(0300):
1000 break;
1001
1002 case 0310:
1003 if (bits == 64)
1004 return -1;
1005 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1006 break;
1007
1008 case 0311:
1009 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1010 break;
1011
1012 case 0312:
1013 break;
1014
1015 case 0313:
1016 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1017 has_prefix(ins, PPS_ASIZE, P_A32))
1018 return -1;
1019 break;
1020
1021 case4(0314):
1022 break;
1023
1024 case 0320:
1025 {
1026 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1027 if (pfx == P_O16)
1028 break;
1029 if (pfx != P_none)
1030 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1031 else
1032 ins->prefixes[PPS_OSIZE] = P_O16;
1033 break;
1034 }
1035
1036 case 0321:
1037 {
1038 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1039 if (pfx == P_O32)
1040 break;
1041 if (pfx != P_none)
1042 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1043 else
1044 ins->prefixes[PPS_OSIZE] = P_O32;
1045 break;
1046 }
1047
1048 case 0322:
1049 break;
1050
1051 case 0323:
1052 rex_mask &= ~REX_W;
1053 break;
1054
1055 case 0324:
1056 ins->rex |= REX_W;
1057 break;
1058
1059 case 0325:
1060 ins->rex |= REX_NH;
1061 break;
1062
1063 case 0326:
1064 break;
1065
1066 case 0330:
1067 codes++, length++;
1068 break;
1069
1070 case 0331:
1071 break;
1072
1073 case 0332:
1074 case 0333:
1075 length++;
1076 break;
1077
1078 case 0334:
1079 ins->rex |= REX_L;
1080 break;
1081
1082 case 0335:
1083 break;
1084
1085 case 0336:
1086 if (!ins->prefixes[PPS_REP])
1087 ins->prefixes[PPS_REP] = P_REP;
1088 break;
1089
1090 case 0337:
1091 if (!ins->prefixes[PPS_REP])
1092 ins->prefixes[PPS_REP] = P_REPNE;
1093 break;
1094
1095 case 0340:
1096 if (ins->oprs[0].segment != NO_SEG)
1097 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1098 " quantity of BSS space");
1099 else
1100 length += ins->oprs[0].offset;
1101 break;
1102
1103 case 0341:
1104 if (!ins->prefixes[PPS_WAIT])
1105 ins->prefixes[PPS_WAIT] = P_WAIT;
1106 break;
1107
1108 case 0360:
1109 break;
1110
1111 case 0361:
1112 length++;
1113 break;
1114
1115 case 0364:
1116 case 0365:
1117 break;
1118
1119 case 0366:
1120 case 0367:
1121 length++;
1122 break;
1123
1124 case3(0370):
1125 break;
1126
1127 case 0373:
1128 length++;
1129 break;
1130
1131 case 0374:
1132 eat = EA_XMMVSIB;
1133 break;
1134
1135 case 0375:
1136 eat = EA_YMMVSIB;
1137 break;
1138
1139 case 0376:
1140 eat = EA_ZMMVSIB;
1141 break;
1142
1143 case4(0100):
1144 case4(0110):
1145 case4(0120):
1146 case4(0130):
1147 case4(0200):
1148 case4(0204):
1149 case4(0210):
1150 case4(0214):
1151 case4(0220):
1152 case4(0224):
1153 case4(0230):
1154 case4(0234):
1155 {
1156 ea ea_data;
1157 int rfield;
1158 opflags_t rflags;
1159 struct operand *opy = &ins->oprs[op2];
1160 struct operand *op_er_sae;
1161
1162 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1163
1164 if (c <= 0177) {
1165 /* pick rfield from operand b (opx) */
1166 rflags = regflag(opx);
1167 rfield = nasm_regvals[opx->basereg];
1168 } else {
1169 rflags = 0;
1170 rfield = c & 7;
1171 }
1172
1173 /* EVEX.b1 : evex_brerop contains the operand position */
1174 op_er_sae = (ins->evex_brerop >= 0 ?
1175 &ins->oprs[ins->evex_brerop] : NULL);
1176
1177 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1178 /* set EVEX.b */
1179 ins->evex_p[2] |= EVEX_P2B;
1180 if (op_er_sae->decoflags & ER) {
1181 /* set EVEX.RC (rounding control) */
1182 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1183 & EVEX_P2RC;
1184 }
1185 } else {
1186 /* set EVEX.L'L (vector length) */
1187 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1188 if (opy->decoflags & BRDCAST_MASK) {
1189 /* set EVEX.b */
1190 ins->evex_p[2] |= EVEX_P2B;
1191 }
1192 }
1193
1194 /*
1195 * if a separate form of MIB (ICC style) is used,
1196 * the index reg info is merged into mem operand
1197 */
1198 if (mib_index != R_none) {
1199 opy->indexreg = mib_index;
1200 opy->scale = 1;
1201 opy->hintbase = mib_index;
1202 opy->hinttype = EAH_NOTBASE;
1203 }
1204
1205 if (process_ea(opy, &ea_data, bits,
1206 rfield, rflags, ins) != eat) {
1207 errfunc(ERR_NONFATAL, "invalid effective address");
1208 return -1;
1209 } else {
1210 ins->rex |= ea_data.rex;
1211 length += ea_data.size;
1212 }
1213 }
1214 break;
1215
1216 default:
1217 errfunc(ERR_PANIC, "internal instruction table corrupt"
1218 ": instruction code \\%o (0x%02X) given", c, c);
1219 break;
1220 }
1221 }
1222
1223 ins->rex &= rex_mask;
1224
1225 if (ins->rex & REX_NH) {
1226 if (ins->rex & REX_H) {
1227 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1228 return -1;
1229 }
1230 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1231 }
1232
1233 if (ins->rex & (REX_V | REX_EV)) {
1234 int bad32 = REX_R|REX_W|REX_X|REX_B;
1235
1236 if (ins->rex & REX_H) {
1237 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1238 return -1;
1239 }
1240 switch (ins->vex_wlp & 060) {
1241 case 000:
1242 case 040:
1243 ins->rex &= ~REX_W;
1244 break;
1245 case 020:
1246 ins->rex |= REX_W;
1247 bad32 &= ~REX_W;
1248 break;
1249 case 060:
1250 /* Follow REX_W */
1251 break;
1252 }
1253
1254 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1255 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1256 return -1;
1257 } else if (!(ins->rex & REX_EV) &&
1258 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1259 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1260 return -1;
1261 }
1262 if (ins->rex & REX_EV)
1263 length += 4;
1264 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1265 length += 3;
1266 else
1267 length += 2;
1268 } else if (ins->rex & REX_REAL) {
1269 if (ins->rex & REX_H) {
1270 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1271 return -1;
1272 } else if (bits == 64) {
1273 length++;
1274 } else if ((ins->rex & REX_L) &&
1275 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1276 cpu >= IF_X86_64) {
1277 /* LOCK-as-REX.R */
1278 assert_no_prefix(ins, PPS_LOCK);
1279 lockcheck = false; /* Already errored, no need for warning */
1280 length++;
1281 } else {
1282 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1283 return -1;
1284 }
1285 }
1286
1287 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1288 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1289 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1290 "instruction is not lockable");
1291 }
1292
1293 bad_hle_warn(ins, hleok);
1294
1295 return length;
1296 }
1297
1298 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1299 {
1300 if (bits == 64) {
1301 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1302 ins->rex = (ins->rex & REX_REAL) | REX_P;
1303 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1304 ins->rex = 0;
1305 return 1;
1306 }
1307 }
1308
1309 return 0;
1310 }
1311
1312 static void gencode(int32_t segment, int64_t offset, int bits,
1313 insn * ins, const struct itemplate *temp,
1314 int64_t insn_end)
1315 {
1316 uint8_t c;
1317 uint8_t bytes[4];
1318 int64_t size;
1319 int64_t data;
1320 int op1, op2;
1321 struct operand *opx;
1322 const uint8_t *codes = temp->code;
1323 uint8_t opex = 0;
1324 enum ea_type eat = EA_SCALAR;
1325
1326 while (*codes) {
1327 c = *codes++;
1328 op1 = (c & 3) + ((opex & 1) << 2);
1329 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1330 opx = &ins->oprs[op1];
1331 opex = 0; /* For the next iteration */
1332
1333 switch (c) {
1334 case 01:
1335 case 02:
1336 case 03:
1337 case 04:
1338 offset += emit_rex(ins, segment, offset, bits);
1339 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1340 codes += c;
1341 offset += c;
1342 break;
1343
1344 case 05:
1345 case 06:
1346 case 07:
1347 opex = c;
1348 break;
1349
1350 case4(010):
1351 offset += emit_rex(ins, segment, offset, bits);
1352 bytes[0] = *codes++ + (regval(opx) & 7);
1353 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1354 offset += 1;
1355 break;
1356
1357 case4(014):
1358 break;
1359
1360 case4(020):
1361 if (opx->offset < -256 || opx->offset > 255) {
1362 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1363 "byte value exceeds bounds");
1364 }
1365 out_imm8(offset, segment, opx);
1366 offset += 1;
1367 break;
1368
1369 case4(024):
1370 if (opx->offset < 0 || opx->offset > 255)
1371 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1372 "unsigned byte value exceeds bounds");
1373 out_imm8(offset, segment, opx);
1374 offset += 1;
1375 break;
1376
1377 case4(030):
1378 warn_overflow_opd(opx, 2);
1379 data = opx->offset;
1380 out(offset, segment, &data, OUT_ADDRESS, 2,
1381 opx->segment, opx->wrt);
1382 offset += 2;
1383 break;
1384
1385 case4(034):
1386 if (opx->type & (BITS16 | BITS32))
1387 size = (opx->type & BITS16) ? 2 : 4;
1388 else
1389 size = (bits == 16) ? 2 : 4;
1390 warn_overflow_opd(opx, size);
1391 data = opx->offset;
1392 out(offset, segment, &data, OUT_ADDRESS, size,
1393 opx->segment, opx->wrt);
1394 offset += size;
1395 break;
1396
1397 case4(040):
1398 warn_overflow_opd(opx, 4);
1399 data = opx->offset;
1400 out(offset, segment, &data, OUT_ADDRESS, 4,
1401 opx->segment, opx->wrt);
1402 offset += 4;
1403 break;
1404
1405 case4(044):
1406 data = opx->offset;
1407 size = ins->addr_size >> 3;
1408 warn_overflow_opd(opx, size);
1409 out(offset, segment, &data, OUT_ADDRESS, size,
1410 opx->segment, opx->wrt);
1411 offset += size;
1412 break;
1413
1414 case4(050):
1415 if (opx->segment != segment) {
1416 data = opx->offset;
1417 out(offset, segment, &data,
1418 OUT_REL1ADR, insn_end - offset,
1419 opx->segment, opx->wrt);
1420 } else {
1421 data = opx->offset - insn_end;
1422 if (data > 127 || data < -128)
1423 errfunc(ERR_NONFATAL, "short jump is out of range");
1424 out(offset, segment, &data,
1425 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1426 }
1427 offset += 1;
1428 break;
1429
1430 case4(054):
1431 data = (int64_t)opx->offset;
1432 out(offset, segment, &data, OUT_ADDRESS, 8,
1433 opx->segment, opx->wrt);
1434 offset += 8;
1435 break;
1436
1437 case4(060):
1438 if (opx->segment != segment) {
1439 data = opx->offset;
1440 out(offset, segment, &data,
1441 OUT_REL2ADR, insn_end - offset,
1442 opx->segment, opx->wrt);
1443 } else {
1444 data = opx->offset - insn_end;
1445 out(offset, segment, &data,
1446 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1447 }
1448 offset += 2;
1449 break;
1450
1451 case4(064):
1452 if (opx->type & (BITS16 | BITS32 | BITS64))
1453 size = (opx->type & BITS16) ? 2 : 4;
1454 else
1455 size = (bits == 16) ? 2 : 4;
1456 if (opx->segment != segment) {
1457 data = opx->offset;
1458 out(offset, segment, &data,
1459 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1460 insn_end - offset, opx->segment, opx->wrt);
1461 } else {
1462 data = opx->offset - insn_end;
1463 out(offset, segment, &data,
1464 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1465 }
1466 offset += size;
1467 break;
1468
1469 case4(070):
1470 if (opx->segment != segment) {
1471 data = opx->offset;
1472 out(offset, segment, &data,
1473 OUT_REL4ADR, insn_end - offset,
1474 opx->segment, opx->wrt);
1475 } else {
1476 data = opx->offset - insn_end;
1477 out(offset, segment, &data,
1478 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1479 }
1480 offset += 4;
1481 break;
1482
1483 case4(074):
1484 if (opx->segment == NO_SEG)
1485 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1486 " relocatable");
1487 data = 0;
1488 out(offset, segment, &data, OUT_ADDRESS, 2,
1489 outfmt->segbase(1 + opx->segment),
1490 opx->wrt);
1491 offset += 2;
1492 break;
1493
1494 case 0172:
1495 c = *codes++;
1496 opx = &ins->oprs[c >> 3];
1497 bytes[0] = nasm_regvals[opx->basereg] << 4;
1498 opx = &ins->oprs[c & 7];
1499 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1500 errfunc(ERR_NONFATAL,
1501 "non-absolute expression not permitted as argument %d",
1502 c & 7);
1503 } else {
1504 if (opx->offset & ~15) {
1505 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1506 "four-bit argument exceeds bounds");
1507 }
1508 bytes[0] |= opx->offset & 15;
1509 }
1510 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1511 offset++;
1512 break;
1513
1514 case 0173:
1515 c = *codes++;
1516 opx = &ins->oprs[c >> 4];
1517 bytes[0] = nasm_regvals[opx->basereg] << 4;
1518 bytes[0] |= c & 15;
1519 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1520 offset++;
1521 break;
1522
1523 case4(0174):
1524 bytes[0] = nasm_regvals[opx->basereg] << 4;
1525 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1526 offset++;
1527 break;
1528
1529 case4(0254):
1530 data = opx->offset;
1531 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1532 (int32_t)data != (int64_t)data) {
1533 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1534 "signed dword immediate exceeds bounds");
1535 }
1536 out(offset, segment, &data, OUT_ADDRESS, 4,
1537 opx->segment, opx->wrt);
1538 offset += 4;
1539 break;
1540
1541 case4(0240):
1542 case 0250:
1543 codes += 3;
1544 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1545 EVEX_P2Z | EVEX_P2AAA, 2);
1546 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1547 bytes[0] = 0x62;
1548 /* EVEX.X can be set by either REX or EVEX for different reasons */
1549 bytes[1] = (~(((ins->rex & 7) << 5) |
1550 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) & 0xf0) |
1551 (ins->vex_cm & 3);
1552 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1553 ((~ins->vexreg & 15) << 3) |
1554 (1 << 2) | (ins->vex_wlp & 3);
1555 bytes[3] = ins->evex_p[2];
1556 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1557 offset += 4;
1558 break;
1559
1560 case4(0260):
1561 case 0270:
1562 codes += 2;
1563 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1564 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1565 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1566 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1567 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1568 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1569 offset += 3;
1570 } else {
1571 bytes[0] = 0xc5;
1572 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1573 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1574 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1575 offset += 2;
1576 }
1577 break;
1578
1579 case 0271:
1580 case 0272:
1581 case 0273:
1582 break;
1583
1584 case4(0274):
1585 {
1586 uint64_t uv, um;
1587 int s;
1588
1589 if (ins->rex & REX_W)
1590 s = 64;
1591 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1592 s = 16;
1593 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1594 s = 32;
1595 else
1596 s = bits;
1597
1598 um = (uint64_t)2 << (s-1);
1599 uv = opx->offset;
1600
1601 if (uv > 127 && uv < (uint64_t)-128 &&
1602 (uv < um-128 || uv > um-1)) {
1603 /* If this wasn't explicitly byte-sized, warn as though we
1604 * had fallen through to the imm16/32/64 case.
1605 */
1606 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1607 "%s value exceeds bounds",
1608 (opx->type & BITS8) ? "signed byte" :
1609 s == 16 ? "word" :
1610 s == 32 ? "dword" :
1611 "signed dword");
1612 }
1613 if (opx->segment != NO_SEG) {
1614 data = uv;
1615 out(offset, segment, &data, OUT_ADDRESS, 1,
1616 opx->segment, opx->wrt);
1617 } else {
1618 bytes[0] = uv;
1619 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1620 NO_SEG);
1621 }
1622 offset += 1;
1623 break;
1624 }
1625
1626 case4(0300):
1627 break;
1628
1629 case 0310:
1630 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1631 *bytes = 0x67;
1632 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1633 offset += 1;
1634 } else
1635 offset += 0;
1636 break;
1637
1638 case 0311:
1639 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1640 *bytes = 0x67;
1641 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1642 offset += 1;
1643 } else
1644 offset += 0;
1645 break;
1646
1647 case 0312:
1648 break;
1649
1650 case 0313:
1651 ins->rex = 0;
1652 break;
1653
1654 case4(0314):
1655 break;
1656
1657 case 0320:
1658 case 0321:
1659 break;
1660
1661 case 0322:
1662 case 0323:
1663 break;
1664
1665 case 0324:
1666 ins->rex |= REX_W;
1667 break;
1668
1669 case 0325:
1670 break;
1671
1672 case 0326:
1673 break;
1674
1675 case 0330:
1676 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1677 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1678 offset += 1;
1679 break;
1680
1681 case 0331:
1682 break;
1683
1684 case 0332:
1685 case 0333:
1686 *bytes = c - 0332 + 0xF2;
1687 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1688 offset += 1;
1689 break;
1690
1691 case 0334:
1692 if (ins->rex & REX_R) {
1693 *bytes = 0xF0;
1694 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1695 offset += 1;
1696 }
1697 ins->rex &= ~(REX_L|REX_R);
1698 break;
1699
1700 case 0335:
1701 break;
1702
1703 case 0336:
1704 case 0337:
1705 break;
1706
1707 case 0340:
1708 if (ins->oprs[0].segment != NO_SEG)
1709 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1710 else {
1711 int64_t size = ins->oprs[0].offset;
1712 if (size > 0)
1713 out(offset, segment, NULL,
1714 OUT_RESERVE, size, NO_SEG, NO_SEG);
1715 offset += size;
1716 }
1717 break;
1718
1719 case 0341:
1720 break;
1721
1722 case 0360:
1723 break;
1724
1725 case 0361:
1726 bytes[0] = 0x66;
1727 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1728 offset += 1;
1729 break;
1730
1731 case 0364:
1732 case 0365:
1733 break;
1734
1735 case 0366:
1736 case 0367:
1737 *bytes = c - 0366 + 0x66;
1738 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1739 offset += 1;
1740 break;
1741
1742 case 0370:
1743 case 0371:
1744 break;
1745
1746 case 0373:
1747 *bytes = bits == 16 ? 3 : 5;
1748 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1749 offset += 1;
1750 break;
1751
1752 case 0374:
1753 eat = EA_XMMVSIB;
1754 break;
1755
1756 case 0375:
1757 eat = EA_YMMVSIB;
1758 break;
1759
1760 case 0376:
1761 eat = EA_ZMMVSIB;
1762 break;
1763
1764 case4(0100):
1765 case4(0110):
1766 case4(0120):
1767 case4(0130):
1768 case4(0200):
1769 case4(0204):
1770 case4(0210):
1771 case4(0214):
1772 case4(0220):
1773 case4(0224):
1774 case4(0230):
1775 case4(0234):
1776 {
1777 ea ea_data;
1778 int rfield;
1779 opflags_t rflags;
1780 uint8_t *p;
1781 int32_t s;
1782 struct operand *opy = &ins->oprs[op2];
1783
1784 if (c <= 0177) {
1785 /* pick rfield from operand b (opx) */
1786 rflags = regflag(opx);
1787 rfield = nasm_regvals[opx->basereg];
1788 } else {
1789 /* rfield is constant */
1790 rflags = 0;
1791 rfield = c & 7;
1792 }
1793
1794 if (process_ea(opy, &ea_data, bits,
1795 rfield, rflags, ins) != eat)
1796 errfunc(ERR_NONFATAL, "invalid effective address");
1797
1798 p = bytes;
1799 *p++ = ea_data.modrm;
1800 if (ea_data.sib_present)
1801 *p++ = ea_data.sib;
1802
1803 s = p - bytes;
1804 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1805
1806 /*
1807 * Make sure the address gets the right offset in case
1808 * the line breaks in the .lst file (BR 1197827)
1809 */
1810 offset += s;
1811 s = 0;
1812
1813 switch (ea_data.bytes) {
1814 case 0:
1815 break;
1816 case 1:
1817 case 2:
1818 case 4:
1819 case 8:
1820 /* use compressed displacement, if available */
1821 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1822 s += ea_data.bytes;
1823 if (ea_data.rip) {
1824 if (opy->segment == segment) {
1825 data -= insn_end;
1826 if (overflow_signed(data, ea_data.bytes))
1827 warn_overflow(ERR_PASS2, ea_data.bytes);
1828 out(offset, segment, &data, OUT_ADDRESS,
1829 ea_data.bytes, NO_SEG, NO_SEG);
1830 } else {
1831 /* overflow check in output/linker? */
1832 out(offset, segment, &data, OUT_REL4ADR,
1833 insn_end - offset, opy->segment, opy->wrt);
1834 }
1835 } else {
1836 if (overflow_general(data, ins->addr_size >> 3) ||
1837 signed_bits(data, ins->addr_size) !=
1838 signed_bits(data, ea_data.bytes * 8))
1839 warn_overflow(ERR_PASS2, ea_data.bytes);
1840
1841 out(offset, segment, &data, OUT_ADDRESS,
1842 ea_data.bytes, opy->segment, opy->wrt);
1843 }
1844 break;
1845 default:
1846 /* Impossible! */
1847 errfunc(ERR_PANIC,
1848 "Invalid amount of bytes (%d) for offset?!",
1849 ea_data.bytes);
1850 break;
1851 }
1852 offset += s;
1853 }
1854 break;
1855
1856 default:
1857 errfunc(ERR_PANIC, "internal instruction table corrupt"
1858 ": instruction code \\%o (0x%02X) given", c, c);
1859 break;
1860 }
1861 }
1862 }
1863
1864 static opflags_t regflag(const operand * o)
1865 {
1866 if (!is_register(o->basereg))
1867 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1868 return nasm_reg_flags[o->basereg];
1869 }
1870
1871 static int32_t regval(const operand * o)
1872 {
1873 if (!is_register(o->basereg))
1874 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1875 return nasm_regvals[o->basereg];
1876 }
1877
1878 static int op_rexflags(const operand * o, int mask)
1879 {
1880 opflags_t flags;
1881 int val;
1882
1883 if (!is_register(o->basereg))
1884 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1885
1886 flags = nasm_reg_flags[o->basereg];
1887 val = nasm_regvals[o->basereg];
1888
1889 return rexflags(val, flags, mask);
1890 }
1891
1892 static int rexflags(int val, opflags_t flags, int mask)
1893 {
1894 int rex = 0;
1895
1896 if (val >= 8)
1897 rex |= REX_B|REX_X|REX_R;
1898 if (flags & BITS64)
1899 rex |= REX_W;
1900 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1901 rex |= REX_H;
1902 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1903 rex |= REX_P;
1904
1905 return rex & mask;
1906 }
1907
1908 static int evexflags(int val, decoflags_t deco,
1909 int mask, uint8_t byte)
1910 {
1911 int evex = 0;
1912
1913 switch(byte) {
1914 case 0:
1915 if (val >= 16)
1916 evex |= (EVEX_P0RP | EVEX_P0X);
1917 break;
1918 case 2:
1919 if (val >= 16)
1920 evex |= EVEX_P2VP;
1921 if (deco & Z)
1922 evex |= EVEX_P2Z;
1923 if (deco & OPMASK_MASK)
1924 evex |= deco & EVEX_P2AAA;
1925 break;
1926 }
1927 return evex & mask;
1928 }
1929
1930 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1931 {
1932 int val;
1933
1934 if (!is_register(o->basereg))
1935 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1936
1937 val = nasm_regvals[o->basereg];
1938
1939 return evexflags(val, o->decoflags, mask, byte);
1940 }
1941
1942 static enum match_result find_match(const struct itemplate **tempp,
1943 insn *instruction,
1944 int32_t segment, int64_t offset, int bits)
1945 {
1946 const struct itemplate *temp;
1947 enum match_result m, merr;
1948 opflags_t xsizeflags[MAX_OPERANDS];
1949 bool opsizemissing = false;
1950 int8_t broadcast = instruction->evex_brerop;
1951 int i;
1952
1953 /* broadcasting uses a different data element size */
1954 for (i = 0; i < instruction->operands; i++)
1955 if (i == broadcast)
1956 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1957 else
1958 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1959
1960 merr = MERR_INVALOP;
1961
1962 for (temp = nasm_instructions[instruction->opcode];
1963 temp->opcode != I_none; temp++) {
1964 m = matches(temp, instruction, bits);
1965 if (m == MOK_JUMP) {
1966 if (jmp_match(segment, offset, bits, instruction, temp))
1967 m = MOK_GOOD;
1968 else
1969 m = MERR_INVALOP;
1970 } else if (m == MERR_OPSIZEMISSING &&
1971 (temp->flags & IF_SMASK) != IF_SX) {
1972 /*
1973 * Missing operand size and a candidate for fuzzy matching...
1974 */
1975 for (i = 0; i < temp->operands; i++)
1976 if (i == broadcast)
1977 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1978 else
1979 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1980 opsizemissing = true;
1981 }
1982 if (m > merr)
1983 merr = m;
1984 if (merr == MOK_GOOD)
1985 goto done;
1986 }
1987
1988 /* No match, but see if we can get a fuzzy operand size match... */
1989 if (!opsizemissing)
1990 goto done;
1991
1992 for (i = 0; i < instruction->operands; i++) {
1993 /*
1994 * We ignore extrinsic operand sizes on registers, so we should
1995 * never try to fuzzy-match on them. This also resolves the case
1996 * when we have e.g. "xmmrm128" in two different positions.
1997 */
1998 if (is_class(REGISTER, instruction->oprs[i].type))
1999 continue;
2000
2001 /* This tests if xsizeflags[i] has more than one bit set */
2002 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2003 goto done; /* No luck */
2004
2005 if (i == broadcast)
2006 instruction->oprs[i].decoflags |= xsizeflags[i];
2007 else
2008 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2009 }
2010
2011 /* Try matching again... */
2012 for (temp = nasm_instructions[instruction->opcode];
2013 temp->opcode != I_none; temp++) {
2014 m = matches(temp, instruction, bits);
2015 if (m == MOK_JUMP) {
2016 if (jmp_match(segment, offset, bits, instruction, temp))
2017 m = MOK_GOOD;
2018 else
2019 m = MERR_INVALOP;
2020 }
2021 if (m > merr)
2022 merr = m;
2023 if (merr == MOK_GOOD)
2024 goto done;
2025 }
2026
2027 done:
2028 *tempp = temp;
2029 return merr;
2030 }
2031
2032 static enum match_result matches(const struct itemplate *itemp,
2033 insn *instruction, int bits)
2034 {
2035 opflags_t size[MAX_OPERANDS], asize;
2036 bool opsizemissing = false;
2037 int i, oprs;
2038
2039 /*
2040 * Check the opcode
2041 */
2042 if (itemp->opcode != instruction->opcode)
2043 return MERR_INVALOP;
2044
2045 /*
2046 * Count the operands
2047 */
2048 if (itemp->operands != instruction->operands)
2049 return MERR_INVALOP;
2050
2051 /*
2052 * Is it legal?
2053 */
2054 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2055 return MERR_INVALOP;
2056
2057 /*
2058 * Check that no spurious colons or TOs are present
2059 */
2060 for (i = 0; i < itemp->operands; i++)
2061 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2062 return MERR_INVALOP;
2063
2064 /*
2065 * Process size flags
2066 */
2067 switch (itemp->flags & IF_SMASK) {
2068 case IF_SB:
2069 asize = BITS8;
2070 break;
2071 case IF_SW:
2072 asize = BITS16;
2073 break;
2074 case IF_SD:
2075 asize = BITS32;
2076 break;
2077 case IF_SQ:
2078 asize = BITS64;
2079 break;
2080 case IF_SO:
2081 asize = BITS128;
2082 break;
2083 case IF_SY:
2084 asize = BITS256;
2085 break;
2086 case IF_SZ:
2087 asize = BITS512;
2088 break;
2089 case IF_SIZE:
2090 switch (bits) {
2091 case 16:
2092 asize = BITS16;
2093 break;
2094 case 32:
2095 asize = BITS32;
2096 break;
2097 case 64:
2098 asize = BITS64;
2099 break;
2100 default:
2101 asize = 0;
2102 break;
2103 }
2104 break;
2105 default:
2106 asize = 0;
2107 break;
2108 }
2109
2110 if (itemp->flags & IF_ARMASK) {
2111 /* S- flags only apply to a specific operand */
2112 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2113 memset(size, 0, sizeof size);
2114 size[i] = asize;
2115 } else {
2116 /* S- flags apply to all operands */
2117 for (i = 0; i < MAX_OPERANDS; i++)
2118 size[i] = asize;
2119 }
2120
2121 /*
2122 * Check that the operand flags all match up,
2123 * it's a bit tricky so lets be verbose:
2124 *
2125 * 1) Find out the size of operand. If instruction
2126 * doesn't have one specified -- we're trying to
2127 * guess it either from template (IF_S* flag) or
2128 * from code bits.
2129 *
2130 * 2) If template operand do not match the instruction OR
2131 * template has an operand size specified AND this size differ
2132 * from which instruction has (perhaps we got it from code bits)
2133 * we are:
2134 * a) Check that only size of instruction and operand is differ
2135 * other characteristics do match
2136 * b) Perhaps it's a register specified in instruction so
2137 * for such a case we just mark that operand as "size
2138 * missing" and this will turn on fuzzy operand size
2139 * logic facility (handled by a caller)
2140 */
2141 for (i = 0; i < itemp->operands; i++) {
2142 opflags_t type = instruction->oprs[i].type;
2143 decoflags_t deco = instruction->oprs[i].decoflags;
2144 if (!(type & SIZE_MASK))
2145 type |= size[i];
2146
2147 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2148 (itemp->deco[i] & deco) != deco) {
2149 return MERR_INVALOP;
2150 } else if ((itemp->opd[i] & SIZE_MASK) &&
2151 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2152 if (type & SIZE_MASK) {
2153 /*
2154 * when broadcasting, the element size depends on
2155 * the instruction type. decorator flag should match.
2156 */
2157 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2158 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2159 if (!((deco & BRDCAST_MASK) &&
2160 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2161 return MERR_INVALOP;
2162 }
2163 } else if (!is_class(REGISTER, type)) {
2164 /*
2165 * Note: we don't honor extrinsic operand sizes for registers,
2166 * so "missing operand size" for a register should be
2167 * considered a wildcard match rather than an error.
2168 */
2169 opsizemissing = true;
2170 }
2171 } else if (is_register(instruction->oprs[i].basereg) &&
2172 nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2173 !(itemp->flags & IF_AVX512)) {
2174 return MERR_ENCMISMATCH;
2175 }
2176 }
2177
2178 if (opsizemissing)
2179 return MERR_OPSIZEMISSING;
2180
2181 /*
2182 * Check operand sizes
2183 */
2184 if (itemp->flags & (IF_SM | IF_SM2)) {
2185 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2186 for (i = 0; i < oprs; i++) {
2187 asize = itemp->opd[i] & SIZE_MASK;
2188 if (asize) {
2189 for (i = 0; i < oprs; i++)
2190 size[i] = asize;
2191 break;
2192 }
2193 }
2194 } else {
2195 oprs = itemp->operands;
2196 }
2197
2198 for (i = 0; i < itemp->operands; i++) {
2199 if (!(itemp->opd[i] & SIZE_MASK) &&
2200 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2201 return MERR_OPSIZEMISMATCH;
2202 }
2203
2204 /*
2205 * Check template is okay at the set cpu level
2206 */
2207 if (((itemp->flags & IF_PLEVEL) > cpu))
2208 return MERR_BADCPU;
2209
2210 /*
2211 * Verify the appropriate long mode flag.
2212 */
2213 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2214 return MERR_BADMODE;
2215
2216 /*
2217 * If we have a HLE prefix, look for the NOHLE flag
2218 */
2219 if ((itemp->flags & IF_NOHLE) &&
2220 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2221 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2222 return MERR_BADHLE;
2223
2224 /*
2225 * Check if special handling needed for Jumps
2226 */
2227 if ((itemp->code[0] & ~1) == 0370)
2228 return MOK_JUMP;
2229
2230 return MOK_GOOD;
2231 }
2232
2233 /*
2234 * Check if offset is a multiple of N with corresponding tuple type
2235 * if Disp8*N is available, compressed displacement is stored in compdisp
2236 */
2237 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2238 {
2239 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2240 {{16, 32, 64}, {8, 8, 8}}};
2241 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2242 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2243
2244 bool evex_b = input->decoflags & BRDCAST_MASK;
2245 enum ttypes tuple = ins->evex_tuple;
2246 /* vex_wlp composed as [wwllpp] */
2247 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2248 /* wig(=2) is treated as w0(=0) */
2249 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2250 int32_t off = input->offset;
2251 uint8_t n = 0;
2252 int32_t disp8;
2253
2254 switch(tuple) {
2255 case FV:
2256 n = fv_n[evex_w][evex_b][vectlen];
2257 break;
2258 case HV:
2259 n = hv_n[evex_b][vectlen];
2260 break;
2261
2262 case FVM:
2263 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2264 n = 1 << (vectlen + 4);
2265 break;
2266 case T1S8: /* N = 1 */
2267 case T1S16: /* N = 2 */
2268 n = tuple - T1S8 + 1;
2269 break;
2270 case T1S:
2271 /* N = 4 for 32bit, 8 for 64bit */
2272 n = evex_w ? 8 : 4;
2273 break;
2274 case T1F32:
2275 case T1F64:
2276 /* N = 4 for 32bit, 8 for 64bit */
2277 n = (tuple == T1F32 ? 4 : 8);
2278 break;
2279 case T2:
2280 case T4:
2281 case T8:
2282 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2283 n = 0;
2284 else
2285 n = 1 << (tuple - T2 + evex_w + 3);
2286 break;
2287 case HVM:
2288 case QVM:
2289 case OVM:
2290 n = 1 << (OVM - tuple + vectlen + 1);
2291 break;
2292 case M128:
2293 n = 16;
2294 break;
2295 case DUP:
2296 n = dup_n[vectlen];
2297 break;
2298
2299 default:
2300 break;
2301 }
2302
2303 if (n && !(off & (n - 1))) {
2304 disp8 = off / n;
2305 /* if it fits in Disp8 */
2306 if (disp8 >= -128 && disp8 <= 127) {
2307 *compdisp = disp8;
2308 return true;
2309 }
2310 }
2311
2312 *compdisp = 0;
2313 return false;
2314 }
2315
2316 /*
2317 * Check if ModR/M.mod should/can be 01.
2318 * - EAF_BYTEOFFS is set
2319 * - offset can fit in a byte when EVEX is not used
2320 * - offset can be compressed when EVEX is used
2321 */
2322 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2323 (o >= -128 && o <= 127 && \
2324 seg == NO_SEG && !forw_ref && \
2325 !(input->eaflags & EAF_WORDOFFS) && \
2326 !(ins->rex & REX_EV)) || \
2327 (ins->rex & REX_EV && \
2328 is_disp8n(input, ins, &output->disp8)))
2329
2330 static enum ea_type process_ea(operand *input, ea *output, int bits,
2331 int rfield, opflags_t rflags, insn *ins)
2332 {
2333 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2334 int addrbits = ins->addr_size;
2335
2336 output->type = EA_SCALAR;
2337 output->rip = false;
2338 output->disp8 = 0;
2339
2340 /* REX flags for the rfield operand */
2341 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2342 /* EVEX.R' flag for the REG operand */
2343 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2344
2345 if (is_class(REGISTER, input->type)) {
2346 /*
2347 * It's a direct register.
2348 */
2349 if (!is_register(input->basereg))
2350 goto err;
2351
2352 if (!is_reg_class(REG_EA, input->basereg))
2353 goto err;
2354
2355 /* broadcasting is not available with a direct register operand. */
2356 if (input->decoflags & BRDCAST_MASK) {
2357 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2358 goto err;
2359 }
2360
2361 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2362 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2363 output->sib_present = false; /* no SIB necessary */
2364 output->bytes = 0; /* no offset necessary either */
2365 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2366 } else {
2367 /*
2368 * It's a memory reference.
2369 */
2370
2371 /* Embedded rounding or SAE is not available with a mem ref operand. */
2372 if (input->decoflags & (ER | SAE)) {
2373 nasm_error(ERR_NONFATAL,
2374 "Embedded rounding is available only with reg-reg op.");
2375 return -1;
2376 }
2377
2378 if (input->basereg == -1 &&
2379 (input->indexreg == -1 || input->scale == 0)) {
2380 /*
2381 * It's a pure offset.
2382 */
2383 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2384 input->segment == NO_SEG) {
2385 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2386 input->type &= ~IP_REL;
2387 input->type |= MEMORY;
2388 }
2389
2390 if (input->eaflags & EAF_BYTEOFFS ||
2391 (input->eaflags & EAF_WORDOFFS &&
2392 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2393 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2394 }
2395
2396 if (bits == 64 && (~input->type & IP_REL)) {
2397 output->sib_present = true;
2398 output->sib = GEN_SIB(0, 4, 5);
2399 output->bytes = 4;
2400 output->modrm = GEN_MODRM(0, rfield, 4);
2401 output->rip = false;
2402 } else {
2403 output->sib_present = false;
2404 output->bytes = (addrbits != 16 ? 4 : 2);
2405 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2406 output->rip = bits == 64;
2407 }
2408 } else {
2409 /*
2410 * It's an indirection.
2411 */
2412 int i = input->indexreg, b = input->basereg, s = input->scale;
2413 int32_t seg = input->segment;
2414 int hb = input->hintbase, ht = input->hinttype;
2415 int t, it, bt; /* register numbers */
2416 opflags_t x, ix, bx; /* register flags */
2417
2418 if (s == 0)
2419 i = -1; /* make this easy, at least */
2420
2421 if (is_register(i)) {
2422 it = nasm_regvals[i];
2423 ix = nasm_reg_flags[i];
2424 } else {
2425 it = -1;
2426 ix = 0;
2427 }
2428
2429 if (is_register(b)) {
2430 bt = nasm_regvals[b];
2431 bx = nasm_reg_flags[b];
2432 } else {
2433 bt = -1;
2434 bx = 0;
2435 }
2436
2437 /* if either one are a vector register... */
2438 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2439 opflags_t sok = BITS32 | BITS64;
2440 int32_t o = input->offset;
2441 int mod, scale, index, base;
2442
2443 /*
2444 * For a vector SIB, one has to be a vector and the other,
2445 * if present, a GPR. The vector must be the index operand.
2446 */
2447 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2448 if (s == 0)
2449 s = 1;
2450 else if (s != 1)
2451 goto err;
2452
2453 t = bt, bt = it, it = t;
2454 x = bx, bx = ix, ix = x;
2455 }
2456
2457 if (bt != -1) {
2458 if (REG_GPR & ~bx)
2459 goto err;
2460 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2461 sok &= bx;
2462 else
2463 goto err;
2464 }
2465
2466 /*
2467 * While we're here, ensure the user didn't specify
2468 * WORD or QWORD
2469 */
2470 if (input->disp_size == 16 || input->disp_size == 64)
2471 goto err;
2472
2473 if (addrbits == 16 ||
2474 (addrbits == 32 && !(sok & BITS32)) ||
2475 (addrbits == 64 && !(sok & BITS64)))
2476 goto err;
2477
2478 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2479 : ((ix & YMMREG & ~REG_EA)
2480 ? EA_YMMVSIB : EA_XMMVSIB));
2481
2482 output->rex |= rexflags(it, ix, REX_X);
2483 output->rex |= rexflags(bt, bx, REX_B);
2484 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2485
2486 index = it & 7; /* it is known to be != -1 */
2487
2488 switch (s) {
2489 case 1:
2490 scale = 0;
2491 break;
2492 case 2:
2493 scale = 1;
2494 break;
2495 case 4:
2496 scale = 2;
2497 break;
2498 case 8:
2499 scale = 3;
2500 break;
2501 default: /* then what the smeg is it? */
2502 goto err; /* panic */
2503 }
2504
2505 if (bt == -1) {
2506 base = 5;
2507 mod = 0;
2508 } else {
2509 base = (bt & 7);
2510 if (base != REG_NUM_EBP && o == 0 &&
2511 seg == NO_SEG && !forw_ref &&
2512 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2513 mod = 0;
2514 else if (IS_MOD_01())
2515 mod = 1;
2516 else
2517 mod = 2;
2518 }
2519
2520 output->sib_present = true;
2521 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2522 output->modrm = GEN_MODRM(mod, rfield, 4);
2523 output->sib = GEN_SIB(scale, index, base);
2524 } else if ((ix|bx) & (BITS32|BITS64)) {
2525 /*
2526 * it must be a 32/64-bit memory reference. Firstly we have
2527 * to check that all registers involved are type E/Rxx.
2528 */
2529 opflags_t sok = BITS32 | BITS64;
2530 int32_t o = input->offset;
2531
2532 if (it != -1) {
2533 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2534 sok &= ix;
2535 else
2536 goto err;
2537 }
2538
2539 if (bt != -1) {
2540 if (REG_GPR & ~bx)
2541 goto err; /* Invalid register */
2542 if (~sok & bx & SIZE_MASK)
2543 goto err; /* Invalid size */
2544 sok &= bx;
2545 }
2546
2547 /*
2548 * While we're here, ensure the user didn't specify
2549 * WORD or QWORD
2550 */
2551 if (input->disp_size == 16 || input->disp_size == 64)
2552 goto err;
2553
2554 if (addrbits == 16 ||
2555 (addrbits == 32 && !(sok & BITS32)) ||
2556 (addrbits == 64 && !(sok & BITS64)))
2557 goto err;
2558
2559 /* now reorganize base/index */
2560 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2561 ((hb == b && ht == EAH_NOTBASE) ||
2562 (hb == i && ht == EAH_MAKEBASE))) {
2563 /* swap if hints say so */
2564 t = bt, bt = it, it = t;
2565 x = bx, bx = ix, ix = x;
2566 }
2567 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2568 bt = -1, bx = 0, s++;
2569 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2570 /* make single reg base, unless hint */
2571 bt = it, bx = ix, it = -1, ix = 0;
2572 }
2573 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2574 s == 3 || s == 5 || s == 9) && bt == -1)
2575 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2576 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2577 (input->eaflags & EAF_TIMESTWO))
2578 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2579 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2580 if (s == 1 && it == REG_NUM_ESP) {
2581 /* swap ESP into base if scale is 1 */
2582 t = it, it = bt, bt = t;
2583 x = ix, ix = bx, bx = x;
2584 }
2585 if (it == REG_NUM_ESP ||
2586 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2587 goto err; /* wrong, for various reasons */
2588
2589 output->rex |= rexflags(it, ix, REX_X);
2590 output->rex |= rexflags(bt, bx, REX_B);
2591
2592 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2593 /* no SIB needed */
2594 int mod, rm;
2595
2596 if (bt == -1) {
2597 rm = 5;
2598 mod = 0;
2599 } else {
2600 rm = (bt & 7);
2601 if (rm != REG_NUM_EBP && o == 0 &&
2602 seg == NO_SEG && !forw_ref &&
2603 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2604 mod = 0;
2605 else if (IS_MOD_01())
2606 mod = 1;
2607 else
2608 mod = 2;
2609 }
2610
2611 output->sib_present = false;
2612 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2613 output->modrm = GEN_MODRM(mod, rfield, rm);
2614 } else {
2615 /* we need a SIB */
2616 int mod, scale, index, base;
2617
2618 if (it == -1)
2619 index = 4, s = 1;
2620 else
2621 index = (it & 7);
2622
2623 switch (s) {
2624 case 1:
2625 scale = 0;
2626 break;
2627 case 2:
2628 scale = 1;
2629 break;
2630 case 4:
2631 scale = 2;
2632 break;
2633 case 8:
2634 scale = 3;
2635 break;
2636 default: /* then what the smeg is it? */
2637 goto err; /* panic */
2638 }
2639
2640 if (bt == -1) {
2641 base = 5;
2642 mod = 0;
2643 } else {
2644 base = (bt & 7);
2645 if (base != REG_NUM_EBP && o == 0 &&
2646 seg == NO_SEG && !forw_ref &&
2647 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2648 mod = 0;
2649 else if (IS_MOD_01())
2650 mod = 1;
2651 else
2652 mod = 2;
2653 }
2654
2655 output->sib_present = true;
2656 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2657 output->modrm = GEN_MODRM(mod, rfield, 4);
2658 output->sib = GEN_SIB(scale, index, base);
2659 }
2660 } else { /* it's 16-bit */
2661 int mod, rm;
2662 int16_t o = input->offset;
2663
2664 /* check for 64-bit long mode */
2665 if (addrbits == 64)
2666 goto err;
2667
2668 /* check all registers are BX, BP, SI or DI */
2669 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2670 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2671 goto err;
2672
2673 /* ensure the user didn't specify DWORD/QWORD */
2674 if (input->disp_size == 32 || input->disp_size == 64)
2675 goto err;
2676
2677 if (s != 1 && i != -1)
2678 goto err; /* no can do, in 16-bit EA */
2679 if (b == -1 && i != -1) {
2680 int tmp = b;
2681 b = i;
2682 i = tmp;
2683 } /* swap */
2684 if ((b == R_SI || b == R_DI) && i != -1) {
2685 int tmp = b;
2686 b = i;
2687 i = tmp;
2688 }
2689 /* have BX/BP as base, SI/DI index */
2690 if (b == i)
2691 goto err; /* shouldn't ever happen, in theory */
2692 if (i != -1 && b != -1 &&
2693 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2694 goto err; /* invalid combinations */
2695 if (b == -1) /* pure offset: handled above */
2696 goto err; /* so if it gets to here, panic! */
2697
2698 rm = -1;
2699 if (i != -1)
2700 switch (i * 256 + b) {
2701 case R_SI * 256 + R_BX:
2702 rm = 0;
2703 break;
2704 case R_DI * 256 + R_BX:
2705 rm = 1;
2706 break;
2707 case R_SI * 256 + R_BP:
2708 rm = 2;
2709 break;
2710 case R_DI * 256 + R_BP:
2711 rm = 3;
2712 break;
2713 } else
2714 switch (b) {
2715 case R_SI:
2716 rm = 4;
2717 break;
2718 case R_DI:
2719 rm = 5;
2720 break;
2721 case R_BP:
2722 rm = 6;
2723 break;
2724 case R_BX:
2725 rm = 7;
2726 break;
2727 }
2728 if (rm == -1) /* can't happen, in theory */
2729 goto err; /* so panic if it does */
2730
2731 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2732 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2733 mod = 0;
2734 else if (IS_MOD_01())
2735 mod = 1;
2736 else
2737 mod = 2;
2738
2739 output->sib_present = false; /* no SIB - it's 16-bit */
2740 output->bytes = mod; /* bytes of offset needed */
2741 output->modrm = GEN_MODRM(mod, rfield, rm);
2742 }
2743 }
2744 }
2745
2746 output->size = 1 + output->sib_present + output->bytes;
2747 return output->type;
2748
2749 err:
2750 return output->type = EA_INVALID;
2751 }
2752
2753 static void add_asp(insn *ins, int addrbits)
2754 {
2755 int j, valid;
2756 int defdisp;
2757
2758 valid = (addrbits == 64) ? 64|32 : 32|16;
2759
2760 switch (ins->prefixes[PPS_ASIZE]) {
2761 case P_A16:
2762 valid &= 16;
2763 break;
2764 case P_A32:
2765 valid &= 32;
2766 break;
2767 case P_A64:
2768 valid &= 64;
2769 break;
2770 case P_ASP:
2771 valid &= (addrbits == 32) ? 16 : 32;
2772 break;
2773 default:
2774 break;
2775 }
2776
2777 for (j = 0; j < ins->operands; j++) {
2778 if (is_class(MEMORY, ins->oprs[j].type)) {
2779 opflags_t i, b;
2780
2781 /* Verify as Register */
2782 if (!is_register(ins->oprs[j].indexreg))
2783 i = 0;
2784 else
2785 i = nasm_reg_flags[ins->oprs[j].indexreg];
2786
2787 /* Verify as Register */
2788 if (!is_register(ins->oprs[j].basereg))
2789 b = 0;
2790 else
2791 b = nasm_reg_flags[ins->oprs[j].basereg];
2792
2793 if (ins->oprs[j].scale == 0)
2794 i = 0;
2795
2796 if (!i && !b) {
2797 int ds = ins->oprs[j].disp_size;
2798 if ((addrbits != 64 && ds > 8) ||
2799 (addrbits == 64 && ds == 16))
2800 valid &= ds;
2801 } else {
2802 if (!(REG16 & ~b))
2803 valid &= 16;
2804 if (!(REG32 & ~b))
2805 valid &= 32;
2806 if (!(REG64 & ~b))
2807 valid &= 64;
2808
2809 if (!(REG16 & ~i))
2810 valid &= 16;
2811 if (!(REG32 & ~i))
2812 valid &= 32;
2813 if (!(REG64 & ~i))
2814 valid &= 64;
2815 }
2816 }
2817 }
2818
2819 if (valid & addrbits) {
2820 ins->addr_size = addrbits;
2821 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2822 /* Add an address size prefix */
2823 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2824 ins->addr_size = (addrbits == 32) ? 16 : 32;
2825 } else {
2826 /* Impossible... */
2827 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2828 ins->addr_size = addrbits; /* Error recovery */
2829 }
2830
2831 defdisp = ins->addr_size == 16 ? 16 : 32;
2832
2833 for (j = 0; j < ins->operands; j++) {
2834 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2835 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2836 /*
2837 * mem_offs sizes must match the address size; if not,
2838 * strip the MEM_OFFS bit and match only EA instructions
2839 */
2840 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2841 }
2842 }
2843 }
Adding AVX-512 features