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MPX: Add MPX instructions
[nasm/avx512.git] / disasm.c
blobf50ceb91c980b930f17407f037915e8b69d63f0c
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 size_t i;
116
117 static const struct {
118 opflags_t flags;
119 enum reg_enum reg;
120 } specific_registers[] = {
121 {REG_AL, R_AL},
122 {REG_AX, R_AX},
123 {REG_EAX, R_EAX},
124 {REG_RAX, R_RAX},
125 {REG_DL, R_DL},
126 {REG_DX, R_DX},
127 {REG_EDX, R_EDX},
128 {REG_RDX, R_RDX},
129 {REG_CL, R_CL},
130 {REG_CX, R_CX},
131 {REG_ECX, R_ECX},
132 {REG_RCX, R_RCX},
133 {FPU0, R_ST0},
134 {XMM0, R_XMM0},
135 {YMM0, R_YMM0},
136 {REG_ES, R_ES},
137 {REG_CS, R_CS},
138 {REG_SS, R_SS},
139 {REG_DS, R_DS},
140 {REG_FS, R_FS},
141 {REG_GS, R_GS}
142 };
143
144 if (!(regflags & (REGISTER|REGMEM)))
145 return 0; /* Registers not permissible?! */
146
147 regflags |= REGISTER;
148
149 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
150 if (!(specific_registers[i].flags & ~regflags))
151 return specific_registers[i].reg;
152
153 /* All the entries below look up regval in an 16-entry array */
154 if (regval < 0 || regval > 15)
155 return 0;
156
157 if (!(REG8 & ~regflags)) {
158 if (rex & (REX_P|REX_NH))
159 return nasm_rd_reg8_rex[regval];
160 else
161 return nasm_rd_reg8[regval];
162 }
163 if (!(REG16 & ~regflags))
164 return nasm_rd_reg16[regval];
165 if (!(REG32 & ~regflags))
166 return nasm_rd_reg32[regval];
167 if (!(REG64 & ~regflags))
168 return nasm_rd_reg64[regval];
169 if (!(REG_SREG & ~regflags))
170 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
171 if (!(REG_CREG & ~regflags))
172 return nasm_rd_creg[regval];
173 if (!(REG_DREG & ~regflags))
174 return nasm_rd_dreg[regval];
175 if (!(REG_TREG & ~regflags)) {
176 if (regval > 7)
177 return 0; /* TR registers are ill-defined with rex */
178 return nasm_rd_treg[regval];
179 }
180 if (!(FPUREG & ~regflags))
181 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
182 if (!(MMXREG & ~regflags))
183 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
184 if (!(XMMREG & ~regflags))
185 return nasm_rd_xmmreg[regval];
186 if (!(YMMREG & ~regflags))
187 return nasm_rd_ymmreg[regval];
188
189 return 0;
190 }
191
192 /*
193 * Process an effective address (ModRM) specification.
194 */
195 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
196 int segsize, enum ea_type type,
197 operand *op, insn *ins)
198 {
199 int mod, rm, scale, index, base;
200 int rex;
201 uint8_t sib = 0;
202
203 mod = (modrm >> 6) & 03;
204 rm = modrm & 07;
205
206 if (mod != 3 && asize != 16 && rm == 4)
207 sib = *data++;
208
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227
228 if (type != EA_SCALAR)
229 return NULL;
230
231 op->indexreg = op->basereg = -1;
232 op->scale = 1; /* always, in 16 bits */
233 switch (rm) {
234 case 0:
235 op->basereg = R_BX;
236 op->indexreg = R_SI;
237 break;
238 case 1:
239 op->basereg = R_BX;
240 op->indexreg = R_DI;
241 break;
242 case 2:
243 op->basereg = R_BP;
244 op->indexreg = R_SI;
245 break;
246 case 3:
247 op->basereg = R_BP;
248 op->indexreg = R_DI;
249 break;
250 case 4:
251 op->basereg = R_SI;
252 break;
253 case 5:
254 op->basereg = R_DI;
255 break;
256 case 6:
257 op->basereg = R_BP;
258 break;
259 case 7:
260 op->basereg = R_BX;
261 break;
262 }
263 if (rm == 6 && mod == 0) { /* special case */
264 op->basereg = -1;
265 if (segsize != 16)
266 op->disp_size = 16;
267 mod = 2; /* fake disp16 */
268 }
269 switch (mod) {
270 case 0:
271 op->segment |= SEG_NODISP;
272 break;
273 case 1:
274 op->segment |= SEG_DISP8;
275 op->offset = (int8_t)*data++;
276 break;
277 case 2:
278 op->segment |= SEG_DISP16;
279 op->offset = *data++;
280 op->offset |= ((unsigned)*data++) << 8;
281 break;
282 }
283 return data;
284 } else {
285 /*
286 * Once again, <mod> specifies displacement size (this time
287 * none, byte or *dword*), while <rm> specifies the base
288 * register. Again, [EBP] is missing, replaced by a pure
289 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
290 * and RIP-relative addressing in 64-bit mode.
291 *
292 * However, rm=4
293 * indicates not a single base register, but instead the
294 * presence of a SIB byte...
295 */
296 int a64 = asize == 64;
297
298 op->indexreg = -1;
299
300 if (a64)
301 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
302 else
303 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
304
305 if (rm == 5 && mod == 0) {
306 if (segsize == 64) {
307 op->eaflags |= EAF_REL;
308 op->segment |= SEG_RELATIVE;
309 mod = 2; /* fake disp32 */
310 }
311
312 if (asize != 64)
313 op->disp_size = asize;
314
315 op->basereg = -1;
316 mod = 2; /* fake disp32 */
317 }
318
319
320 if (rm == 4) { /* process SIB */
321 scale = (sib >> 6) & 03;
322 index = (sib >> 3) & 07;
323 base = sib & 07;
324
325 op->scale = 1 << scale;
326
327 if (type == EA_XMMVSIB)
328 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
329 else if (type == EA_YMMVSIB)
330 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
331 else if (type == EA_ZMMVSIB)
332 op->indexreg = nasm_rd_zmmreg[index | ((rex & REX_X) ? 8 : 0)];
333 else if (index == 4 && !(rex & REX_X))
334 op->indexreg = -1; /* ESP/RSP cannot be an index */
335 else if (a64)
336 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
337 else
338 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
339
340 if (base == 5 && mod == 0) {
341 op->basereg = -1;
342 mod = 2; /* Fake disp32 */
343 } else if (a64)
344 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
345 else
346 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
347
348 if (segsize == 16)
349 op->disp_size = 32;
350 } else if (type != EA_SCALAR) {
351 /* Can't have VSIB without SIB */
352 return NULL;
353 }
354
355 switch (mod) {
356 case 0:
357 op->segment |= SEG_NODISP;
358 break;
359 case 1:
360 op->segment |= SEG_DISP8;
361 op->offset = gets8(data);
362 data++;
363 break;
364 case 2:
365 op->segment |= SEG_DISP32;
366 op->offset = gets32(data);
367 data += 4;
368 break;
369 }
370 return data;
371 }
372 }
373
374 /*
375 * Determine whether the instruction template in t corresponds to the data
376 * stream in data. Return the number of bytes matched if so.
377 */
378 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
379
380 static int matches(const struct itemplate *t, uint8_t *data,
381 const struct prefix_info *prefix, int segsize, insn *ins)
382 {
383 uint8_t *r = (uint8_t *)(t->code);
384 uint8_t *origdata = data;
385 bool a_used = false, o_used = false;
386 enum prefixes drep = 0;
387 enum prefixes dwait = 0;
388 uint8_t lock = prefix->lock;
389 int osize = prefix->osize;
390 int asize = prefix->asize;
391 int i, c;
392 int op1, op2;
393 struct operand *opx, *opy;
394 uint8_t opex = 0;
395 bool vex_ok = false;
396 int regmask = (segsize == 64) ? 15 : 7;
397 enum ea_type eat = EA_SCALAR;
398
399 for (i = 0; i < MAX_OPERANDS; i++) {
400 ins->oprs[i].segment = ins->oprs[i].disp_size =
401 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
402 }
403 ins->condition = -1;
404 ins->rex = prefix->rex;
405 memset(ins->prefixes, 0, sizeof ins->prefixes);
406
407 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
408 return false;
409
410 if (prefix->rep == 0xF2)
411 drep = P_REPNE;
412 else if (prefix->rep == 0xF3)
413 drep = P_REP;
414
415 dwait = prefix->wait ? P_WAIT : 0;
416
417 while ((c = *r++) != 0) {
418 op1 = (c & 3) + ((opex & 1) << 2);
419 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
420 opx = &ins->oprs[op1];
421 opy = &ins->oprs[op2];
422 opex = 0;
423
424 switch (c) {
425 case 01:
426 case 02:
427 case 03:
428 case 04:
429 while (c--)
430 if (*r++ != *data++)
431 return false;
432 break;
433
434 case 05:
435 case 06:
436 case 07:
437 opex = c;
438 break;
439
440 case4(010):
441 {
442 int t = *r++, d = *data++;
443 if (d < t || d > t + 7)
444 return false;
445 else {
446 opx->basereg = (d-t)+
447 (ins->rex & REX_B ? 8 : 0);
448 opx->segment |= SEG_RMREG;
449 }
450 break;
451 }
452
453 case4(0274):
454 opx->offset = (int8_t)*data++;
455 opx->segment |= SEG_SIGNED;
456 break;
457
458 case4(020):
459 opx->offset = *data++;
460 break;
461
462 case4(024):
463 opx->offset = *data++;
464 break;
465
466 case4(030):
467 opx->offset = getu16(data);
468 data += 2;
469 break;
470
471 case4(034):
472 if (osize == 32) {
473 opx->offset = getu32(data);
474 data += 4;
475 } else {
476 opx->offset = getu16(data);
477 data += 2;
478 }
479 if (segsize != asize)
480 opx->disp_size = asize;
481 break;
482
483 case4(040):
484 opx->offset = getu32(data);
485 data += 4;
486 break;
487
488 case4(0254):
489 opx->offset = gets32(data);
490 data += 4;
491 break;
492
493 case4(044):
494 switch (asize) {
495 case 16:
496 opx->offset = getu16(data);
497 data += 2;
498 if (segsize != 16)
499 opx->disp_size = 16;
500 break;
501 case 32:
502 opx->offset = getu32(data);
503 data += 4;
504 if (segsize == 16)
505 opx->disp_size = 32;
506 break;
507 case 64:
508 opx->offset = getu64(data);
509 opx->disp_size = 64;
510 data += 8;
511 break;
512 }
513 break;
514
515 case4(050):
516 opx->offset = gets8(data++);
517 opx->segment |= SEG_RELATIVE;
518 break;
519
520 case4(054):
521 opx->offset = getu64(data);
522 data += 8;
523 break;
524
525 case4(060):
526 opx->offset = gets16(data);
527 data += 2;
528 opx->segment |= SEG_RELATIVE;
529 opx->segment &= ~SEG_32BIT;
530 break;
531
532 case4(064): /* rel */
533 opx->segment |= SEG_RELATIVE;
534 /* In long mode rel is always 32 bits, sign extended. */
535 if (segsize == 64 || osize == 32) {
536 opx->offset = gets32(data);
537 data += 4;
538 if (segsize != 64)
539 opx->segment |= SEG_32BIT;
540 opx->type = (opx->type & ~SIZE_MASK)
541 | (segsize == 64 ? BITS64 : BITS32);
542 } else {
543 opx->offset = gets16(data);
544 data += 2;
545 opx->segment &= ~SEG_32BIT;
546 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
547 }
548 break;
549
550 case4(070):
551 opx->offset = gets32(data);
552 data += 4;
553 opx->segment |= SEG_32BIT | SEG_RELATIVE;
554 break;
555
556 case4(0100):
557 case4(0110):
558 case4(0120):
559 case4(0130):
560 {
561 int modrm = *data++;
562 opx->segment |= SEG_RMREG;
563 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
564 if (!data)
565 return false;
566 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
567 break;
568 }
569
570 case 0172:
571 {
572 uint8_t ximm = *data++;
573 c = *r++;
574 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
575 ins->oprs[c >> 3].segment |= SEG_RMREG;
576 ins->oprs[c & 7].offset = ximm & 15;
577 }
578 break;
579
580 case 0173:
581 {
582 uint8_t ximm = *data++;
583 c = *r++;
584
585 if ((c ^ ximm) & 15)
586 return false;
587
588 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
589 ins->oprs[c >> 4].segment |= SEG_RMREG;
590 }
591 break;
592
593 case4(0174):
594 {
595 uint8_t ximm = *data++;
596
597 opx->basereg = (ximm >> 4) & regmask;
598 opx->segment |= SEG_RMREG;
599 }
600 break;
601
602 case4(0200):
603 case4(0204):
604 case4(0210):
605 case4(0214):
606 case4(0220):
607 case4(0224):
608 case4(0230):
609 case4(0234):
610 {
611 int modrm = *data++;
612 if (((modrm >> 3) & 07) != (c & 07))
613 return false; /* spare field doesn't match up */
614 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
615 if (!data)
616 return false;
617 break;
618 }
619
620 case4(0260):
621 case 0270:
622 {
623 int vexm = *r++;
624 int vexwlp = *r++;
625
626 ins->rex |= REX_V;
627 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
628 return false;
629
630 if ((vexm & 0x1f) != prefix->vex_m)
631 return false;
632
633 switch (vexwlp & 060) {
634 case 000:
635 if (prefix->rex & REX_W)
636 return false;
637 break;
638 case 020:
639 if (!(prefix->rex & REX_W))
640 return false;
641 ins->rex &= ~REX_W;
642 break;
643 case 040: /* VEX.W is a don't care */
644 ins->rex &= ~REX_W;
645 break;
646 case 060:
647 break;
648 }
649
650 /* The 010 bit of vexwlp is set if VEX.L is ignored */
651 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
652 return false;
653
654 if (c == 0270) {
655 if (prefix->vex_v != 0)
656 return false;
657 } else {
658 opx->segment |= SEG_RMREG;
659 opx->basereg = prefix->vex_v;
660 }
661 vex_ok = true;
662 break;
663 }
664
665 case 0271:
666 if (prefix->rep == 0xF3)
667 drep = P_XRELEASE;
668 break;
669
670 case 0272:
671 if (prefix->rep == 0xF2)
672 drep = P_XACQUIRE;
673 else if (prefix->rep == 0xF3)
674 drep = P_XRELEASE;
675 break;
676
677 case 0273:
678 if (prefix->lock == 0xF0) {
679 if (prefix->rep == 0xF2)
680 drep = P_XACQUIRE;
681 else if (prefix->rep == 0xF3)
682 drep = P_XRELEASE;
683 }
684 break;
685
686 case 0310:
687 if (asize != 16)
688 return false;
689 else
690 a_used = true;
691 break;
692
693 case 0311:
694 if (asize != 32)
695 return false;
696 else
697 a_used = true;
698 break;
699
700 case 0312:
701 if (asize != segsize)
702 return false;
703 else
704 a_used = true;
705 break;
706
707 case 0313:
708 if (asize != 64)
709 return false;
710 else
711 a_used = true;
712 break;
713
714 case 0314:
715 if (prefix->rex & REX_B)
716 return false;
717 break;
718
719 case 0315:
720 if (prefix->rex & REX_X)
721 return false;
722 break;
723
724 case 0316:
725 if (prefix->rex & REX_R)
726 return false;
727 break;
728
729 case 0317:
730 if (prefix->rex & REX_W)
731 return false;
732 break;
733
734 case 0320:
735 if (osize != 16)
736 return false;
737 else
738 o_used = true;
739 break;
740
741 case 0321:
742 if (osize != 32)
743 return false;
744 else
745 o_used = true;
746 break;
747
748 case 0322:
749 if (osize != (segsize == 16) ? 16 : 32)
750 return false;
751 else
752 o_used = true;
753 break;
754
755 case 0323:
756 ins->rex |= REX_W; /* 64-bit only instruction */
757 osize = 64;
758 o_used = true;
759 break;
760
761 case 0324:
762 if (osize != 64)
763 return false;
764 o_used = true;
765 break;
766
767 case 0325:
768 ins->rex |= REX_NH;
769 break;
770
771 case 0330:
772 {
773 int t = *r++, d = *data++;
774 if (d < t || d > t + 15)
775 return false;
776 else
777 ins->condition = d - t;
778 break;
779 }
780
781 case 0326:
782 if (prefix->rep == 0xF3)
783 return false;
784 break;
785
786 case 0331:
787 if (prefix->rep)
788 return false;
789 break;
790
791 case 0332:
792 if (prefix->rep != 0xF2)
793 return false;
794 drep = 0;
795 break;
796
797 case 0333:
798 if (prefix->rep != 0xF3)
799 return false;
800 drep = 0;
801 break;
802
803 case 0334:
804 if (lock) {
805 ins->rex |= REX_R;
806 lock = 0;
807 }
808 break;
809
810 case 0335:
811 if (drep == P_REP)
812 drep = P_REPE;
813 break;
814
815 case 0336:
816 case 0337:
817 break;
818
819 case 0340:
820 return false;
821
822 case 0341:
823 if (prefix->wait != 0x9B)
824 return false;
825 dwait = 0;
826 break;
827
828 case 0360:
829 if (prefix->osp || prefix->rep)
830 return false;
831 break;
832
833 case 0361:
834 if (!prefix->osp || prefix->rep)
835 return false;
836 o_used = true;
837 break;
838
839 case 0364:
840 if (prefix->osp)
841 return false;
842 break;
843
844 case 0365:
845 if (prefix->asp)
846 return false;
847 break;
848
849 case 0366:
850 if (!prefix->osp)
851 return false;
852 o_used = true;
853 break;
854
855 case 0367:
856 if (!prefix->asp)
857 return false;
858 a_used = true;
859 break;
860
861 case 0370:
862 case 0371:
863 break;
864
865 case 0374:
866 eat = EA_XMMVSIB;
867 break;
868
869 case 0375:
870 eat = EA_YMMVSIB;
871 break;
872
873 case 0376:
874 eat = EA_ZMMVSIB;
875 break;
876
877 default:
878 return false; /* Unknown code */
879 }
880 }
881
882 if (!vex_ok && (ins->rex & REX_V))
883 return false;
884
885 /* REX cannot be combined with VEX */
886 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
887 return false;
888
889 /*
890 * Check for unused rep or a/o prefixes.
891 */
892 for (i = 0; i < t->operands; i++) {
893 if (ins->oprs[i].segment != SEG_RMREG)
894 a_used = true;
895 }
896
897 if (lock) {
898 if (ins->prefixes[PPS_LOCK])
899 return false;
900 ins->prefixes[PPS_LOCK] = P_LOCK;
901 }
902 if (drep) {
903 if (ins->prefixes[PPS_REP])
904 return false;
905 ins->prefixes[PPS_REP] = drep;
906 }
907 ins->prefixes[PPS_WAIT] = dwait;
908 if (!o_used) {
909 if (osize != ((segsize == 16) ? 16 : 32)) {
910 enum prefixes pfx = 0;
911
912 switch (osize) {
913 case 16:
914 pfx = P_O16;
915 break;
916 case 32:
917 pfx = P_O32;
918 break;
919 case 64:
920 pfx = P_O64;
921 break;
922 }
923
924 if (ins->prefixes[PPS_OSIZE])
925 return false;
926 ins->prefixes[PPS_OSIZE] = pfx;
927 }
928 }
929 if (!a_used && asize != segsize) {
930 if (ins->prefixes[PPS_ASIZE])
931 return false;
932 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
933 }
934
935 /* Fix: check for redundant REX prefixes */
936
937 return data - origdata;
938 }
939
940 /* Condition names for disassembly, sorted by x86 code */
941 static const char * const condition_name[16] = {
942 "o", "no", "c", "nc", "z", "nz", "na", "a",
943 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
944 };
945
946 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
947 int32_t offset, int autosync, iflags_t prefer)
948 {
949 const struct itemplate * const *p, * const *best_p;
950 const struct disasm_index *ix;
951 uint8_t *dp;
952 int length, best_length = 0;
953 char *segover;
954 int i, slen, colon, n;
955 uint8_t *origdata;
956 int works;
957 insn tmp_ins, ins;
958 iflags_t goodness, best, flags;
959 int best_pref;
960 struct prefix_info prefix;
961 bool end_prefix;
962
963 memset(&ins, 0, sizeof ins);
964
965 /*
966 * Scan for prefixes.
967 */
968 memset(&prefix, 0, sizeof prefix);
969 prefix.asize = segsize;
970 prefix.osize = (segsize == 64) ? 32 : segsize;
971 segover = NULL;
972 origdata = data;
973
974 ix = itable;
975
976 end_prefix = false;
977 while (!end_prefix) {
978 switch (*data) {
979 case 0xF2:
980 case 0xF3:
981 prefix.rep = *data++;
982 break;
983
984 case 0x9B:
985 prefix.wait = *data++;
986 break;
987
988 case 0xF0:
989 prefix.lock = *data++;
990 break;
991
992 case 0x2E:
993 segover = "cs", prefix.seg = *data++;
994 break;
995 case 0x36:
996 segover = "ss", prefix.seg = *data++;
997 break;
998 case 0x3E:
999 segover = "ds", prefix.seg = *data++;
1000 break;
1001 case 0x26:
1002 segover = "es", prefix.seg = *data++;
1003 break;
1004 case 0x64:
1005 segover = "fs", prefix.seg = *data++;
1006 break;
1007 case 0x65:
1008 segover = "gs", prefix.seg = *data++;
1009 break;
1010
1011 case 0x66:
1012 prefix.osize = (segsize == 16) ? 32 : 16;
1013 prefix.osp = *data++;
1014 break;
1015 case 0x67:
1016 prefix.asize = (segsize == 32) ? 16 : 32;
1017 prefix.asp = *data++;
1018 break;
1019
1020 case 0xC4:
1021 case 0xC5:
1022 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1023 prefix.vex[0] = *data++;
1024 prefix.vex[1] = *data++;
1025
1026 prefix.rex = REX_V;
1027 prefix.vex_c = RV_VEX;
1028
1029 if (prefix.vex[0] == 0xc4) {
1030 prefix.vex[2] = *data++;
1031 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1032 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1033 prefix.vex_m = prefix.vex[1] & 0x1f;
1034 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1035 prefix.vex_lp = prefix.vex[2] & 7;
1036 } else {
1037 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1038 prefix.vex_m = 1;
1039 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1040 prefix.vex_lp = prefix.vex[1] & 7;
1041 }
1042
1043 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1044 }
1045 end_prefix = true;
1046 break;
1047
1048 case 0x8F:
1049 if ((data[1] & 030) != 0 &&
1050 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1051 prefix.vex[0] = *data++;
1052 prefix.vex[1] = *data++;
1053 prefix.vex[2] = *data++;
1054
1055 prefix.rex = REX_V;
1056 prefix.vex_c = RV_XOP;
1057
1058 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1059 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1060 prefix.vex_m = prefix.vex[1] & 0x1f;
1061 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1062 prefix.vex_lp = prefix.vex[2] & 7;
1063
1064 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1065 }
1066 end_prefix = true;
1067 break;
1068
1069 case REX_P + 0x0:
1070 case REX_P + 0x1:
1071 case REX_P + 0x2:
1072 case REX_P + 0x3:
1073 case REX_P + 0x4:
1074 case REX_P + 0x5:
1075 case REX_P + 0x6:
1076 case REX_P + 0x7:
1077 case REX_P + 0x8:
1078 case REX_P + 0x9:
1079 case REX_P + 0xA:
1080 case REX_P + 0xB:
1081 case REX_P + 0xC:
1082 case REX_P + 0xD:
1083 case REX_P + 0xE:
1084 case REX_P + 0xF:
1085 if (segsize == 64) {
1086 prefix.rex = *data++;
1087 if (prefix.rex & REX_W)
1088 prefix.osize = 64;
1089 }
1090 end_prefix = true;
1091 break;
1092
1093 default:
1094 end_prefix = true;
1095 break;
1096 }
1097 }
1098
1099 best = -1; /* Worst possible */
1100 best_p = NULL;
1101 best_pref = INT_MAX;
1102
1103 if (!ix)
1104 return 0; /* No instruction table at all... */
1105
1106 dp = data;
1107 ix += *dp++;
1108 while (ix->n == -1) {
1109 ix = (const struct disasm_index *)ix->p + *dp++;
1110 }
1111
1112 p = (const struct itemplate * const *)ix->p;
1113 for (n = ix->n; n; n--, p++) {
1114 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1115 works = true;
1116 /*
1117 * Final check to make sure the types of r/m match up.
1118 * XXX: Need to make sure this is actually correct.
1119 */
1120 for (i = 0; i < (*p)->operands; i++) {
1121 if (
1122 /* If it's a mem-only EA but we have a
1123 register, die. */
1124 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1125 is_class(MEMORY, (*p)->opd[i])) ||
1126 /* If it's a reg-only EA but we have a memory
1127 ref, die. */
1128 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1129 !(REG_EA & ~(*p)->opd[i]) &&
1130 !((*p)->opd[i] & REG_SMASK)) ||
1131 /* Register type mismatch (eg FS vs REG_DESS):
1132 die. */
1133 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1134 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1135 !whichreg((*p)->opd[i],
1136 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1137 ) {
1138 works = false;
1139 break;
1140 }
1141 }
1142
1143 /*
1144 * Note: we always prefer instructions which incorporate
1145 * prefixes in the instructions themselves. This is to allow
1146 * e.g. PAUSE to be preferred to REP NOP, and deal with
1147 * MMX/SSE instructions where prefixes are used to select
1148 * between MMX and SSE register sets or outright opcode
1149 * selection.
1150 */
1151 if (works) {
1152 int i, nprefix;
1153 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1154 nprefix = 0;
1155 for (i = 0; i < MAXPREFIX; i++)
1156 if (tmp_ins.prefixes[i])
1157 nprefix++;
1158 if (nprefix < best_pref ||
1159 (nprefix == best_pref && goodness < best)) {
1160 /* This is the best one found so far */
1161 best = goodness;
1162 best_p = p;
1163 best_pref = nprefix;
1164 best_length = length;
1165 ins = tmp_ins;
1166 }
1167 }
1168 }
1169 }
1170
1171 if (!best_p)
1172 return 0; /* no instruction was matched */
1173
1174 /* Pick the best match */
1175 p = best_p;
1176 length = best_length;
1177 flags = (*p)->flags;
1178
1179 slen = 0;
1180
1181 /* TODO: snprintf returns the value that the string would have if
1182 * the buffer were long enough, and not the actual length of
1183 * the returned string, so each instance of using the return
1184 * value of snprintf should actually be checked to assure that
1185 * the return value is "sane." Maybe a macro wrapper could
1186 * be used for that purpose.
1187 */
1188 for (i = 0; i < MAXPREFIX; i++) {
1189 const char *prefix = prefix_name(ins.prefixes[i]);
1190 if (prefix)
1191 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1192 }
1193
1194 i = (*p)->opcode;
1195 if (i >= FIRST_COND_OPCODE)
1196 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1197 nasm_insn_names[i], condition_name[ins.condition]);
1198 else
1199 slen += snprintf(output + slen, outbufsize - slen, "%s",
1200 nasm_insn_names[i]);
1201
1202 colon = false;
1203 length += data - origdata; /* fix up for prefixes */
1204 for (i = 0; i < (*p)->operands; i++) {
1205 opflags_t t = (*p)->opd[i];
1206 const operand *o = &ins.oprs[i];
1207 int64_t offs;
1208
1209 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1210
1211 offs = o->offset;
1212 if (o->segment & SEG_RELATIVE) {
1213 offs += offset + length;
1214 /*
1215 * sort out wraparound
1216 */
1217 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1218 offs &= 0xffff;
1219 else if (segsize != 64)
1220 offs &= 0xffffffff;
1221
1222 /*
1223 * add sync marker, if autosync is on
1224 */
1225 if (autosync)
1226 add_sync(offs, 0L);
1227 }
1228
1229 if (t & COLON)
1230 colon = true;
1231 else
1232 colon = false;
1233
1234 if ((t & (REGISTER | FPUREG)) ||
1235 (o->segment & SEG_RMREG)) {
1236 enum reg_enum reg;
1237 reg = whichreg(t, o->basereg, ins.rex);
1238 if (t & TO)
1239 slen += snprintf(output + slen, outbufsize - slen, "to ");
1240 slen += snprintf(output + slen, outbufsize - slen, "%s",
1241 nasm_reg_names[reg-EXPR_REG_START]);
1242 } else if (!(UNITY & ~t)) {
1243 output[slen++] = '1';
1244 } else if (t & IMMEDIATE) {
1245 if (t & BITS8) {
1246 slen +=
1247 snprintf(output + slen, outbufsize - slen, "byte ");
1248 if (o->segment & SEG_SIGNED) {
1249 if (offs < 0) {
1250 offs *= -1;
1251 output[slen++] = '-';
1252 } else
1253 output[slen++] = '+';
1254 }
1255 } else if (t & BITS16) {
1256 slen +=
1257 snprintf(output + slen, outbufsize - slen, "word ");
1258 } else if (t & BITS32) {
1259 slen +=
1260 snprintf(output + slen, outbufsize - slen, "dword ");
1261 } else if (t & BITS64) {
1262 slen +=
1263 snprintf(output + slen, outbufsize - slen, "qword ");
1264 } else if (t & NEAR) {
1265 slen +=
1266 snprintf(output + slen, outbufsize - slen, "near ");
1267 } else if (t & SHORT) {
1268 slen +=
1269 snprintf(output + slen, outbufsize - slen, "short ");
1270 }
1271 slen +=
1272 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1273 offs);
1274 } else if (!(MEM_OFFS & ~t)) {
1275 slen +=
1276 snprintf(output + slen, outbufsize - slen,
1277 "[%s%s%s0x%"PRIx64"]",
1278 (segover ? segover : ""),
1279 (segover ? ":" : ""),
1280 (o->disp_size == 64 ? "qword " :
1281 o->disp_size == 32 ? "dword " :
1282 o->disp_size == 16 ? "word " : ""), offs);
1283 segover = NULL;
1284 } else if (is_class(REGMEM, t)) {
1285 int started = false;
1286 if (t & BITS8)
1287 slen +=
1288 snprintf(output + slen, outbufsize - slen, "byte ");
1289 if (t & BITS16)
1290 slen +=
1291 snprintf(output + slen, outbufsize - slen, "word ");
1292 if (t & BITS32)
1293 slen +=
1294 snprintf(output + slen, outbufsize - slen, "dword ");
1295 if (t & BITS64)
1296 slen +=
1297 snprintf(output + slen, outbufsize - slen, "qword ");
1298 if (t & BITS80)
1299 slen +=
1300 snprintf(output + slen, outbufsize - slen, "tword ");
1301 if (t & BITS128)
1302 slen +=
1303 snprintf(output + slen, outbufsize - slen, "oword ");
1304 if (t & BITS256)
1305 slen +=
1306 snprintf(output + slen, outbufsize - slen, "yword ");
1307 if (t & BITS512)
1308 slen +=
1309 snprintf(output + slen, outbufsize - slen, "zword ");
1310 if (t & FAR)
1311 slen += snprintf(output + slen, outbufsize - slen, "far ");
1312 if (t & NEAR)
1313 slen +=
1314 snprintf(output + slen, outbufsize - slen, "near ");
1315 output[slen++] = '[';
1316 if (o->disp_size)
1317 slen += snprintf(output + slen, outbufsize - slen, "%s",
1318 (o->disp_size == 64 ? "qword " :
1319 o->disp_size == 32 ? "dword " :
1320 o->disp_size == 16 ? "word " :
1321 ""));
1322 if (o->eaflags & EAF_REL)
1323 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1324 if (segover) {
1325 slen +=
1326 snprintf(output + slen, outbufsize - slen, "%s:",
1327 segover);
1328 segover = NULL;
1329 }
1330 if (o->basereg != -1) {
1331 slen += snprintf(output + slen, outbufsize - slen, "%s",
1332 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1333 started = true;
1334 }
1335 if (o->indexreg != -1 && !(flags & IF_MIB)) {
1336 if (started)
1337 output[slen++] = '+';
1338 slen += snprintf(output + slen, outbufsize - slen, "%s",
1339 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1340 if (o->scale > 1)
1341 slen +=
1342 snprintf(output + slen, outbufsize - slen, "*%d",
1343 o->scale);
1344 started = true;
1345 }
1346
1347
1348 if (o->segment & SEG_DISP8) {
1349 const char *prefix;
1350 uint8_t offset = offs;
1351 if ((int8_t)offset < 0) {
1352 prefix = "-";
1353 offset = -offset;
1354 } else {
1355 prefix = "+";
1356 }
1357 slen +=
1358 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1359 prefix, offset);
1360 } else if (o->segment & SEG_DISP16) {
1361 const char *prefix;
1362 uint16_t offset = offs;
1363 if ((int16_t)offset < 0 && started) {
1364 offset = -offset;
1365 prefix = "-";
1366 } else {
1367 prefix = started ? "+" : "";
1368 }
1369 slen +=
1370 snprintf(output + slen, outbufsize - slen,
1371 "%s0x%"PRIx16"", prefix, offset);
1372 } else if (o->segment & SEG_DISP32) {
1373 if (prefix.asize == 64) {
1374 const char *prefix;
1375 uint64_t offset = (int64_t)(int32_t)offs;
1376 if ((int32_t)offs < 0 && started) {
1377 offset = -offset;
1378 prefix = "-";
1379 } else {
1380 prefix = started ? "+" : "";
1381 }
1382 slen +=
1383 snprintf(output + slen, outbufsize - slen,
1384 "%s0x%"PRIx64"", prefix, offset);
1385 } else {
1386 const char *prefix;
1387 uint32_t offset = offs;
1388 if ((int32_t) offset < 0 && started) {
1389 offset = -offset;
1390 prefix = "-";
1391 } else {
1392 prefix = started ? "+" : "";
1393 }
1394 slen +=
1395 snprintf(output + slen, outbufsize - slen,
1396 "%s0x%"PRIx32"", prefix, offset);
1397 }
1398 }
1399
1400 if (o->indexreg != -1 && (flags & IF_MIB)) {
1401 output[slen++] = ',';
1402 slen += snprintf(output + slen, outbufsize - slen, "%s",
1403 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1404 if (o->scale > 1)
1405 slen +=
1406 snprintf(output + slen, outbufsize - slen, "*%d",
1407 o->scale);
1408 started = true;
1409 }
1410
1411 output[slen++] = ']';
1412 } else {
1413 slen +=
1414 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1415 i);
1416 }
1417 }
1418 output[slen] = '\0';
1419 if (segover) { /* unused segment override */
1420 char *p = output;
1421 int count = slen + 1;
1422 while (count--)
1423 p[count + 3] = p[count];
1424 strncpy(output, segover, 2);
1425 output[2] = ' ';
1426 }
1427 return length;
1428 }
1429
1430 /*
1431 * This is called when we don't have a complete instruction. If it
1432 * is a standalone *single-byte* prefix show it as such, otherwise
1433 * print it as a literal.
1434 */
1435 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1436 {
1437 uint8_t byte = *data;
1438 const char *str = NULL;
1439
1440 switch (byte) {
1441 case 0xF2:
1442 str = "repne";
1443 break;
1444 case 0xF3:
1445 str = "rep";
1446 break;
1447 case 0x9B:
1448 str = "wait";
1449 break;
1450 case 0xF0:
1451 str = "lock";
1452 break;
1453 case 0x2E:
1454 str = "cs";
1455 break;
1456 case 0x36:
1457 str = "ss";
1458 break;
1459 case 0x3E:
1460 str = "ss";
1461 break;
1462 case 0x26:
1463 str = "es";
1464 break;
1465 case 0x64:
1466 str = "fs";
1467 break;
1468 case 0x65:
1469 str = "gs";
1470 break;
1471 case 0x66:
1472 str = (segsize == 16) ? "o32" : "o16";
1473 break;
1474 case 0x67:
1475 str = (segsize == 32) ? "a16" : "a32";
1476 break;
1477 case REX_P + 0x0:
1478 case REX_P + 0x1:
1479 case REX_P + 0x2:
1480 case REX_P + 0x3:
1481 case REX_P + 0x4:
1482 case REX_P + 0x5:
1483 case REX_P + 0x6:
1484 case REX_P + 0x7:
1485 case REX_P + 0x8:
1486 case REX_P + 0x9:
1487 case REX_P + 0xA:
1488 case REX_P + 0xB:
1489 case REX_P + 0xC:
1490 case REX_P + 0xD:
1491 case REX_P + 0xE:
1492 case REX_P + 0xF:
1493 if (segsize == 64) {
1494 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1495 (byte == REX_P) ? "" : ".",
1496 (byte & REX_W) ? "w" : "",
1497 (byte & REX_R) ? "r" : "",
1498 (byte & REX_X) ? "x" : "",
1499 (byte & REX_B) ? "b" : "");
1500 break;
1501 }
1502 /* else fall through */
1503 default:
1504 snprintf(output, outbufsize, "db 0x%02x", byte);
1505 break;
1506 }
1507
1508 if (str)
1509 snprintf(output, outbufsize, "%s", str);
1510
1511 return 1;
1512 }
Adding AVX-512 features