1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
22 extern struct itemplate
**itable
[];
25 * Flags that go into the `segment' field of `insn' structures
28 #define SEG_RELATIVE 1
35 #define SEG_SIGNED 128
40 #define getu8(x) (*(uint8_t *)(x))
41 #if defined(__i386__) || defined(__x86_64__)
42 /* Littleendian CPU which can handle unaligned references */
43 #define getu16(x) (*(uint16_t *)(x))
44 #define getu32(x) (*(uint32_t *)(x))
45 #define getu64(x) (*(uint64_t *)(x))
47 static uint16_t getu16(uint8_t *data
)
49 return (uint16_t)data
[0] + ((uint16_t)data
[1] << 8);
51 static uint32_t getu32(uint8_t *data
)
53 return (uint32_t)getu16(data
) + ((uint32_t)getu16(data
+2) << 16);
55 static uint64_t getu64(uint8_t *data
)
57 return (uint64_t)getu32(data
) + ((uint64_t)getu32(data
+4) << 32);
61 #define gets8(x) ((int8_t)getu8(x))
62 #define gets16(x) ((int16_t)getu16(x))
63 #define gets32(x) ((int32_t)getu32(x))
64 #define gets64(x) ((int64_t)getu64(x))
66 /* Important: regval must already have been adjusted for rex extensions */
67 static int whichreg(int32_t regflags
, int regval
, int rex
)
69 if (!(REG_AL
& ~regflags
))
71 if (!(REG_AX
& ~regflags
))
73 if (!(REG_EAX
& ~regflags
))
75 if (!(REG_RAX
& ~regflags
))
77 if (!(REG_DL
& ~regflags
))
79 if (!(REG_DX
& ~regflags
))
81 if (!(REG_EDX
& ~regflags
))
83 if (!(REG_RDX
& ~regflags
))
85 if (!(REG_CL
& ~regflags
))
87 if (!(REG_CX
& ~regflags
))
89 if (!(REG_ECX
& ~regflags
))
91 if (!(REG_RCX
& ~regflags
))
93 if (!(FPU0
& ~regflags
))
95 if (!(REG_CS
& ~regflags
))
96 return (regval
== 1) ? R_CS
: 0;
97 if (!(REG_DESS
& ~regflags
))
98 return (regval
== 0 || regval
== 2
99 || regval
== 3 ? rd_sreg
[regval
] : 0);
100 if (!(REG_FSGS
& ~regflags
))
101 return (regval
== 4 || regval
== 5 ? rd_sreg
[regval
] : 0);
102 if (!(REG_SEG67
& ~regflags
))
103 return (regval
== 6 || regval
== 7 ? rd_sreg
[regval
] : 0);
105 /* All the entries below look up regval in an 16-entry array */
106 if (regval
< 0 || regval
> 15)
109 if (!((REGMEM
| BITS8
) & ~regflags
)) {
111 return rd_reg8_rex
[regval
];
113 return rd_reg8
[regval
];
115 if (!((REGMEM
| BITS16
) & ~regflags
))
116 return rd_reg16
[regval
];
117 if (!((REGMEM
| BITS32
) & ~regflags
))
118 return rd_reg32
[regval
];
119 if (!((REGMEM
| BITS64
) & ~regflags
))
120 return rd_reg64
[regval
];
121 if (!(REG_SREG
& ~regflags
))
122 return rd_sreg
[regval
& 7]; /* Ignore REX */
123 if (!(REG_CREG
& ~regflags
))
124 return rd_creg
[regval
];
125 if (!(REG_DREG
& ~regflags
))
126 return rd_dreg
[regval
];
127 if (!(REG_TREG
& ~regflags
)) {
129 return 0; /* TR registers are ill-defined with rex */
130 return rd_treg
[regval
];
132 if (!(FPUREG
& ~regflags
))
133 return rd_fpureg
[regval
& 7]; /* Ignore REX */
134 if (!(MMXREG
& ~regflags
))
135 return rd_mmxreg
[regval
& 7]; /* Ignore REX */
136 if (!(XMMREG
& ~regflags
))
137 return rd_xmmreg
[regval
];
142 static const char *whichcond(int condval
)
144 static int conds
[] = {
145 C_O
, C_NO
, C_C
, C_NC
, C_Z
, C_NZ
, C_NA
, C_A
,
146 C_S
, C_NS
, C_PE
, C_PO
, C_L
, C_NL
, C_NG
, C_G
148 return conditions
[conds
[condval
]];
152 * Process an effective address (ModRM) specification.
154 static uint8_t *do_ea(uint8_t *data
, int modrm
, int asize
,
155 int segsize
, operand
* op
, int rex
)
157 int mod
, rm
, scale
, index
, base
;
159 mod
= (modrm
>> 6) & 03;
162 if (mod
== 3) { /* pure register version */
163 op
->basereg
= rm
+(rex
& REX_B
? 8 : 0);
164 op
->segment
|= SEG_RMREG
;
173 * <mod> specifies the displacement size (none, byte or
174 * word), and <rm> specifies the register combination.
175 * Exception: mod=0,rm=6 does not specify [BP] as one might
176 * expect, but instead specifies [disp16].
178 op
->indexreg
= op
->basereg
= -1;
179 op
->scale
= 1; /* always, in 16 bits */
210 if (rm
== 6 && mod
== 0) { /* special case */
214 mod
= 2; /* fake disp16 */
218 op
->segment
|= SEG_NODISP
;
221 op
->segment
|= SEG_DISP8
;
222 op
->offset
= (int8_t)*data
++;
225 op
->segment
|= SEG_DISP16
;
226 op
->offset
= *data
++;
227 op
->offset
|= ((unsigned)*data
++) << 8;
233 * Once again, <mod> specifies displacement size (this time
234 * none, byte or *dword*), while <rm> specifies the base
235 * register. Again, [EBP] is missing, replaced by a pure
236 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
237 * and RIP-relative addressing in 64-bit mode.
240 * indicates not a single base register, but instead the
241 * presence of a SIB byte...
243 int a64
= asize
== 64;
248 op
->basereg
= rd_reg64
[rm
| ((rex
& REX_B
) ? 8 : 0)];
250 op
->basereg
= rd_reg32
[rm
| ((rex
& REX_B
) ? 8 : 0)];
252 if (rm
== 5 && mod
== 0) {
254 op
->eaflags
|= EAF_REL
;
255 op
->segment
|= SEG_RELATIVE
;
256 mod
= 2; /* fake disp32 */
260 op
->addr_size
= asize
;
263 mod
= 2; /* fake disp32 */
266 if (rm
== 4) { /* process SIB */
267 scale
= (*data
>> 6) & 03;
268 index
= (*data
>> 3) & 07;
272 op
->scale
= 1 << scale
;
275 op
->indexreg
= -1; /* ESP/RSP/R12 cannot be an index */
277 op
->indexreg
= rd_reg64
[index
| ((rex
& REX_X
) ? 8 : 0)];
279 op
->indexreg
= rd_reg64
[index
| ((rex
& REX_X
) ? 8 : 0)];
281 if (base
== 5 && mod
== 0) {
283 mod
= 2; /* Fake disp32 */
285 op
->basereg
= rd_reg64
[base
| ((rex
& REX_B
) ? 8 : 0)];
287 op
->basereg
= rd_reg32
[base
| ((rex
& REX_B
) ? 8 : 0)];
295 op
->segment
|= SEG_NODISP
;
298 op
->segment
|= SEG_DISP8
;
299 op
->offset
= gets8(data
);
303 op
->segment
|= SEG_DISP32
;
304 op
->offset
= getu32(data
);
313 * Determine whether the instruction template in t corresponds to the data
314 * stream in data. Return the number of bytes matched if so.
316 static int matches(struct itemplate
*t
, uint8_t *data
, int asize
,
317 int osize
, int segsize
, int rep
, insn
* ins
,
318 int rex
, int *rexout
, int lock
)
320 uint8_t *r
= (uint8_t *)(t
->code
);
321 uint8_t *origdata
= data
;
322 int a_used
= FALSE
, o_used
= FALSE
;
327 if (t
->flags
& (segsize
== 64 ? IF_NOLONG
: IF_LONG
))
332 else if (rep
== 0xF3)
338 /* FIX: change this into a switch */
339 if (c
>= 01 && c
<= 03) {
343 } else if (c
== 04) {
346 ins
->oprs
[0].basereg
= 0;
349 ins
->oprs
[0].basereg
= 2;
352 ins
->oprs
[0].basereg
= 3;
357 } else if (c
== 05) {
360 ins
->oprs
[0].basereg
= 4;
363 ins
->oprs
[0].basereg
= 5;
368 } else if (c
== 06) {
371 ins
->oprs
[0].basereg
= 0;
374 ins
->oprs
[0].basereg
= 1;
377 ins
->oprs
[0].basereg
= 2;
380 ins
->oprs
[0].basereg
= 3;
385 } else if (c
== 07) {
388 ins
->oprs
[0].basereg
= 4;
391 ins
->oprs
[0].basereg
= 5;
396 } else if (c
>= 010 && c
<= 012) {
397 int t
= *r
++, d
= *data
++;
398 if (d
< t
|| d
> t
+ 7)
401 ins
->oprs
[c
- 010].basereg
= (d
-t
)+(rex
& REX_B
? 8 : 0);
402 ins
->oprs
[c
- 010].segment
|= SEG_RMREG
;
404 } else if (c
== 017) {
407 } else if (c
>= 014 && c
<= 016) {
408 ins
->oprs
[c
- 014].offset
= (int8_t)*data
++;
409 ins
->oprs
[c
- 014].segment
|= SEG_SIGNED
;
410 } else if (c
>= 020 && c
<= 022) {
411 ins
->oprs
[c
- 020].offset
= *data
++;
412 } else if (c
>= 024 && c
<= 026) {
413 ins
->oprs
[c
- 024].offset
= *data
++;
414 } else if (c
>= 030 && c
<= 032) {
415 ins
->oprs
[c
- 030].offset
= getu16(data
);
417 } else if (c
>= 034 && c
<= 036) {
419 ins
->oprs
[c
- 034].offset
= getu32(data
);
422 ins
->oprs
[c
- 034].offset
= getu16(data
);
425 if (segsize
!= asize
)
426 ins
->oprs
[c
- 034].addr_size
= asize
;
427 } else if (c
>= 040 && c
<= 042) {
428 ins
->oprs
[c
- 040].offset
= getu32(data
);
430 } else if (c
>= 044 && c
<= 046) {
433 ins
->oprs
[c
- 044].offset
= getu16(data
);
437 ins
->oprs
[c
- 044].offset
= getu32(data
);
441 ins
->oprs
[c
- 044].offset
= getu64(data
);
445 if (segsize
!= asize
)
446 ins
->oprs
[c
- 044].addr_size
= asize
;
447 } else if (c
>= 050 && c
<= 052) {
448 ins
->oprs
[c
- 050].offset
= gets8(data
++);
449 ins
->oprs
[c
- 050].segment
|= SEG_RELATIVE
;
450 } else if (c
>= 054 && c
<= 056) {
451 ins
->oprs
[c
- 054].offset
= getu64(data
);
453 } else if (c
>= 060 && c
<= 062) {
454 ins
->oprs
[c
- 060].offset
= gets16(data
);
456 ins
->oprs
[c
- 060].segment
|= SEG_RELATIVE
;
457 ins
->oprs
[c
- 060].segment
&= ~SEG_32BIT
;
458 } else if (c
>= 064 && c
<= 066) {
460 ins
->oprs
[c
- 064].offset
= getu16(data
);
462 ins
->oprs
[c
- 064].segment
&= ~(SEG_32BIT
|SEG_64BIT
);
463 } else if (osize
== 32) {
464 ins
->oprs
[c
- 064].offset
= getu32(data
);
466 ins
->oprs
[c
- 064].segment
&= ~SEG_64BIT
;
467 ins
->oprs
[c
- 064].segment
|= SEG_32BIT
;
469 if (segsize
!= osize
) {
470 ins
->oprs
[c
- 064].type
=
471 (ins
->oprs
[c
- 064].type
& ~SIZE_MASK
)
472 | ((osize
== 16) ? BITS16
: BITS32
);
474 } else if (c
>= 070 && c
<= 072) {
475 ins
->oprs
[c
- 070].offset
= getu32(data
);
477 ins
->oprs
[c
- 070].segment
|= SEG_32BIT
| SEG_RELATIVE
;
478 } else if (c
>= 0100 && c
< 0130) {
480 ins
->oprs
[c
& 07].basereg
= ((modrm
>> 3)&7)+(rex
& REX_R
? 8 : 0);
481 ins
->oprs
[c
& 07].segment
|= SEG_RMREG
;
482 data
= do_ea(data
, modrm
, asize
, segsize
,
483 &ins
->oprs
[(c
>> 3) & 07], rex
);
484 } else if (c
>= 0130 && c
<= 0132) {
485 ins
->oprs
[c
- 0130].offset
= getu16(data
);
487 } else if (c
>= 0140 && c
<= 0142) {
488 ins
->oprs
[c
- 0140].offset
= getu32(data
);
490 } else if (c
>= 0200 && c
<= 0277) {
492 if (((modrm
>> 3) & 07) != (c
& 07))
493 return FALSE
; /* spare field doesn't match up */
494 data
= do_ea(data
, modrm
, asize
, segsize
,
495 &ins
->oprs
[(c
>> 3) & 07], rex
);
496 } else if (c
>= 0300 && c
<= 0302) {
498 } else if (c
== 0310) {
503 } else if (c
== 0311) {
508 } else if (c
== 0312) {
509 if (asize
!= segsize
)
513 } else if (c
== 0313) {
518 } else if (c
== 0320) {
523 } else if (c
== 0321) {
528 } else if (c
== 0322) {
529 if (osize
!= (segsize
== 16) ? 16 : 32)
533 } else if (c
== 0323) {
534 rex
|= REX_W
; /* 64-bit only instruction */
536 } else if (c
== 0324) {
537 if (!(rex
& (REX_P
|REX_W
)) || osize
!= 64)
539 } else if (c
== 0330) {
540 int t
= *r
++, d
= *data
++;
541 if (d
< t
|| d
> t
+ 15)
544 ins
->condition
= d
- t
;
545 } else if (c
== 0331) {
548 } else if (c
== 0332) {
551 } else if (c
== 0333) {
555 } else if (c
== 0334) {
564 * Check for unused rep or a/o prefixes.
568 ins
->prefixes
[ins
->nprefix
++] = P_LOCK
;
570 ins
->prefixes
[ins
->nprefix
++] = drep
;
571 if (!a_used
&& asize
!= segsize
)
572 ins
->prefixes
[ins
->nprefix
++] = asize
== 16 ? P_A16
: P_A32
;
573 if (!o_used
&& osize
== ((segsize
== 16) ? 32 : 16))
574 ins
->prefixes
[ins
->nprefix
++] = osize
== 16 ? P_O16
: P_O32
;
576 /* Fix: check for redundant REX prefixes */
579 return data
- origdata
;
582 int32_t disasm(uint8_t *data
, char *output
, int outbufsize
, int segsize
,
583 int32_t offset
, int autosync
, uint32_t prefer
)
585 struct itemplate
**p
, **best_p
;
586 int length
, best_length
= 0;
588 int rep
, lock
, asize
, osize
, i
, slen
, colon
, rex
, rexout
, best_rex
;
592 uint32_t goodness
, best
;
598 osize
= (segsize
== 64) ? 32 : segsize
;
604 if (*data
== 0xF3 || *data
== 0xF2)
606 else if (*data
== 0xF0)
608 else if (*data
== 0x2E)
609 segover
= "cs", data
++;
610 else if (*data
== 0x36)
611 segover
= "ss", data
++;
612 else if (*data
== 0x3E)
613 segover
= "ds", data
++;
614 else if (*data
== 0x26)
615 segover
= "es", data
++;
616 else if (*data
== 0x64)
617 segover
= "fs", data
++;
618 else if (*data
== 0x65)
619 segover
= "gs", data
++;
620 else if (*data
== 0x66) {
621 osize
= (segsize
== 16) ? 32 : 16;
623 } else if (*data
== 0x67) {
624 asize
= (segsize
== 32) ? 16 : 32;
626 } else if (segsize
== 64 && (*data
& 0xf0) == REX_P
) {
630 break; /* REX is always the last prefix */
636 tmp_ins
.oprs
[0].segment
= tmp_ins
.oprs
[1].segment
=
637 tmp_ins
.oprs
[2].segment
=
638 tmp_ins
.oprs
[0].addr_size
= tmp_ins
.oprs
[1].addr_size
=
639 tmp_ins
.oprs
[2].addr_size
= (segsize
== 64 ? SEG_64BIT
:
640 segsize
== 32 ? SEG_32BIT
: 0);
641 tmp_ins
.condition
= -1;
642 best
= -1; /* Worst possible */
645 for (p
= itable
[*data
]; *p
; p
++) {
646 if ((length
= matches(*p
, data
, asize
, osize
, segsize
, rep
,
647 &tmp_ins
, rex
, &rexout
, lock
))) {
650 * Final check to make sure the types of r/m match up.
651 * XXX: Need to make sure this is actually correct.
653 for (i
= 0; i
< (*p
)->operands
; i
++) {
655 /* If it's a mem-only EA but we have a register, die. */
656 ((tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
657 !(MEMORY
& ~(*p
)->opd
[i
])) ||
658 /* If it's a reg-only EA but we have a memory ref, die. */
659 (!(tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
660 !(REG_EA
& ~(*p
)->opd
[i
]) &&
661 !((*p
)->opd
[i
] & REG_SMASK
)) ||
662 /* Register type mismatch (eg FS vs REG_DESS): die. */
663 ((((*p
)->opd
[i
] & (REGISTER
| FPUREG
)) ||
664 (tmp_ins
.oprs
[i
].segment
& SEG_RMREG
)) &&
665 !whichreg((*p
)->opd
[i
],
666 tmp_ins
.oprs
[i
].basereg
, rexout
))) {
673 goodness
= ((*p
)->flags
& IF_PFMASK
) ^ prefer
;
674 if (goodness
< best
) {
675 /* This is the best one found so far */
678 best_length
= length
;
687 return 0; /* no instruction was matched */
689 /* Pick the best match */
691 length
= best_length
;
693 if (best_rex
& REX_W
)
698 /* TODO: snprintf returns the value that the string would have if
699 * the buffer were long enough, and not the actual length of
700 * the returned string, so each instance of using the return
701 * value of snprintf should actually be checked to assure that
702 * the return value is "sane." Maybe a macro wrapper could
703 * be used for that purpose.
705 for (i
= 0; i
< ins
.nprefix
; i
++)
706 switch (ins
.prefixes
[i
]) {
708 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "lock ");
711 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "rep ");
714 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "repe ");
717 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "repne ");
720 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "a16 ");
723 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "a32 ");
726 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "o16 ");
729 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "o32 ");
733 for (i
= 0; i
< elements(ico
); i
++)
734 if ((*p
)->opcode
== ico
[i
]) {
736 snprintf(output
+ slen
, outbufsize
- slen
, "%s%s", icn
[i
],
737 whichcond(ins
.condition
));
740 if (i
>= elements(ico
))
742 snprintf(output
+ slen
, outbufsize
- slen
, "%s",
743 insn_names
[(*p
)->opcode
]);
745 length
+= data
- origdata
; /* fix up for prefixes */
746 for (i
= 0; i
< (*p
)->operands
; i
++) {
747 output
[slen
++] = (colon
? ':' : i
== 0 ? ' ' : ',');
749 if (ins
.oprs
[i
].segment
& SEG_RELATIVE
) {
750 ins
.oprs
[i
].offset
+= offset
+ length
;
752 * sort out wraparound
754 if (!(ins
.oprs
[i
].segment
& (SEG_32BIT
|SEG_64BIT
)))
755 ins
.oprs
[i
].offset
&= 0xffff;
757 * add sync marker, if autosync is on
760 add_sync(ins
.oprs
[i
].offset
, 0L);
763 if ((*p
)->opd
[i
] & COLON
)
768 if (((*p
)->opd
[i
] & (REGISTER
| FPUREG
)) ||
769 (ins
.oprs
[i
].segment
& SEG_RMREG
)) {
770 ins
.oprs
[i
].basereg
= whichreg((*p
)->opd
[i
],
771 ins
.oprs
[i
].basereg
, rex
);
772 if ((*p
)->opd
[i
] & TO
)
773 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "to ");
774 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
775 reg_names
[ins
.oprs
[i
].basereg
-
777 } else if (!(UNITY
& ~(*p
)->opd
[i
])) {
778 output
[slen
++] = '1';
779 } else if ((*p
)->opd
[i
] & IMMEDIATE
) {
780 if ((*p
)->opd
[i
] & BITS8
) {
782 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
783 if (ins
.oprs
[i
].segment
& SEG_SIGNED
) {
784 if (ins
.oprs
[i
].offset
< 0) {
785 ins
.oprs
[i
].offset
*= -1;
786 output
[slen
++] = '-';
788 output
[slen
++] = '+';
790 } else if ((*p
)->opd
[i
] & BITS16
) {
792 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
793 } else if ((*p
)->opd
[i
] & BITS32
) {
795 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
796 } else if ((*p
)->opd
[i
] & BITS64
) {
798 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
799 } else if ((*p
)->opd
[i
] & NEAR
) {
801 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
802 } else if ((*p
)->opd
[i
] & SHORT
) {
804 snprintf(output
+ slen
, outbufsize
- slen
, "short ");
807 snprintf(output
+ slen
, outbufsize
- slen
, "0x%"PRIx64
"",
809 } else if (!(MEM_OFFS
& ~(*p
)->opd
[i
])) {
811 snprintf(output
+ slen
, outbufsize
- slen
, "[%s%s%s0x%"PRIx64
"]",
812 ((const char*)segover
? (const char*)segover
: ""), /* placate type mistmatch warning */
813 ((const char*)segover
? ":" : ""), /* by using (const char*) instead of uint8_t* */
814 (ins
.oprs
[i
].addr_size
==
815 32 ? "dword " : ins
.oprs
[i
].addr_size
==
816 16 ? "word " : ""), ins
.oprs
[i
].offset
);
818 } else if (!(REGMEM
& ~(*p
)->opd
[i
])) {
820 if ((*p
)->opd
[i
] & BITS8
)
822 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
823 if ((*p
)->opd
[i
] & BITS16
)
825 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
826 if ((*p
)->opd
[i
] & BITS32
)
828 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
829 if ((*p
)->opd
[i
] & BITS64
)
831 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
832 if ((*p
)->opd
[i
] & BITS80
)
834 snprintf(output
+ slen
, outbufsize
- slen
, "tword ");
835 if ((*p
)->opd
[i
] & FAR
)
836 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "far ");
837 if ((*p
)->opd
[i
] & NEAR
)
839 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
840 output
[slen
++] = '[';
841 if (ins
.oprs
[i
].addr_size
)
842 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
843 (ins
.oprs
[i
].addr_size
== 64 ? "qword " :
844 ins
.oprs
[i
].addr_size
== 32 ? "dword " :
845 ins
.oprs
[i
].addr_size
== 16 ? "word " :
847 if (ins
.oprs
[i
].eaflags
& EAF_REL
)
848 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "rel ");
851 snprintf(output
+ slen
, outbufsize
- slen
, "%s:",
855 if (ins
.oprs
[i
].basereg
!= -1) {
856 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
857 reg_names
[(ins
.oprs
[i
].basereg
-
861 if (ins
.oprs
[i
].indexreg
!= -1) {
863 output
[slen
++] = '+';
864 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
865 reg_names
[(ins
.oprs
[i
].indexreg
-
867 if (ins
.oprs
[i
].scale
> 1)
869 snprintf(output
+ slen
, outbufsize
- slen
, "*%d",
873 if (ins
.oprs
[i
].segment
& SEG_DISP8
) {
875 int8_t offset
= ins
.oprs
[i
].offset
;
881 snprintf(output
+ slen
, outbufsize
- slen
, "%s0x%"PRIx8
"",
882 minus
? "-" : "+", offset
);
883 } else if (ins
.oprs
[i
].segment
& SEG_DISP16
) {
885 int16_t offset
= ins
.oprs
[i
].offset
;
891 snprintf(output
+ slen
, outbufsize
- slen
, "%s0x%"PRIx16
"",
892 minus
? "-" : started
? "+" : "", offset
);
893 } else if (ins
.oprs
[i
].segment
& SEG_DISP32
) {
895 int32_t offset
= ins
.oprs
[i
].offset
;
900 prefix
= started
? "+" : "";
903 snprintf(output
+ slen
, outbufsize
- slen
,
904 "%s0x%"PRIx32
"", prefix
, offset
);
906 output
[slen
++] = ']';
909 snprintf(output
+ slen
, outbufsize
- slen
, "<operand%d>",
914 if (segover
) { /* unused segment override */
916 int count
= slen
+ 1;
918 p
[count
+ 3] = p
[count
];
919 strncpy(output
, segover
, 2);
925 int32_t eatbyte(uint8_t *data
, char *output
, int outbufsize
)
927 snprintf(output
, outbufsize
, "db 0x%02X", *data
);