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Add automation to avx test.
[nasm/avx512.git] / disasm.c
blob81e6d07cd0f63c4cf02bb0203485d97db4968ed7
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(REG_CS & ~regflags))
118 return (regval == 1) ? R_CS : 0;
119 if (!(REG_DESS & ~regflags))
120 return (regval == 0 || regval == 2
121 || regval == 3 ? nasm_rd_sreg[regval] : 0);
122 if (!(REG_FSGS & ~regflags))
123 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
124 if (!(REG_SEG67 & ~regflags))
125 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
126
127 /* All the entries below look up regval in an 16-entry array */
128 if (regval < 0 || regval > 15)
129 return 0;
130
131 if (!(REG8 & ~regflags)) {
132 if (rex & REX_P)
133 return nasm_rd_reg8_rex[regval];
134 else
135 return nasm_rd_reg8[regval];
136 }
137 if (!(REG16 & ~regflags))
138 return nasm_rd_reg16[regval];
139 if (!(REG32 & ~regflags))
140 return nasm_rd_reg32[regval];
141 if (!(REG64 & ~regflags))
142 return nasm_rd_reg64[regval];
143 if (!(REG_SREG & ~regflags))
144 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
145 if (!(REG_CREG & ~regflags))
146 return nasm_rd_creg[regval];
147 if (!(REG_DREG & ~regflags))
148 return nasm_rd_dreg[regval];
149 if (!(REG_TREG & ~regflags)) {
150 if (rex & REX_P)
151 return 0; /* TR registers are ill-defined with rex */
152 return nasm_rd_treg[regval];
153 }
154 if (!(FPUREG & ~regflags))
155 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
156 if (!(MMXREG & ~regflags))
157 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
158 if (!(XMMREG & ~regflags))
159 return nasm_rd_xmmreg[regval];
160 if (!(YMMREG & ~regflags))
161 return nasm_rd_ymmreg[regval];
162
163 return 0;
164 }
165
166 /*
167 * Process a DREX suffix
168 */
169 static uint8_t *do_drex(uint8_t *data, insn *ins)
170 {
171 uint8_t drex = *data++;
172 operand *dst = &ins->oprs[ins->drexdst];
173
174 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
175 return NULL; /* OC0 mismatch */
176 ins->rex = (ins->rex & ~7) | (drex & 7);
177
178 dst->segment = SEG_RMREG;
179 dst->basereg = drex >> 4;
180 return data;
181 }
182
183
184 /*
185 * Process an effective address (ModRM) specification.
186 */
187 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
188 int segsize, operand * op, insn *ins)
189 {
190 int mod, rm, scale, index, base;
191 int rex;
192 uint8_t sib = 0;
193
194 mod = (modrm >> 6) & 03;
195 rm = modrm & 07;
196
197 if (mod != 3 && rm == 4 && asize != 16)
198 sib = *data++;
199
200 if (ins->rex & REX_D) {
201 data = do_drex(data, ins);
202 if (!data)
203 return NULL;
204 }
205 rex = ins->rex;
206
207 if (mod == 3) { /* pure register version */
208 op->basereg = rm+(rex & REX_B ? 8 : 0);
209 op->segment |= SEG_RMREG;
210 return data;
211 }
212
213 op->disp_size = 0;
214 op->eaflags = 0;
215
216 if (asize == 16) {
217 /*
218 * <mod> specifies the displacement size (none, byte or
219 * word), and <rm> specifies the register combination.
220 * Exception: mod=0,rm=6 does not specify [BP] as one might
221 * expect, but instead specifies [disp16].
222 */
223 op->indexreg = op->basereg = -1;
224 op->scale = 1; /* always, in 16 bits */
225 switch (rm) {
226 case 0:
227 op->basereg = R_BX;
228 op->indexreg = R_SI;
229 break;
230 case 1:
231 op->basereg = R_BX;
232 op->indexreg = R_DI;
233 break;
234 case 2:
235 op->basereg = R_BP;
236 op->indexreg = R_SI;
237 break;
238 case 3:
239 op->basereg = R_BP;
240 op->indexreg = R_DI;
241 break;
242 case 4:
243 op->basereg = R_SI;
244 break;
245 case 5:
246 op->basereg = R_DI;
247 break;
248 case 6:
249 op->basereg = R_BP;
250 break;
251 case 7:
252 op->basereg = R_BX;
253 break;
254 }
255 if (rm == 6 && mod == 0) { /* special case */
256 op->basereg = -1;
257 if (segsize != 16)
258 op->disp_size = 16;
259 mod = 2; /* fake disp16 */
260 }
261 switch (mod) {
262 case 0:
263 op->segment |= SEG_NODISP;
264 break;
265 case 1:
266 op->segment |= SEG_DISP8;
267 op->offset = (int8_t)*data++;
268 break;
269 case 2:
270 op->segment |= SEG_DISP16;
271 op->offset = *data++;
272 op->offset |= ((unsigned)*data++) << 8;
273 break;
274 }
275 return data;
276 } else {
277 /*
278 * Once again, <mod> specifies displacement size (this time
279 * none, byte or *dword*), while <rm> specifies the base
280 * register. Again, [EBP] is missing, replaced by a pure
281 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
282 * and RIP-relative addressing in 64-bit mode.
283 *
284 * However, rm=4
285 * indicates not a single base register, but instead the
286 * presence of a SIB byte...
287 */
288 int a64 = asize == 64;
289
290 op->indexreg = -1;
291
292 if (a64)
293 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
294 else
295 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
296
297 if (rm == 5 && mod == 0) {
298 if (segsize == 64) {
299 op->eaflags |= EAF_REL;
300 op->segment |= SEG_RELATIVE;
301 mod = 2; /* fake disp32 */
302 }
303
304 if (asize != 64)
305 op->disp_size = asize;
306
307 op->basereg = -1;
308 mod = 2; /* fake disp32 */
309 }
310
311 if (rm == 4) { /* process SIB */
312 scale = (sib >> 6) & 03;
313 index = (sib >> 3) & 07;
314 base = sib & 07;
315
316 op->scale = 1 << scale;
317
318 if (index == 4)
319 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
320 else if (a64)
321 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
322 else
323 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
324
325 if (base == 5 && mod == 0) {
326 op->basereg = -1;
327 mod = 2; /* Fake disp32 */
328 } else if (a64)
329 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
330 else
331 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
332
333 if (segsize == 16)
334 op->disp_size = 32;
335 }
336
337 switch (mod) {
338 case 0:
339 op->segment |= SEG_NODISP;
340 break;
341 case 1:
342 op->segment |= SEG_DISP8;
343 op->offset = gets8(data);
344 data++;
345 break;
346 case 2:
347 op->segment |= SEG_DISP32;
348 op->offset = gets32(data);
349 data += 4;
350 break;
351 }
352 return data;
353 }
354 }
355
356 /*
357 * Determine whether the instruction template in t corresponds to the data
358 * stream in data. Return the number of bytes matched if so.
359 */
360 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
361
362 static int matches(const struct itemplate *t, uint8_t *data,
363 const struct prefix_info *prefix, int segsize, insn *ins)
364 {
365 uint8_t *r = (uint8_t *)(t->code);
366 uint8_t *origdata = data;
367 bool a_used = false, o_used = false;
368 enum prefixes drep = 0;
369 uint8_t lock = prefix->lock;
370 int osize = prefix->osize;
371 int asize = prefix->asize;
372 int i, c;
373 struct operand *opx;
374 int s_field_for = -1; /* No 144/154 series code encountered */
375 bool vex_ok = false;
376
377 for (i = 0; i < MAX_OPERANDS; i++) {
378 ins->oprs[i].segment = ins->oprs[i].disp_size =
379 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
380 }
381 ins->condition = -1;
382 ins->rex = prefix->rex;
383 memset(ins->prefixes, 0, sizeof ins->prefixes);
384
385 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
386 return false;
387
388 if (prefix->rep == 0xF2)
389 drep = P_REPNE;
390 else if (prefix->rep == 0xF3)
391 drep = P_REP;
392
393 while ((c = *r++) != 0) {
394 opx = &ins->oprs[c & 3];
395
396 switch (c) {
397 case 01:
398 case 02:
399 case 03:
400 while (c--)
401 if (*r++ != *data++)
402 return false;
403 break;
404
405 case 04:
406 switch (*data++) {
407 case 0x07:
408 ins->oprs[0].basereg = 0;
409 break;
410 case 0x17:
411 ins->oprs[0].basereg = 2;
412 break;
413 case 0x1F:
414 ins->oprs[0].basereg = 3;
415 break;
416 default:
417 return false;
418 }
419 break;
420
421 case 05:
422 switch (*data++) {
423 case 0xA1:
424 ins->oprs[0].basereg = 4;
425 break;
426 case 0xA9:
427 ins->oprs[0].basereg = 5;
428 break;
429 default:
430 return false;
431 }
432 break;
433
434 case 06:
435 switch (*data++) {
436 case 0x06:
437 ins->oprs[0].basereg = 0;
438 break;
439 case 0x0E:
440 ins->oprs[0].basereg = 1;
441 break;
442 case 0x16:
443 ins->oprs[0].basereg = 2;
444 break;
445 case 0x1E:
446 ins->oprs[0].basereg = 3;
447 break;
448 default:
449 return false;
450 }
451 break;
452
453 case 07:
454 switch (*data++) {
455 case 0xA0:
456 ins->oprs[0].basereg = 4;
457 break;
458 case 0xA8:
459 ins->oprs[0].basereg = 5;
460 break;
461 default:
462 return false;
463 }
464 break;
465
466 case4(010):
467 {
468 int t = *r++, d = *data++;
469 if (d < t || d > t + 7)
470 return false;
471 else {
472 opx->basereg = (d-t)+
473 (ins->rex & REX_B ? 8 : 0);
474 opx->segment |= SEG_RMREG;
475 }
476 break;
477 }
478
479 case4(014):
480 opx->offset = (int8_t)*data++;
481 opx->segment |= SEG_SIGNED;
482 break;
483
484 case4(020):
485 opx->offset = *data++;
486 break;
487
488 case4(024):
489 opx->offset = *data++;
490 break;
491
492 case4(030):
493 opx->offset = getu16(data);
494 data += 2;
495 break;
496
497 case4(034):
498 if (osize == 32) {
499 opx->offset = getu32(data);
500 data += 4;
501 } else {
502 opx->offset = getu16(data);
503 data += 2;
504 }
505 if (segsize != asize)
506 opx->disp_size = asize;
507 break;
508
509 case4(040):
510 opx->offset = getu32(data);
511 data += 4;
512 break;
513
514 case4(044):
515 switch (asize) {
516 case 16:
517 opx->offset = getu16(data);
518 data += 2;
519 if (segsize != 16)
520 opx->disp_size = 16;
521 break;
522 case 32:
523 opx->offset = getu32(data);
524 data += 4;
525 if (segsize == 16)
526 opx->disp_size = 32;
527 break;
528 case 64:
529 opx->offset = getu64(data);
530 opx->disp_size = 64;
531 data += 8;
532 break;
533 }
534 break;
535
536 case4(050):
537 opx->offset = gets8(data++);
538 opx->segment |= SEG_RELATIVE;
539 break;
540
541 case4(054):
542 opx->offset = getu64(data);
543 data += 8;
544 break;
545
546 case4(060):
547 opx->offset = gets16(data);
548 data += 2;
549 opx->segment |= SEG_RELATIVE;
550 opx->segment &= ~SEG_32BIT;
551 break;
552
553 case4(064):
554 opx->segment |= SEG_RELATIVE;
555 if (osize == 16) {
556 opx->offset = gets16(data);
557 data += 2;
558 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
559 } else if (osize == 32) {
560 opx->offset = gets32(data);
561 data += 4;
562 opx->segment &= ~SEG_64BIT;
563 opx->segment |= SEG_32BIT;
564 }
565 if (segsize != osize) {
566 opx->type =
567 (opx->type & ~SIZE_MASK)
568 | ((osize == 16) ? BITS16 : BITS32);
569 }
570 break;
571
572 case4(070):
573 opx->offset = gets32(data);
574 data += 4;
575 opx->segment |= SEG_32BIT | SEG_RELATIVE;
576 break;
577
578 case4(0100):
579 case4(0110):
580 case4(0120):
581 case4(0130):
582 {
583 int modrm = *data++;
584 opx->segment |= SEG_RMREG;
585 data = do_ea(data, modrm, asize, segsize,
586 &ins->oprs[(c >> 3) & 3], ins);
587 if (!data)
588 return false;
589 opx->basereg = ((modrm >> 3)&7)+
590 (ins->rex & REX_R ? 8 : 0);
591 break;
592 }
593
594 case4(0140):
595 if (s_field_for == (c & 3)) {
596 opx->offset = gets8(data);
597 data++;
598 } else {
599 opx->offset = getu16(data);
600 data += 2;
601 }
602 break;
603
604 case4(0144):
605 case4(0154):
606 s_field_for = (*data & 0x02) ? c & 3 : -1;
607 if ((*data++ & ~0x02) != *r++)
608 return false;
609 break;
610
611 case4(0150):
612 if (s_field_for == (c & 3)) {
613 opx->offset = gets8(data);
614 data++;
615 } else {
616 opx->offset = getu32(data);
617 data += 4;
618 }
619 break;
620
621 case4(0160):
622 ins->rex |= REX_D;
623 ins->drexdst = c & 3;
624 break;
625
626 case4(0164):
627 ins->rex |= REX_D|REX_OC;
628 ins->drexdst = c & 3;
629 break;
630
631 case 0171:
632 data = do_drex(data, ins);
633 if (!data)
634 return false;
635 break;
636
637 case 0172:
638 {
639 uint8_t ximm = *data++;
640 c = *r++;
641 ins->oprs[c >> 3].basereg = ximm >> 4;
642 ins->oprs[c >> 3].segment |= SEG_RMREG;
643 ins->oprs[c & 7].offset = ximm & 15;
644 }
645 break;
646
647 case 0173:
648 {
649 uint8_t ximm = *data++;
650 c = *r++;
651
652 if ((c ^ ximm) & 15)
653 return false;
654
655 ins->oprs[c >> 4].basereg = ximm >> 4;
656 ins->oprs[c >> 4].segment |= SEG_RMREG;
657 }
658 break;
659
660 case 0174:
661 {
662 uint8_t ximm = *data++;
663 c = *r++;
664
665 ins->oprs[c].basereg = ximm >> 4;
666 ins->oprs[c].segment |= SEG_RMREG;
667 }
668 break;
669
670 case4(0200):
671 case4(0204):
672 case4(0210):
673 case4(0214):
674 case4(0220):
675 case4(0224):
676 case4(0230):
677 case4(0234):
678 {
679 int modrm = *data++;
680 if (((modrm >> 3) & 07) != (c & 07))
681 return false; /* spare field doesn't match up */
682 data = do_ea(data, modrm, asize, segsize,
683 &ins->oprs[(c >> 3) & 07], ins);
684 if (!data)
685 return false;
686 break;
687 }
688
689 case4(0260):
690 {
691 int vexm = *r++;
692 int vexwlp = *r++;
693 ins->rex |= REX_V;
694 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
695 return false;
696
697 if ((vexm & 0x1f) != prefix->vex_m)
698 return false;
699
700 switch (vexwlp & 030) {
701 case 000:
702 if (prefix->rex & REX_W)
703 return false;
704 break;
705 case 010:
706 if (!(prefix->rex & REX_W))
707 return false;
708 break;
709 default:
710 break; /* XXX: Need to do anything special here? */
711 }
712
713 if ((vexwlp & 007) != prefix->vex_lp)
714 return false;
715
716 opx->segment |= SEG_RMREG;
717 opx->basereg = prefix->vex_v;
718 vex_ok = true;
719 break;
720 }
721
722 case 0270:
723 {
724 int vexm = *r++;
725 int vexwlp = *r++;
726 ins->rex |= REX_V;
727 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
728 return false;
729
730 if ((vexm & 0x1f) != prefix->vex_m)
731 return false;
732
733 switch (vexwlp & 030) {
734 case 000:
735 if (ins->rex & REX_W)
736 return false;
737 break;
738 case 010:
739 if (!(ins->rex & REX_W))
740 return false;
741 break;
742 default:
743 break; /* Need to do anything special here? */
744 }
745
746 if ((vexwlp & 007) != prefix->vex_lp)
747 return false;
748
749 if (prefix->vex_v != 0)
750 return false;
751
752 vex_ok = true;
753 break;
754 }
755
756 case 0310:
757 if (asize != 16)
758 return false;
759 else
760 a_used = true;
761 break;
762
763 case 0311:
764 if (asize == 16)
765 return false;
766 else
767 a_used = true;
768 break;
769
770 case 0312:
771 if (asize != segsize)
772 return false;
773 else
774 a_used = true;
775 break;
776
777 case 0313:
778 if (asize != 64)
779 return false;
780 else
781 a_used = true;
782 break;
783
784 case 0314:
785 if (prefix->rex & REX_B)
786 return false;
787 break;
788
789 case 0315:
790 if (prefix->rex & REX_X)
791 return false;
792 break;
793
794 case 0316:
795 if (prefix->rex & REX_R)
796 return false;
797 break;
798
799 case 0317:
800 if (prefix->rex & REX_W)
801 return false;
802 break;
803
804 case 0320:
805 if (osize != 16)
806 return false;
807 else
808 o_used = true;
809 break;
810
811 case 0321:
812 if (osize != 32)
813 return false;
814 else
815 o_used = true;
816 break;
817
818 case 0322:
819 if (osize != (segsize == 16) ? 16 : 32)
820 return false;
821 else
822 o_used = true;
823 break;
824
825 case 0323:
826 ins->rex |= REX_W; /* 64-bit only instruction */
827 osize = 64;
828 o_used = true;
829 break;
830
831 case 0324:
832 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
833 return false;
834 o_used = true;
835 break;
836
837 case 0330:
838 {
839 int t = *r++, d = *data++;
840 if (d < t || d > t + 15)
841 return false;
842 else
843 ins->condition = d - t;
844 break;
845 }
846
847 case 0331:
848 if (prefix->rep)
849 return false;
850 break;
851
852 case 0332:
853 if (prefix->rep != 0xF2)
854 return false;
855 drep = 0;
856 break;
857
858 case 0333:
859 if (prefix->rep != 0xF3)
860 return false;
861 drep = 0;
862 break;
863
864 case 0334:
865 if (lock) {
866 ins->rex |= REX_R;
867 lock = 0;
868 }
869 break;
870
871 case 0335:
872 if (drep == P_REP)
873 drep = P_REPE;
874 break;
875
876 case 0340:
877 return false;
878
879 case 0360:
880 if (prefix->osp || prefix->rep)
881 return false;
882 break;
883
884 case 0361:
885 if (!prefix->osp || prefix->rep)
886 return false;
887 break;
888
889 case 0362:
890 if (prefix->osp || prefix->rep != 0xf2)
891 return false;
892 break;
893
894 case 0363:
895 if (prefix->osp || prefix->rep != 0xf3)
896 return false;
897 break;
898
899 case 0364:
900 if (prefix->osp)
901 return false;
902 break;
903
904 case 0365:
905 if (prefix->asp)
906 return false;
907 break;
908
909 case 0366:
910 if (!prefix->osp)
911 return false;
912 o_used = true;
913 break;
914
915 case 0367:
916 if (!prefix->asp)
917 return false;
918 a_used = true;
919 break;
920
921 default:
922 return false; /* Unknown code */
923 }
924 }
925
926 if (!vex_ok && (ins->rex & REX_V))
927 return false;
928
929 /* REX cannot be combined with DREX or VEX */
930 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
931 return false;
932
933 /*
934 * Check for unused rep or a/o prefixes.
935 */
936 for (i = 0; i < t->operands; i++) {
937 if (ins->oprs[i].segment != SEG_RMREG)
938 a_used = true;
939 }
940
941 if (lock) {
942 if (ins->prefixes[PPS_LREP])
943 return false;
944 ins->prefixes[PPS_LREP] = P_LOCK;
945 }
946 if (drep) {
947 if (ins->prefixes[PPS_LREP])
948 return false;
949 ins->prefixes[PPS_LREP] = drep;
950 }
951 if (!o_used) {
952 if (osize != ((segsize == 16) ? 16 : 32)) {
953 enum prefixes pfx = 0;
954
955 switch (osize) {
956 case 16:
957 pfx = P_O16;
958 break;
959 case 32:
960 pfx = P_O32;
961 break;
962 case 64:
963 pfx = P_O64;
964 break;
965 }
966
967 if (ins->prefixes[PPS_OSIZE])
968 return false;
969 ins->prefixes[PPS_OSIZE] = pfx;
970 }
971 }
972 if (!a_used && asize != segsize) {
973 if (ins->prefixes[PPS_ASIZE])
974 return false;
975 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
976 }
977
978 /* Fix: check for redundant REX prefixes */
979
980 return data - origdata;
981 }
982
983 /* Condition names for disassembly, sorted by x86 code */
984 static const char * const condition_name[16] = {
985 "o", "no", "c", "nc", "z", "nz", "na", "a",
986 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
987 };
988
989 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
990 int32_t offset, int autosync, uint32_t prefer)
991 {
992 const struct itemplate * const *p, * const *best_p;
993 const struct disasm_index *ix;
994 uint8_t *dp;
995 int length, best_length = 0;
996 char *segover;
997 int i, slen, colon, n;
998 uint8_t *origdata;
999 int works;
1000 insn tmp_ins, ins;
1001 uint32_t goodness, best;
1002 int best_pref;
1003 struct prefix_info prefix;
1004 bool end_prefix;
1005
1006 memset(&ins, 0, sizeof ins);
1007
1008 /*
1009 * Scan for prefixes.
1010 */
1011 memset(&prefix, 0, sizeof prefix);
1012 prefix.asize = segsize;
1013 prefix.osize = (segsize == 64) ? 32 : segsize;
1014 segover = NULL;
1015 origdata = data;
1016
1017 end_prefix = false;
1018 while (!end_prefix) {
1019 switch (*data) {
1020 case 0xF2:
1021 case 0xF3:
1022 prefix.rep = *data++;
1023 break;
1024 case 0xF0:
1025 prefix.lock = *data++;
1026 break;
1027 case 0x2E:
1028 segover = "cs", prefix.seg = *data++;
1029 break;
1030 case 0x36:
1031 segover = "ss", prefix.seg = *data++;
1032 break;
1033 case 0x3E:
1034 segover = "ds", prefix.seg = *data++;
1035 break;
1036 case 0x26:
1037 segover = "es", prefix.seg = *data++;
1038 break;
1039 case 0x64:
1040 segover = "fs", prefix.seg = *data++;
1041 break;
1042 case 0x65:
1043 segover = "gs", prefix.seg = *data++;
1044 break;
1045 case 0x66:
1046 prefix.osize = (segsize == 16) ? 32 : 16;
1047 prefix.osp = *data++;
1048 break;
1049 case 0x67:
1050 prefix.asize = (segsize == 32) ? 16 : 32;
1051 prefix.asp = *data++;
1052 break;
1053 case 0xC4:
1054 case 0xC5:
1055 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1056 prefix.vex[0] = *data++;
1057 prefix.vex[1] = *data++;
1058 if (prefix.vex[0] == 0xc4)
1059 prefix.vex[2] = *data++;
1060 }
1061 prefix.rex = REX_V;
1062 if (prefix.vex[0] == 0xc4) {
1063 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1064 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1065 prefix.vex_m = prefix.vex[1] & 0x1f;
1066 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1067 prefix.vex_lp = prefix.vex[2] & 7;
1068 } else {
1069 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1070 prefix.vex_m = 1;
1071 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1072 prefix.vex_lp = prefix.vex[1] & 7;
1073 }
1074 end_prefix = true;
1075 break;
1076 case REX_P + 0x0:
1077 case REX_P + 0x1:
1078 case REX_P + 0x2:
1079 case REX_P + 0x3:
1080 case REX_P + 0x4:
1081 case REX_P + 0x5:
1082 case REX_P + 0x6:
1083 case REX_P + 0x7:
1084 case REX_P + 0x8:
1085 case REX_P + 0x9:
1086 case REX_P + 0xA:
1087 case REX_P + 0xB:
1088 case REX_P + 0xC:
1089 case REX_P + 0xD:
1090 case REX_P + 0xE:
1091 case REX_P + 0xF:
1092 if (segsize == 64) {
1093 prefix.rex = *data++;
1094 if (prefix.rex & REX_W)
1095 prefix.osize = 64;
1096 }
1097 end_prefix = true;
1098 break;
1099 default:
1100 end_prefix = true;
1101 break;
1102 }
1103 }
1104
1105 best = -1; /* Worst possible */
1106 best_p = NULL;
1107 best_pref = INT_MAX;
1108
1109 dp = data;
1110 ix = itable + *dp++;
1111 while (ix->n == -1) {
1112 ix = (const struct disasm_index *)ix->p + *dp++;
1113 }
1114
1115 p = (const struct itemplate * const *)ix->p;
1116 for (n = ix->n; n; n--, p++) {
1117 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1118 works = true;
1119 /*
1120 * Final check to make sure the types of r/m match up.
1121 * XXX: Need to make sure this is actually correct.
1122 */
1123 for (i = 0; i < (*p)->operands; i++) {
1124 if (!((*p)->opd[i] & SAME_AS) &&
1125 (
1126 /* If it's a mem-only EA but we have a
1127 register, die. */
1128 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1129 !(MEMORY & ~(*p)->opd[i])) ||
1130 /* If it's a reg-only EA but we have a memory
1131 ref, die. */
1132 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1133 !(REG_EA & ~(*p)->opd[i]) &&
1134 !((*p)->opd[i] & REG_SMASK)) ||
1135 /* Register type mismatch (eg FS vs REG_DESS):
1136 die. */
1137 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1138 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1139 !whichreg((*p)->opd[i],
1140 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1141 )) {
1142 works = false;
1143 break;
1144 }
1145 }
1146
1147 /*
1148 * Note: we always prefer instructions which incorporate
1149 * prefixes in the instructions themselves. This is to allow
1150 * e.g. PAUSE to be preferred to REP NOP, and deal with
1151 * MMX/SSE instructions where prefixes are used to select
1152 * between MMX and SSE register sets or outright opcode
1153 * selection.
1154 */
1155 if (works) {
1156 int i, nprefix;
1157 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1158 nprefix = 0;
1159 for (i = 0; i < MAXPREFIX; i++)
1160 if (tmp_ins.prefixes[i])
1161 nprefix++;
1162 if (nprefix < best_pref ||
1163 (nprefix == best_pref && goodness < best)) {
1164 /* This is the best one found so far */
1165 best = goodness;
1166 best_p = p;
1167 best_pref = nprefix;
1168 best_length = length;
1169 ins = tmp_ins;
1170 }
1171 }
1172 }
1173 }
1174
1175 if (!best_p)
1176 return 0; /* no instruction was matched */
1177
1178 /* Pick the best match */
1179 p = best_p;
1180 length = best_length;
1181
1182 slen = 0;
1183
1184 /* TODO: snprintf returns the value that the string would have if
1185 * the buffer were long enough, and not the actual length of
1186 * the returned string, so each instance of using the return
1187 * value of snprintf should actually be checked to assure that
1188 * the return value is "sane." Maybe a macro wrapper could
1189 * be used for that purpose.
1190 */
1191 for (i = 0; i < MAXPREFIX; i++)
1192 switch (ins.prefixes[i]) {
1193 case P_LOCK:
1194 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1195 break;
1196 case P_REP:
1197 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1198 break;
1199 case P_REPE:
1200 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1201 break;
1202 case P_REPNE:
1203 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1204 break;
1205 case P_A16:
1206 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1207 break;
1208 case P_A32:
1209 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1210 break;
1211 case P_A64:
1212 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1213 break;
1214 case P_O16:
1215 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1216 break;
1217 case P_O32:
1218 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1219 break;
1220 case P_O64:
1221 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1222 break;
1223 default:
1224 break;
1225 }
1226
1227 i = (*p)->opcode;
1228 if (i >= FIRST_COND_OPCODE) {
1229 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1230 nasm_cond_insn_names[i-FIRST_COND_OPCODE],
1231 condition_name[ins.condition]);
1232 } else {
1233 slen += snprintf(output + slen, outbufsize - slen, "%s",
1234 nasm_insn_names[i]);
1235 }
1236 colon = false;
1237 length += data - origdata; /* fix up for prefixes */
1238 for (i = 0; i < (*p)->operands; i++) {
1239 opflags_t t = (*p)->opd[i];
1240 const operand *o = &ins.oprs[i];
1241 int64_t offs;
1242
1243 if (t & SAME_AS) {
1244 o = &ins.oprs[t & ~SAME_AS];
1245 t = (*p)->opd[t & ~SAME_AS];
1246 }
1247
1248 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1249
1250 offs = o->offset;
1251 if (o->segment & SEG_RELATIVE) {
1252 offs += offset + length;
1253 /*
1254 * sort out wraparound
1255 */
1256 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1257 offs &= 0xffff;
1258 else if (segsize != 64)
1259 offs &= 0xffffffff;
1260
1261 /*
1262 * add sync marker, if autosync is on
1263 */
1264 if (autosync)
1265 add_sync(offs, 0L);
1266 }
1267
1268 if (t & COLON)
1269 colon = true;
1270 else
1271 colon = false;
1272
1273 if ((t & (REGISTER | FPUREG)) ||
1274 (o->segment & SEG_RMREG)) {
1275 enum reg_enum reg;
1276 reg = whichreg(t, o->basereg, ins.rex);
1277 if (t & TO)
1278 slen += snprintf(output + slen, outbufsize - slen, "to ");
1279 slen += snprintf(output + slen, outbufsize - slen, "%s",
1280 nasm_reg_names[reg-EXPR_REG_START]);
1281 } else if (!(UNITY & ~t)) {
1282 output[slen++] = '1';
1283 } else if (t & IMMEDIATE) {
1284 if (t & BITS8) {
1285 slen +=
1286 snprintf(output + slen, outbufsize - slen, "byte ");
1287 if (o->segment & SEG_SIGNED) {
1288 if (offs < 0) {
1289 offs *= -1;
1290 output[slen++] = '-';
1291 } else
1292 output[slen++] = '+';
1293 }
1294 } else if (t & BITS16) {
1295 slen +=
1296 snprintf(output + slen, outbufsize - slen, "word ");
1297 } else if (t & BITS32) {
1298 slen +=
1299 snprintf(output + slen, outbufsize - slen, "dword ");
1300 } else if (t & BITS64) {
1301 slen +=
1302 snprintf(output + slen, outbufsize - slen, "qword ");
1303 } else if (t & NEAR) {
1304 slen +=
1305 snprintf(output + slen, outbufsize - slen, "near ");
1306 } else if (t & SHORT) {
1307 slen +=
1308 snprintf(output + slen, outbufsize - slen, "short ");
1309 }
1310 slen +=
1311 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1312 offs);
1313 } else if (!(MEM_OFFS & ~t)) {
1314 slen +=
1315 snprintf(output + slen, outbufsize - slen,
1316 "[%s%s%s0x%"PRIx64"]",
1317 (segover ? segover : ""),
1318 (segover ? ":" : ""),
1319 (o->disp_size == 64 ? "qword " :
1320 o->disp_size == 32 ? "dword " :
1321 o->disp_size == 16 ? "word " : ""), offs);
1322 segover = NULL;
1323 } else if (!(REGMEM & ~t)) {
1324 int started = false;
1325 if (t & BITS8)
1326 slen +=
1327 snprintf(output + slen, outbufsize - slen, "byte ");
1328 if (t & BITS16)
1329 slen +=
1330 snprintf(output + slen, outbufsize - slen, "word ");
1331 if (t & BITS32)
1332 slen +=
1333 snprintf(output + slen, outbufsize - slen, "dword ");
1334 if (t & BITS64)
1335 slen +=
1336 snprintf(output + slen, outbufsize - slen, "qword ");
1337 if (t & BITS80)
1338 slen +=
1339 snprintf(output + slen, outbufsize - slen, "tword ");
1340 if (t & BITS128)
1341 slen +=
1342 snprintf(output + slen, outbufsize - slen, "oword ");
1343 if (t & BITS256)
1344 slen +=
1345 snprintf(output + slen, outbufsize - slen, "yword ");
1346 if (t & FAR)
1347 slen += snprintf(output + slen, outbufsize - slen, "far ");
1348 if (t & NEAR)
1349 slen +=
1350 snprintf(output + slen, outbufsize - slen, "near ");
1351 output[slen++] = '[';
1352 if (o->disp_size)
1353 slen += snprintf(output + slen, outbufsize - slen, "%s",
1354 (o->disp_size == 64 ? "qword " :
1355 o->disp_size == 32 ? "dword " :
1356 o->disp_size == 16 ? "word " :
1357 ""));
1358 if (o->eaflags & EAF_REL)
1359 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1360 if (segover) {
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "%s:",
1363 segover);
1364 segover = NULL;
1365 }
1366 if (o->basereg != -1) {
1367 slen += snprintf(output + slen, outbufsize - slen, "%s",
1368 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1369 started = true;
1370 }
1371 if (o->indexreg != -1) {
1372 if (started)
1373 output[slen++] = '+';
1374 slen += snprintf(output + slen, outbufsize - slen, "%s",
1375 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1376 if (o->scale > 1)
1377 slen +=
1378 snprintf(output + slen, outbufsize - slen, "*%d",
1379 o->scale);
1380 started = true;
1381 }
1382
1383
1384 if (o->segment & SEG_DISP8) {
1385 const char *prefix;
1386 uint8_t offset = offs;
1387 if ((int8_t)offset < 0) {
1388 prefix = "-";
1389 offset = -offset;
1390 } else {
1391 prefix = "+";
1392 }
1393 slen +=
1394 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1395 prefix, offset);
1396 } else if (o->segment & SEG_DISP16) {
1397 const char *prefix;
1398 uint16_t offset = offs;
1399 if ((int16_t)offset < 0 && started) {
1400 offset = -offset;
1401 prefix = "-";
1402 } else {
1403 prefix = started ? "+" : "";
1404 }
1405 slen +=
1406 snprintf(output + slen, outbufsize - slen,
1407 "%s0x%"PRIx16"", prefix, offset);
1408 } else if (o->segment & SEG_DISP32) {
1409 if (prefix.asize == 64) {
1410 const char *prefix;
1411 uint64_t offset = (int64_t)(int32_t)offs;
1412 if ((int32_t)offs < 0 && started) {
1413 offset = -offset;
1414 prefix = "-";
1415 } else {
1416 prefix = started ? "+" : "";
1417 }
1418 slen +=
1419 snprintf(output + slen, outbufsize - slen,
1420 "%s0x%"PRIx64"", prefix, offset);
1421 } else {
1422 const char *prefix;
1423 uint32_t offset = offs;
1424 if ((int32_t) offset < 0 && started) {
1425 offset = -offset;
1426 prefix = "-";
1427 } else {
1428 prefix = started ? "+" : "";
1429 }
1430 slen +=
1431 snprintf(output + slen, outbufsize - slen,
1432 "%s0x%"PRIx32"", prefix, offset);
1433 }
1434 }
1435 output[slen++] = ']';
1436 } else {
1437 slen +=
1438 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1439 i);
1440 }
1441 }
1442 output[slen] = '\0';
1443 if (segover) { /* unused segment override */
1444 char *p = output;
1445 int count = slen + 1;
1446 while (count--)
1447 p[count + 3] = p[count];
1448 strncpy(output, segover, 2);
1449 output[2] = ' ';
1450 }
1451 return length;
1452 }
1453
1454 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1455 {
1456 snprintf(output, outbufsize, "db 0x%02X", *data);
1457 return 1;
1458 }
Adding AVX-512 features