1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
82 * [l0] ll = 0 (.128, .lz)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
172 #include "compiler.h"
176 #include <inttypes.h>
180 #include "assemble.h"
186 * Matching errors. These should be sorted so that more specific
187 * errors come later in the sequence.
198 * Matching success; the conditional ones first
200 MOK_JUMP
, /* Matching OK but needs jmp_match() */
201 MOK_GOOD
/* Matching unconditionally OK */
205 enum ea_type type
; /* what kind of EA is this? */
206 int sib_present
; /* is a SIB byte necessary? */
207 int bytes
; /* # of bytes of offset needed */
208 int size
; /* lazy - this is sib+bytes+1 */
209 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
210 int8_t disp8
; /* compressed displacement for EVEX */
213 #define GEN_SIB(scale, index, base) \
214 (((scale) << 6) | ((index) << 3) | ((base)))
216 #define GEN_MODRM(mod, reg, rm) \
217 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
219 static iflags_t cpu
; /* cpu level received from nasm.c */
220 static efunc errfunc
;
221 static struct ofmt
*outfmt
;
222 static ListGen
*list
;
224 static int64_t calcsize(int32_t, int64_t, int, insn
*,
225 const struct itemplate
*);
226 static void gencode(int32_t segment
, int64_t offset
, int bits
,
227 insn
* ins
, const struct itemplate
*temp
,
229 static enum match_result
find_match(const struct itemplate
**tempp
,
231 int32_t segment
, int64_t offset
, int bits
);
232 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
233 static opflags_t
regflag(const operand
*);
234 static int32_t regval(const operand
*);
235 static int rexflags(int, opflags_t
, int);
236 static int op_rexflags(const operand
*, int);
237 static int op_evexflags(const operand
*, int, uint8_t);
238 static void add_asp(insn
*, int);
240 static enum ea_type
process_ea(operand
*, ea
*, int, int, opflags_t
, insn
*);
242 static int has_prefix(insn
* ins
, enum prefix_pos pos
, int prefix
)
244 return ins
->prefixes
[pos
] == prefix
;
247 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
249 if (ins
->prefixes
[pos
])
250 errfunc(ERR_NONFATAL
, "invalid %s prefix",
251 prefix_name(ins
->prefixes
[pos
]));
254 static const char *size_name(int size
)
278 static void warn_overflow(int pass
, int size
)
280 errfunc(ERR_WARNING
| pass
| ERR_WARN_NOV
,
281 "%s data exceeds bounds", size_name(size
));
284 static void warn_overflow_const(int64_t data
, int size
)
286 if (overflow_general(data
, size
))
287 warn_overflow(ERR_PASS1
, size
);
290 static void warn_overflow_opd(const struct operand
*o
, int size
)
292 if (o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
293 if (overflow_general(o
->offset
, size
))
294 warn_overflow(ERR_PASS2
, size
);
299 * This routine wrappers the real output format's output routine,
300 * in order to pass a copy of the data off to the listing file
301 * generator at the same time.
303 static void out(int64_t offset
, int32_t segto
, const void *data
,
304 enum out_type type
, uint64_t size
,
305 int32_t segment
, int32_t wrt
)
307 static int32_t lineno
= 0; /* static!!! */
308 static char *lnfname
= NULL
;
311 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
313 * This is a non-relocated address, and we're going to
314 * convert it into RAWDATA format.
319 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
323 WRITEADDR(q
, *(int64_t *)data
, size
);
328 list
->output(offset
, data
, type
, size
);
331 * this call to src_get determines when we call the
332 * debug-format-specific "linenum" function
333 * it updates lineno and lnfname to the current values
334 * returning 0 if "same as last time", -2 if lnfname
335 * changed, and the amount by which lineno changed,
336 * if it did. thus, these variables must be static
339 if (src_get(&lineno
, &lnfname
))
340 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
342 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
345 static void out_imm8(int64_t offset
, int32_t segment
, struct operand
*opx
)
347 if (opx
->segment
!= NO_SEG
) {
348 uint64_t data
= opx
->offset
;
349 out(offset
, segment
, &data
, OUT_ADDRESS
, 1, opx
->segment
, opx
->wrt
);
351 uint8_t byte
= opx
->offset
;
352 out(offset
, segment
, &byte
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
356 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
357 insn
* ins
, const struct itemplate
*temp
)
360 const uint8_t *code
= temp
->code
;
363 if (((c
& ~1) != 0370) || (ins
->oprs
[0].type
& STRICT
))
367 if (optimizing
< 0 && c
== 0371)
370 isize
= calcsize(segment
, offset
, bits
, ins
, temp
);
372 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
373 /* Be optimistic in pass 1 */
376 if (ins
->oprs
[0].segment
!= segment
)
379 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
380 return (isize
>= -128 && isize
<= 127); /* is it byte size? */
383 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, iflags_t cp
,
384 insn
* instruction
, struct ofmt
*output
, efunc error
,
387 const struct itemplate
*temp
;
392 int64_t start
= offset
;
393 int64_t wsize
; /* size for DB etc. */
395 errfunc
= error
; /* to pass to other functions */
397 outfmt
= output
; /* likewise */
398 list
= listgen
; /* and again */
400 wsize
= idata_bytes(instruction
->opcode
);
406 int32_t t
= instruction
->times
;
409 "instruction->times < 0 (%ld) in assemble()", t
);
411 while (t
--) { /* repeat TIMES times */
412 list_for_each(e
, instruction
->eops
) {
413 if (e
->type
== EOT_DB_NUMBER
) {
415 errfunc(ERR_NONFATAL
,
416 "integer supplied to a DT, DO or DY"
419 out(offset
, segment
, &e
->offset
,
420 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
423 } else if (e
->type
== EOT_DB_STRING
||
424 e
->type
== EOT_DB_STRING_FREE
) {
427 out(offset
, segment
, e
->stringval
,
428 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
429 align
= e
->stringlen
% wsize
;
432 align
= wsize
- align
;
433 out(offset
, segment
, zero_buffer
,
434 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
436 offset
+= e
->stringlen
+ align
;
439 if (t
> 0 && t
== instruction
->times
- 1) {
441 * Dummy call to list->output to give the offset to the
444 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
445 list
->uplevel(LIST_TIMES
);
448 if (instruction
->times
> 1)
449 list
->downlevel(LIST_TIMES
);
450 return offset
- start
;
453 if (instruction
->opcode
== I_INCBIN
) {
454 const char *fname
= instruction
->eops
->stringval
;
457 fp
= fopen(fname
, "rb");
459 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
461 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
462 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
466 static char buf
[4096];
467 size_t t
= instruction
->times
;
472 if (instruction
->eops
->next
) {
473 base
= instruction
->eops
->next
->offset
;
475 if (instruction
->eops
->next
->next
&&
476 len
> (size_t)instruction
->eops
->next
->next
->offset
)
477 len
= (size_t)instruction
->eops
->next
->next
->offset
;
480 * Dummy call to list->output to give the offset to the
483 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
484 list
->uplevel(LIST_INCBIN
);
488 fseek(fp
, base
, SEEK_SET
);
492 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
495 * This shouldn't happen unless the file
496 * actually changes while we are reading
500 "`incbin': unexpected EOF while"
501 " reading file `%s'", fname
);
502 t
= 0; /* Try to exit cleanly */
505 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
510 list
->downlevel(LIST_INCBIN
);
511 if (instruction
->times
> 1) {
513 * Dummy call to list->output to give the offset to the
516 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
517 list
->uplevel(LIST_TIMES
);
518 list
->downlevel(LIST_TIMES
);
521 return instruction
->times
* len
;
523 return 0; /* if we're here, there's an error */
526 /* Check to see if we need an address-size prefix */
527 add_asp(instruction
, bits
);
529 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
533 int64_t insn_size
= calcsize(segment
, offset
, bits
, instruction
, temp
);
534 itimes
= instruction
->times
;
535 if (insn_size
< 0) /* shouldn't be, on pass two */
536 error(ERR_PANIC
, "errors made it through from pass one");
539 for (j
= 0; j
< MAXPREFIX
; j
++) {
541 switch (instruction
->prefixes
[j
]) {
562 error(ERR_WARNING
| ERR_PASS2
,
563 "cs segment base generated, but will be ignored in 64-bit mode");
569 error(ERR_WARNING
| ERR_PASS2
,
570 "ds segment base generated, but will be ignored in 64-bit mode");
576 error(ERR_WARNING
| ERR_PASS2
,
577 "es segment base generated, but will be ignored in 64-bit mode");
589 error(ERR_WARNING
| ERR_PASS2
,
590 "ss segment base generated, but will be ignored in 64-bit mode");
597 "segr6 and segr7 cannot be used as prefixes");
602 "16-bit addressing is not supported "
604 } else if (bits
!= 16)
614 "64-bit addressing is only supported "
641 error(ERR_PANIC
, "invalid instruction prefix");
644 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
649 insn_end
= offset
+ insn_size
;
650 gencode(segment
, offset
, bits
, instruction
,
653 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
655 * Dummy call to list->output to give the offset to the
658 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
659 list
->uplevel(LIST_TIMES
);
662 if (instruction
->times
> 1)
663 list
->downlevel(LIST_TIMES
);
664 return offset
- start
;
668 case MERR_OPSIZEMISSING
:
669 error(ERR_NONFATAL
, "operation size not specified");
671 case MERR_OPSIZEMISMATCH
:
672 error(ERR_NONFATAL
, "mismatch in operand sizes");
675 error(ERR_NONFATAL
, "no instruction for this cpu level");
678 error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
683 "invalid combination of opcode and operands");
690 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, iflags_t cp
,
691 insn
* instruction
, efunc error
)
693 const struct itemplate
*temp
;
696 errfunc
= error
; /* to pass to other functions */
699 if (instruction
->opcode
== I_none
)
702 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
703 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
704 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
705 instruction
->opcode
== I_DY
) {
707 int32_t isize
, osize
, wsize
;
710 wsize
= idata_bytes(instruction
->opcode
);
712 list_for_each(e
, instruction
->eops
) {
716 if (e
->type
== EOT_DB_NUMBER
) {
718 warn_overflow_const(e
->offset
, wsize
);
719 } else if (e
->type
== EOT_DB_STRING
||
720 e
->type
== EOT_DB_STRING_FREE
)
721 osize
= e
->stringlen
;
723 align
= (-osize
) % wsize
;
726 isize
+= osize
+ align
;
728 return isize
* instruction
->times
;
731 if (instruction
->opcode
== I_INCBIN
) {
732 const char *fname
= instruction
->eops
->stringval
;
737 fp
= fopen(fname
, "rb");
739 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
741 else if (fseek(fp
, 0L, SEEK_END
) < 0)
742 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
746 if (instruction
->eops
->next
) {
747 len
-= instruction
->eops
->next
->offset
;
748 if (instruction
->eops
->next
->next
&&
749 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
750 len
= (size_t)instruction
->eops
->next
->next
->offset
;
753 val
= instruction
->times
* len
;
760 /* Check to see if we need an address-size prefix */
761 add_asp(instruction
, bits
);
763 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
765 /* we've matched an instruction. */
769 isize
= calcsize(segment
, offset
, bits
, instruction
, temp
);
772 for (j
= 0; j
< MAXPREFIX
; j
++) {
773 switch (instruction
->prefixes
[j
]) {
800 return isize
* instruction
->times
;
802 return -1; /* didn't match any instruction */
806 static void bad_hle_warn(const insn
* ins
, uint8_t hleok
)
808 enum prefixes rep_pfx
= ins
->prefixes
[PPS_REP
];
809 enum whatwarn
{ w_none
, w_lock
, w_inval
} ww
;
810 static const enum whatwarn warn
[2][4] =
812 { w_inval
, w_inval
, w_none
, w_lock
}, /* XACQUIRE */
813 { w_inval
, w_none
, w_none
, w_lock
}, /* XRELEASE */
817 n
= (unsigned int)rep_pfx
- P_XACQUIRE
;
819 return; /* Not XACQUIRE/XRELEASE */
822 if (!is_class(MEMORY
, ins
->oprs
[0].type
))
823 ww
= w_inval
; /* HLE requires operand 0 to be memory */
830 if (ins
->prefixes
[PPS_LOCK
] != P_LOCK
) {
831 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
832 "%s with this instruction requires lock",
833 prefix_name(rep_pfx
));
838 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
839 "%s invalid with this instruction",
840 prefix_name(rep_pfx
));
845 /* Common construct */
846 #define case3(x) case (x): case (x)+1: case (x)+2
847 #define case4(x) case3(x): case (x)+3
849 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
850 insn
* ins
, const struct itemplate
*temp
)
852 const uint8_t *codes
= temp
->code
;
861 bool lockcheck
= true;
862 enum reg_enum mib_index
= R_none
; /* For a separate index MIB reg form */
864 ins
->rex
= 0; /* Ensure REX is reset */
865 eat
= EA_SCALAR
; /* Expect a scalar EA */
866 memset(ins
->evex_p
, 0, 3); /* Ensure EVEX is reset */
868 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
871 (void)segment
; /* Don't warn that this parameter is unused */
872 (void)offset
; /* Don't warn that this parameter is unused */
876 op1
= (c
& 3) + ((opex
& 1) << 2);
877 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
878 opx
= &ins
->oprs
[op1
];
879 opex
= 0; /* For the next iteration */
883 codes
+= c
, length
+= c
;
892 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
897 /* this is an index reg of MIB operand */
898 mib_index
= opx
->basereg
;
911 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
912 length
+= (opx
->type
& BITS16
) ? 2 : 4;
914 length
+= (bits
== 16) ? 2 : 4;
922 length
+= ins
->addr_size
>> 3;
930 length
+= 8; /* MOV reg64/imm */
938 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
939 length
+= (opx
->type
& BITS16
) ? 2 : 4;
941 length
+= (bits
== 16) ? 2 : 4;
964 ins
->vexreg
= regval(opx
);
965 ins
->evex_p
[2] |= op_evexflags(opx
, EVEX_P2VP
, 2); /* High-16 NDS */
966 ins
->vex_cm
= *codes
++;
967 ins
->vex_wlp
= *codes
++;
968 ins
->evex_tuple
= (*codes
++ - 0300);
974 ins
->vex_cm
= *codes
++;
975 ins
->vex_wlp
= *codes
++;
976 ins
->evex_tuple
= (*codes
++ - 0300);
985 ins
->vexreg
= regval(opx
);
986 ins
->vex_cm
= *codes
++;
987 ins
->vex_wlp
= *codes
++;
993 ins
->vex_cm
= *codes
++;
994 ins
->vex_wlp
= *codes
++;
1011 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
1015 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
1022 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
1023 has_prefix(ins
, PPS_ASIZE
, P_A32
))
1032 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1036 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1038 ins
->prefixes
[PPS_OSIZE
] = P_O16
;
1044 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1048 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1050 ins
->prefixes
[PPS_OSIZE
] = P_O32
;
1092 if (!ins
->prefixes
[PPS_REP
])
1093 ins
->prefixes
[PPS_REP
] = P_REP
;
1097 if (!ins
->prefixes
[PPS_REP
])
1098 ins
->prefixes
[PPS_REP
] = P_REPNE
;
1102 if (ins
->oprs
[0].segment
!= NO_SEG
)
1103 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1104 " quantity of BSS space");
1106 length
+= ins
->oprs
[0].offset
;
1110 if (!ins
->prefixes
[PPS_WAIT
])
1111 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1166 struct operand
*opy
= &ins
->oprs
[op2
];
1167 struct operand
*op_er_sae
;
1169 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1172 /* pick rfield from operand b (opx) */
1173 rflags
= regflag(opx
);
1174 rfield
= nasm_regvals
[opx
->basereg
];
1180 /* EVEX.b1 : evex_brerop contains the operand position */
1181 op_er_sae
= (ins
->evex_brerop
>= 0 ?
1182 &ins
->oprs
[ins
->evex_brerop
] : NULL
);
1184 if (op_er_sae
&& (op_er_sae
->decoflags
& (ER
| SAE
))) {
1186 ins
->evex_p
[2] |= EVEX_P2B
;
1187 if (op_er_sae
->decoflags
& ER
) {
1188 /* set EVEX.RC (rounding control) */
1189 ins
->evex_p
[2] |= ((ins
->evex_rm
- BRC_RN
) << 5)
1193 /* set EVEX.L'L (vector length) */
1194 ins
->evex_p
[2] |= ((ins
->vex_wlp
<< (5 - 2)) & EVEX_P2LL
);
1195 if (opy
->decoflags
& BRDCAST_MASK
) {
1197 ins
->evex_p
[2] |= EVEX_P2B
;
1202 * if a separate form of MIB (ICC style) is used,
1203 * the index reg info is merged into mem operand
1205 if (mib_index
!= R_none
) {
1206 opy
->indexreg
= mib_index
;
1208 opy
->hintbase
= mib_index
;
1209 opy
->hinttype
= EAH_NOTBASE
;
1213 * only for mib operands, make a single reg index [reg*1].
1214 * gas uses this form to explicitly denote index register.
1216 if ((temp
->flags
& IF_MIB
) &&
1217 (opy
->indexreg
== -1 && opy
->hintbase
== opy
->basereg
&&
1218 opy
->hinttype
== EAH_NOTBASE
)) {
1219 opy
->indexreg
= opy
->basereg
;
1224 if (process_ea(opy
, &ea_data
, bits
,
1225 rfield
, rflags
, ins
) != eat
) {
1226 errfunc(ERR_NONFATAL
, "invalid effective address");
1229 ins
->rex
|= ea_data
.rex
;
1230 length
+= ea_data
.size
;
1236 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1237 ": instruction code \\%o (0x%02X) given", c
, c
);
1242 ins
->rex
&= rex_mask
;
1244 if (ins
->rex
& REX_NH
) {
1245 if (ins
->rex
& REX_H
) {
1246 errfunc(ERR_NONFATAL
, "instruction cannot use high registers");
1249 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1252 if (ins
->rex
& (REX_V
| REX_EV
)) {
1253 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1255 if (ins
->rex
& REX_H
) {
1256 errfunc(ERR_NONFATAL
, "cannot use high register in AVX instruction");
1259 switch (ins
->vex_wlp
& 060) {
1273 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->vexreg
> 7)) {
1274 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1276 } else if (!(ins
->rex
& REX_EV
) &&
1277 ((ins
->vexreg
> 15) || (ins
->evex_p
[0] & 0xf0))) {
1278 errfunc(ERR_NONFATAL
, "invalid high-16 register in non-AVX-512");
1281 if (ins
->rex
& REX_EV
)
1283 else if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)))
1287 } else if (ins
->rex
& REX_REAL
) {
1288 if (ins
->rex
& REX_H
) {
1289 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1291 } else if (bits
== 64) {
1293 } else if ((ins
->rex
& REX_L
) &&
1294 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1297 assert_no_prefix(ins
, PPS_LOCK
);
1298 lockcheck
= false; /* Already errored, no need for warning */
1301 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1306 if (has_prefix(ins
, PPS_LOCK
, P_LOCK
) && lockcheck
&&
1307 (!(temp
->flags
& IF_LOCK
) || !is_class(MEMORY
, ins
->oprs
[0].type
))) {
1308 errfunc(ERR_WARNING
| ERR_WARN_LOCK
| ERR_PASS2
,
1309 "instruction is not lockable");
1312 bad_hle_warn(ins
, hleok
);
1317 static inline unsigned int emit_rex(insn
*ins
, int32_t segment
, int64_t offset
, int bits
)
1320 if ((ins
->rex
& REX_REAL
) && !(ins
->rex
& (REX_V
| REX_EV
))) {
1321 ins
->rex
= (ins
->rex
& REX_REAL
) | REX_P
;
1322 out(offset
, segment
, &ins
->rex
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1331 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1332 insn
* ins
, const struct itemplate
*temp
,
1340 struct operand
*opx
;
1341 const uint8_t *codes
= temp
->code
;
1343 enum ea_type eat
= EA_SCALAR
;
1347 op1
= (c
& 3) + ((opex
& 1) << 2);
1348 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1349 opx
= &ins
->oprs
[op1
];
1350 opex
= 0; /* For the next iteration */
1357 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1358 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1370 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1371 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1372 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1380 if (opx
->offset
< -256 || opx
->offset
> 255) {
1381 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1382 "byte value exceeds bounds");
1384 out_imm8(offset
, segment
, opx
);
1389 if (opx
->offset
< 0 || opx
->offset
> 255)
1390 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1391 "unsigned byte value exceeds bounds");
1392 out_imm8(offset
, segment
, opx
);
1397 warn_overflow_opd(opx
, 2);
1399 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1400 opx
->segment
, opx
->wrt
);
1405 if (opx
->type
& (BITS16
| BITS32
))
1406 size
= (opx
->type
& BITS16
) ? 2 : 4;
1408 size
= (bits
== 16) ? 2 : 4;
1409 warn_overflow_opd(opx
, size
);
1411 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1412 opx
->segment
, opx
->wrt
);
1417 warn_overflow_opd(opx
, 4);
1419 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1420 opx
->segment
, opx
->wrt
);
1426 size
= ins
->addr_size
>> 3;
1427 warn_overflow_opd(opx
, size
);
1428 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1429 opx
->segment
, opx
->wrt
);
1434 if (opx
->segment
!= segment
) {
1436 out(offset
, segment
, &data
,
1437 OUT_REL1ADR
, insn_end
- offset
,
1438 opx
->segment
, opx
->wrt
);
1440 data
= opx
->offset
- insn_end
;
1441 if (data
> 127 || data
< -128)
1442 errfunc(ERR_NONFATAL
, "short jump is out of range");
1443 out(offset
, segment
, &data
,
1444 OUT_ADDRESS
, 1, NO_SEG
, NO_SEG
);
1450 data
= (int64_t)opx
->offset
;
1451 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1452 opx
->segment
, opx
->wrt
);
1457 if (opx
->segment
!= segment
) {
1459 out(offset
, segment
, &data
,
1460 OUT_REL2ADR
, insn_end
- offset
,
1461 opx
->segment
, opx
->wrt
);
1463 data
= opx
->offset
- insn_end
;
1464 out(offset
, segment
, &data
,
1465 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1471 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1472 size
= (opx
->type
& BITS16
) ? 2 : 4;
1474 size
= (bits
== 16) ? 2 : 4;
1475 if (opx
->segment
!= segment
) {
1477 out(offset
, segment
, &data
,
1478 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1479 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1481 data
= opx
->offset
- insn_end
;
1482 out(offset
, segment
, &data
,
1483 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1489 if (opx
->segment
!= segment
) {
1491 out(offset
, segment
, &data
,
1492 OUT_REL4ADR
, insn_end
- offset
,
1493 opx
->segment
, opx
->wrt
);
1495 data
= opx
->offset
- insn_end
;
1496 out(offset
, segment
, &data
,
1497 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1503 if (opx
->segment
== NO_SEG
)
1504 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1507 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1508 outfmt
->segbase(1 + opx
->segment
),
1515 opx
= &ins
->oprs
[c
>> 3];
1516 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1517 opx
= &ins
->oprs
[c
& 7];
1518 if (opx
->segment
!= NO_SEG
|| opx
->wrt
!= NO_SEG
) {
1519 errfunc(ERR_NONFATAL
,
1520 "non-absolute expression not permitted as argument %d",
1523 if (opx
->offset
& ~15) {
1524 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1525 "four-bit argument exceeds bounds");
1527 bytes
[0] |= opx
->offset
& 15;
1529 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1535 opx
= &ins
->oprs
[c
>> 4];
1536 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1538 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1543 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1544 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1550 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1551 (int32_t)data
!= (int64_t)data
) {
1552 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1553 "signed dword immediate exceeds bounds");
1555 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1556 opx
->segment
, opx
->wrt
);
1563 ins
->evex_p
[2] |= op_evexflags(&ins
->oprs
[0],
1564 EVEX_P2Z
| EVEX_P2AAA
, 2);
1565 ins
->evex_p
[2] ^= EVEX_P2VP
; /* 1's complement */
1567 /* EVEX.X can be set by either REX or EVEX for different reasons */
1568 bytes
[1] = ((((ins
->rex
& 7) << 5) |
1569 (ins
->evex_p
[0] & (EVEX_P0X
| EVEX_P0RP
))) ^ 0xf0) |
1571 bytes
[2] = ((ins
->rex
& REX_W
) << (7 - 3)) |
1572 ((~ins
->vexreg
& 15) << 3) |
1573 (1 << 2) | (ins
->vex_wlp
& 3);
1574 bytes
[3] = ins
->evex_p
[2];
1575 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 4, NO_SEG
, NO_SEG
);
1582 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
))) {
1583 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1584 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1585 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1586 ((~ins
->vexreg
& 15)<< 3) | (ins
->vex_wlp
& 07);
1587 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1591 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1592 ((~ins
->vexreg
& 15) << 3) | (ins
->vex_wlp
& 07);
1593 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1608 if (ins
->rex
& REX_W
)
1610 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1612 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1617 um
= (uint64_t)2 << (s
-1);
1620 if (uv
> 127 && uv
< (uint64_t)-128 &&
1621 (uv
< um
-128 || uv
> um
-1)) {
1622 /* If this wasn't explicitly byte-sized, warn as though we
1623 * had fallen through to the imm16/32/64 case.
1625 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1626 "%s value exceeds bounds",
1627 (opx
->type
& BITS8
) ? "signed byte" :
1632 if (opx
->segment
!= NO_SEG
) {
1634 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1635 opx
->segment
, opx
->wrt
);
1638 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1649 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1651 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1658 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1660 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1695 *bytes
= *codes
++ ^ get_cond_opcode(ins
->condition
);
1696 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1705 *bytes
= c
- 0332 + 0xF2;
1706 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1711 if (ins
->rex
& REX_R
) {
1713 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1716 ins
->rex
&= ~(REX_L
|REX_R
);
1727 if (ins
->oprs
[0].segment
!= NO_SEG
)
1728 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1730 int64_t size
= ins
->oprs
[0].offset
;
1732 out(offset
, segment
, NULL
,
1733 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1746 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1756 *bytes
= c
- 0366 + 0x66;
1757 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1765 *bytes
= bits
== 16 ? 3 : 5;
1766 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1800 struct operand
*opy
= &ins
->oprs
[op2
];
1803 /* pick rfield from operand b (opx) */
1804 rflags
= regflag(opx
);
1805 rfield
= nasm_regvals
[opx
->basereg
];
1807 /* rfield is constant */
1812 if (process_ea(opy
, &ea_data
, bits
,
1813 rfield
, rflags
, ins
) != eat
)
1814 errfunc(ERR_NONFATAL
, "invalid effective address");
1817 *p
++ = ea_data
.modrm
;
1818 if (ea_data
.sib_present
)
1822 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1825 * Make sure the address gets the right offset in case
1826 * the line breaks in the .lst file (BR 1197827)
1831 switch (ea_data
.bytes
) {
1838 /* use compressed displacement, if available */
1839 data
= ea_data
.disp8
? ea_data
.disp8
: opy
->offset
;
1842 if (opy
->segment
== segment
) {
1844 if (overflow_signed(data
, ea_data
.bytes
))
1845 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1846 out(offset
, segment
, &data
, OUT_ADDRESS
,
1847 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1849 /* overflow check in output/linker? */
1850 out(offset
, segment
, &data
, OUT_REL4ADR
,
1851 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1854 if (overflow_general(data
, ins
->addr_size
>> 3) ||
1855 signed_bits(data
, ins
->addr_size
) !=
1856 signed_bits(data
, ea_data
.bytes
* 8))
1857 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1859 out(offset
, segment
, &data
, OUT_ADDRESS
,
1860 ea_data
.bytes
, opy
->segment
, opy
->wrt
);
1866 "Invalid amount of bytes (%d) for offset?!",
1875 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1876 ": instruction code \\%o (0x%02X) given", c
, c
);
1882 static opflags_t
regflag(const operand
* o
)
1884 if (!is_register(o
->basereg
))
1885 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1886 return nasm_reg_flags
[o
->basereg
];
1889 static int32_t regval(const operand
* o
)
1891 if (!is_register(o
->basereg
))
1892 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1893 return nasm_regvals
[o
->basereg
];
1896 static int op_rexflags(const operand
* o
, int mask
)
1901 if (!is_register(o
->basereg
))
1902 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1904 flags
= nasm_reg_flags
[o
->basereg
];
1905 val
= nasm_regvals
[o
->basereg
];
1907 return rexflags(val
, flags
, mask
);
1910 static int rexflags(int val
, opflags_t flags
, int mask
)
1914 if (val
>= 0 && val
& 8)
1915 rex
|= REX_B
|REX_X
|REX_R
;
1918 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1920 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1926 static int evexflags(int val
, decoflags_t deco
,
1927 int mask
, uint8_t byte
)
1933 if (val
>= 0 && val
& 16)
1934 evex
|= (EVEX_P0RP
| EVEX_P0X
);
1937 if (val
>= 0 && val
& 16)
1941 if (deco
& OPMASK_MASK
)
1942 evex
|= deco
& EVEX_P2AAA
;
1948 static int op_evexflags(const operand
* o
, int mask
, uint8_t byte
)
1952 if (!is_register(o
->basereg
))
1953 errfunc(ERR_PANIC
, "invalid operand passed to op_evexflags()");
1955 val
= nasm_regvals
[o
->basereg
];
1957 return evexflags(val
, o
->decoflags
, mask
, byte
);
1960 static enum match_result
find_match(const struct itemplate
**tempp
,
1962 int32_t segment
, int64_t offset
, int bits
)
1964 const struct itemplate
*temp
;
1965 enum match_result m
, merr
;
1966 opflags_t xsizeflags
[MAX_OPERANDS
];
1967 bool opsizemissing
= false;
1968 int8_t broadcast
= instruction
->evex_brerop
;
1971 /* broadcasting uses a different data element size */
1972 for (i
= 0; i
< instruction
->operands
; i
++)
1974 xsizeflags
[i
] = instruction
->oprs
[i
].decoflags
& BRSIZE_MASK
;
1976 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
1978 merr
= MERR_INVALOP
;
1980 for (temp
= nasm_instructions
[instruction
->opcode
];
1981 temp
->opcode
!= I_none
; temp
++) {
1982 m
= matches(temp
, instruction
, bits
);
1983 if (m
== MOK_JUMP
) {
1984 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
1988 } else if (m
== MERR_OPSIZEMISSING
&&
1989 (temp
->flags
& IF_SMASK
) != IF_SX
) {
1991 * Missing operand size and a candidate for fuzzy matching...
1993 for (i
= 0; i
< temp
->operands
; i
++)
1995 xsizeflags
[i
] |= temp
->deco
[i
] & BRSIZE_MASK
;
1997 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
1998 opsizemissing
= true;
2002 if (merr
== MOK_GOOD
)
2006 /* No match, but see if we can get a fuzzy operand size match... */
2010 for (i
= 0; i
< instruction
->operands
; i
++) {
2012 * We ignore extrinsic operand sizes on registers, so we should
2013 * never try to fuzzy-match on them. This also resolves the case
2014 * when we have e.g. "xmmrm128" in two different positions.
2016 if (is_class(REGISTER
, instruction
->oprs
[i
].type
))
2019 /* This tests if xsizeflags[i] has more than one bit set */
2020 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
2021 goto done
; /* No luck */
2023 if (i
== broadcast
) {
2024 instruction
->oprs
[i
].decoflags
|= xsizeflags
[i
];
2025 instruction
->oprs
[i
].type
|= (xsizeflags
[i
] == BR_BITS32
?
2028 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2032 /* Try matching again... */
2033 for (temp
= nasm_instructions
[instruction
->opcode
];
2034 temp
->opcode
!= I_none
; temp
++) {
2035 m
= matches(temp
, instruction
, bits
);
2036 if (m
== MOK_JUMP
) {
2037 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2044 if (merr
== MOK_GOOD
)
2053 static enum match_result
matches(const struct itemplate
*itemp
,
2054 insn
*instruction
, int bits
)
2056 opflags_t size
[MAX_OPERANDS
], asize
;
2057 bool opsizemissing
= false;
2063 if (itemp
->opcode
!= instruction
->opcode
)
2064 return MERR_INVALOP
;
2067 * Count the operands
2069 if (itemp
->operands
!= instruction
->operands
)
2070 return MERR_INVALOP
;
2075 if (!(optimizing
> 0) && (itemp
->flags
& IF_OPT
))
2076 return MERR_INVALOP
;
2079 * Check that no spurious colons or TOs are present
2081 for (i
= 0; i
< itemp
->operands
; i
++)
2082 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2083 return MERR_INVALOP
;
2086 * Process size flags
2088 switch (itemp
->flags
& IF_SMASK
) {
2131 if (itemp
->flags
& IF_ARMASK
) {
2132 /* S- flags only apply to a specific operand */
2133 i
= ((itemp
->flags
& IF_ARMASK
) >> IF_ARSHFT
) - 1;
2134 memset(size
, 0, sizeof size
);
2137 /* S- flags apply to all operands */
2138 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2143 * Check that the operand flags all match up,
2144 * it's a bit tricky so lets be verbose:
2146 * 1) Find out the size of operand. If instruction
2147 * doesn't have one specified -- we're trying to
2148 * guess it either from template (IF_S* flag) or
2151 * 2) If template operand do not match the instruction OR
2152 * template has an operand size specified AND this size differ
2153 * from which instruction has (perhaps we got it from code bits)
2155 * a) Check that only size of instruction and operand is differ
2156 * other characteristics do match
2157 * b) Perhaps it's a register specified in instruction so
2158 * for such a case we just mark that operand as "size
2159 * missing" and this will turn on fuzzy operand size
2160 * logic facility (handled by a caller)
2162 for (i
= 0; i
< itemp
->operands
; i
++) {
2163 opflags_t type
= instruction
->oprs
[i
].type
;
2164 decoflags_t deco
= instruction
->oprs
[i
].decoflags
;
2165 bool is_broadcast
= deco
& BRDCAST_MASK
;
2166 opflags_t template_opsize
, insn_opsize
;
2168 if (!(type
& SIZE_MASK
))
2171 insn_opsize
= type
& SIZE_MASK
;
2172 if (!is_broadcast
) {
2173 template_opsize
= itemp
->opd
[i
] & SIZE_MASK
;
2175 decoflags_t deco_brsize
= itemp
->deco
[i
] & BRSIZE_MASK
;
2177 * when broadcasting, the element size depends on
2178 * the instruction type. decorator flag should match.
2182 template_opsize
= (deco_brsize
== BR_BITS32
? BITS32
: BITS64
);
2184 template_opsize
= 0;
2188 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) ||
2189 (itemp
->deco
[i
] & deco
) != deco
) {
2190 return MERR_INVALOP
;
2191 } else if (template_opsize
) {
2192 if (template_opsize
!= insn_opsize
) {
2194 return MERR_INVALOP
;
2195 } else if (!is_class(REGISTER
, type
)) {
2197 * Note: we don't honor extrinsic operand sizes for registers,
2198 * so "missing operand size" for a register should be
2199 * considered a wildcard match rather than an error.
2201 opsizemissing
= true;
2204 } else if (is_register(instruction
->oprs
[i
].basereg
) &&
2205 nasm_regvals
[instruction
->oprs
[i
].basereg
] >= 16 &&
2206 !(itemp
->flags
& IF_AVX512
)) {
2207 return MERR_ENCMISMATCH
;
2208 } else if (instruction
->prefixes
[PPS_EVEX
] &&
2209 !(itemp
->flags
& IF_AVX512
)) {
2210 return MERR_ENCMISMATCH
;
2215 return MERR_OPSIZEMISSING
;
2218 * Check operand sizes
2220 if (itemp
->flags
& (IF_SM
| IF_SM2
)) {
2221 oprs
= (itemp
->flags
& IF_SM2
? 2 : itemp
->operands
);
2222 for (i
= 0; i
< oprs
; i
++) {
2223 asize
= itemp
->opd
[i
] & SIZE_MASK
;
2225 for (i
= 0; i
< oprs
; i
++)
2231 oprs
= itemp
->operands
;
2234 for (i
= 0; i
< itemp
->operands
; i
++) {
2235 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2236 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2237 return MERR_OPSIZEMISMATCH
;
2241 * Check template is okay at the set cpu level
2243 if (((itemp
->flags
& IF_PLEVEL
) > cpu
))
2247 * Verify the appropriate long mode flag.
2249 if ((itemp
->flags
& (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2250 return MERR_BADMODE
;
2253 * If we have a HLE prefix, look for the NOHLE flag
2255 if ((itemp
->flags
& IF_NOHLE
) &&
2256 (has_prefix(instruction
, PPS_REP
, P_XACQUIRE
) ||
2257 has_prefix(instruction
, PPS_REP
, P_XRELEASE
)))
2261 * Check if special handling needed for Jumps
2263 if ((itemp
->code
[0] & ~1) == 0370)
2267 * Check if BND prefix is allowed
2269 if ((IF_BND
& ~itemp
->flags
) &&
2270 has_prefix(instruction
, PPS_REP
, P_BND
))
2277 * Check if offset is a multiple of N with corresponding tuple type
2278 * if Disp8*N is available, compressed displacement is stored in compdisp
2280 static bool is_disp8n(operand
*input
, insn
*ins
, int8_t *compdisp
)
2282 const uint8_t fv_n
[2][2][VLMAX
] = {{{16, 32, 64}, {4, 4, 4}},
2283 {{16, 32, 64}, {8, 8, 8}}};
2284 const uint8_t hv_n
[2][VLMAX
] = {{8, 16, 32}, {4, 4, 4}};
2285 const uint8_t dup_n
[VLMAX
] = {8, 32, 64};
2287 bool evex_b
= input
->decoflags
& BRDCAST_MASK
;
2288 enum ttypes tuple
= ins
->evex_tuple
;
2289 /* vex_wlp composed as [wwllpp] */
2290 enum vectlens vectlen
= (ins
->vex_wlp
& 0x0c) >> 2;
2291 /* wig(=2) is treated as w0(=0) */
2292 bool evex_w
= (ins
->vex_wlp
& 0x10) >> 4;
2293 int32_t off
= input
->offset
;
2299 n
= fv_n
[evex_w
][evex_b
][vectlen
];
2302 n
= hv_n
[evex_b
][vectlen
];
2306 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2307 n
= 1 << (vectlen
+ 4);
2309 case T1S8
: /* N = 1 */
2310 case T1S16
: /* N = 2 */
2311 n
= tuple
- T1S8
+ 1;
2314 /* N = 4 for 32bit, 8 for 64bit */
2319 /* N = 4 for 32bit, 8 for 64bit */
2320 n
= (tuple
== T1F32
? 4 : 8);
2325 if (vectlen
+ 7 <= (evex_w
+ 5) + (tuple
- T2
+ 1))
2328 n
= 1 << (tuple
- T2
+ evex_w
+ 3);
2333 n
= 1 << (OVM
- tuple
+ vectlen
+ 1);
2346 if (n
&& !(off
& (n
- 1))) {
2348 /* if it fits in Disp8 */
2349 if (disp8
>= -128 && disp8
<= 127) {
2360 * Check if ModR/M.mod should/can be 01.
2361 * - EAF_BYTEOFFS is set
2362 * - offset can fit in a byte when EVEX is not used
2363 * - offset can be compressed when EVEX is used
2365 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2366 (o >= -128 && o <= 127 && \
2367 seg == NO_SEG && !forw_ref && \
2368 !(input->eaflags & EAF_WORDOFFS) && \
2369 !(ins->rex & REX_EV)) || \
2370 (ins->rex & REX_EV && \
2371 is_disp8n(input, ins, &output->disp8)))
2373 static enum ea_type
process_ea(operand
*input
, ea
*output
, int bits
,
2374 int rfield
, opflags_t rflags
, insn
*ins
)
2376 bool forw_ref
= !!(input
->opflags
& OPFLAG_UNKNOWN
);
2377 int addrbits
= ins
->addr_size
;
2379 output
->type
= EA_SCALAR
;
2380 output
->rip
= false;
2383 /* REX flags for the rfield operand */
2384 output
->rex
|= rexflags(rfield
, rflags
, REX_R
| REX_P
| REX_W
| REX_H
);
2385 /* EVEX.R' flag for the REG operand */
2386 ins
->evex_p
[0] |= evexflags(rfield
, 0, EVEX_P0RP
, 0);
2388 if (is_class(REGISTER
, input
->type
)) {
2390 * It's a direct register.
2392 if (!is_register(input
->basereg
))
2395 if (!is_reg_class(REG_EA
, input
->basereg
))
2398 /* broadcasting is not available with a direct register operand. */
2399 if (input
->decoflags
& BRDCAST_MASK
) {
2400 nasm_error(ERR_NONFATAL
, "Broadcasting not allowed from a register");
2404 output
->rex
|= op_rexflags(input
, REX_B
| REX_P
| REX_W
| REX_H
);
2405 ins
->evex_p
[0] |= op_evexflags(input
, EVEX_P0X
, 0);
2406 output
->sib_present
= false; /* no SIB necessary */
2407 output
->bytes
= 0; /* no offset necessary either */
2408 output
->modrm
= GEN_MODRM(3, rfield
, nasm_regvals
[input
->basereg
]);
2411 * It's a memory reference.
2414 /* Embedded rounding or SAE is not available with a mem ref operand. */
2415 if (input
->decoflags
& (ER
| SAE
)) {
2416 nasm_error(ERR_NONFATAL
,
2417 "Embedded rounding is available only with reg-reg op.");
2421 if (input
->basereg
== -1 &&
2422 (input
->indexreg
== -1 || input
->scale
== 0)) {
2424 * It's a pure offset.
2426 if (bits
== 64 && ((input
->type
& IP_REL
) == IP_REL
) &&
2427 input
->segment
== NO_SEG
) {
2428 nasm_error(ERR_WARNING
| ERR_PASS1
, "absolute address can not be RIP-relative");
2429 input
->type
&= ~IP_REL
;
2430 input
->type
|= MEMORY
;
2433 if (input
->eaflags
& EAF_BYTEOFFS
||
2434 (input
->eaflags
& EAF_WORDOFFS
&&
2435 input
->disp_size
!= (addrbits
!= 16 ? 32 : 16))) {
2436 nasm_error(ERR_WARNING
| ERR_PASS1
, "displacement size ignored on absolute address");
2439 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2440 output
->sib_present
= true;
2441 output
->sib
= GEN_SIB(0, 4, 5);
2443 output
->modrm
= GEN_MODRM(0, rfield
, 4);
2444 output
->rip
= false;
2446 output
->sib_present
= false;
2447 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2448 output
->modrm
= GEN_MODRM(0, rfield
, (addrbits
!= 16 ? 5 : 6));
2449 output
->rip
= bits
== 64;
2453 * It's an indirection.
2455 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2456 int32_t seg
= input
->segment
;
2457 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2458 int t
, it
, bt
; /* register numbers */
2459 opflags_t x
, ix
, bx
; /* register flags */
2462 i
= -1; /* make this easy, at least */
2464 if (is_register(i
)) {
2465 it
= nasm_regvals
[i
];
2466 ix
= nasm_reg_flags
[i
];
2472 if (is_register(b
)) {
2473 bt
= nasm_regvals
[b
];
2474 bx
= nasm_reg_flags
[b
];
2480 /* if either one are a vector register... */
2481 if ((ix
|bx
) & (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
) {
2482 opflags_t sok
= BITS32
| BITS64
;
2483 int32_t o
= input
->offset
;
2484 int mod
, scale
, index
, base
;
2487 * For a vector SIB, one has to be a vector and the other,
2488 * if present, a GPR. The vector must be the index operand.
2490 if (it
== -1 || (bx
& (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
)) {
2496 t
= bt
, bt
= it
, it
= t
;
2497 x
= bx
, bx
= ix
, ix
= x
;
2503 if (!(REG64
& ~bx
) || !(REG32
& ~bx
))
2510 * While we're here, ensure the user didn't specify
2513 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2516 if (addrbits
== 16 ||
2517 (addrbits
== 32 && !(sok
& BITS32
)) ||
2518 (addrbits
== 64 && !(sok
& BITS64
)))
2521 output
->type
= ((ix
& ZMMREG
& ~REG_EA
) ? EA_ZMMVSIB
2522 : ((ix
& YMMREG
& ~REG_EA
)
2523 ? EA_YMMVSIB
: EA_XMMVSIB
));
2525 output
->rex
|= rexflags(it
, ix
, REX_X
);
2526 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2527 ins
->evex_p
[2] |= evexflags(it
, 0, EVEX_P2VP
, 2);
2529 index
= it
& 7; /* it is known to be != -1 */
2544 default: /* then what the smeg is it? */
2545 goto err
; /* panic */
2553 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2554 seg
== NO_SEG
&& !forw_ref
&&
2555 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2557 else if (IS_MOD_01())
2563 output
->sib_present
= true;
2564 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2565 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2566 output
->sib
= GEN_SIB(scale
, index
, base
);
2567 } else if ((ix
|bx
) & (BITS32
|BITS64
)) {
2569 * it must be a 32/64-bit memory reference. Firstly we have
2570 * to check that all registers involved are type E/Rxx.
2572 opflags_t sok
= BITS32
| BITS64
;
2573 int32_t o
= input
->offset
;
2576 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2584 goto err
; /* Invalid register */
2585 if (~sok
& bx
& SIZE_MASK
)
2586 goto err
; /* Invalid size */
2591 * While we're here, ensure the user didn't specify
2594 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2597 if (addrbits
== 16 ||
2598 (addrbits
== 32 && !(sok
& BITS32
)) ||
2599 (addrbits
== 64 && !(sok
& BITS64
)))
2602 /* now reorganize base/index */
2603 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2604 ((hb
== b
&& ht
== EAH_NOTBASE
) ||
2605 (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2606 /* swap if hints say so */
2607 t
= bt
, bt
= it
, it
= t
;
2608 x
= bx
, bx
= ix
, ix
= x
;
2610 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
2611 bt
= -1, bx
= 0, s
++;
2612 if (bt
== -1 && s
== 1 && !(hb
== i
&& ht
== EAH_NOTBASE
)) {
2613 /* make single reg base, unless hint */
2614 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2616 if (((s
== 2 && it
!= REG_NUM_ESP
&& !(input
->eaflags
& EAF_TIMESTWO
)) ||
2617 s
== 3 || s
== 5 || s
== 9) && bt
== -1)
2618 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2619 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
&&
2620 (input
->eaflags
& EAF_TIMESTWO
))
2621 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2622 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2623 if (s
== 1 && it
== REG_NUM_ESP
) {
2624 /* swap ESP into base if scale is 1 */
2625 t
= it
, it
= bt
, bt
= t
;
2626 x
= ix
, ix
= bx
, bx
= x
;
2628 if (it
== REG_NUM_ESP
||
2629 (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2630 goto err
; /* wrong, for various reasons */
2632 output
->rex
|= rexflags(it
, ix
, REX_X
);
2633 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2635 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2644 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2645 seg
== NO_SEG
&& !forw_ref
&&
2646 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2648 else if (IS_MOD_01())
2654 output
->sib_present
= false;
2655 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2656 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2659 int mod
, scale
, index
, base
;
2679 default: /* then what the smeg is it? */
2680 goto err
; /* panic */
2688 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2689 seg
== NO_SEG
&& !forw_ref
&&
2690 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2692 else if (IS_MOD_01())
2698 output
->sib_present
= true;
2699 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2700 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2701 output
->sib
= GEN_SIB(scale
, index
, base
);
2703 } else { /* it's 16-bit */
2705 int16_t o
= input
->offset
;
2707 /* check for 64-bit long mode */
2711 /* check all registers are BX, BP, SI or DI */
2712 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
&& b
!= R_DI
) ||
2713 (i
!= -1 && i
!= R_BP
&& i
!= R_BX
&& i
!= R_SI
&& i
!= R_DI
))
2716 /* ensure the user didn't specify DWORD/QWORD */
2717 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2720 if (s
!= 1 && i
!= -1)
2721 goto err
; /* no can do, in 16-bit EA */
2722 if (b
== -1 && i
!= -1) {
2727 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2732 /* have BX/BP as base, SI/DI index */
2734 goto err
; /* shouldn't ever happen, in theory */
2735 if (i
!= -1 && b
!= -1 &&
2736 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2737 goto err
; /* invalid combinations */
2738 if (b
== -1) /* pure offset: handled above */
2739 goto err
; /* so if it gets to here, panic! */
2743 switch (i
* 256 + b
) {
2744 case R_SI
* 256 + R_BX
:
2747 case R_DI
* 256 + R_BX
:
2750 case R_SI
* 256 + R_BP
:
2753 case R_DI
* 256 + R_BP
:
2771 if (rm
== -1) /* can't happen, in theory */
2772 goto err
; /* so panic if it does */
2774 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2775 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2777 else if (IS_MOD_01())
2782 output
->sib_present
= false; /* no SIB - it's 16-bit */
2783 output
->bytes
= mod
; /* bytes of offset needed */
2784 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2789 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2790 return output
->type
;
2793 return output
->type
= EA_INVALID
;
2796 static void add_asp(insn
*ins
, int addrbits
)
2801 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2803 switch (ins
->prefixes
[PPS_ASIZE
]) {
2814 valid
&= (addrbits
== 32) ? 16 : 32;
2820 for (j
= 0; j
< ins
->operands
; j
++) {
2821 if (is_class(MEMORY
, ins
->oprs
[j
].type
)) {
2824 /* Verify as Register */
2825 if (!is_register(ins
->oprs
[j
].indexreg
))
2828 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2830 /* Verify as Register */
2831 if (!is_register(ins
->oprs
[j
].basereg
))
2834 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2836 if (ins
->oprs
[j
].scale
== 0)
2840 int ds
= ins
->oprs
[j
].disp_size
;
2841 if ((addrbits
!= 64 && ds
> 8) ||
2842 (addrbits
== 64 && ds
== 16))
2862 if (valid
& addrbits
) {
2863 ins
->addr_size
= addrbits
;
2864 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2865 /* Add an address size prefix */
2866 ins
->prefixes
[PPS_ASIZE
] = (addrbits
== 32) ? P_A16
: P_A32
;;
2867 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2870 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2871 ins
->addr_size
= addrbits
; /* Error recovery */
2874 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2876 for (j
= 0; j
< ins
->operands
; j
++) {
2877 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2878 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
) != ins
->addr_size
) {
2880 * mem_offs sizes must match the address size; if not,
2881 * strip the MEM_OFFS bit and match only EA instructions
2883 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);