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doc: document the %use fp macro package
[nasm/avx512.git] / disasm.c
blobba282d34c837f4b168f7e601cb0840e73cbbde69
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2010 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
117
118 regflags |= REGISTER;
119
120 if (!(REG_AL & ~regflags))
121 return R_AL;
122 if (!(REG_AX & ~regflags))
123 return R_AX;
124 if (!(REG_EAX & ~regflags))
125 return R_EAX;
126 if (!(REG_RAX & ~regflags))
127 return R_RAX;
128 if (!(REG_DL & ~regflags))
129 return R_DL;
130 if (!(REG_DX & ~regflags))
131 return R_DX;
132 if (!(REG_EDX & ~regflags))
133 return R_EDX;
134 if (!(REG_RDX & ~regflags))
135 return R_RDX;
136 if (!(REG_CL & ~regflags))
137 return R_CL;
138 if (!(REG_CX & ~regflags))
139 return R_CX;
140 if (!(REG_ECX & ~regflags))
141 return R_ECX;
142 if (!(REG_RCX & ~regflags))
143 return R_RCX;
144 if (!(FPU0 & ~regflags))
145 return R_ST0;
146 if (!(XMM0 & ~regflags))
147 return R_XMM0;
148 if (!(YMM0 & ~regflags))
149 return R_YMM0;
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
159
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
162 return 0;
163
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
167 else
168 return nasm_rd_reg8[regval];
169 }
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
183 if (regval > 7)
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
186 }
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
195
196 return 0;
197 }
198
199 /*
200 * Process a DREX suffix
201 */
202 static uint8_t *do_drex(uint8_t *data, insn *ins)
203 {
204 uint8_t drex = *data++;
205 operand *dst = &ins->oprs[ins->drexdst];
206
207 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
208 return NULL; /* OC0 mismatch */
209 ins->rex = (ins->rex & ~7) | (drex & 7);
210
211 dst->segment = SEG_RMREG;
212 dst->basereg = drex >> 4;
213 return data;
214 }
215
216
217 /*
218 * Process an effective address (ModRM) specification.
219 */
220 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
221 int segsize, operand * op, insn *ins)
222 {
223 int mod, rm, scale, index, base;
224 int rex;
225 uint8_t sib = 0;
226
227 mod = (modrm >> 6) & 03;
228 rm = modrm & 07;
229
230 if (mod != 3 && rm == 4 && asize != 16)
231 sib = *data++;
232
233 if (ins->rex & REX_D) {
234 data = do_drex(data, ins);
235 if (!data)
236 return NULL;
237 }
238 rex = ins->rex;
239
240 if (mod == 3) { /* pure register version */
241 op->basereg = rm+(rex & REX_B ? 8 : 0);
242 op->segment |= SEG_RMREG;
243 return data;
244 }
245
246 op->disp_size = 0;
247 op->eaflags = 0;
248
249 if (asize == 16) {
250 /*
251 * <mod> specifies the displacement size (none, byte or
252 * word), and <rm> specifies the register combination.
253 * Exception: mod=0,rm=6 does not specify [BP] as one might
254 * expect, but instead specifies [disp16].
255 */
256 op->indexreg = op->basereg = -1;
257 op->scale = 1; /* always, in 16 bits */
258 switch (rm) {
259 case 0:
260 op->basereg = R_BX;
261 op->indexreg = R_SI;
262 break;
263 case 1:
264 op->basereg = R_BX;
265 op->indexreg = R_DI;
266 break;
267 case 2:
268 op->basereg = R_BP;
269 op->indexreg = R_SI;
270 break;
271 case 3:
272 op->basereg = R_BP;
273 op->indexreg = R_DI;
274 break;
275 case 4:
276 op->basereg = R_SI;
277 break;
278 case 5:
279 op->basereg = R_DI;
280 break;
281 case 6:
282 op->basereg = R_BP;
283 break;
284 case 7:
285 op->basereg = R_BX;
286 break;
287 }
288 if (rm == 6 && mod == 0) { /* special case */
289 op->basereg = -1;
290 if (segsize != 16)
291 op->disp_size = 16;
292 mod = 2; /* fake disp16 */
293 }
294 switch (mod) {
295 case 0:
296 op->segment |= SEG_NODISP;
297 break;
298 case 1:
299 op->segment |= SEG_DISP8;
300 op->offset = (int8_t)*data++;
301 break;
302 case 2:
303 op->segment |= SEG_DISP16;
304 op->offset = *data++;
305 op->offset |= ((unsigned)*data++) << 8;
306 break;
307 }
308 return data;
309 } else {
310 /*
311 * Once again, <mod> specifies displacement size (this time
312 * none, byte or *dword*), while <rm> specifies the base
313 * register. Again, [EBP] is missing, replaced by a pure
314 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
315 * and RIP-relative addressing in 64-bit mode.
316 *
317 * However, rm=4
318 * indicates not a single base register, but instead the
319 * presence of a SIB byte...
320 */
321 int a64 = asize == 64;
322
323 op->indexreg = -1;
324
325 if (a64)
326 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
327 else
328 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
329
330 if (rm == 5 && mod == 0) {
331 if (segsize == 64) {
332 op->eaflags |= EAF_REL;
333 op->segment |= SEG_RELATIVE;
334 mod = 2; /* fake disp32 */
335 }
336
337 if (asize != 64)
338 op->disp_size = asize;
339
340 op->basereg = -1;
341 mod = 2; /* fake disp32 */
342 }
343
344 if (rm == 4) { /* process SIB */
345 scale = (sib >> 6) & 03;
346 index = (sib >> 3) & 07;
347 base = sib & 07;
348
349 op->scale = 1 << scale;
350
351 if (index == 4 && !(rex & REX_X))
352 op->indexreg = -1; /* ESP/RSP cannot be an index */
353 else if (a64)
354 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
355 else
356 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
357
358 if (base == 5 && mod == 0) {
359 op->basereg = -1;
360 mod = 2; /* Fake disp32 */
361 } else if (a64)
362 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
363 else
364 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
365
366 if (segsize == 16)
367 op->disp_size = 32;
368 }
369
370 switch (mod) {
371 case 0:
372 op->segment |= SEG_NODISP;
373 break;
374 case 1:
375 op->segment |= SEG_DISP8;
376 op->offset = gets8(data);
377 data++;
378 break;
379 case 2:
380 op->segment |= SEG_DISP32;
381 op->offset = gets32(data);
382 data += 4;
383 break;
384 }
385 return data;
386 }
387 }
388
389 /*
390 * Determine whether the instruction template in t corresponds to the data
391 * stream in data. Return the number of bytes matched if so.
392 */
393 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
394
395 static int matches(const struct itemplate *t, uint8_t *data,
396 const struct prefix_info *prefix, int segsize, insn *ins)
397 {
398 uint8_t *r = (uint8_t *)(t->code);
399 uint8_t *origdata = data;
400 bool a_used = false, o_used = false;
401 enum prefixes drep = 0;
402 enum prefixes dwait = 0;
403 uint8_t lock = prefix->lock;
404 int osize = prefix->osize;
405 int asize = prefix->asize;
406 int i, c;
407 int op1, op2;
408 struct operand *opx, *opy;
409 uint8_t opex = 0;
410 int s_field_for = -1; /* No 144/154 series code encountered */
411 bool vex_ok = false;
412 int regmask = (segsize == 64) ? 15 : 7;
413
414 for (i = 0; i < MAX_OPERANDS; i++) {
415 ins->oprs[i].segment = ins->oprs[i].disp_size =
416 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
417 }
418 ins->condition = -1;
419 ins->rex = prefix->rex;
420 memset(ins->prefixes, 0, sizeof ins->prefixes);
421
422 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
423 return false;
424
425 if (prefix->rep == 0xF2)
426 drep = P_REPNE;
427 else if (prefix->rep == 0xF3)
428 drep = P_REP;
429
430 dwait = prefix->wait ? P_WAIT : 0;
431
432 while ((c = *r++) != 0) {
433 op1 = (c & 3) + ((opex & 1) << 2);
434 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
435 opx = &ins->oprs[op1];
436 opy = &ins->oprs[op2];
437 opex = 0;
438
439 switch (c) {
440 case 01:
441 case 02:
442 case 03:
443 case 04:
444 while (c--)
445 if (*r++ != *data++)
446 return false;
447 break;
448
449 case 05:
450 case 06:
451 case 07:
452 opex = c;
453 break;
454
455 case4(010):
456 {
457 int t = *r++, d = *data++;
458 if (d < t || d > t + 7)
459 return false;
460 else {
461 opx->basereg = (d-t)+
462 (ins->rex & REX_B ? 8 : 0);
463 opx->segment |= SEG_RMREG;
464 }
465 break;
466 }
467
468 case4(014):
469 case4(0274):
470 opx->offset = (int8_t)*data++;
471 opx->segment |= SEG_SIGNED;
472 break;
473
474 case4(020):
475 opx->offset = *data++;
476 break;
477
478 case4(024):
479 opx->offset = *data++;
480 break;
481
482 case4(030):
483 opx->offset = getu16(data);
484 data += 2;
485 break;
486
487 case4(034):
488 if (osize == 32) {
489 opx->offset = getu32(data);
490 data += 4;
491 } else {
492 opx->offset = getu16(data);
493 data += 2;
494 }
495 if (segsize != asize)
496 opx->disp_size = asize;
497 break;
498
499 case4(040):
500 case4(0254):
501 opx->offset = getu32(data);
502 data += 4;
503 break;
504
505 case4(044):
506 switch (asize) {
507 case 16:
508 opx->offset = getu16(data);
509 data += 2;
510 if (segsize != 16)
511 opx->disp_size = 16;
512 break;
513 case 32:
514 opx->offset = getu32(data);
515 data += 4;
516 if (segsize == 16)
517 opx->disp_size = 32;
518 break;
519 case 64:
520 opx->offset = getu64(data);
521 opx->disp_size = 64;
522 data += 8;
523 break;
524 }
525 break;
526
527 case4(050):
528 opx->offset = gets8(data++);
529 opx->segment |= SEG_RELATIVE;
530 break;
531
532 case4(054):
533 opx->offset = getu64(data);
534 data += 8;
535 break;
536
537 case4(060):
538 opx->offset = gets16(data);
539 data += 2;
540 opx->segment |= SEG_RELATIVE;
541 opx->segment &= ~SEG_32BIT;
542 break;
543
544 case4(064):
545 opx->segment |= SEG_RELATIVE;
546 if (osize == 16) {
547 opx->offset = gets16(data);
548 data += 2;
549 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
550 } else if (osize == 32) {
551 opx->offset = gets32(data);
552 data += 4;
553 opx->segment &= ~SEG_64BIT;
554 opx->segment |= SEG_32BIT;
555 }
556 if (segsize != osize) {
557 opx->type =
558 (opx->type & ~SIZE_MASK)
559 | ((osize == 16) ? BITS16 : BITS32);
560 }
561 break;
562
563 case4(070):
564 opx->offset = gets32(data);
565 data += 4;
566 opx->segment |= SEG_32BIT | SEG_RELATIVE;
567 break;
568
569 case4(0100):
570 case4(0110):
571 case4(0120):
572 case4(0130):
573 {
574 int modrm = *data++;
575 opx->segment |= SEG_RMREG;
576 data = do_ea(data, modrm, asize, segsize, opy, ins);
577 if (!data)
578 return false;
579 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
580 break;
581 }
582
583 case4(0140):
584 if (s_field_for == op1) {
585 opx->offset = gets8(data);
586 data++;
587 } else {
588 opx->offset = getu16(data);
589 data += 2;
590 }
591 break;
592
593 case4(0144):
594 case4(0154):
595 s_field_for = (*data & 0x02) ? op1 : -1;
596 if ((*data++ & ~0x02) != *r++)
597 return false;
598 break;
599
600 case4(0150):
601 if (s_field_for == op1) {
602 opx->offset = gets8(data);
603 data++;
604 } else {
605 opx->offset = getu32(data);
606 data += 4;
607 }
608 break;
609
610 case4(0160):
611 ins->rex |= REX_D;
612 ins->drexdst = op1;
613 break;
614
615 case4(0164):
616 ins->rex |= REX_D|REX_OC;
617 ins->drexdst = op1;
618 break;
619
620 case 0171:
621 data = do_drex(data, ins);
622 if (!data)
623 return false;
624 break;
625
626 case 0172:
627 {
628 uint8_t ximm = *data++;
629 c = *r++;
630 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
631 ins->oprs[c >> 3].segment |= SEG_RMREG;
632 ins->oprs[c & 7].offset = ximm & 15;
633 }
634 break;
635
636 case 0173:
637 {
638 uint8_t ximm = *data++;
639 c = *r++;
640
641 if ((c ^ ximm) & 15)
642 return false;
643
644 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
645 ins->oprs[c >> 4].segment |= SEG_RMREG;
646 }
647 break;
648
649 case 0174:
650 {
651 uint8_t ximm = *data++;
652 c = *r++;
653
654 ins->oprs[c].basereg = (ximm >> 4) & regmask;
655 ins->oprs[c].segment |= SEG_RMREG;
656 }
657 break;
658
659 case4(0200):
660 case4(0204):
661 case4(0210):
662 case4(0214):
663 case4(0220):
664 case4(0224):
665 case4(0230):
666 case4(0234):
667 {
668 int modrm = *data++;
669 if (((modrm >> 3) & 07) != (c & 07))
670 return false; /* spare field doesn't match up */
671 data = do_ea(data, modrm, asize, segsize, opy, ins);
672 if (!data)
673 return false;
674 break;
675 }
676
677 case4(0250):
678 if (s_field_for == op1) {
679 opx->offset = gets8(data);
680 data++;
681 } else {
682 opx->offset = gets32(data);
683 data += 4;
684 }
685 break;
686
687 case4(0260):
688 case 0270:
689 {
690 int vexm = *r++;
691 int vexwlp = *r++;
692
693 ins->rex |= REX_V;
694 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
695 return false;
696
697 if ((vexm & 0x1f) != prefix->vex_m)
698 return false;
699
700 switch (vexwlp & 060) {
701 case 000:
702 if (prefix->rex & REX_W)
703 return false;
704 break;
705 case 020:
706 if (!(prefix->rex & REX_W))
707 return false;
708 ins->rex &= ~REX_W;
709 break;
710 case 040: /* VEX.W is a don't care */
711 ins->rex &= ~REX_W;
712 break;
713 case 060:
714 break;
715 }
716
717 /* The 010 bit of vexwlp is set if VEX.L is ignored */
718 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
719 return false;
720
721 if (c == 0270) {
722 if (prefix->vex_v != 0)
723 return false;
724 } else {
725 opx->segment |= SEG_RMREG;
726 opx->basereg = prefix->vex_v;
727 }
728 vex_ok = true;
729 break;
730 }
731
732 case 0310:
733 if (asize != 16)
734 return false;
735 else
736 a_used = true;
737 break;
738
739 case 0311:
740 if (asize != 32)
741 return false;
742 else
743 a_used = true;
744 break;
745
746 case 0312:
747 if (asize != segsize)
748 return false;
749 else
750 a_used = true;
751 break;
752
753 case 0313:
754 if (asize != 64)
755 return false;
756 else
757 a_used = true;
758 break;
759
760 case 0314:
761 if (prefix->rex & REX_B)
762 return false;
763 break;
764
765 case 0315:
766 if (prefix->rex & REX_X)
767 return false;
768 break;
769
770 case 0316:
771 if (prefix->rex & REX_R)
772 return false;
773 break;
774
775 case 0317:
776 if (prefix->rex & REX_W)
777 return false;
778 break;
779
780 case 0320:
781 if (osize != 16)
782 return false;
783 else
784 o_used = true;
785 break;
786
787 case 0321:
788 if (osize != 32)
789 return false;
790 else
791 o_used = true;
792 break;
793
794 case 0322:
795 if (osize != (segsize == 16) ? 16 : 32)
796 return false;
797 else
798 o_used = true;
799 break;
800
801 case 0323:
802 ins->rex |= REX_W; /* 64-bit only instruction */
803 osize = 64;
804 o_used = true;
805 break;
806
807 case 0324:
808 if (osize != 64)
809 return false;
810 o_used = true;
811 break;
812
813 case 0325:
814 ins->rex |= REX_NH;
815 break;
816
817 case 0330:
818 {
819 int t = *r++, d = *data++;
820 if (d < t || d > t + 15)
821 return false;
822 else
823 ins->condition = d - t;
824 break;
825 }
826
827 case 0331:
828 if (prefix->rep)
829 return false;
830 break;
831
832 case 0332:
833 if (prefix->rep != 0xF2)
834 return false;
835 drep = 0;
836 break;
837
838 case 0333:
839 if (prefix->rep != 0xF3)
840 return false;
841 drep = 0;
842 break;
843
844 case 0334:
845 if (lock) {
846 ins->rex |= REX_R;
847 lock = 0;
848 }
849 break;
850
851 case 0335:
852 if (drep == P_REP)
853 drep = P_REPE;
854 break;
855
856 case 0336:
857 case 0337:
858 break;
859
860 case 0340:
861 return false;
862
863 case 0341:
864 if (prefix->wait != 0x9B)
865 return false;
866 dwait = 0;
867 break;
868
869 case4(0344):
870 ins->oprs[0].basereg = (*data++ >> 3) & 7;
871 break;
872
873 case 0360:
874 if (prefix->osp || prefix->rep)
875 return false;
876 break;
877
878 case 0361:
879 if (!prefix->osp || prefix->rep)
880 return false;
881 o_used = true;
882 break;
883
884 case 0362:
885 if (prefix->osp || prefix->rep != 0xf2)
886 return false;
887 drep = 0;
888 break;
889
890 case 0363:
891 if (prefix->osp || prefix->rep != 0xf3)
892 return false;
893 drep = 0;
894 break;
895
896 case 0364:
897 if (prefix->osp)
898 return false;
899 break;
900
901 case 0365:
902 if (prefix->asp)
903 return false;
904 break;
905
906 case 0366:
907 if (!prefix->osp)
908 return false;
909 o_used = true;
910 break;
911
912 case 0367:
913 if (!prefix->asp)
914 return false;
915 a_used = true;
916 break;
917
918 default:
919 return false; /* Unknown code */
920 }
921 }
922
923 if (!vex_ok && (ins->rex & REX_V))
924 return false;
925
926 /* REX cannot be combined with DREX or VEX */
927 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
928 return false;
929
930 /*
931 * Check for unused rep or a/o prefixes.
932 */
933 for (i = 0; i < t->operands; i++) {
934 if (ins->oprs[i].segment != SEG_RMREG)
935 a_used = true;
936 }
937
938 if (lock) {
939 if (ins->prefixes[PPS_LREP])
940 return false;
941 ins->prefixes[PPS_LREP] = P_LOCK;
942 }
943 if (drep) {
944 if (ins->prefixes[PPS_LREP])
945 return false;
946 ins->prefixes[PPS_LREP] = drep;
947 }
948 ins->prefixes[PPS_WAIT] = dwait;
949 if (!o_used) {
950 if (osize != ((segsize == 16) ? 16 : 32)) {
951 enum prefixes pfx = 0;
952
953 switch (osize) {
954 case 16:
955 pfx = P_O16;
956 break;
957 case 32:
958 pfx = P_O32;
959 break;
960 case 64:
961 pfx = P_O64;
962 break;
963 }
964
965 if (ins->prefixes[PPS_OSIZE])
966 return false;
967 ins->prefixes[PPS_OSIZE] = pfx;
968 }
969 }
970 if (!a_used && asize != segsize) {
971 if (ins->prefixes[PPS_ASIZE])
972 return false;
973 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
974 }
975
976 /* Fix: check for redundant REX prefixes */
977
978 return data - origdata;
979 }
980
981 /* Condition names for disassembly, sorted by x86 code */
982 static const char * const condition_name[16] = {
983 "o", "no", "c", "nc", "z", "nz", "na", "a",
984 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
985 };
986
987 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
988 int32_t offset, int autosync, uint32_t prefer)
989 {
990 const struct itemplate * const *p, * const *best_p;
991 const struct disasm_index *ix;
992 uint8_t *dp;
993 int length, best_length = 0;
994 char *segover;
995 int i, slen, colon, n;
996 uint8_t *origdata;
997 int works;
998 insn tmp_ins, ins;
999 uint32_t goodness, best;
1000 int best_pref;
1001 struct prefix_info prefix;
1002 bool end_prefix;
1003
1004 memset(&ins, 0, sizeof ins);
1005
1006 /*
1007 * Scan for prefixes.
1008 */
1009 memset(&prefix, 0, sizeof prefix);
1010 prefix.asize = segsize;
1011 prefix.osize = (segsize == 64) ? 32 : segsize;
1012 segover = NULL;
1013 origdata = data;
1014
1015 ix = itable;
1016
1017 end_prefix = false;
1018 while (!end_prefix) {
1019 switch (*data) {
1020 case 0xF2:
1021 case 0xF3:
1022 prefix.rep = *data++;
1023 break;
1024
1025 case 0x9B:
1026 prefix.wait = *data++;
1027 break;
1028
1029 case 0xF0:
1030 prefix.lock = *data++;
1031 break;
1032
1033 case 0x2E:
1034 segover = "cs", prefix.seg = *data++;
1035 break;
1036 case 0x36:
1037 segover = "ss", prefix.seg = *data++;
1038 break;
1039 case 0x3E:
1040 segover = "ds", prefix.seg = *data++;
1041 break;
1042 case 0x26:
1043 segover = "es", prefix.seg = *data++;
1044 break;
1045 case 0x64:
1046 segover = "fs", prefix.seg = *data++;
1047 break;
1048 case 0x65:
1049 segover = "gs", prefix.seg = *data++;
1050 break;
1051
1052 case 0x66:
1053 prefix.osize = (segsize == 16) ? 32 : 16;
1054 prefix.osp = *data++;
1055 break;
1056 case 0x67:
1057 prefix.asize = (segsize == 32) ? 16 : 32;
1058 prefix.asp = *data++;
1059 break;
1060
1061 case 0xC4:
1062 case 0xC5:
1063 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1064 prefix.vex[0] = *data++;
1065 prefix.vex[1] = *data++;
1066
1067 prefix.rex = REX_V;
1068 prefix.vex_c = RV_VEX;
1069
1070 if (prefix.vex[0] == 0xc4) {
1071 prefix.vex[2] = *data++;
1072 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1073 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1074 prefix.vex_m = prefix.vex[1] & 0x1f;
1075 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1076 prefix.vex_lp = prefix.vex[2] & 7;
1077 } else {
1078 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1079 prefix.vex_m = 1;
1080 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1081 prefix.vex_lp = prefix.vex[1] & 7;
1082 }
1083
1084 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1085 }
1086 end_prefix = true;
1087 break;
1088
1089 case 0x8F:
1090 if ((data[1] & 030) != 0 &&
1091 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1092 prefix.vex[0] = *data++;
1093 prefix.vex[1] = *data++;
1094 prefix.vex[2] = *data++;
1095
1096 prefix.rex = REX_V;
1097 prefix.vex_c = RV_XOP;
1098
1099 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1100 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1101 prefix.vex_m = prefix.vex[1] & 0x1f;
1102 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1103 prefix.vex_lp = prefix.vex[2] & 7;
1104
1105 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp];
1106 }
1107 end_prefix = true;
1108 break;
1109
1110 case REX_P + 0x0:
1111 case REX_P + 0x1:
1112 case REX_P + 0x2:
1113 case REX_P + 0x3:
1114 case REX_P + 0x4:
1115 case REX_P + 0x5:
1116 case REX_P + 0x6:
1117 case REX_P + 0x7:
1118 case REX_P + 0x8:
1119 case REX_P + 0x9:
1120 case REX_P + 0xA:
1121 case REX_P + 0xB:
1122 case REX_P + 0xC:
1123 case REX_P + 0xD:
1124 case REX_P + 0xE:
1125 case REX_P + 0xF:
1126 if (segsize == 64) {
1127 prefix.rex = *data++;
1128 if (prefix.rex & REX_W)
1129 prefix.osize = 64;
1130 }
1131 end_prefix = true;
1132 break;
1133
1134 default:
1135 end_prefix = true;
1136 break;
1137 }
1138 }
1139
1140 best = -1; /* Worst possible */
1141 best_p = NULL;
1142 best_pref = INT_MAX;
1143
1144 if (!ix)
1145 return 0; /* No instruction table at all... */
1146
1147 dp = data;
1148 ix += *dp++;
1149 while (ix->n == -1) {
1150 ix = (const struct disasm_index *)ix->p + *dp++;
1151 }
1152
1153 p = (const struct itemplate * const *)ix->p;
1154 for (n = ix->n; n; n--, p++) {
1155 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1156 works = true;
1157 /*
1158 * Final check to make sure the types of r/m match up.
1159 * XXX: Need to make sure this is actually correct.
1160 */
1161 for (i = 0; i < (*p)->operands; i++) {
1162 if (!((*p)->opd[i] & SAME_AS) &&
1163 (
1164 /* If it's a mem-only EA but we have a
1165 register, die. */
1166 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1167 is_class(MEMORY, (*p)->opd[i])) ||
1168 /* If it's a reg-only EA but we have a memory
1169 ref, die. */
1170 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1171 !(REG_EA & ~(*p)->opd[i]) &&
1172 !((*p)->opd[i] & REG_SMASK)) ||
1173 /* Register type mismatch (eg FS vs REG_DESS):
1174 die. */
1175 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1176 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1177 !whichreg((*p)->opd[i],
1178 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1179 )) {
1180 works = false;
1181 break;
1182 }
1183 }
1184
1185 /*
1186 * Note: we always prefer instructions which incorporate
1187 * prefixes in the instructions themselves. This is to allow
1188 * e.g. PAUSE to be preferred to REP NOP, and deal with
1189 * MMX/SSE instructions where prefixes are used to select
1190 * between MMX and SSE register sets or outright opcode
1191 * selection.
1192 */
1193 if (works) {
1194 int i, nprefix;
1195 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1196 nprefix = 0;
1197 for (i = 0; i < MAXPREFIX; i++)
1198 if (tmp_ins.prefixes[i])
1199 nprefix++;
1200 if (nprefix < best_pref ||
1201 (nprefix == best_pref && goodness < best)) {
1202 /* This is the best one found so far */
1203 best = goodness;
1204 best_p = p;
1205 best_pref = nprefix;
1206 best_length = length;
1207 ins = tmp_ins;
1208 }
1209 }
1210 }
1211 }
1212
1213 if (!best_p)
1214 return 0; /* no instruction was matched */
1215
1216 /* Pick the best match */
1217 p = best_p;
1218 length = best_length;
1219
1220 slen = 0;
1221
1222 /* TODO: snprintf returns the value that the string would have if
1223 * the buffer were long enough, and not the actual length of
1224 * the returned string, so each instance of using the return
1225 * value of snprintf should actually be checked to assure that
1226 * the return value is "sane." Maybe a macro wrapper could
1227 * be used for that purpose.
1228 */
1229 for (i = 0; i < MAXPREFIX; i++) {
1230 const char *prefix = prefix_name(ins.prefixes[i]);
1231 if (prefix)
1232 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1233 }
1234
1235 i = (*p)->opcode;
1236 if (i >= FIRST_COND_OPCODE)
1237 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1238 nasm_insn_names[i], condition_name[ins.condition]);
1239 else
1240 slen += snprintf(output + slen, outbufsize - slen, "%s",
1241 nasm_insn_names[i]);
1242
1243 colon = false;
1244 length += data - origdata; /* fix up for prefixes */
1245 for (i = 0; i < (*p)->operands; i++) {
1246 opflags_t t = (*p)->opd[i];
1247 const operand *o = &ins.oprs[i];
1248 int64_t offs;
1249
1250 if (t & SAME_AS) {
1251 o = &ins.oprs[t & ~SAME_AS];
1252 t = (*p)->opd[t & ~SAME_AS];
1253 }
1254
1255 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1256
1257 offs = o->offset;
1258 if (o->segment & SEG_RELATIVE) {
1259 offs += offset + length;
1260 /*
1261 * sort out wraparound
1262 */
1263 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1264 offs &= 0xffff;
1265 else if (segsize != 64)
1266 offs &= 0xffffffff;
1267
1268 /*
1269 * add sync marker, if autosync is on
1270 */
1271 if (autosync)
1272 add_sync(offs, 0L);
1273 }
1274
1275 if (t & COLON)
1276 colon = true;
1277 else
1278 colon = false;
1279
1280 if ((t & (REGISTER | FPUREG)) ||
1281 (o->segment & SEG_RMREG)) {
1282 enum reg_enum reg;
1283 reg = whichreg(t, o->basereg, ins.rex);
1284 if (t & TO)
1285 slen += snprintf(output + slen, outbufsize - slen, "to ");
1286 slen += snprintf(output + slen, outbufsize - slen, "%s",
1287 nasm_reg_names[reg-EXPR_REG_START]);
1288 } else if (!(UNITY & ~t)) {
1289 output[slen++] = '1';
1290 } else if (t & IMMEDIATE) {
1291 if (t & BITS8) {
1292 slen +=
1293 snprintf(output + slen, outbufsize - slen, "byte ");
1294 if (o->segment & SEG_SIGNED) {
1295 if (offs < 0) {
1296 offs *= -1;
1297 output[slen++] = '-';
1298 } else
1299 output[slen++] = '+';
1300 }
1301 } else if (t & BITS16) {
1302 slen +=
1303 snprintf(output + slen, outbufsize - slen, "word ");
1304 } else if (t & BITS32) {
1305 slen +=
1306 snprintf(output + slen, outbufsize - slen, "dword ");
1307 } else if (t & BITS64) {
1308 slen +=
1309 snprintf(output + slen, outbufsize - slen, "qword ");
1310 } else if (t & NEAR) {
1311 slen +=
1312 snprintf(output + slen, outbufsize - slen, "near ");
1313 } else if (t & SHORT) {
1314 slen +=
1315 snprintf(output + slen, outbufsize - slen, "short ");
1316 }
1317 slen +=
1318 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1319 offs);
1320 } else if (!(MEM_OFFS & ~t)) {
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen,
1323 "[%s%s%s0x%"PRIx64"]",
1324 (segover ? segover : ""),
1325 (segover ? ":" : ""),
1326 (o->disp_size == 64 ? "qword " :
1327 o->disp_size == 32 ? "dword " :
1328 o->disp_size == 16 ? "word " : ""), offs);
1329 segover = NULL;
1330 } else if (is_class(REGMEM, t)) {
1331 int started = false;
1332 if (t & BITS8)
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "byte ");
1335 if (t & BITS16)
1336 slen +=
1337 snprintf(output + slen, outbufsize - slen, "word ");
1338 if (t & BITS32)
1339 slen +=
1340 snprintf(output + slen, outbufsize - slen, "dword ");
1341 if (t & BITS64)
1342 slen +=
1343 snprintf(output + slen, outbufsize - slen, "qword ");
1344 if (t & BITS80)
1345 slen +=
1346 snprintf(output + slen, outbufsize - slen, "tword ");
1347 if (t & BITS128)
1348 slen +=
1349 snprintf(output + slen, outbufsize - slen, "oword ");
1350 if (t & BITS256)
1351 slen +=
1352 snprintf(output + slen, outbufsize - slen, "yword ");
1353 if (t & FAR)
1354 slen += snprintf(output + slen, outbufsize - slen, "far ");
1355 if (t & NEAR)
1356 slen +=
1357 snprintf(output + slen, outbufsize - slen, "near ");
1358 output[slen++] = '[';
1359 if (o->disp_size)
1360 slen += snprintf(output + slen, outbufsize - slen, "%s",
1361 (o->disp_size == 64 ? "qword " :
1362 o->disp_size == 32 ? "dword " :
1363 o->disp_size == 16 ? "word " :
1364 ""));
1365 if (o->eaflags & EAF_REL)
1366 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1367 if (segover) {
1368 slen +=
1369 snprintf(output + slen, outbufsize - slen, "%s:",
1370 segover);
1371 segover = NULL;
1372 }
1373 if (o->basereg != -1) {
1374 slen += snprintf(output + slen, outbufsize - slen, "%s",
1375 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1376 started = true;
1377 }
1378 if (o->indexreg != -1) {
1379 if (started)
1380 output[slen++] = '+';
1381 slen += snprintf(output + slen, outbufsize - slen, "%s",
1382 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1383 if (o->scale > 1)
1384 slen +=
1385 snprintf(output + slen, outbufsize - slen, "*%d",
1386 o->scale);
1387 started = true;
1388 }
1389
1390
1391 if (o->segment & SEG_DISP8) {
1392 const char *prefix;
1393 uint8_t offset = offs;
1394 if ((int8_t)offset < 0) {
1395 prefix = "-";
1396 offset = -offset;
1397 } else {
1398 prefix = "+";
1399 }
1400 slen +=
1401 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1402 prefix, offset);
1403 } else if (o->segment & SEG_DISP16) {
1404 const char *prefix;
1405 uint16_t offset = offs;
1406 if ((int16_t)offset < 0 && started) {
1407 offset = -offset;
1408 prefix = "-";
1409 } else {
1410 prefix = started ? "+" : "";
1411 }
1412 slen +=
1413 snprintf(output + slen, outbufsize - slen,
1414 "%s0x%"PRIx16"", prefix, offset);
1415 } else if (o->segment & SEG_DISP32) {
1416 if (prefix.asize == 64) {
1417 const char *prefix;
1418 uint64_t offset = (int64_t)(int32_t)offs;
1419 if ((int32_t)offs < 0 && started) {
1420 offset = -offset;
1421 prefix = "-";
1422 } else {
1423 prefix = started ? "+" : "";
1424 }
1425 slen +=
1426 snprintf(output + slen, outbufsize - slen,
1427 "%s0x%"PRIx64"", prefix, offset);
1428 } else {
1429 const char *prefix;
1430 uint32_t offset = offs;
1431 if ((int32_t) offset < 0 && started) {
1432 offset = -offset;
1433 prefix = "-";
1434 } else {
1435 prefix = started ? "+" : "";
1436 }
1437 slen +=
1438 snprintf(output + slen, outbufsize - slen,
1439 "%s0x%"PRIx32"", prefix, offset);
1440 }
1441 }
1442 output[slen++] = ']';
1443 } else {
1444 slen +=
1445 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1446 i);
1447 }
1448 }
1449 output[slen] = '\0';
1450 if (segover) { /* unused segment override */
1451 char *p = output;
1452 int count = slen + 1;
1453 while (count--)
1454 p[count + 3] = p[count];
1455 strncpy(output, segover, 2);
1456 output[2] = ' ';
1457 }
1458 return length;
1459 }
1460
1461 /*
1462 * This is called when we don't have a complete instruction. If it
1463 * is a standalone *single-byte* prefix show it as such, otherwise
1464 * print it as a literal.
1465 */
1466 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1467 {
1468 uint8_t byte = *data;
1469 const char *str = NULL;
1470
1471 switch (byte) {
1472 case 0xF2:
1473 str = "repne";
1474 break;
1475 case 0xF3:
1476 str = "rep";
1477 break;
1478 case 0x9B:
1479 str = "wait";
1480 break;
1481 case 0xF0:
1482 str = "lock";
1483 break;
1484 case 0x2E:
1485 str = "cs";
1486 break;
1487 case 0x36:
1488 str = "ss";
1489 break;
1490 case 0x3E:
1491 str = "ss";
1492 break;
1493 case 0x26:
1494 str = "es";
1495 break;
1496 case 0x64:
1497 str = "fs";
1498 break;
1499 case 0x65:
1500 str = "gs";
1501 break;
1502 case 0x66:
1503 str = (segsize == 16) ? "o32" : "o16";
1504 break;
1505 case 0x67:
1506 str = (segsize == 32) ? "a16" : "a32";
1507 break;
1508 case REX_P + 0x0:
1509 case REX_P + 0x1:
1510 case REX_P + 0x2:
1511 case REX_P + 0x3:
1512 case REX_P + 0x4:
1513 case REX_P + 0x5:
1514 case REX_P + 0x6:
1515 case REX_P + 0x7:
1516 case REX_P + 0x8:
1517 case REX_P + 0x9:
1518 case REX_P + 0xA:
1519 case REX_P + 0xB:
1520 case REX_P + 0xC:
1521 case REX_P + 0xD:
1522 case REX_P + 0xE:
1523 case REX_P + 0xF:
1524 if (segsize == 64) {
1525 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1526 (byte == REX_P) ? "" : ".",
1527 (byte & REX_W) ? "w" : "",
1528 (byte & REX_R) ? "r" : "",
1529 (byte & REX_X) ? "x" : "",
1530 (byte & REX_B) ? "b" : "");
1531 break;
1532 }
1533 /* else fall through */
1534 default:
1535 snprintf(output, outbufsize, "db 0x%02x", byte);
1536 break;
1537 }
1538
1539 if (str)
1540 snprintf(output, outbufsize, "%s", str);
1541
1542 return 1;
1543 }
Adding AVX-512 features