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SHA: Add SHA instructions
[nasm/avx512.git] / assemble.c
blob07e472337305c94b59c430e220a041cd4a85f196
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \372 - BND prefix (0xF2 byte) used for preserving bnd0..3
166 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
167 * used for conditional jump over longer jump
168 * \374 - this instruction takes an XMM VSIB memory EA
169 * \375 - this instruction takes an YMM VSIB memory EA
170 * \376 - this instruction takes an ZMM VSIB memory EA
171 */
172
173 #include "compiler.h"
174
175 #include <stdio.h>
176 #include <string.h>
177 #include <inttypes.h>
178
179 #include "nasm.h"
180 #include "nasmlib.h"
181 #include "assemble.h"
182 #include "insns.h"
183 #include "tables.h"
184
185 enum match_result {
186 /*
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
189 */
190 MERR_INVALOP,
191 MERR_OPSIZEMISSING,
192 MERR_OPSIZEMISMATCH,
193 MERR_BADCPU,
194 MERR_BADMODE,
195 MERR_BADHLE,
196 MERR_ENCMISMATCH,
197 MERR_BADBND,
198 /*
199 * Matching success; the conditional ones first
200 */
201 MOK_JUMP, /* Matching OK but needs jmp_match() */
202 MOK_GOOD /* Matching unconditionally OK */
203 };
204
205 typedef struct {
206 enum ea_type type; /* what kind of EA is this? */
207 int sib_present; /* is a SIB byte necessary? */
208 int bytes; /* # of bytes of offset needed */
209 int size; /* lazy - this is sib+bytes+1 */
210 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
211 int8_t disp8; /* compressed displacement for EVEX */
212 } ea;
213
214 #define GEN_SIB(scale, index, base) \
215 (((scale) << 6) | ((index) << 3) | ((base)))
216
217 #define GEN_MODRM(mod, reg, rm) \
218 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
219
220 static iflags_t cpu; /* cpu level received from nasm.c */
221 static efunc errfunc;
222 static struct ofmt *outfmt;
223 static ListGen *list;
224
225 static int64_t calcsize(int32_t, int64_t, int, insn *,
226 const struct itemplate *);
227 static void gencode(int32_t segment, int64_t offset, int bits,
228 insn * ins, const struct itemplate *temp,
229 int64_t insn_end);
230 static enum match_result find_match(const struct itemplate **tempp,
231 insn *instruction,
232 int32_t segment, int64_t offset, int bits);
233 static enum match_result matches(const struct itemplate *, insn *, int bits);
234 static opflags_t regflag(const operand *);
235 static int32_t regval(const operand *);
236 static int rexflags(int, opflags_t, int);
237 static int op_rexflags(const operand *, int);
238 static int op_evexflags(const operand *, int, uint8_t);
239 static void add_asp(insn *, int);
240
241 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
242
243 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
244 {
245 return ins->prefixes[pos] == prefix;
246 }
247
248 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
249 {
250 if (ins->prefixes[pos])
251 errfunc(ERR_NONFATAL, "invalid %s prefix",
252 prefix_name(ins->prefixes[pos]));
253 }
254
255 static const char *size_name(int size)
256 {
257 switch (size) {
258 case 1:
259 return "byte";
260 case 2:
261 return "word";
262 case 4:
263 return "dword";
264 case 8:
265 return "qword";
266 case 10:
267 return "tword";
268 case 16:
269 return "oword";
270 case 32:
271 return "yword";
272 case 64:
273 return "zword";
274 default:
275 return "???";
276 }
277 }
278
279 static void warn_overflow(int pass, int size)
280 {
281 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
282 "%s data exceeds bounds", size_name(size));
283 }
284
285 static void warn_overflow_const(int64_t data, int size)
286 {
287 if (overflow_general(data, size))
288 warn_overflow(ERR_PASS1, size);
289 }
290
291 static void warn_overflow_opd(const struct operand *o, int size)
292 {
293 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
294 if (overflow_general(o->offset, size))
295 warn_overflow(ERR_PASS2, size);
296 }
297 }
298
299 /*
300 * This routine wrappers the real output format's output routine,
301 * in order to pass a copy of the data off to the listing file
302 * generator at the same time.
303 */
304 static void out(int64_t offset, int32_t segto, const void *data,
305 enum out_type type, uint64_t size,
306 int32_t segment, int32_t wrt)
307 {
308 static int32_t lineno = 0; /* static!!! */
309 static char *lnfname = NULL;
310 uint8_t p[8];
311
312 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
313 /*
314 * This is a non-relocated address, and we're going to
315 * convert it into RAWDATA format.
316 */
317 uint8_t *q = p;
318
319 if (size > 8) {
320 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
321 return;
322 }
323
324 WRITEADDR(q, *(int64_t *)data, size);
325 data = p;
326 type = OUT_RAWDATA;
327 }
328
329 list->output(offset, data, type, size);
330
331 /*
332 * this call to src_get determines when we call the
333 * debug-format-specific "linenum" function
334 * it updates lineno and lnfname to the current values
335 * returning 0 if "same as last time", -2 if lnfname
336 * changed, and the amount by which lineno changed,
337 * if it did. thus, these variables must be static
338 */
339
340 if (src_get(&lineno, &lnfname))
341 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
342
343 outfmt->output(segto, data, type, size, segment, wrt);
344 }
345
346 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
347 {
348 if (opx->segment != NO_SEG) {
349 uint64_t data = opx->offset;
350 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
351 } else {
352 uint8_t byte = opx->offset;
353 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
354 }
355 }
356
357 static bool jmp_match(int32_t segment, int64_t offset, int bits,
358 insn * ins, const struct itemplate *temp)
359 {
360 int64_t isize;
361 const uint8_t *code = temp->code;
362 uint8_t c = code[0];
363
364 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
365 return false;
366 if (!optimizing)
367 return false;
368 if (optimizing < 0 && c == 0371)
369 return false;
370
371 isize = calcsize(segment, offset, bits, ins, temp);
372
373 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
374 /* Be optimistic in pass 1 */
375 return true;
376
377 if (ins->oprs[0].segment != segment)
378 return false;
379
380 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
381 return (isize >= -128 && isize <= 127); /* is it byte size? */
382 }
383
384 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
385 insn * instruction, struct ofmt *output, efunc error,
386 ListGen * listgen)
387 {
388 const struct itemplate *temp;
389 int j;
390 enum match_result m;
391 int64_t insn_end;
392 int32_t itimes;
393 int64_t start = offset;
394 int64_t wsize; /* size for DB etc. */
395
396 errfunc = error; /* to pass to other functions */
397 cpu = cp;
398 outfmt = output; /* likewise */
399 list = listgen; /* and again */
400
401 wsize = idata_bytes(instruction->opcode);
402 if (wsize == -1)
403 return 0;
404
405 if (wsize) {
406 extop *e;
407 int32_t t = instruction->times;
408 if (t < 0)
409 errfunc(ERR_PANIC,
410 "instruction->times < 0 (%ld) in assemble()", t);
411
412 while (t--) { /* repeat TIMES times */
413 list_for_each(e, instruction->eops) {
414 if (e->type == EOT_DB_NUMBER) {
415 if (wsize > 8) {
416 errfunc(ERR_NONFATAL,
417 "integer supplied to a DT, DO or DY"
418 " instruction");
419 } else {
420 out(offset, segment, &e->offset,
421 OUT_ADDRESS, wsize, e->segment, e->wrt);
422 offset += wsize;
423 }
424 } else if (e->type == EOT_DB_STRING ||
425 e->type == EOT_DB_STRING_FREE) {
426 int align;
427
428 out(offset, segment, e->stringval,
429 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
430 align = e->stringlen % wsize;
431
432 if (align) {
433 align = wsize - align;
434 out(offset, segment, zero_buffer,
435 OUT_RAWDATA, align, NO_SEG, NO_SEG);
436 }
437 offset += e->stringlen + align;
438 }
439 }
440 if (t > 0 && t == instruction->times - 1) {
441 /*
442 * Dummy call to list->output to give the offset to the
443 * listing module.
444 */
445 list->output(offset, NULL, OUT_RAWDATA, 0);
446 list->uplevel(LIST_TIMES);
447 }
448 }
449 if (instruction->times > 1)
450 list->downlevel(LIST_TIMES);
451 return offset - start;
452 }
453
454 if (instruction->opcode == I_INCBIN) {
455 const char *fname = instruction->eops->stringval;
456 FILE *fp;
457
458 fp = fopen(fname, "rb");
459 if (!fp) {
460 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
461 fname);
462 } else if (fseek(fp, 0L, SEEK_END) < 0) {
463 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
464 fname);
465 fclose(fp);
466 } else {
467 static char buf[4096];
468 size_t t = instruction->times;
469 size_t base = 0;
470 size_t len;
471
472 len = ftell(fp);
473 if (instruction->eops->next) {
474 base = instruction->eops->next->offset;
475 len -= base;
476 if (instruction->eops->next->next &&
477 len > (size_t)instruction->eops->next->next->offset)
478 len = (size_t)instruction->eops->next->next->offset;
479 }
480 /*
481 * Dummy call to list->output to give the offset to the
482 * listing module.
483 */
484 list->output(offset, NULL, OUT_RAWDATA, 0);
485 list->uplevel(LIST_INCBIN);
486 while (t--) {
487 size_t l;
488
489 fseek(fp, base, SEEK_SET);
490 l = len;
491 while (l > 0) {
492 int32_t m;
493 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
494 if (!m) {
495 /*
496 * This shouldn't happen unless the file
497 * actually changes while we are reading
498 * it.
499 */
500 error(ERR_NONFATAL,
501 "`incbin': unexpected EOF while"
502 " reading file `%s'", fname);
503 t = 0; /* Try to exit cleanly */
504 break;
505 }
506 out(offset, segment, buf, OUT_RAWDATA, m,
507 NO_SEG, NO_SEG);
508 l -= m;
509 }
510 }
511 list->downlevel(LIST_INCBIN);
512 if (instruction->times > 1) {
513 /*
514 * Dummy call to list->output to give the offset to the
515 * listing module.
516 */
517 list->output(offset, NULL, OUT_RAWDATA, 0);
518 list->uplevel(LIST_TIMES);
519 list->downlevel(LIST_TIMES);
520 }
521 fclose(fp);
522 return instruction->times * len;
523 }
524 return 0; /* if we're here, there's an error */
525 }
526
527 /* Check to see if we need an address-size prefix */
528 add_asp(instruction, bits);
529
530 m = find_match(&temp, instruction, segment, offset, bits);
531
532 if (m == MOK_GOOD) {
533 /* Matches! */
534 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
535 itimes = instruction->times;
536 if (insn_size < 0) /* shouldn't be, on pass two */
537 error(ERR_PANIC, "errors made it through from pass one");
538 else
539 while (itimes--) {
540 for (j = 0; j < MAXPREFIX; j++) {
541 uint8_t c = 0;
542 switch (instruction->prefixes[j]) {
543 case P_WAIT:
544 c = 0x9B;
545 break;
546 case P_LOCK:
547 c = 0xF0;
548 break;
549 case P_REPNE:
550 case P_REPNZ:
551 case P_XACQUIRE:
552 case P_BND:
553 c = 0xF2;
554 break;
555 case P_REPE:
556 case P_REPZ:
557 case P_REP:
558 case P_XRELEASE:
559 c = 0xF3;
560 break;
561 case R_CS:
562 if (bits == 64) {
563 error(ERR_WARNING | ERR_PASS2,
564 "cs segment base generated, but will be ignored in 64-bit mode");
565 }
566 c = 0x2E;
567 break;
568 case R_DS:
569 if (bits == 64) {
570 error(ERR_WARNING | ERR_PASS2,
571 "ds segment base generated, but will be ignored in 64-bit mode");
572 }
573 c = 0x3E;
574 break;
575 case R_ES:
576 if (bits == 64) {
577 error(ERR_WARNING | ERR_PASS2,
578 "es segment base generated, but will be ignored in 64-bit mode");
579 }
580 c = 0x26;
581 break;
582 case R_FS:
583 c = 0x64;
584 break;
585 case R_GS:
586 c = 0x65;
587 break;
588 case R_SS:
589 if (bits == 64) {
590 error(ERR_WARNING | ERR_PASS2,
591 "ss segment base generated, but will be ignored in 64-bit mode");
592 }
593 c = 0x36;
594 break;
595 case R_SEGR6:
596 case R_SEGR7:
597 error(ERR_NONFATAL,
598 "segr6 and segr7 cannot be used as prefixes");
599 break;
600 case P_A16:
601 if (bits == 64) {
602 error(ERR_NONFATAL,
603 "16-bit addressing is not supported "
604 "in 64-bit mode");
605 } else if (bits != 16)
606 c = 0x67;
607 break;
608 case P_A32:
609 if (bits != 32)
610 c = 0x67;
611 break;
612 case P_A64:
613 if (bits != 64) {
614 error(ERR_NONFATAL,
615 "64-bit addressing is only supported "
616 "in 64-bit mode");
617 }
618 break;
619 case P_ASP:
620 c = 0x67;
621 break;
622 case P_O16:
623 if (bits != 16)
624 c = 0x66;
625 break;
626 case P_O32:
627 if (bits == 16)
628 c = 0x66;
629 break;
630 case P_O64:
631 /* REX.W */
632 break;
633 case P_OSP:
634 c = 0x66;
635 break;
636 case P_none:
637 break;
638 default:
639 error(ERR_PANIC, "invalid instruction prefix");
640 }
641 if (c != 0) {
642 out(offset, segment, &c, OUT_RAWDATA, 1,
643 NO_SEG, NO_SEG);
644 offset++;
645 }
646 }
647 insn_end = offset + insn_size;
648 gencode(segment, offset, bits, instruction,
649 temp, insn_end);
650 offset += insn_size;
651 if (itimes > 0 && itimes == instruction->times - 1) {
652 /*
653 * Dummy call to list->output to give the offset to the
654 * listing module.
655 */
656 list->output(offset, NULL, OUT_RAWDATA, 0);
657 list->uplevel(LIST_TIMES);
658 }
659 }
660 if (instruction->times > 1)
661 list->downlevel(LIST_TIMES);
662 return offset - start;
663 } else {
664 /* No match */
665 switch (m) {
666 case MERR_OPSIZEMISSING:
667 error(ERR_NONFATAL, "operation size not specified");
668 break;
669 case MERR_OPSIZEMISMATCH:
670 error(ERR_NONFATAL, "mismatch in operand sizes");
671 break;
672 case MERR_BADCPU:
673 error(ERR_NONFATAL, "no instruction for this cpu level");
674 break;
675 case MERR_BADMODE:
676 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
677 bits);
678 break;
679 default:
680 error(ERR_NONFATAL,
681 "invalid combination of opcode and operands");
682 break;
683 }
684 }
685 return 0;
686 }
687
688 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
689 insn * instruction, efunc error)
690 {
691 const struct itemplate *temp;
692 enum match_result m;
693
694 errfunc = error; /* to pass to other functions */
695 cpu = cp;
696
697 if (instruction->opcode == I_none)
698 return 0;
699
700 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
701 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
702 instruction->opcode == I_DT || instruction->opcode == I_DO ||
703 instruction->opcode == I_DY) {
704 extop *e;
705 int32_t isize, osize, wsize;
706
707 isize = 0;
708 wsize = idata_bytes(instruction->opcode);
709
710 list_for_each(e, instruction->eops) {
711 int32_t align;
712
713 osize = 0;
714 if (e->type == EOT_DB_NUMBER) {
715 osize = 1;
716 warn_overflow_const(e->offset, wsize);
717 } else if (e->type == EOT_DB_STRING ||
718 e->type == EOT_DB_STRING_FREE)
719 osize = e->stringlen;
720
721 align = (-osize) % wsize;
722 if (align < 0)
723 align += wsize;
724 isize += osize + align;
725 }
726 return isize * instruction->times;
727 }
728
729 if (instruction->opcode == I_INCBIN) {
730 const char *fname = instruction->eops->stringval;
731 FILE *fp;
732 int64_t val = 0;
733 size_t len;
734
735 fp = fopen(fname, "rb");
736 if (!fp)
737 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
738 fname);
739 else if (fseek(fp, 0L, SEEK_END) < 0)
740 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
741 fname);
742 else {
743 len = ftell(fp);
744 if (instruction->eops->next) {
745 len -= instruction->eops->next->offset;
746 if (instruction->eops->next->next &&
747 len > (size_t)instruction->eops->next->next->offset) {
748 len = (size_t)instruction->eops->next->next->offset;
749 }
750 }
751 val = instruction->times * len;
752 }
753 if (fp)
754 fclose(fp);
755 return val;
756 }
757
758 /* Check to see if we need an address-size prefix */
759 add_asp(instruction, bits);
760
761 m = find_match(&temp, instruction, segment, offset, bits);
762 if (m == MOK_GOOD) {
763 /* we've matched an instruction. */
764 int64_t isize;
765 int j;
766
767 isize = calcsize(segment, offset, bits, instruction, temp);
768 if (isize < 0)
769 return -1;
770 for (j = 0; j < MAXPREFIX; j++) {
771 switch (instruction->prefixes[j]) {
772 case P_A16:
773 if (bits != 16)
774 isize++;
775 break;
776 case P_A32:
777 if (bits != 32)
778 isize++;
779 break;
780 case P_O16:
781 if (bits != 16)
782 isize++;
783 break;
784 case P_O32:
785 if (bits == 16)
786 isize++;
787 break;
788 case P_A64:
789 case P_O64:
790 case P_none:
791 break;
792 default:
793 isize++;
794 break;
795 }
796 }
797 return isize * instruction->times;
798 } else {
799 return -1; /* didn't match any instruction */
800 }
801 }
802
803 static void bad_hle_warn(const insn * ins, uint8_t hleok)
804 {
805 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
806 enum whatwarn { w_none, w_lock, w_inval } ww;
807 static const enum whatwarn warn[2][4] =
808 {
809 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
810 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
811 };
812 unsigned int n;
813
814 n = (unsigned int)rep_pfx - P_XACQUIRE;
815 if (n > 1)
816 return; /* Not XACQUIRE/XRELEASE */
817
818 ww = warn[n][hleok];
819 if (!is_class(MEMORY, ins->oprs[0].type))
820 ww = w_inval; /* HLE requires operand 0 to be memory */
821
822 switch (ww) {
823 case w_none:
824 break;
825
826 case w_lock:
827 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
828 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
829 "%s with this instruction requires lock",
830 prefix_name(rep_pfx));
831 }
832 break;
833
834 case w_inval:
835 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
836 "%s invalid with this instruction",
837 prefix_name(rep_pfx));
838 break;
839 }
840 }
841
842 /* Common construct */
843 #define case3(x) case (x): case (x)+1: case (x)+2
844 #define case4(x) case3(x): case (x)+3
845
846 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
847 insn * ins, const struct itemplate *temp)
848 {
849 const uint8_t *codes = temp->code;
850 int64_t length = 0;
851 uint8_t c;
852 int rex_mask = ~0;
853 int op1, op2;
854 struct operand *opx;
855 uint8_t opex = 0;
856 enum ea_type eat;
857 uint8_t hleok = 0;
858 bool lockcheck = true;
859 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
860
861 ins->rex = 0; /* Ensure REX is reset */
862 eat = EA_SCALAR; /* Expect a scalar EA */
863 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
864
865 if (ins->prefixes[PPS_OSIZE] == P_O64)
866 ins->rex |= REX_W;
867
868 (void)segment; /* Don't warn that this parameter is unused */
869 (void)offset; /* Don't warn that this parameter is unused */
870
871 while (*codes) {
872 c = *codes++;
873 op1 = (c & 3) + ((opex & 1) << 2);
874 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
875 opx = &ins->oprs[op1];
876 opex = 0; /* For the next iteration */
877
878 switch (c) {
879 case4(01):
880 codes += c, length += c;
881 break;
882
883 case3(05):
884 opex = c;
885 break;
886
887 case4(010):
888 ins->rex |=
889 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
890 codes++, length++;
891 break;
892
893 case4(014):
894 /* this is an index reg of MIB operand */
895 mib_index = opx->basereg;
896 break;
897
898 case4(020):
899 case4(024):
900 length++;
901 break;
902
903 case4(030):
904 length += 2;
905 break;
906
907 case4(034):
908 if (opx->type & (BITS16 | BITS32 | BITS64))
909 length += (opx->type & BITS16) ? 2 : 4;
910 else
911 length += (bits == 16) ? 2 : 4;
912 break;
913
914 case4(040):
915 length += 4;
916 break;
917
918 case4(044):
919 length += ins->addr_size >> 3;
920 break;
921
922 case4(050):
923 length++;
924 break;
925
926 case4(054):
927 length += 8; /* MOV reg64/imm */
928 break;
929
930 case4(060):
931 length += 2;
932 break;
933
934 case4(064):
935 if (opx->type & (BITS16 | BITS32 | BITS64))
936 length += (opx->type & BITS16) ? 2 : 4;
937 else
938 length += (bits == 16) ? 2 : 4;
939 break;
940
941 case4(070):
942 length += 4;
943 break;
944
945 case4(074):
946 length += 2;
947 break;
948
949 case 0172:
950 case 0173:
951 codes++;
952 length++;
953 break;
954
955 case4(0174):
956 length++;
957 break;
958
959 case4(0240):
960 ins->rex |= REX_EV;
961 ins->vexreg = regval(opx);
962 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
963 ins->vex_cm = *codes++;
964 ins->vex_wlp = *codes++;
965 ins->evex_tuple = (*codes++ - 0300);
966 break;
967
968 case 0250:
969 ins->rex |= REX_EV;
970 ins->vexreg = 0;
971 ins->vex_cm = *codes++;
972 ins->vex_wlp = *codes++;
973 ins->evex_tuple = (*codes++ - 0300);
974 break;
975
976 case4(0254):
977 length += 4;
978 break;
979
980 case4(0260):
981 ins->rex |= REX_V;
982 ins->vexreg = regval(opx);
983 ins->vex_cm = *codes++;
984 ins->vex_wlp = *codes++;
985 break;
986
987 case 0270:
988 ins->rex |= REX_V;
989 ins->vexreg = 0;
990 ins->vex_cm = *codes++;
991 ins->vex_wlp = *codes++;
992 break;
993
994 case3(0271):
995 hleok = c & 3;
996 break;
997
998 case4(0274):
999 length++;
1000 break;
1001
1002 case4(0300):
1003 break;
1004
1005 case 0310:
1006 if (bits == 64)
1007 return -1;
1008 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1009 break;
1010
1011 case 0311:
1012 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1013 break;
1014
1015 case 0312:
1016 break;
1017
1018 case 0313:
1019 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1020 has_prefix(ins, PPS_ASIZE, P_A32))
1021 return -1;
1022 break;
1023
1024 case4(0314):
1025 break;
1026
1027 case 0320:
1028 {
1029 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1030 if (pfx == P_O16)
1031 break;
1032 if (pfx != P_none)
1033 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1034 else
1035 ins->prefixes[PPS_OSIZE] = P_O16;
1036 break;
1037 }
1038
1039 case 0321:
1040 {
1041 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1042 if (pfx == P_O32)
1043 break;
1044 if (pfx != P_none)
1045 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1046 else
1047 ins->prefixes[PPS_OSIZE] = P_O32;
1048 break;
1049 }
1050
1051 case 0322:
1052 break;
1053
1054 case 0323:
1055 rex_mask &= ~REX_W;
1056 break;
1057
1058 case 0324:
1059 ins->rex |= REX_W;
1060 break;
1061
1062 case 0325:
1063 ins->rex |= REX_NH;
1064 break;
1065
1066 case 0326:
1067 break;
1068
1069 case 0330:
1070 codes++, length++;
1071 break;
1072
1073 case 0331:
1074 break;
1075
1076 case 0332:
1077 case 0333:
1078 length++;
1079 break;
1080
1081 case 0334:
1082 ins->rex |= REX_L;
1083 break;
1084
1085 case 0335:
1086 break;
1087
1088 case 0336:
1089 if (!ins->prefixes[PPS_REP])
1090 ins->prefixes[PPS_REP] = P_REP;
1091 break;
1092
1093 case 0337:
1094 if (!ins->prefixes[PPS_REP])
1095 ins->prefixes[PPS_REP] = P_REPNE;
1096 break;
1097
1098 case 0340:
1099 if (ins->oprs[0].segment != NO_SEG)
1100 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1101 " quantity of BSS space");
1102 else
1103 length += ins->oprs[0].offset;
1104 break;
1105
1106 case 0341:
1107 if (!ins->prefixes[PPS_WAIT])
1108 ins->prefixes[PPS_WAIT] = P_WAIT;
1109 break;
1110
1111 case 0360:
1112 break;
1113
1114 case 0361:
1115 length++;
1116 break;
1117
1118 case 0364:
1119 case 0365:
1120 break;
1121
1122 case 0366:
1123 case 0367:
1124 length++;
1125 break;
1126
1127 case3(0370):
1128 break;
1129
1130 case 0373:
1131 length++;
1132 break;
1133
1134 case 0374:
1135 eat = EA_XMMVSIB;
1136 break;
1137
1138 case 0375:
1139 eat = EA_YMMVSIB;
1140 break;
1141
1142 case 0376:
1143 eat = EA_ZMMVSIB;
1144 break;
1145
1146 case4(0100):
1147 case4(0110):
1148 case4(0120):
1149 case4(0130):
1150 case4(0200):
1151 case4(0204):
1152 case4(0210):
1153 case4(0214):
1154 case4(0220):
1155 case4(0224):
1156 case4(0230):
1157 case4(0234):
1158 {
1159 ea ea_data;
1160 int rfield;
1161 opflags_t rflags;
1162 struct operand *opy = &ins->oprs[op2];
1163 struct operand *op_er_sae;
1164
1165 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1166
1167 if (c <= 0177) {
1168 /* pick rfield from operand b (opx) */
1169 rflags = regflag(opx);
1170 rfield = nasm_regvals[opx->basereg];
1171 } else {
1172 rflags = 0;
1173 rfield = c & 7;
1174 }
1175
1176 /* EVEX.b1 : evex_brerop contains the operand position */
1177 op_er_sae = (ins->evex_brerop >= 0 ?
1178 &ins->oprs[ins->evex_brerop] : NULL);
1179
1180 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1181 /* set EVEX.b */
1182 ins->evex_p[2] |= EVEX_P2B;
1183 if (op_er_sae->decoflags & ER) {
1184 /* set EVEX.RC (rounding control) */
1185 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1186 & EVEX_P2RC;
1187 }
1188 } else {
1189 /* set EVEX.L'L (vector length) */
1190 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1191 if (opy->decoflags & BRDCAST_MASK) {
1192 /* set EVEX.b */
1193 ins->evex_p[2] |= EVEX_P2B;
1194 }
1195 }
1196
1197 /*
1198 * if a separate form of MIB (ICC style) is used,
1199 * the index reg info is merged into mem operand
1200 */
1201 if (mib_index != R_none) {
1202 opy->indexreg = mib_index;
1203 opy->scale = 1;
1204 opy->hintbase = mib_index;
1205 opy->hinttype = EAH_NOTBASE;
1206 }
1207
1208 if (process_ea(opy, &ea_data, bits,
1209 rfield, rflags, ins) != eat) {
1210 errfunc(ERR_NONFATAL, "invalid effective address");
1211 return -1;
1212 } else {
1213 ins->rex |= ea_data.rex;
1214 length += ea_data.size;
1215 }
1216 }
1217 break;
1218
1219 default:
1220 errfunc(ERR_PANIC, "internal instruction table corrupt"
1221 ": instruction code \\%o (0x%02X) given", c, c);
1222 break;
1223 }
1224 }
1225
1226 ins->rex &= rex_mask;
1227
1228 if (ins->rex & REX_NH) {
1229 if (ins->rex & REX_H) {
1230 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1231 return -1;
1232 }
1233 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1234 }
1235
1236 if (ins->rex & (REX_V | REX_EV)) {
1237 int bad32 = REX_R|REX_W|REX_X|REX_B;
1238
1239 if (ins->rex & REX_H) {
1240 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1241 return -1;
1242 }
1243 switch (ins->vex_wlp & 060) {
1244 case 000:
1245 case 040:
1246 ins->rex &= ~REX_W;
1247 break;
1248 case 020:
1249 ins->rex |= REX_W;
1250 bad32 &= ~REX_W;
1251 break;
1252 case 060:
1253 /* Follow REX_W */
1254 break;
1255 }
1256
1257 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1258 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1259 return -1;
1260 } else if (!(ins->rex & REX_EV) &&
1261 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1262 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1263 return -1;
1264 }
1265 if (ins->rex & REX_EV)
1266 length += 4;
1267 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1268 length += 3;
1269 else
1270 length += 2;
1271 } else if (ins->rex & REX_REAL) {
1272 if (ins->rex & REX_H) {
1273 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1274 return -1;
1275 } else if (bits == 64) {
1276 length++;
1277 } else if ((ins->rex & REX_L) &&
1278 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1279 cpu >= IF_X86_64) {
1280 /* LOCK-as-REX.R */
1281 assert_no_prefix(ins, PPS_LOCK);
1282 lockcheck = false; /* Already errored, no need for warning */
1283 length++;
1284 } else {
1285 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1286 return -1;
1287 }
1288 }
1289
1290 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1291 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1292 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1293 "instruction is not lockable");
1294 }
1295
1296 bad_hle_warn(ins, hleok);
1297
1298 return length;
1299 }
1300
1301 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1302 {
1303 if (bits == 64) {
1304 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1305 ins->rex = (ins->rex & REX_REAL) | REX_P;
1306 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1307 ins->rex = 0;
1308 return 1;
1309 }
1310 }
1311
1312 return 0;
1313 }
1314
1315 static void gencode(int32_t segment, int64_t offset, int bits,
1316 insn * ins, const struct itemplate *temp,
1317 int64_t insn_end)
1318 {
1319 uint8_t c;
1320 uint8_t bytes[4];
1321 int64_t size;
1322 int64_t data;
1323 int op1, op2;
1324 struct operand *opx;
1325 const uint8_t *codes = temp->code;
1326 uint8_t opex = 0;
1327 enum ea_type eat = EA_SCALAR;
1328
1329 while (*codes) {
1330 c = *codes++;
1331 op1 = (c & 3) + ((opex & 1) << 2);
1332 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1333 opx = &ins->oprs[op1];
1334 opex = 0; /* For the next iteration */
1335
1336 switch (c) {
1337 case 01:
1338 case 02:
1339 case 03:
1340 case 04:
1341 offset += emit_rex(ins, segment, offset, bits);
1342 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1343 codes += c;
1344 offset += c;
1345 break;
1346
1347 case 05:
1348 case 06:
1349 case 07:
1350 opex = c;
1351 break;
1352
1353 case4(010):
1354 offset += emit_rex(ins, segment, offset, bits);
1355 bytes[0] = *codes++ + (regval(opx) & 7);
1356 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1357 offset += 1;
1358 break;
1359
1360 case4(014):
1361 break;
1362
1363 case4(020):
1364 if (opx->offset < -256 || opx->offset > 255) {
1365 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1366 "byte value exceeds bounds");
1367 }
1368 out_imm8(offset, segment, opx);
1369 offset += 1;
1370 break;
1371
1372 case4(024):
1373 if (opx->offset < 0 || opx->offset > 255)
1374 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1375 "unsigned byte value exceeds bounds");
1376 out_imm8(offset, segment, opx);
1377 offset += 1;
1378 break;
1379
1380 case4(030):
1381 warn_overflow_opd(opx, 2);
1382 data = opx->offset;
1383 out(offset, segment, &data, OUT_ADDRESS, 2,
1384 opx->segment, opx->wrt);
1385 offset += 2;
1386 break;
1387
1388 case4(034):
1389 if (opx->type & (BITS16 | BITS32))
1390 size = (opx->type & BITS16) ? 2 : 4;
1391 else
1392 size = (bits == 16) ? 2 : 4;
1393 warn_overflow_opd(opx, size);
1394 data = opx->offset;
1395 out(offset, segment, &data, OUT_ADDRESS, size,
1396 opx->segment, opx->wrt);
1397 offset += size;
1398 break;
1399
1400 case4(040):
1401 warn_overflow_opd(opx, 4);
1402 data = opx->offset;
1403 out(offset, segment, &data, OUT_ADDRESS, 4,
1404 opx->segment, opx->wrt);
1405 offset += 4;
1406 break;
1407
1408 case4(044):
1409 data = opx->offset;
1410 size = ins->addr_size >> 3;
1411 warn_overflow_opd(opx, size);
1412 out(offset, segment, &data, OUT_ADDRESS, size,
1413 opx->segment, opx->wrt);
1414 offset += size;
1415 break;
1416
1417 case4(050):
1418 if (opx->segment != segment) {
1419 data = opx->offset;
1420 out(offset, segment, &data,
1421 OUT_REL1ADR, insn_end - offset,
1422 opx->segment, opx->wrt);
1423 } else {
1424 data = opx->offset - insn_end;
1425 if (data > 127 || data < -128)
1426 errfunc(ERR_NONFATAL, "short jump is out of range");
1427 out(offset, segment, &data,
1428 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1429 }
1430 offset += 1;
1431 break;
1432
1433 case4(054):
1434 data = (int64_t)opx->offset;
1435 out(offset, segment, &data, OUT_ADDRESS, 8,
1436 opx->segment, opx->wrt);
1437 offset += 8;
1438 break;
1439
1440 case4(060):
1441 if (opx->segment != segment) {
1442 data = opx->offset;
1443 out(offset, segment, &data,
1444 OUT_REL2ADR, insn_end - offset,
1445 opx->segment, opx->wrt);
1446 } else {
1447 data = opx->offset - insn_end;
1448 out(offset, segment, &data,
1449 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1450 }
1451 offset += 2;
1452 break;
1453
1454 case4(064):
1455 if (opx->type & (BITS16 | BITS32 | BITS64))
1456 size = (opx->type & BITS16) ? 2 : 4;
1457 else
1458 size = (bits == 16) ? 2 : 4;
1459 if (opx->segment != segment) {
1460 data = opx->offset;
1461 out(offset, segment, &data,
1462 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1463 insn_end - offset, opx->segment, opx->wrt);
1464 } else {
1465 data = opx->offset - insn_end;
1466 out(offset, segment, &data,
1467 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1468 }
1469 offset += size;
1470 break;
1471
1472 case4(070):
1473 if (opx->segment != segment) {
1474 data = opx->offset;
1475 out(offset, segment, &data,
1476 OUT_REL4ADR, insn_end - offset,
1477 opx->segment, opx->wrt);
1478 } else {
1479 data = opx->offset - insn_end;
1480 out(offset, segment, &data,
1481 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1482 }
1483 offset += 4;
1484 break;
1485
1486 case4(074):
1487 if (opx->segment == NO_SEG)
1488 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1489 " relocatable");
1490 data = 0;
1491 out(offset, segment, &data, OUT_ADDRESS, 2,
1492 outfmt->segbase(1 + opx->segment),
1493 opx->wrt);
1494 offset += 2;
1495 break;
1496
1497 case 0172:
1498 c = *codes++;
1499 opx = &ins->oprs[c >> 3];
1500 bytes[0] = nasm_regvals[opx->basereg] << 4;
1501 opx = &ins->oprs[c & 7];
1502 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1503 errfunc(ERR_NONFATAL,
1504 "non-absolute expression not permitted as argument %d",
1505 c & 7);
1506 } else {
1507 if (opx->offset & ~15) {
1508 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1509 "four-bit argument exceeds bounds");
1510 }
1511 bytes[0] |= opx->offset & 15;
1512 }
1513 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1514 offset++;
1515 break;
1516
1517 case 0173:
1518 c = *codes++;
1519 opx = &ins->oprs[c >> 4];
1520 bytes[0] = nasm_regvals[opx->basereg] << 4;
1521 bytes[0] |= c & 15;
1522 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1523 offset++;
1524 break;
1525
1526 case4(0174):
1527 bytes[0] = nasm_regvals[opx->basereg] << 4;
1528 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1529 offset++;
1530 break;
1531
1532 case4(0254):
1533 data = opx->offset;
1534 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1535 (int32_t)data != (int64_t)data) {
1536 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1537 "signed dword immediate exceeds bounds");
1538 }
1539 out(offset, segment, &data, OUT_ADDRESS, 4,
1540 opx->segment, opx->wrt);
1541 offset += 4;
1542 break;
1543
1544 case4(0240):
1545 case 0250:
1546 codes += 3;
1547 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1548 EVEX_P2Z | EVEX_P2AAA, 2);
1549 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1550 bytes[0] = 0x62;
1551 /* EVEX.X can be set by either REX or EVEX for different reasons */
1552 bytes[1] = (~(((ins->rex & 7) << 5) |
1553 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) & 0xf0) |
1554 (ins->vex_cm & 3);
1555 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1556 ((~ins->vexreg & 15) << 3) |
1557 (1 << 2) | (ins->vex_wlp & 3);
1558 bytes[3] = ins->evex_p[2];
1559 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1560 offset += 4;
1561 break;
1562
1563 case4(0260):
1564 case 0270:
1565 codes += 2;
1566 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1567 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1568 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1569 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1570 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1571 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1572 offset += 3;
1573 } else {
1574 bytes[0] = 0xc5;
1575 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1576 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1577 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1578 offset += 2;
1579 }
1580 break;
1581
1582 case 0271:
1583 case 0272:
1584 case 0273:
1585 break;
1586
1587 case4(0274):
1588 {
1589 uint64_t uv, um;
1590 int s;
1591
1592 if (ins->rex & REX_W)
1593 s = 64;
1594 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1595 s = 16;
1596 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1597 s = 32;
1598 else
1599 s = bits;
1600
1601 um = (uint64_t)2 << (s-1);
1602 uv = opx->offset;
1603
1604 if (uv > 127 && uv < (uint64_t)-128 &&
1605 (uv < um-128 || uv > um-1)) {
1606 /* If this wasn't explicitly byte-sized, warn as though we
1607 * had fallen through to the imm16/32/64 case.
1608 */
1609 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1610 "%s value exceeds bounds",
1611 (opx->type & BITS8) ? "signed byte" :
1612 s == 16 ? "word" :
1613 s == 32 ? "dword" :
1614 "signed dword");
1615 }
1616 if (opx->segment != NO_SEG) {
1617 data = uv;
1618 out(offset, segment, &data, OUT_ADDRESS, 1,
1619 opx->segment, opx->wrt);
1620 } else {
1621 bytes[0] = uv;
1622 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1623 NO_SEG);
1624 }
1625 offset += 1;
1626 break;
1627 }
1628
1629 case4(0300):
1630 break;
1631
1632 case 0310:
1633 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1634 *bytes = 0x67;
1635 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1636 offset += 1;
1637 } else
1638 offset += 0;
1639 break;
1640
1641 case 0311:
1642 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1643 *bytes = 0x67;
1644 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1645 offset += 1;
1646 } else
1647 offset += 0;
1648 break;
1649
1650 case 0312:
1651 break;
1652
1653 case 0313:
1654 ins->rex = 0;
1655 break;
1656
1657 case4(0314):
1658 break;
1659
1660 case 0320:
1661 case 0321:
1662 break;
1663
1664 case 0322:
1665 case 0323:
1666 break;
1667
1668 case 0324:
1669 ins->rex |= REX_W;
1670 break;
1671
1672 case 0325:
1673 break;
1674
1675 case 0326:
1676 break;
1677
1678 case 0330:
1679 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1680 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1681 offset += 1;
1682 break;
1683
1684 case 0331:
1685 break;
1686
1687 case 0332:
1688 case 0333:
1689 *bytes = c - 0332 + 0xF2;
1690 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1691 offset += 1;
1692 break;
1693
1694 case 0334:
1695 if (ins->rex & REX_R) {
1696 *bytes = 0xF0;
1697 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1698 offset += 1;
1699 }
1700 ins->rex &= ~(REX_L|REX_R);
1701 break;
1702
1703 case 0335:
1704 break;
1705
1706 case 0336:
1707 case 0337:
1708 break;
1709
1710 case 0340:
1711 if (ins->oprs[0].segment != NO_SEG)
1712 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1713 else {
1714 int64_t size = ins->oprs[0].offset;
1715 if (size > 0)
1716 out(offset, segment, NULL,
1717 OUT_RESERVE, size, NO_SEG, NO_SEG);
1718 offset += size;
1719 }
1720 break;
1721
1722 case 0341:
1723 break;
1724
1725 case 0360:
1726 break;
1727
1728 case 0361:
1729 bytes[0] = 0x66;
1730 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1731 offset += 1;
1732 break;
1733
1734 case 0364:
1735 case 0365:
1736 break;
1737
1738 case 0366:
1739 case 0367:
1740 *bytes = c - 0366 + 0x66;
1741 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1742 offset += 1;
1743 break;
1744
1745 case3(0370):
1746 break;
1747
1748 case 0373:
1749 *bytes = bits == 16 ? 3 : 5;
1750 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1751 offset += 1;
1752 break;
1753
1754 case 0374:
1755 eat = EA_XMMVSIB;
1756 break;
1757
1758 case 0375:
1759 eat = EA_YMMVSIB;
1760 break;
1761
1762 case 0376:
1763 eat = EA_ZMMVSIB;
1764 break;
1765
1766 case4(0100):
1767 case4(0110):
1768 case4(0120):
1769 case4(0130):
1770 case4(0200):
1771 case4(0204):
1772 case4(0210):
1773 case4(0214):
1774 case4(0220):
1775 case4(0224):
1776 case4(0230):
1777 case4(0234):
1778 {
1779 ea ea_data;
1780 int rfield;
1781 opflags_t rflags;
1782 uint8_t *p;
1783 int32_t s;
1784 struct operand *opy = &ins->oprs[op2];
1785
1786 if (c <= 0177) {
1787 /* pick rfield from operand b (opx) */
1788 rflags = regflag(opx);
1789 rfield = nasm_regvals[opx->basereg];
1790 } else {
1791 /* rfield is constant */
1792 rflags = 0;
1793 rfield = c & 7;
1794 }
1795
1796 if (process_ea(opy, &ea_data, bits,
1797 rfield, rflags, ins) != eat)
1798 errfunc(ERR_NONFATAL, "invalid effective address");
1799
1800 p = bytes;
1801 *p++ = ea_data.modrm;
1802 if (ea_data.sib_present)
1803 *p++ = ea_data.sib;
1804
1805 s = p - bytes;
1806 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1807
1808 /*
1809 * Make sure the address gets the right offset in case
1810 * the line breaks in the .lst file (BR 1197827)
1811 */
1812 offset += s;
1813 s = 0;
1814
1815 switch (ea_data.bytes) {
1816 case 0:
1817 break;
1818 case 1:
1819 case 2:
1820 case 4:
1821 case 8:
1822 /* use compressed displacement, if available */
1823 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1824 s += ea_data.bytes;
1825 if (ea_data.rip) {
1826 if (opy->segment == segment) {
1827 data -= insn_end;
1828 if (overflow_signed(data, ea_data.bytes))
1829 warn_overflow(ERR_PASS2, ea_data.bytes);
1830 out(offset, segment, &data, OUT_ADDRESS,
1831 ea_data.bytes, NO_SEG, NO_SEG);
1832 } else {
1833 /* overflow check in output/linker? */
1834 out(offset, segment, &data, OUT_REL4ADR,
1835 insn_end - offset, opy->segment, opy->wrt);
1836 }
1837 } else {
1838 if (overflow_general(data, ins->addr_size >> 3) ||
1839 signed_bits(data, ins->addr_size) !=
1840 signed_bits(data, ea_data.bytes * 8))
1841 warn_overflow(ERR_PASS2, ea_data.bytes);
1842
1843 out(offset, segment, &data, OUT_ADDRESS,
1844 ea_data.bytes, opy->segment, opy->wrt);
1845 }
1846 break;
1847 default:
1848 /* Impossible! */
1849 errfunc(ERR_PANIC,
1850 "Invalid amount of bytes (%d) for offset?!",
1851 ea_data.bytes);
1852 break;
1853 }
1854 offset += s;
1855 }
1856 break;
1857
1858 default:
1859 errfunc(ERR_PANIC, "internal instruction table corrupt"
1860 ": instruction code \\%o (0x%02X) given", c, c);
1861 break;
1862 }
1863 }
1864 }
1865
1866 static opflags_t regflag(const operand * o)
1867 {
1868 if (!is_register(o->basereg))
1869 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1870 return nasm_reg_flags[o->basereg];
1871 }
1872
1873 static int32_t regval(const operand * o)
1874 {
1875 if (!is_register(o->basereg))
1876 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1877 return nasm_regvals[o->basereg];
1878 }
1879
1880 static int op_rexflags(const operand * o, int mask)
1881 {
1882 opflags_t flags;
1883 int val;
1884
1885 if (!is_register(o->basereg))
1886 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1887
1888 flags = nasm_reg_flags[o->basereg];
1889 val = nasm_regvals[o->basereg];
1890
1891 return rexflags(val, flags, mask);
1892 }
1893
1894 static int rexflags(int val, opflags_t flags, int mask)
1895 {
1896 int rex = 0;
1897
1898 if (val >= 8)
1899 rex |= REX_B|REX_X|REX_R;
1900 if (flags & BITS64)
1901 rex |= REX_W;
1902 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1903 rex |= REX_H;
1904 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1905 rex |= REX_P;
1906
1907 return rex & mask;
1908 }
1909
1910 static int evexflags(int val, decoflags_t deco,
1911 int mask, uint8_t byte)
1912 {
1913 int evex = 0;
1914
1915 switch(byte) {
1916 case 0:
1917 if (val >= 16)
1918 evex |= (EVEX_P0RP | EVEX_P0X);
1919 break;
1920 case 2:
1921 if (val >= 16)
1922 evex |= EVEX_P2VP;
1923 if (deco & Z)
1924 evex |= EVEX_P2Z;
1925 if (deco & OPMASK_MASK)
1926 evex |= deco & EVEX_P2AAA;
1927 break;
1928 }
1929 return evex & mask;
1930 }
1931
1932 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1933 {
1934 int val;
1935
1936 if (!is_register(o->basereg))
1937 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1938
1939 val = nasm_regvals[o->basereg];
1940
1941 return evexflags(val, o->decoflags, mask, byte);
1942 }
1943
1944 static enum match_result find_match(const struct itemplate **tempp,
1945 insn *instruction,
1946 int32_t segment, int64_t offset, int bits)
1947 {
1948 const struct itemplate *temp;
1949 enum match_result m, merr;
1950 opflags_t xsizeflags[MAX_OPERANDS];
1951 bool opsizemissing = false;
1952 int8_t broadcast = instruction->evex_brerop;
1953 int i;
1954
1955 /* broadcasting uses a different data element size */
1956 for (i = 0; i < instruction->operands; i++)
1957 if (i == broadcast)
1958 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1959 else
1960 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1961
1962 merr = MERR_INVALOP;
1963
1964 for (temp = nasm_instructions[instruction->opcode];
1965 temp->opcode != I_none; temp++) {
1966 m = matches(temp, instruction, bits);
1967 if (m == MOK_JUMP) {
1968 if (jmp_match(segment, offset, bits, instruction, temp))
1969 m = MOK_GOOD;
1970 else
1971 m = MERR_INVALOP;
1972 } else if (m == MERR_OPSIZEMISSING &&
1973 (temp->flags & IF_SMASK) != IF_SX) {
1974 /*
1975 * Missing operand size and a candidate for fuzzy matching...
1976 */
1977 for (i = 0; i < temp->operands; i++)
1978 if (i == broadcast)
1979 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1980 else
1981 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1982 opsizemissing = true;
1983 }
1984 if (m > merr)
1985 merr = m;
1986 if (merr == MOK_GOOD)
1987 goto done;
1988 }
1989
1990 /* No match, but see if we can get a fuzzy operand size match... */
1991 if (!opsizemissing)
1992 goto done;
1993
1994 for (i = 0; i < instruction->operands; i++) {
1995 /*
1996 * We ignore extrinsic operand sizes on registers, so we should
1997 * never try to fuzzy-match on them. This also resolves the case
1998 * when we have e.g. "xmmrm128" in two different positions.
1999 */
2000 if (is_class(REGISTER, instruction->oprs[i].type))
2001 continue;
2002
2003 /* This tests if xsizeflags[i] has more than one bit set */
2004 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2005 goto done; /* No luck */
2006
2007 if (i == broadcast)
2008 instruction->oprs[i].decoflags |= xsizeflags[i];
2009 else
2010 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2011 }
2012
2013 /* Try matching again... */
2014 for (temp = nasm_instructions[instruction->opcode];
2015 temp->opcode != I_none; temp++) {
2016 m = matches(temp, instruction, bits);
2017 if (m == MOK_JUMP) {
2018 if (jmp_match(segment, offset, bits, instruction, temp))
2019 m = MOK_GOOD;
2020 else
2021 m = MERR_INVALOP;
2022 }
2023 if (m > merr)
2024 merr = m;
2025 if (merr == MOK_GOOD)
2026 goto done;
2027 }
2028
2029 done:
2030 *tempp = temp;
2031 return merr;
2032 }
2033
2034 static enum match_result matches(const struct itemplate *itemp,
2035 insn *instruction, int bits)
2036 {
2037 opflags_t size[MAX_OPERANDS], asize;
2038 bool opsizemissing = false;
2039 int i, oprs;
2040
2041 /*
2042 * Check the opcode
2043 */
2044 if (itemp->opcode != instruction->opcode)
2045 return MERR_INVALOP;
2046
2047 /*
2048 * Count the operands
2049 */
2050 if (itemp->operands != instruction->operands)
2051 return MERR_INVALOP;
2052
2053 /*
2054 * Is it legal?
2055 */
2056 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2057 return MERR_INVALOP;
2058
2059 /*
2060 * Check that no spurious colons or TOs are present
2061 */
2062 for (i = 0; i < itemp->operands; i++)
2063 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2064 return MERR_INVALOP;
2065
2066 /*
2067 * Process size flags
2068 */
2069 switch (itemp->flags & IF_SMASK) {
2070 case IF_SB:
2071 asize = BITS8;
2072 break;
2073 case IF_SW:
2074 asize = BITS16;
2075 break;
2076 case IF_SD:
2077 asize = BITS32;
2078 break;
2079 case IF_SQ:
2080 asize = BITS64;
2081 break;
2082 case IF_SO:
2083 asize = BITS128;
2084 break;
2085 case IF_SY:
2086 asize = BITS256;
2087 break;
2088 case IF_SZ:
2089 asize = BITS512;
2090 break;
2091 case IF_SIZE:
2092 switch (bits) {
2093 case 16:
2094 asize = BITS16;
2095 break;
2096 case 32:
2097 asize = BITS32;
2098 break;
2099 case 64:
2100 asize = BITS64;
2101 break;
2102 default:
2103 asize = 0;
2104 break;
2105 }
2106 break;
2107 default:
2108 asize = 0;
2109 break;
2110 }
2111
2112 if (itemp->flags & IF_ARMASK) {
2113 /* S- flags only apply to a specific operand */
2114 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2115 memset(size, 0, sizeof size);
2116 size[i] = asize;
2117 } else {
2118 /* S- flags apply to all operands */
2119 for (i = 0; i < MAX_OPERANDS; i++)
2120 size[i] = asize;
2121 }
2122
2123 /*
2124 * Check that the operand flags all match up,
2125 * it's a bit tricky so lets be verbose:
2126 *
2127 * 1) Find out the size of operand. If instruction
2128 * doesn't have one specified -- we're trying to
2129 * guess it either from template (IF_S* flag) or
2130 * from code bits.
2131 *
2132 * 2) If template operand do not match the instruction OR
2133 * template has an operand size specified AND this size differ
2134 * from which instruction has (perhaps we got it from code bits)
2135 * we are:
2136 * a) Check that only size of instruction and operand is differ
2137 * other characteristics do match
2138 * b) Perhaps it's a register specified in instruction so
2139 * for such a case we just mark that operand as "size
2140 * missing" and this will turn on fuzzy operand size
2141 * logic facility (handled by a caller)
2142 */
2143 for (i = 0; i < itemp->operands; i++) {
2144 opflags_t type = instruction->oprs[i].type;
2145 decoflags_t deco = instruction->oprs[i].decoflags;
2146 if (!(type & SIZE_MASK))
2147 type |= size[i];
2148
2149 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2150 (itemp->deco[i] & deco) != deco) {
2151 return MERR_INVALOP;
2152 } else if ((itemp->opd[i] & SIZE_MASK) &&
2153 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2154 if (type & SIZE_MASK) {
2155 /*
2156 * when broadcasting, the element size depends on
2157 * the instruction type. decorator flag should match.
2158 */
2159 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2160 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2161 if (!((deco & BRDCAST_MASK) &&
2162 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2163 return MERR_INVALOP;
2164 }
2165 } else if (!is_class(REGISTER, type)) {
2166 /*
2167 * Note: we don't honor extrinsic operand sizes for registers,
2168 * so "missing operand size" for a register should be
2169 * considered a wildcard match rather than an error.
2170 */
2171 opsizemissing = true;
2172 }
2173 } else if (is_register(instruction->oprs[i].basereg) &&
2174 nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2175 !(itemp->flags & IF_AVX512)) {
2176 return MERR_ENCMISMATCH;
2177 }
2178 }
2179
2180 if (opsizemissing)
2181 return MERR_OPSIZEMISSING;
2182
2183 /*
2184 * Check operand sizes
2185 */
2186 if (itemp->flags & (IF_SM | IF_SM2)) {
2187 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2188 for (i = 0; i < oprs; i++) {
2189 asize = itemp->opd[i] & SIZE_MASK;
2190 if (asize) {
2191 for (i = 0; i < oprs; i++)
2192 size[i] = asize;
2193 break;
2194 }
2195 }
2196 } else {
2197 oprs = itemp->operands;
2198 }
2199
2200 for (i = 0; i < itemp->operands; i++) {
2201 if (!(itemp->opd[i] & SIZE_MASK) &&
2202 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2203 return MERR_OPSIZEMISMATCH;
2204 }
2205
2206 /*
2207 * Check template is okay at the set cpu level
2208 */
2209 if (((itemp->flags & IF_PLEVEL) > cpu))
2210 return MERR_BADCPU;
2211
2212 /*
2213 * Verify the appropriate long mode flag.
2214 */
2215 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2216 return MERR_BADMODE;
2217
2218 /*
2219 * If we have a HLE prefix, look for the NOHLE flag
2220 */
2221 if ((itemp->flags & IF_NOHLE) &&
2222 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2223 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2224 return MERR_BADHLE;
2225
2226 /*
2227 * Check if special handling needed for Jumps
2228 */
2229 if ((itemp->code[0] & ~1) == 0370)
2230 return MOK_JUMP;
2231
2232 /*
2233 * Check if BND prefix is allowed
2234 */
2235 if ((itemp->code[0] != 0372) &&
2236 has_prefix(instruction, PPS_REP, P_BND))
2237 return MERR_BADBND;
2238
2239 return MOK_GOOD;
2240 }
2241
2242 /*
2243 * Check if offset is a multiple of N with corresponding tuple type
2244 * if Disp8*N is available, compressed displacement is stored in compdisp
2245 */
2246 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2247 {
2248 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2249 {{16, 32, 64}, {8, 8, 8}}};
2250 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2251 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2252
2253 bool evex_b = input->decoflags & BRDCAST_MASK;
2254 enum ttypes tuple = ins->evex_tuple;
2255 /* vex_wlp composed as [wwllpp] */
2256 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2257 /* wig(=2) is treated as w0(=0) */
2258 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2259 int32_t off = input->offset;
2260 uint8_t n = 0;
2261 int32_t disp8;
2262
2263 switch(tuple) {
2264 case FV:
2265 n = fv_n[evex_w][evex_b][vectlen];
2266 break;
2267 case HV:
2268 n = hv_n[evex_b][vectlen];
2269 break;
2270
2271 case FVM:
2272 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2273 n = 1 << (vectlen + 4);
2274 break;
2275 case T1S8: /* N = 1 */
2276 case T1S16: /* N = 2 */
2277 n = tuple - T1S8 + 1;
2278 break;
2279 case T1S:
2280 /* N = 4 for 32bit, 8 for 64bit */
2281 n = evex_w ? 8 : 4;
2282 break;
2283 case T1F32:
2284 case T1F64:
2285 /* N = 4 for 32bit, 8 for 64bit */
2286 n = (tuple == T1F32 ? 4 : 8);
2287 break;
2288 case T2:
2289 case T4:
2290 case T8:
2291 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2292 n = 0;
2293 else
2294 n = 1 << (tuple - T2 + evex_w + 3);
2295 break;
2296 case HVM:
2297 case QVM:
2298 case OVM:
2299 n = 1 << (OVM - tuple + vectlen + 1);
2300 break;
2301 case M128:
2302 n = 16;
2303 break;
2304 case DUP:
2305 n = dup_n[vectlen];
2306 break;
2307
2308 default:
2309 break;
2310 }
2311
2312 if (n && !(off & (n - 1))) {
2313 disp8 = off / n;
2314 /* if it fits in Disp8 */
2315 if (disp8 >= -128 && disp8 <= 127) {
2316 *compdisp = disp8;
2317 return true;
2318 }
2319 }
2320
2321 *compdisp = 0;
2322 return false;
2323 }
2324
2325 /*
2326 * Check if ModR/M.mod should/can be 01.
2327 * - EAF_BYTEOFFS is set
2328 * - offset can fit in a byte when EVEX is not used
2329 * - offset can be compressed when EVEX is used
2330 */
2331 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2332 (o >= -128 && o <= 127 && \
2333 seg == NO_SEG && !forw_ref && \
2334 !(input->eaflags & EAF_WORDOFFS) && \
2335 !(ins->rex & REX_EV)) || \
2336 (ins->rex & REX_EV && \
2337 is_disp8n(input, ins, &output->disp8)))
2338
2339 static enum ea_type process_ea(operand *input, ea *output, int bits,
2340 int rfield, opflags_t rflags, insn *ins)
2341 {
2342 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2343 int addrbits = ins->addr_size;
2344
2345 output->type = EA_SCALAR;
2346 output->rip = false;
2347 output->disp8 = 0;
2348
2349 /* REX flags for the rfield operand */
2350 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2351 /* EVEX.R' flag for the REG operand */
2352 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2353
2354 if (is_class(REGISTER, input->type)) {
2355 /*
2356 * It's a direct register.
2357 */
2358 if (!is_register(input->basereg))
2359 goto err;
2360
2361 if (!is_reg_class(REG_EA, input->basereg))
2362 goto err;
2363
2364 /* broadcasting is not available with a direct register operand. */
2365 if (input->decoflags & BRDCAST_MASK) {
2366 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2367 goto err;
2368 }
2369
2370 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2371 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2372 output->sib_present = false; /* no SIB necessary */
2373 output->bytes = 0; /* no offset necessary either */
2374 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2375 } else {
2376 /*
2377 * It's a memory reference.
2378 */
2379
2380 /* Embedded rounding or SAE is not available with a mem ref operand. */
2381 if (input->decoflags & (ER | SAE)) {
2382 nasm_error(ERR_NONFATAL,
2383 "Embedded rounding is available only with reg-reg op.");
2384 return -1;
2385 }
2386
2387 if (input->basereg == -1 &&
2388 (input->indexreg == -1 || input->scale == 0)) {
2389 /*
2390 * It's a pure offset.
2391 */
2392 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2393 input->segment == NO_SEG) {
2394 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2395 input->type &= ~IP_REL;
2396 input->type |= MEMORY;
2397 }
2398
2399 if (input->eaflags & EAF_BYTEOFFS ||
2400 (input->eaflags & EAF_WORDOFFS &&
2401 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2402 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2403 }
2404
2405 if (bits == 64 && (~input->type & IP_REL)) {
2406 output->sib_present = true;
2407 output->sib = GEN_SIB(0, 4, 5);
2408 output->bytes = 4;
2409 output->modrm = GEN_MODRM(0, rfield, 4);
2410 output->rip = false;
2411 } else {
2412 output->sib_present = false;
2413 output->bytes = (addrbits != 16 ? 4 : 2);
2414 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2415 output->rip = bits == 64;
2416 }
2417 } else {
2418 /*
2419 * It's an indirection.
2420 */
2421 int i = input->indexreg, b = input->basereg, s = input->scale;
2422 int32_t seg = input->segment;
2423 int hb = input->hintbase, ht = input->hinttype;
2424 int t, it, bt; /* register numbers */
2425 opflags_t x, ix, bx; /* register flags */
2426
2427 if (s == 0)
2428 i = -1; /* make this easy, at least */
2429
2430 if (is_register(i)) {
2431 it = nasm_regvals[i];
2432 ix = nasm_reg_flags[i];
2433 } else {
2434 it = -1;
2435 ix = 0;
2436 }
2437
2438 if (is_register(b)) {
2439 bt = nasm_regvals[b];
2440 bx = nasm_reg_flags[b];
2441 } else {
2442 bt = -1;
2443 bx = 0;
2444 }
2445
2446 /* if either one are a vector register... */
2447 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2448 opflags_t sok = BITS32 | BITS64;
2449 int32_t o = input->offset;
2450 int mod, scale, index, base;
2451
2452 /*
2453 * For a vector SIB, one has to be a vector and the other,
2454 * if present, a GPR. The vector must be the index operand.
2455 */
2456 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2457 if (s == 0)
2458 s = 1;
2459 else if (s != 1)
2460 goto err;
2461
2462 t = bt, bt = it, it = t;
2463 x = bx, bx = ix, ix = x;
2464 }
2465
2466 if (bt != -1) {
2467 if (REG_GPR & ~bx)
2468 goto err;
2469 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2470 sok &= bx;
2471 else
2472 goto err;
2473 }
2474
2475 /*
2476 * While we're here, ensure the user didn't specify
2477 * WORD or QWORD
2478 */
2479 if (input->disp_size == 16 || input->disp_size == 64)
2480 goto err;
2481
2482 if (addrbits == 16 ||
2483 (addrbits == 32 && !(sok & BITS32)) ||
2484 (addrbits == 64 && !(sok & BITS64)))
2485 goto err;
2486
2487 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2488 : ((ix & YMMREG & ~REG_EA)
2489 ? EA_YMMVSIB : EA_XMMVSIB));
2490
2491 output->rex |= rexflags(it, ix, REX_X);
2492 output->rex |= rexflags(bt, bx, REX_B);
2493 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2494
2495 index = it & 7; /* it is known to be != -1 */
2496
2497 switch (s) {
2498 case 1:
2499 scale = 0;
2500 break;
2501 case 2:
2502 scale = 1;
2503 break;
2504 case 4:
2505 scale = 2;
2506 break;
2507 case 8:
2508 scale = 3;
2509 break;
2510 default: /* then what the smeg is it? */
2511 goto err; /* panic */
2512 }
2513
2514 if (bt == -1) {
2515 base = 5;
2516 mod = 0;
2517 } else {
2518 base = (bt & 7);
2519 if (base != REG_NUM_EBP && o == 0 &&
2520 seg == NO_SEG && !forw_ref &&
2521 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2522 mod = 0;
2523 else if (IS_MOD_01())
2524 mod = 1;
2525 else
2526 mod = 2;
2527 }
2528
2529 output->sib_present = true;
2530 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2531 output->modrm = GEN_MODRM(mod, rfield, 4);
2532 output->sib = GEN_SIB(scale, index, base);
2533 } else if ((ix|bx) & (BITS32|BITS64)) {
2534 /*
2535 * it must be a 32/64-bit memory reference. Firstly we have
2536 * to check that all registers involved are type E/Rxx.
2537 */
2538 opflags_t sok = BITS32 | BITS64;
2539 int32_t o = input->offset;
2540
2541 if (it != -1) {
2542 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2543 sok &= ix;
2544 else
2545 goto err;
2546 }
2547
2548 if (bt != -1) {
2549 if (REG_GPR & ~bx)
2550 goto err; /* Invalid register */
2551 if (~sok & bx & SIZE_MASK)
2552 goto err; /* Invalid size */
2553 sok &= bx;
2554 }
2555
2556 /*
2557 * While we're here, ensure the user didn't specify
2558 * WORD or QWORD
2559 */
2560 if (input->disp_size == 16 || input->disp_size == 64)
2561 goto err;
2562
2563 if (addrbits == 16 ||
2564 (addrbits == 32 && !(sok & BITS32)) ||
2565 (addrbits == 64 && !(sok & BITS64)))
2566 goto err;
2567
2568 /* now reorganize base/index */
2569 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2570 ((hb == b && ht == EAH_NOTBASE) ||
2571 (hb == i && ht == EAH_MAKEBASE))) {
2572 /* swap if hints say so */
2573 t = bt, bt = it, it = t;
2574 x = bx, bx = ix, ix = x;
2575 }
2576 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2577 bt = -1, bx = 0, s++;
2578 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2579 /* make single reg base, unless hint */
2580 bt = it, bx = ix, it = -1, ix = 0;
2581 }
2582 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2583 s == 3 || s == 5 || s == 9) && bt == -1)
2584 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2585 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2586 (input->eaflags & EAF_TIMESTWO))
2587 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2588 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2589 if (s == 1 && it == REG_NUM_ESP) {
2590 /* swap ESP into base if scale is 1 */
2591 t = it, it = bt, bt = t;
2592 x = ix, ix = bx, bx = x;
2593 }
2594 if (it == REG_NUM_ESP ||
2595 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2596 goto err; /* wrong, for various reasons */
2597
2598 output->rex |= rexflags(it, ix, REX_X);
2599 output->rex |= rexflags(bt, bx, REX_B);
2600
2601 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2602 /* no SIB needed */
2603 int mod, rm;
2604
2605 if (bt == -1) {
2606 rm = 5;
2607 mod = 0;
2608 } else {
2609 rm = (bt & 7);
2610 if (rm != REG_NUM_EBP && o == 0 &&
2611 seg == NO_SEG && !forw_ref &&
2612 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2613 mod = 0;
2614 else if (IS_MOD_01())
2615 mod = 1;
2616 else
2617 mod = 2;
2618 }
2619
2620 output->sib_present = false;
2621 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2622 output->modrm = GEN_MODRM(mod, rfield, rm);
2623 } else {
2624 /* we need a SIB */
2625 int mod, scale, index, base;
2626
2627 if (it == -1)
2628 index = 4, s = 1;
2629 else
2630 index = (it & 7);
2631
2632 switch (s) {
2633 case 1:
2634 scale = 0;
2635 break;
2636 case 2:
2637 scale = 1;
2638 break;
2639 case 4:
2640 scale = 2;
2641 break;
2642 case 8:
2643 scale = 3;
2644 break;
2645 default: /* then what the smeg is it? */
2646 goto err; /* panic */
2647 }
2648
2649 if (bt == -1) {
2650 base = 5;
2651 mod = 0;
2652 } else {
2653 base = (bt & 7);
2654 if (base != REG_NUM_EBP && o == 0 &&
2655 seg == NO_SEG && !forw_ref &&
2656 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2657 mod = 0;
2658 else if (IS_MOD_01())
2659 mod = 1;
2660 else
2661 mod = 2;
2662 }
2663
2664 output->sib_present = true;
2665 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2666 output->modrm = GEN_MODRM(mod, rfield, 4);
2667 output->sib = GEN_SIB(scale, index, base);
2668 }
2669 } else { /* it's 16-bit */
2670 int mod, rm;
2671 int16_t o = input->offset;
2672
2673 /* check for 64-bit long mode */
2674 if (addrbits == 64)
2675 goto err;
2676
2677 /* check all registers are BX, BP, SI or DI */
2678 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2679 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2680 goto err;
2681
2682 /* ensure the user didn't specify DWORD/QWORD */
2683 if (input->disp_size == 32 || input->disp_size == 64)
2684 goto err;
2685
2686 if (s != 1 && i != -1)
2687 goto err; /* no can do, in 16-bit EA */
2688 if (b == -1 && i != -1) {
2689 int tmp = b;
2690 b = i;
2691 i = tmp;
2692 } /* swap */
2693 if ((b == R_SI || b == R_DI) && i != -1) {
2694 int tmp = b;
2695 b = i;
2696 i = tmp;
2697 }
2698 /* have BX/BP as base, SI/DI index */
2699 if (b == i)
2700 goto err; /* shouldn't ever happen, in theory */
2701 if (i != -1 && b != -1 &&
2702 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2703 goto err; /* invalid combinations */
2704 if (b == -1) /* pure offset: handled above */
2705 goto err; /* so if it gets to here, panic! */
2706
2707 rm = -1;
2708 if (i != -1)
2709 switch (i * 256 + b) {
2710 case R_SI * 256 + R_BX:
2711 rm = 0;
2712 break;
2713 case R_DI * 256 + R_BX:
2714 rm = 1;
2715 break;
2716 case R_SI * 256 + R_BP:
2717 rm = 2;
2718 break;
2719 case R_DI * 256 + R_BP:
2720 rm = 3;
2721 break;
2722 } else
2723 switch (b) {
2724 case R_SI:
2725 rm = 4;
2726 break;
2727 case R_DI:
2728 rm = 5;
2729 break;
2730 case R_BP:
2731 rm = 6;
2732 break;
2733 case R_BX:
2734 rm = 7;
2735 break;
2736 }
2737 if (rm == -1) /* can't happen, in theory */
2738 goto err; /* so panic if it does */
2739
2740 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2741 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2742 mod = 0;
2743 else if (IS_MOD_01())
2744 mod = 1;
2745 else
2746 mod = 2;
2747
2748 output->sib_present = false; /* no SIB - it's 16-bit */
2749 output->bytes = mod; /* bytes of offset needed */
2750 output->modrm = GEN_MODRM(mod, rfield, rm);
2751 }
2752 }
2753 }
2754
2755 output->size = 1 + output->sib_present + output->bytes;
2756 return output->type;
2757
2758 err:
2759 return output->type = EA_INVALID;
2760 }
2761
2762 static void add_asp(insn *ins, int addrbits)
2763 {
2764 int j, valid;
2765 int defdisp;
2766
2767 valid = (addrbits == 64) ? 64|32 : 32|16;
2768
2769 switch (ins->prefixes[PPS_ASIZE]) {
2770 case P_A16:
2771 valid &= 16;
2772 break;
2773 case P_A32:
2774 valid &= 32;
2775 break;
2776 case P_A64:
2777 valid &= 64;
2778 break;
2779 case P_ASP:
2780 valid &= (addrbits == 32) ? 16 : 32;
2781 break;
2782 default:
2783 break;
2784 }
2785
2786 for (j = 0; j < ins->operands; j++) {
2787 if (is_class(MEMORY, ins->oprs[j].type)) {
2788 opflags_t i, b;
2789
2790 /* Verify as Register */
2791 if (!is_register(ins->oprs[j].indexreg))
2792 i = 0;
2793 else
2794 i = nasm_reg_flags[ins->oprs[j].indexreg];
2795
2796 /* Verify as Register */
2797 if (!is_register(ins->oprs[j].basereg))
2798 b = 0;
2799 else
2800 b = nasm_reg_flags[ins->oprs[j].basereg];
2801
2802 if (ins->oprs[j].scale == 0)
2803 i = 0;
2804
2805 if (!i && !b) {
2806 int ds = ins->oprs[j].disp_size;
2807 if ((addrbits != 64 && ds > 8) ||
2808 (addrbits == 64 && ds == 16))
2809 valid &= ds;
2810 } else {
2811 if (!(REG16 & ~b))
2812 valid &= 16;
2813 if (!(REG32 & ~b))
2814 valid &= 32;
2815 if (!(REG64 & ~b))
2816 valid &= 64;
2817
2818 if (!(REG16 & ~i))
2819 valid &= 16;
2820 if (!(REG32 & ~i))
2821 valid &= 32;
2822 if (!(REG64 & ~i))
2823 valid &= 64;
2824 }
2825 }
2826 }
2827
2828 if (valid & addrbits) {
2829 ins->addr_size = addrbits;
2830 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2831 /* Add an address size prefix */
2832 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2833 ins->addr_size = (addrbits == 32) ? 16 : 32;
2834 } else {
2835 /* Impossible... */
2836 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2837 ins->addr_size = addrbits; /* Error recovery */
2838 }
2839
2840 defdisp = ins->addr_size == 16 ? 16 : 32;
2841
2842 for (j = 0; j < ins->operands; j++) {
2843 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2844 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2845 /*
2846 * mem_offs sizes must match the address size; if not,
2847 * strip the MEM_OFFS bit and match only EA instructions
2848 */
2849 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2850 }
2851 }
2852 }
Adding AVX-512 features