insns.h

   1 /* insns.h   header file for insns.c
   2  *
   3  * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
   4  * Julian Hall. All rights reserved. The software is
   5  * redistributable under the license given in the file "LICENSE"
   6  * distributed in the NASM archive.
   7  */
   8
   9 #ifndef NASM_INSNS_H
  10 #define NASM_INSNS_H
  11
  12 #include "nasm.h"
  13 #include "tokens.h"
  14
  15 /* if changed, ITEMPLATE_END should be also changed accordingly */
  16 struct itemplate {
  17     enum opcode     opcode;             /* the token, passed from "parser.c" */
  18     int             operands;           /* number of operands */
  19     opflags_t       opd[MAX_OPERANDS];  /* bit flags for operand types */
  20     decoflags_t     deco[MAX_OPERANDS]; /* bit flags for operand decorators */
  21     const uint8_t   *code;              /* the code it assembles to */
  22     iflags_t        flags;              /* some flags */
  23 };
  24
  25 /* Disassembler table structure */
  26
  27 /*
  28  * If n == -1, then p points to another table of 256
  29  * struct disasm_index, otherwise p points to a list of n
  30  * struct itemplates to consider.
  31  */
  32 struct disasm_index {
  33     const void *p;
  34     int n;
  35 };
  36
  37 /* Tables for the assembler and disassembler, respectively */
  38 extern const struct itemplate * const nasm_instructions[];
  39 extern const struct disasm_index itable[256];
  40 extern const struct disasm_index * const itable_vex[NASM_VEX_CLASSES][32][4];
  41
  42 /* Common table for the byte codes */
  43 extern const uint8_t nasm_bytecodes[];
  44
  45 /*
  46  * this define is used to signify the end of an itemplate
  47  */
  48 #define ITEMPLATE_END {-1,-1,{-1,-1,-1,-1,-1},{-1,-1,-1,-1,-1},NULL,0}
  49
  50 /*
  51  * Instruction template flags. These specify which processor
  52  * targets the instruction is eligible for, whether it is
  53  * privileged or undocumented, and also specify extra error
  54  * checking on the matching of the instruction.
  55  *
  56  * IF_SM stands for Size Match: any operand whose size is not
  57  * explicitly specified by the template is `really' intended to be
  58  * the same size as the first size-specified operand.
  59  * Non-specification is tolerated in the input instruction, but
  60  * _wrong_ specification is not.
  61  *
  62  * IF_SM2 invokes Size Match on only the first _two_ operands, for
  63  * three-operand instructions such as SHLD: it implies that the
  64  * first two operands must match in size, but that the third is
  65  * required to be _unspecified_.
  66  *
  67  * IF_SB invokes Size Byte: operands with unspecified size in the
  68  * template are really bytes, and so no non-byte specification in
  69  * the input instruction will be tolerated. IF_SW similarly invokes
  70  * Size Word, and IF_SD invokes Size Doubleword.
  71  *
  72  * (The default state if neither IF_SM nor IF_SM2 is specified is
  73  * that any operand with unspecified size in the template is
  74  * required to have unspecified size in the instruction too...)
  75  *
  76  * iflags_t is defined to store these flags.
  77  */
  78
  79 #define IF_SM           0x00000001UL    /* size match */
  80 #define IF_SM2          0x00000002UL    /* size match first two operands */
  81 #define IF_SB           0x00000004UL    /* unsized operands can't be non-byte */
  82 #define IF_SW           0x00000008UL    /* unsized operands can't be non-word */
  83 #define IF_SD           0x0000000CUL    /* unsized operands can't be non-dword */
  84 #define IF_SQ           0x00000010UL    /* unsized operands can't be non-qword */
  85 #define IF_SO           0x00000014UL    /* unsized operands can't be non-oword */
  86 #define IF_SY           0x00000018UL    /* unsized operands can't be non-yword */
  87 #define IF_SZ           0x0000001CUL    /* unsized operands can't be non-zword */
  88 #define IF_SIZE         0x00000038UL    /* unsized operands must match the bitsize */
  89 #define IF_SX           0x0000003CUL    /* unsized operands not allowed */
  90 #define IF_SMASK        0x0000003CUL    /* mask for unsized argument size */
  91 #define IF_AR0          0x00000040UL    /* SB, SW, SD applies to argument 0 */
  92 #define IF_AR1          0x00000080UL    /* SB, SW, SD applies to argument 1 */
  93 #define IF_AR2          0x000000C0UL    /* SB, SW, SD applies to argument 2 */
  94 #define IF_AR3          0x00000100UL    /* SB, SW, SD applies to argument 3 */
  95 #define IF_AR4          0x00000140UL    /* SB, SW, SD applies to argument 4 */
  96 #define IF_ARMASK       0x000001C0UL    /* mask for unsized argument spec */
  97 #define IF_ARSHFT       6               /* LSB in IF_ARMASK */
  98 #define IF_OPT          0x00000200UL    /* optimizing assembly only */
  99 /* The next 3 bits aren't actually used for anything */
 100 #define IF_PRIV         0x00000000UL    /* it's a privileged instruction */
 101 #define IF_SMM          0x00000000UL    /* it's only valid in SMM */
 102 #define IF_PROT         0x00000000UL    /* it's protected mode only */
 103 #define IF_LOCK         0x00000400UL    /* lockable if operand 0 is memory */
 104 #define IF_NOLONG       0x00000800UL    /* it's not available in long mode */
 105 #define IF_LONG         0x00001000UL    /* long mode instruction */
 106 #define IF_NOHLE        0x00002000UL    /* HLE prefixes forbidden */
 107 #define IF_MIB          0x00004000UL    /* Disassemble with split EA */
 108 /* These flags are currently not used for anything - intended for insn set */
 109 #define IF_UNDOC        0x8000000000UL    /* it's an undocumented instruction */
 110 #define IF_HLE          0x4000000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 111 #define IF_AVX512       0x2000000000UL    /* it's an AVX-512F (512b) instruction */
 112 #define IF_FPU          0x0100000000UL    /* it's an FPU instruction */
 113 #define IF_MMX          0x0200000000UL    /* it's an MMX instruction */
 114 #define IF_3DNOW        0x0300000000UL    /* it's a 3DNow! instruction */
 115 #define IF_SSE          0x0400000000UL    /* it's a SSE (KNI, MMX2) instruction */
 116 #define IF_SSE2         0x0500000000UL    /* it's a SSE2 instruction */
 117 #define IF_SSE3         0x0600000000UL    /* it's a SSE3 (PNI) instruction */
 118 #define IF_VMX          0x0700000000UL    /* it's a VMX instruction */
 119 #define IF_SSSE3        0x0800000000UL    /* it's an SSSE3 instruction */
 120 #define IF_SSE4A        0x0900000000UL    /* AMD SSE4a */
 121 #define IF_SSE41        0x0A00000000UL    /* it's an SSE4.1 instruction */
 122 #define IF_SSE42        0x0B00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 123 #define IF_SSE5         0x0C00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 124 #define IF_AVX          0x0D00000000UL    /* it's an AVX     (128b) instruction */
 125 #define IF_AVX2         0x0E00000000UL    /* it's an AVX2    (256b) instruction */
 126 #define IF_FMA          0x1000000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 127 #define IF_BMI1         0x1100000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 128 #define IF_BMI2         0x1200000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 129 #define IF_TBM          0x1300000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 130 #define IF_RTM          0x1400000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 131 #define IF_INVPCID      0x1500000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 132 #define IF_AVX512CD     (0x1600000000UL|IF_AVX512) /* AVX-512 Conflict Detection insns */
 133 #define IF_AVX512ER     (0x1700000000UL|IF_AVX512) /* AVX-512 Exponential and Reciprocal */
 134 #define IF_AVX512PF     (0x1800000000UL|IF_AVX512) /* AVX-512 Prefetch instructions */
 135 #define IF_MPX          0x1900000000UL    /* MPX instructions */
 136 #define IF_SHA          0x1A00000000UL    /* SHA instructions */
 137 #define IF_INSMASK      0xFF00000000UL    /* the mask for instruction set types */
 138 #define IF_PMASK        0xFF000000UL    /* the mask for processor types */
 139 #define IF_PLEVEL       0x0F000000UL    /* the mask for processor instr. level */
 140                                         /* also the highest possible processor */
 141 #define IF_8086         0x00000000UL    /* 8086 instruction */
 142 #define IF_186          0x01000000UL    /* 186+ instruction */
 143 #define IF_286          0x02000000UL    /* 286+ instruction */
 144 #define IF_386          0x03000000UL    /* 386+ instruction */
 145 #define IF_486          0x04000000UL    /* 486+ instruction */
 146 #define IF_PENT         0x05000000UL    /* Pentium instruction */
 147 #define IF_P6           0x06000000UL    /* P6 instruction */
 148 #define IF_KATMAI       0x07000000UL    /* Katmai instructions */
 149 #define IF_WILLAMETTE   0x08000000UL    /* Willamette instructions */
 150 #define IF_PRESCOTT     0x09000000UL    /* Prescott instructions */
 151 #define IF_X86_64       0x0A000000UL    /* x86-64 instruction (long or legacy mode) */
 152 #define IF_NEHALEM      0x0B000000UL    /* Nehalem instruction */
 153 #define IF_WESTMERE     0x0C000000UL    /* Westmere instruction */
 154 #define IF_SANDYBRIDGE  0x0D000000UL    /* Sandy Bridge instruction */
 155 #define IF_FUTURE       0x0E000000UL    /* Future processor (not yet disclosed) */
 156 #define IF_X64          (IF_LONG|IF_X86_64)
 157 #define IF_IA64         0x0F000000UL    /* IA64 instructions (in x86 mode) */
 158 #define IF_CYRIX        0x10000000UL    /* Cyrix-specific instruction */
 159 #define IF_AMD          0x20000000UL    /* AMD-specific instruction */
 160 #define IF_SPMASK       0x30000000UL    /* specific processor types mask */
 161 #define IF_PFMASK       (IF_INSMASK|IF_SPMASK) /* disassembly "prefer" mask */
 162
 163 #endif /* NASM_INSNS_H */