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Version 0.99.03
[nasm/avx512.git] / assemble.c
blobefb022072ea3aafdd4b3369dca46adec4c0150b1
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on assembly mode or the address-size override
26 * on the operand.
27 * \50..\53 - a byte relative operand, from operand 0..3
28 * \54..\57 - a qword immediate operand, from operand 0..3
29 * \60..\63 - a word relative operand, from operand 0..3
30 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
31 * assembly mode or the operand-size override on the operand
32 * \70..\73 - a long relative operand, from operand 0..3
33 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
34 * \1ab - a ModRM, calculated on EA in operand a, with the spare
35 * field the register value of operand b.
36 * \140..\143 - an immediate word or signed byte for operand 0..3
37 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
38 * is a signed byte rather than a word.
39 * \150..\153 - an immediate dword or signed byte for operand 0..3
40 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
41 * is a signed byte rather than a dword.
42 * \160..\163 - this instruction uses DREX rather than REX, with the
43 * OC0 field set to 0, and the dest field taken from
44 * operand 0..3.
45 * \164..\167 - this instruction uses DREX rather than REX, with the
46 * OC0 field set to 1, and the dest field taken from
47 * operand 0..3.
48 * \170 - encodes the literal byte 0. (Some compilers don't take
49 * kindly to a zero byte in the _middle_ of a compile time
50 * string constant, so I had to put this hack in.)
51 * \171 - placement of DREX suffix in the absence of an EA
52 * \2ab - a ModRM, calculated on EA in operand a, with the spare
53 * field equal to digit b.
54 * \30x - might be an 0x67 byte, depending on the address size of
55 * the memory reference in operand x.
56 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
57 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
58 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
59 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
60 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
61 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
62 * \322 - indicates that this instruction is only valid when the
63 * operand size is the default (instruction to disassembler,
64 * generates no code in the assembler)
65 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
66 * \324 - indicates 64-bit operand size requiring REX prefix.
67 * \330 - a literal byte follows in the code stream, to be added
68 * to the condition code value of the instruction.
69 * \331 - instruction not valid with REP prefix. Hint for
70 * disassembler only; for SSE instructions.
71 * \332 - REP prefix (0xF2 byte) used as opcode extension.
72 * \333 - REP prefix (0xF3 byte) used as opcode extension.
73 * \334 - LOCK prefix used instead of REX.R
74 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
75 * \340 - reserve <operand 0> bytes of uninitialized storage.
76 * Operand 0 had better be a segmentless constant.
77 * \364 - operand-size prefix (0x66) not permitted
78 * \365 - address-size prefix (0x67) not permitted
79 * \366 - operand-size prefix (0x66) used as opcode extension
80 * \367 - address-size prefix (0x67) used as opcode extension
81 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
82 * 370 is used for Jcc, 371 is used for JMP.
83 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
84 * used for conditional jump over longer jump
85 */
86
87 #include <stdio.h>
88 #include <string.h>
89 #include <inttypes.h>
90
91 #include "nasm.h"
92 #include "nasmlib.h"
93 #include "assemble.h"
94 #include "insns.h"
95 #include "preproc.h"
96 #include "regflags.c"
97 #include "regvals.c"
98
99 typedef struct {
100 int sib_present; /* is a SIB byte necessary? */
101 int bytes; /* # of bytes of offset needed */
102 int size; /* lazy - this is sib+bytes+1 */
103 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
104 } ea;
105
106 static uint32_t cpu; /* cpu level received from nasm.c */
107 static efunc errfunc;
108 static struct ofmt *outfmt;
109 static ListGen *list;
110
111 static int32_t calcsize(int32_t, int32_t, int, insn *, const char *);
112 static void gencode(int32_t, int32_t, int, insn *, const char *, int32_t);
113 static int matches(const struct itemplate *, insn *, int bits);
114 static int32_t regflag(const operand *);
115 static int32_t regval(const operand *);
116 static int rexflags(int, int32_t, int);
117 static int op_rexflags(const operand *, int);
118 static ea *process_ea(operand *, ea *, int, int, int32_t, int);
119 static int chsize(operand *, int);
120
121 static void assert_no_prefix(insn * ins, int prefix)
122 {
123 int j;
124
125 for (j = 0; j < ins->nprefix; j++) {
126 if (ins->prefixes[j] == prefix) {
127 errfunc(ERR_NONFATAL, "invalid %s prefix", prefix_name(prefix));
128 break;
129 }
130 }
131 }
132
133 /*
134 * This routine wrappers the real output format's output routine,
135 * in order to pass a copy of the data off to the listing file
136 * generator at the same time.
137 */
138 static void out(int32_t offset, int32_t segto, const void *data,
139 uint32_t type, int32_t segment, int32_t wrt)
140 {
141 static int32_t lineno = 0; /* static!!! */
142 static char *lnfname = NULL;
143
144 if ((type & OUT_TYPMASK) == OUT_ADDRESS) {
145 if (segment != NO_SEG || wrt != NO_SEG) {
146 /*
147 * This address is relocated. We must write it as
148 * OUT_ADDRESS, so there's no work to be done here.
149 */
150 list->output(offset, data, type);
151 } else {
152 uint8_t p[8], *q = p;
153 /*
154 * This is a non-relocated address, and we're going to
155 * convert it into RAWDATA format.
156 */
157 if ((type & OUT_SIZMASK) == 4) {
158 WRITELONG(q, *(int32_t *)data);
159 list->output(offset, p, OUT_RAWDATA + 4);
160 } else if ((type & OUT_SIZMASK) == 8) {
161 WRITEDLONG(q, *(int64_t *)data);
162 list->output(offset, p, OUT_RAWDATA + 8);
163 } else {
164 WRITESHORT(q, *(int32_t *)data);
165 list->output(offset, p, OUT_RAWDATA + 2);
166 }
167 }
168 } else if ((type & OUT_TYPMASK) == OUT_RAWDATA) {
169 list->output(offset, data, type);
170 } else if ((type & OUT_TYPMASK) == OUT_RESERVE) {
171 list->output(offset, NULL, type);
172 } else if ((type & OUT_TYPMASK) == OUT_REL2ADR ||
173 (type & OUT_TYPMASK) == OUT_REL4ADR) {
174 list->output(offset, data, type);
175 }
176
177 /*
178 * this call to src_get determines when we call the
179 * debug-format-specific "linenum" function
180 * it updates lineno and lnfname to the current values
181 * returning 0 if "same as last time", -2 if lnfname
182 * changed, and the amount by which lineno changed,
183 * if it did. thus, these variables must be static
184 */
185
186 if (src_get(&lineno, &lnfname)) {
187 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
188 }
189
190 outfmt->output(segto, data, type, segment, wrt);
191 }
192
193 static int jmp_match(int32_t segment, int32_t offset, int bits,
194 insn * ins, const char *code)
195 {
196 int32_t isize;
197 uint8_t c = code[0];
198
199 if (c != 0370 && c != 0371)
200 return 0;
201 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
202 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
203 && c == 0370)
204 return 1;
205 else
206 return (pass0 == 0); /* match a forward reference */
207 }
208 isize = calcsize(segment, offset, bits, ins, code);
209 if (ins->oprs[0].segment != segment)
210 return 0;
211 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
212 if (isize >= -128L && isize <= 127L)
213 return 1; /* it is byte size */
214
215 return 0;
216 }
217
218 int32_t assemble(int32_t segment, int32_t offset, int bits, uint32_t cp,
219 insn * instruction, struct ofmt *output, efunc error,
220 ListGen * listgen)
221 {
222 const struct itemplate *temp;
223 int j;
224 int size_prob;
225 int32_t insn_end;
226 int32_t itimes;
227 int32_t start = offset;
228 int32_t wsize = 0; /* size for DB etc. */
229
230 errfunc = error; /* to pass to other functions */
231 cpu = cp;
232 outfmt = output; /* likewise */
233 list = listgen; /* and again */
234
235 switch (instruction->opcode) {
236 case -1:
237 return 0;
238 case I_DB:
239 wsize = 1;
240 break;
241 case I_DW:
242 wsize = 2;
243 break;
244 case I_DD:
245 wsize = 4;
246 break;
247 case I_DQ:
248 wsize = 8;
249 break;
250 case I_DT:
251 wsize = 10;
252 break;
253 case I_DO:
254 wsize = 16;
255 break;
256 default:
257 break;
258 }
259
260 if (wsize) {
261 extop *e;
262 int32_t t = instruction->times;
263 if (t < 0)
264 errfunc(ERR_PANIC,
265 "instruction->times < 0 (%ld) in assemble()", t);
266
267 while (t--) { /* repeat TIMES times */
268 for (e = instruction->eops; e; e = e->next) {
269 if (e->type == EOT_DB_NUMBER) {
270 if (wsize == 1) {
271 if (e->segment != NO_SEG)
272 errfunc(ERR_NONFATAL,
273 "one-byte relocation attempted");
274 else {
275 uint8_t out_byte = e->offset;
276 out(offset, segment, &out_byte,
277 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
278 }
279 } else if (wsize > 8) {
280 errfunc(ERR_NONFATAL, "integer supplied to a DT"
281 " instruction");
282 } else
283 out(offset, segment, &e->offset,
284 OUT_ADDRESS + wsize, e->segment, e->wrt);
285 offset += wsize;
286 } else if (e->type == EOT_DB_STRING) {
287 int align;
288
289 out(offset, segment, e->stringval,
290 OUT_RAWDATA + e->stringlen, NO_SEG, NO_SEG);
291 align = e->stringlen % wsize;
292
293 if (align) {
294 align = wsize - align;
295 out(offset, segment, "\0\0\0\0\0\0\0\0",
296 OUT_RAWDATA + align, NO_SEG, NO_SEG);
297 }
298 offset += e->stringlen + align;
299 }
300 }
301 if (t > 0 && t == instruction->times - 1) {
302 /*
303 * Dummy call to list->output to give the offset to the
304 * listing module.
305 */
306 list->output(offset, NULL, OUT_RAWDATA);
307 list->uplevel(LIST_TIMES);
308 }
309 }
310 if (instruction->times > 1)
311 list->downlevel(LIST_TIMES);
312 return offset - start;
313 }
314
315 if (instruction->opcode == I_INCBIN) {
316 static char fname[FILENAME_MAX];
317 FILE *fp;
318 int32_t len;
319 char *prefix = "", *combine;
320 char **pPrevPath = NULL;
321
322 len = FILENAME_MAX - 1;
323 if (len > instruction->eops->stringlen)
324 len = instruction->eops->stringlen;
325 strncpy(fname, instruction->eops->stringval, len);
326 fname[len] = '\0';
327
328 while (1) { /* added by alexfru: 'incbin' uses include paths */
329 combine = nasm_malloc(strlen(prefix) + len + 1);
330 strcpy(combine, prefix);
331 strcat(combine, fname);
332
333 if ((fp = fopen(combine, "rb")) != NULL) {
334 nasm_free(combine);
335 break;
336 }
337
338 nasm_free(combine);
339 pPrevPath = pp_get_include_path_ptr(pPrevPath);
340 if (pPrevPath == NULL)
341 break;
342 prefix = *pPrevPath;
343 }
344
345 if (fp == NULL)
346 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
347 fname);
348 else if (fseek(fp, 0L, SEEK_END) < 0)
349 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
350 fname);
351 else {
352 static char buf[2048];
353 int32_t t = instruction->times;
354 int32_t base = 0;
355
356 len = ftell(fp);
357 if (instruction->eops->next) {
358 base = instruction->eops->next->offset;
359 len -= base;
360 if (instruction->eops->next->next &&
361 len > instruction->eops->next->next->offset)
362 len = instruction->eops->next->next->offset;
363 }
364 /*
365 * Dummy call to list->output to give the offset to the
366 * listing module.
367 */
368 list->output(offset, NULL, OUT_RAWDATA);
369 list->uplevel(LIST_INCBIN);
370 while (t--) {
371 int32_t l;
372
373 fseek(fp, base, SEEK_SET);
374 l = len;
375 while (l > 0) {
376 int32_t m =
377 fread(buf, 1, (l > sizeof(buf) ? sizeof(buf) : l),
378 fp);
379 if (!m) {
380 /*
381 * This shouldn't happen unless the file
382 * actually changes while we are reading
383 * it.
384 */
385 error(ERR_NONFATAL,
386 "`incbin': unexpected EOF while"
387 " reading file `%s'", fname);
388 t = 0; /* Try to exit cleanly */
389 break;
390 }
391 out(offset, segment, buf, OUT_RAWDATA + m,
392 NO_SEG, NO_SEG);
393 l -= m;
394 }
395 }
396 list->downlevel(LIST_INCBIN);
397 if (instruction->times > 1) {
398 /*
399 * Dummy call to list->output to give the offset to the
400 * listing module.
401 */
402 list->output(offset, NULL, OUT_RAWDATA);
403 list->uplevel(LIST_TIMES);
404 list->downlevel(LIST_TIMES);
405 }
406 fclose(fp);
407 return instruction->times * len;
408 }
409 return 0; /* if we're here, there's an error */
410 }
411
412 size_prob = FALSE;
413
414 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
415 int m = matches(temp, instruction, bits);
416
417 if (m == 99)
418 m += jmp_match(segment, offset, bits, instruction, temp->code);
419
420 if (m == 100) { /* matches! */
421 const char *codes = temp->code;
422 int32_t insn_size = calcsize(segment, offset, bits,
423 instruction, codes);
424 itimes = instruction->times;
425 if (insn_size < 0) /* shouldn't be, on pass two */
426 error(ERR_PANIC, "errors made it through from pass one");
427 else
428 while (itimes--) {
429 for (j = 0; j < instruction->nprefix; j++) {
430 uint8_t c = 0;
431 switch (instruction->prefixes[j]) {
432 case P_LOCK:
433 c = 0xF0;
434 break;
435 case P_REPNE:
436 case P_REPNZ:
437 c = 0xF2;
438 break;
439 case P_REPE:
440 case P_REPZ:
441 case P_REP:
442 c = 0xF3;
443 break;
444 case R_CS:
445 if (bits == 64) {
446 error(ERR_WARNING,
447 "cs segment base ignored in 64-bit mode");
448 }
449 c = 0x2E;
450 break;
451 case R_DS:
452 if (bits == 64) {
453 error(ERR_WARNING,
454 "ds segment base ignored in 64-bit mode");
455 }
456 c = 0x3E;
457 break;
458 case R_ES:
459 if (bits == 64) {
460 error(ERR_WARNING,
461 "es segment base ignored in 64-bit mode");
462 }
463 c = 0x26;
464 break;
465 case R_FS:
466 c = 0x64;
467 break;
468 case R_GS:
469 c = 0x65;
470 break;
471 case R_SS:
472 if (bits == 64) {
473 error(ERR_WARNING,
474 "ss segment base ignored in 64-bit mode");
475 }
476 c = 0x36;
477 break;
478 case R_SEGR6:
479 case R_SEGR7:
480 error(ERR_NONFATAL,
481 "segr6 and segr7 cannot be used as prefixes");
482 break;
483 case P_A16:
484 if (bits == 64) {
485 error(ERR_NONFATAL,
486 "16-bit addressing is not supported "
487 "in 64-bit mode");
488 break;
489 }
490 if (bits != 16)
491 c = 0x67;
492 break;
493 case P_A32:
494 if (bits != 32)
495 c = 0x67;
496 break;
497 case P_O16:
498 if (bits != 16)
499 c = 0x66;
500 break;
501 case P_O32:
502 if (bits == 16)
503 c = 0x66;
504 break;
505 default:
506 error(ERR_PANIC, "invalid instruction prefix");
507 }
508 if (c != 0) {
509 out(offset, segment, &c, OUT_RAWDATA + 1,
510 NO_SEG, NO_SEG);
511 offset++;
512 }
513 }
514 insn_end = offset + insn_size;
515 gencode(segment, offset, bits, instruction, codes,
516 insn_end);
517 offset += insn_size;
518 if (itimes > 0 && itimes == instruction->times - 1) {
519 /*
520 * Dummy call to list->output to give the offset to the
521 * listing module.
522 */
523 list->output(offset, NULL, OUT_RAWDATA);
524 list->uplevel(LIST_TIMES);
525 }
526 }
527 if (instruction->times > 1)
528 list->downlevel(LIST_TIMES);
529 return offset - start;
530 } else if (m > 0 && m > size_prob) {
531 size_prob = m;
532 }
533 // temp++;
534 }
535
536 if (temp->opcode == -1) { /* didn't match any instruction */
537 switch (size_prob) {
538 case 1:
539 error(ERR_NONFATAL, "operation size not specified");
540 break;
541 case 2:
542 error(ERR_NONFATAL, "mismatch in operand sizes");
543 break;
544 case 3:
545 error(ERR_NONFATAL, "no instruction for this cpu level");
546 break;
547 case 4:
548 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
549 break;
550 default:
551 error(ERR_NONFATAL,
552 "invalid combination of opcode and operands");
553 break;
554 }
555 }
556 return 0;
557 }
558
559 int32_t insn_size(int32_t segment, int32_t offset, int bits, uint32_t cp,
560 insn * instruction, efunc error)
561 {
562 const struct itemplate *temp;
563
564 errfunc = error; /* to pass to other functions */
565 cpu = cp;
566
567 if (instruction->opcode == -1)
568 return 0;
569
570 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
571 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
572 instruction->opcode == I_DT || instruction->opcode == I_DO) {
573 extop *e;
574 int32_t isize, osize, wsize = 0; /* placate gcc */
575
576 isize = 0;
577 switch (instruction->opcode) {
578 case I_DB:
579 wsize = 1;
580 break;
581 case I_DW:
582 wsize = 2;
583 break;
584 case I_DD:
585 wsize = 4;
586 break;
587 case I_DQ:
588 wsize = 8;
589 break;
590 case I_DT:
591 wsize = 10;
592 break;
593 case I_DO:
594 wsize = 16;
595 break;
596 default:
597 break;
598 }
599
600 for (e = instruction->eops; e; e = e->next) {
601 int32_t align;
602
603 osize = 0;
604 if (e->type == EOT_DB_NUMBER)
605 osize = 1;
606 else if (e->type == EOT_DB_STRING)
607 osize = e->stringlen;
608
609 align = (-osize) % wsize;
610 if (align < 0)
611 align += wsize;
612 isize += osize + align;
613 }
614 return isize * instruction->times;
615 }
616
617 if (instruction->opcode == I_INCBIN) {
618 char fname[FILENAME_MAX];
619 FILE *fp;
620 int32_t len;
621 char *prefix = "", *combine;
622 char **pPrevPath = NULL;
623
624 len = FILENAME_MAX - 1;
625 if (len > instruction->eops->stringlen)
626 len = instruction->eops->stringlen;
627 strncpy(fname, instruction->eops->stringval, len);
628 fname[len] = '\0';
629
630 while (1) { /* added by alexfru: 'incbin' uses include paths */
631 combine = nasm_malloc(strlen(prefix) + len + 1);
632 strcpy(combine, prefix);
633 strcat(combine, fname);
634
635 if ((fp = fopen(combine, "rb")) != NULL) {
636 nasm_free(combine);
637 break;
638 }
639
640 nasm_free(combine);
641 pPrevPath = pp_get_include_path_ptr(pPrevPath);
642 if (pPrevPath == NULL)
643 break;
644 prefix = *pPrevPath;
645 }
646
647 if (fp == NULL)
648 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
649 fname);
650 else if (fseek(fp, 0L, SEEK_END) < 0)
651 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
652 fname);
653 else {
654 len = ftell(fp);
655 fclose(fp);
656 if (instruction->eops->next) {
657 len -= instruction->eops->next->offset;
658 if (instruction->eops->next->next &&
659 len > instruction->eops->next->next->offset) {
660 len = instruction->eops->next->next->offset;
661 }
662 }
663 return instruction->times * len;
664 }
665 return 0; /* if we're here, there's an error */
666 }
667
668 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
669 int m = matches(temp, instruction, bits);
670 if (m == 99)
671 m += jmp_match(segment, offset, bits, instruction, temp->code);
672
673 if (m == 100) {
674 /* we've matched an instruction. */
675 int32_t isize;
676 const char *codes = temp->code;
677 int j;
678
679 isize = calcsize(segment, offset, bits, instruction, codes);
680 if (isize < 0)
681 return -1;
682 for (j = 0; j < instruction->nprefix; j++) {
683 if ((instruction->prefixes[j] != P_A16 &&
684 instruction->prefixes[j] != P_O16 && bits == 16) ||
685 (instruction->prefixes[j] != P_A32 &&
686 instruction->prefixes[j] != P_O32 && bits >= 32)) {
687 isize++;
688 }
689 }
690 return isize * instruction->times;
691 }
692 }
693 return -1; /* didn't match any instruction */
694 }
695
696 /* check that opn[op] is a signed byte of size 16 or 32,
697 and return the signed value*/
698 static int is_sbyte(insn * ins, int op, int size)
699 {
700 int32_t v;
701 int ret;
702
703 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
704 optimizing >= 0 &&
705 !(ins->oprs[op].type & STRICT) &&
706 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
707
708 v = ins->oprs[op].offset;
709 if (size == 16)
710 v = (int16_t)v; /* sign extend if 16 bits */
711
712 return ret && v >= -128L && v <= 127L;
713 }
714
715 static int32_t calcsize(int32_t segment, int32_t offset, int bits,
716 insn * ins, const char *codes)
717 {
718 int32_t length = 0;
719 uint8_t c;
720 int rex_mask = ~0;
721 ins->rex = 0; /* Ensure REX is reset */
722
723 (void)segment; /* Don't warn that this parameter is unused */
724 (void)offset; /* Don't warn that this parameter is unused */
725
726 while (*codes)
727 switch (c = *codes++) {
728 case 01:
729 case 02:
730 case 03:
731 codes += c, length += c;
732 break;
733 case 04:
734 case 05:
735 case 06:
736 case 07:
737 length++;
738 break;
739 case 010:
740 case 011:
741 case 012:
742 case 013:
743 ins->rex |=
744 op_rexflags(&ins->oprs[c - 010], REX_B|REX_H|REX_P|REX_W);
745 codes++, length++;
746 break;
747 case 014:
748 case 015:
749 case 016:
750 case 017:
751 length++;
752 break;
753 case 020:
754 case 021:
755 case 022:
756 case 023:
757 length++;
758 break;
759 case 024:
760 case 025:
761 case 026:
762 case 027:
763 length++;
764 break;
765 case 030:
766 case 031:
767 case 032:
768 case 033:
769 length += 2;
770 break;
771 case 034:
772 case 035:
773 case 036:
774 case 037:
775 if (ins->oprs[c - 034].type & (BITS16 | BITS32 | BITS64))
776 length += (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
777 else
778 length += (bits == 16) ? 2 : 4;
779 break;
780 case 040:
781 case 041:
782 case 042:
783 case 043:
784 length += 4;
785 break;
786 case 044:
787 case 045:
788 case 046:
789 case 047:
790 length += ((ins->oprs[c - 044].addr_size ?
791 ins->oprs[c - 044].addr_size : bits) >> 3);
792 break;
793 case 050:
794 case 051:
795 case 052:
796 case 053:
797 length++;
798 break;
799 case 054:
800 case 055:
801 case 056:
802 case 057:
803 length += 8; /* MOV reg64/imm */
804 break;
805 case 060:
806 case 061:
807 case 062:
808 case 063:
809 length += 2;
810 break;
811 case 064:
812 case 065:
813 case 066:
814 case 067:
815 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
816 length += (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
817 else
818 length += (bits == 16) ? 2 : 4;
819 break;
820 case 070:
821 case 071:
822 case 072:
823 case 073:
824 length += 4;
825 break;
826 case 074:
827 case 075:
828 case 076:
829 case 077:
830 length += 2;
831 break;
832 case 0140:
833 case 0141:
834 case 0142:
835 case 0143:
836 length += is_sbyte(ins, c - 0140, 16) ? 1 : 2;
837 break;
838 case 0144:
839 case 0145:
840 case 0146:
841 case 0147:
842 codes += 2;
843 length++;
844 break;
845 case 0150:
846 case 0151:
847 case 0152:
848 case 0153:
849 length += is_sbyte(ins, c - 0150, 32) ? 1 : 4;
850 break;
851 case 0154:
852 case 0155:
853 case 0156:
854 case 0157:
855 codes += 2;
856 length++;
857 break;
858 case 0160:
859 case 0161:
860 case 0162:
861 case 0163:
862 length++;
863 ins->rex |= REX_D;
864 ins->drexdst = regval(&ins->oprs[c & 3]);
865 break;
866 case 0164:
867 case 0165:
868 case 0166:
869 case 0167:
870 length++;
871 ins->rex |= REX_D|REX_OC;
872 ins->drexdst = regval(&ins->oprs[c & 3]);
873 break;
874 case 0170:
875 length++;
876 break;
877 case 0171:
878 break;
879 case 0300:
880 case 0301:
881 case 0302:
882 case 0303:
883 length += chsize(&ins->oprs[c - 0300], bits);
884 break;
885 case 0310:
886 length += (bits != 16);
887 break;
888 case 0311:
889 length += (bits != 32);
890 break;
891 case 0312:
892 break;
893 case 0313:
894 break;
895 case 0320:
896 length += (bits != 16);
897 break;
898 case 0321:
899 length += (bits == 16);
900 break;
901 case 0322:
902 break;
903 case 0323:
904 rex_mask &= ~REX_W;
905 break;
906 case 0324:
907 ins->rex |= REX_W;
908 break;
909 case 0330:
910 codes++, length++;
911 break;
912 case 0331:
913 break;
914 case 0332:
915 case 0333:
916 length++;
917 break;
918 case 0334:
919 assert_no_prefix(ins, P_LOCK);
920 ins->rex |= REX_L;
921 break;
922 case 0335:
923 break;
924 case 0340:
925 case 0341:
926 case 0342:
927 if (ins->oprs[0].segment != NO_SEG)
928 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
929 " quantity of BSS space");
930 else
931 length += ins->oprs[0].offset << (c - 0340);
932 break;
933 case 0364:
934 case 0365:
935 break;
936 case 0366:
937 case 0367:
938 length++;
939 break;
940 case 0370:
941 case 0371:
942 case 0372:
943 break;
944 case 0373:
945 length++;
946 break;
947 default: /* can't do it by 'case' statements */
948 if (c >= 0100 && c <= 0277) { /* it's an EA */
949 ea ea_data;
950 int rfield;
951 int32_t rflags;
952 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
953
954 if (c <= 0177) {
955 /* pick rfield from operand b */
956 rflags = regflag(&ins->oprs[c & 7]);
957 rfield = regvals[ins->oprs[c & 7].basereg];
958 } else {
959 rflags = 0;
960 rfield = c & 7;
961 }
962
963 if (!process_ea
964 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
965 rfield, rflags, ins->forw_ref)) {
966 errfunc(ERR_NONFATAL, "invalid effective address");
967 return -1;
968 } else {
969 ins->rex |= ea_data.rex;
970 length += ea_data.size;
971 }
972 } else
973 errfunc(ERR_PANIC, "internal instruction table corrupt"
974 ": instruction code 0x%02X given", c);
975 }
976
977 ins->rex &= rex_mask;
978
979 if (ins->rex & REX_D) {
980 if (ins->rex & REX_H) {
981 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
982 return -1;
983 }
984 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
985 ins->drexdst > 7)) {
986 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
987 return -1;
988 }
989 length++;
990 } else if (ins->rex & REX_REAL) {
991 if (ins->rex & REX_H) {
992 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
993 return -1;
994 } else if (bits == 64 ||
995 ((ins->rex & REX_L) &&
996 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
997 cpu >= IF_X86_64)) {
998 length++;
999 } else {
1000 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1001 return -1;
1002 }
1003 }
1004
1005 return length;
1006 }
1007
1008 #define EMIT_REX() \
1009 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1010 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1011 out(offset, segment, &ins->rex, OUT_RAWDATA+1, NO_SEG, NO_SEG); \
1012 ins->rex = 0; \
1013 offset += 1; \
1014 }
1015
1016 static void gencode(int32_t segment, int32_t offset, int bits,
1017 insn * ins, const char *codes, int32_t insn_end)
1018 {
1019 static char condval[] = { /* conditional opcodes */
1020 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1021 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1022 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1023 };
1024 uint8_t c;
1025 uint8_t bytes[4];
1026 int32_t size;
1027 int64_t data;
1028
1029 while (*codes)
1030 switch (c = *codes++) {
1031 case 01:
1032 case 02:
1033 case 03:
1034 EMIT_REX();
1035 out(offset, segment, codes, OUT_RAWDATA + c, NO_SEG, NO_SEG);
1036 codes += c;
1037 offset += c;
1038 break;
1039
1040 case 04:
1041 case 06:
1042 switch (ins->oprs[0].basereg) {
1043 case R_CS:
1044 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1045 break;
1046 case R_DS:
1047 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1048 break;
1049 case R_ES:
1050 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1051 break;
1052 case R_SS:
1053 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1054 break;
1055 default:
1056 errfunc(ERR_PANIC,
1057 "bizarre 8086 segment register received");
1058 }
1059 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1060 offset++;
1061 break;
1062
1063 case 05:
1064 case 07:
1065 switch (ins->oprs[0].basereg) {
1066 case R_FS:
1067 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1068 break;
1069 case R_GS:
1070 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1071 break;
1072 default:
1073 errfunc(ERR_PANIC,
1074 "bizarre 386 segment register received");
1075 }
1076 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1077 offset++;
1078 break;
1079
1080 case 010:
1081 case 011:
1082 case 012:
1083 case 013:
1084 EMIT_REX();
1085 bytes[0] = *codes++ + ((regval(&ins->oprs[c - 010])) & 7);
1086 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1087 offset += 1;
1088 break;
1089
1090 case 014:
1091 case 015:
1092 case 016:
1093 case 017:
1094 if (ins->oprs[c - 014].offset < -128
1095 || ins->oprs[c - 014].offset > 127) {
1096 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1097 }
1098
1099 if (ins->oprs[c - 014].segment != NO_SEG) {
1100 data = ins->oprs[c - 014].offset;
1101 out(offset, segment, &data, OUT_ADDRESS + 1,
1102 ins->oprs[c - 014].segment, ins->oprs[c - 014].wrt);
1103 } else {
1104 bytes[0] = ins->oprs[c - 014].offset;
1105 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1106 NO_SEG);
1107 }
1108 offset += 1;
1109 break;
1110
1111 case 020:
1112 case 021:
1113 case 022:
1114 case 023:
1115 if (ins->oprs[c - 020].offset < -256
1116 || ins->oprs[c - 020].offset > 255) {
1117 errfunc(ERR_WARNING, "byte value exceeds bounds");
1118 }
1119 if (ins->oprs[c - 020].segment != NO_SEG) {
1120 data = ins->oprs[c - 020].offset;
1121 out(offset, segment, &data, OUT_ADDRESS + 1,
1122 ins->oprs[c - 020].segment, ins->oprs[c - 020].wrt);
1123 } else {
1124 bytes[0] = ins->oprs[c - 020].offset;
1125 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1126 NO_SEG);
1127 }
1128 offset += 1;
1129 break;
1130
1131 case 024:
1132 case 025:
1133 case 026:
1134 case 027:
1135 if (ins->oprs[c - 024].offset < 0
1136 || ins->oprs[c - 024].offset > 255)
1137 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1138 if (ins->oprs[c - 024].segment != NO_SEG) {
1139 data = ins->oprs[c - 024].offset;
1140 out(offset, segment, &data, OUT_ADDRESS + 1,
1141 ins->oprs[c - 024].segment, ins->oprs[c - 024].wrt);
1142 } else {
1143 bytes[0] = ins->oprs[c - 024].offset;
1144 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1145 NO_SEG);
1146 }
1147 offset += 1;
1148 break;
1149
1150 case 030:
1151 case 031:
1152 case 032:
1153 case 033:
1154 if (ins->oprs[c - 030].segment == NO_SEG &&
1155 ins->oprs[c - 030].wrt == NO_SEG &&
1156 (ins->oprs[c - 030].offset < -65536L ||
1157 ins->oprs[c - 030].offset > 65535L)) {
1158 errfunc(ERR_WARNING, "word value exceeds bounds");
1159 }
1160 data = ins->oprs[c - 030].offset;
1161 out(offset, segment, &data, OUT_ADDRESS + 2,
1162 ins->oprs[c - 030].segment, ins->oprs[c - 030].wrt);
1163 offset += 2;
1164 break;
1165
1166 case 034:
1167 case 035:
1168 case 036:
1169 case 037:
1170 if (ins->oprs[c - 034].type & (BITS16 | BITS32))
1171 size = (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
1172 else
1173 size = (bits == 16) ? 2 : 4;
1174 data = ins->oprs[c - 034].offset;
1175 if (size == 2 && (data < -65536L || data > 65535L))
1176 errfunc(ERR_WARNING, "word value exceeds bounds");
1177 out(offset, segment, &data, OUT_ADDRESS + size,
1178 ins->oprs[c - 034].segment, ins->oprs[c - 034].wrt);
1179 offset += size;
1180 break;
1181
1182 case 040:
1183 case 041:
1184 case 042:
1185 case 043:
1186 data = ins->oprs[c - 040].offset;
1187 out(offset, segment, &data, OUT_ADDRESS + 4,
1188 ins->oprs[c - 040].segment, ins->oprs[c - 040].wrt);
1189 offset += 4;
1190 break;
1191
1192 case 044:
1193 case 045:
1194 case 046:
1195 case 047:
1196 data = ins->oprs[c - 044].offset;
1197 size = ((ins->oprs[c - 044].addr_size ?
1198 ins->oprs[c - 044].addr_size : bits) >> 3);
1199 if (size == 2 && (data < -65536L || data > 65535L))
1200 errfunc(ERR_WARNING, "word value exceeds bounds");
1201 out(offset, segment, &data, OUT_ADDRESS + size,
1202 ins->oprs[c - 044].segment, ins->oprs[c - 044].wrt);
1203 offset += size;
1204 break;
1205
1206 case 050:
1207 case 051:
1208 case 052:
1209 case 053:
1210 if (ins->oprs[c - 050].segment != segment)
1211 errfunc(ERR_NONFATAL,
1212 "short relative jump outside segment");
1213 data = ins->oprs[c - 050].offset - insn_end;
1214 if (data > 127 || data < -128)
1215 errfunc(ERR_NONFATAL, "short jump is out of range");
1216 bytes[0] = data;
1217 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1218 offset += 1;
1219 break;
1220
1221 case 054:
1222 case 055:
1223 case 056:
1224 case 057:
1225 data = (int64_t)ins->oprs[c - 054].offset;
1226 out(offset, segment, &data, OUT_ADDRESS + 8,
1227 ins->oprs[c - 054].segment, ins->oprs[c - 054].wrt);
1228 offset += 8;
1229 break;
1230
1231 case 060:
1232 case 061:
1233 case 062:
1234 case 063:
1235 if (ins->oprs[c - 060].segment != segment) {
1236 data = ins->oprs[c - 060].offset;
1237 out(offset, segment, &data,
1238 OUT_REL2ADR + insn_end - offset,
1239 ins->oprs[c - 060].segment, ins->oprs[c - 060].wrt);
1240 } else {
1241 data = ins->oprs[c - 060].offset - insn_end;
1242 out(offset, segment, &data,
1243 OUT_ADDRESS + 2, NO_SEG, NO_SEG);
1244 }
1245 offset += 2;
1246 break;
1247
1248 case 064:
1249 case 065:
1250 case 066:
1251 case 067:
1252 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
1253 size = (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
1254 else
1255 size = (bits == 16) ? 2 : 4;
1256 if (ins->oprs[c - 064].segment != segment) {
1257 int32_t reltype = (size == 2 ? OUT_REL2ADR : OUT_REL4ADR);
1258 data = ins->oprs[c - 064].offset;
1259 out(offset, segment, &data, reltype + insn_end - offset,
1260 ins->oprs[c - 064].segment, ins->oprs[c - 064].wrt);
1261 } else {
1262 data = ins->oprs[c - 064].offset - insn_end;
1263 out(offset, segment, &data,
1264 OUT_ADDRESS + size, NO_SEG, NO_SEG);
1265 }
1266 offset += size;
1267 break;
1268
1269 case 070:
1270 case 071:
1271 case 072:
1272 case 073:
1273 if (ins->oprs[c - 070].segment != segment) {
1274 data = ins->oprs[c - 070].offset;
1275 out(offset, segment, &data,
1276 OUT_REL4ADR + insn_end - offset,
1277 ins->oprs[c - 070].segment, ins->oprs[c - 070].wrt);
1278 } else {
1279 data = ins->oprs[c - 070].offset - insn_end;
1280 out(offset, segment, &data,
1281 OUT_ADDRESS + 4, NO_SEG, NO_SEG);
1282 }
1283 offset += 4;
1284 break;
1285
1286 case 074:
1287 case 075:
1288 case 076:
1289 case 077:
1290 if (ins->oprs[c - 074].segment == NO_SEG)
1291 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1292 " relocatable");
1293 data = 0L;
1294 out(offset, segment, &data, OUT_ADDRESS + 2,
1295 outfmt->segbase(1 + ins->oprs[c - 074].segment),
1296 ins->oprs[c - 074].wrt);
1297 offset += 2;
1298 break;
1299
1300 case 0140:
1301 case 0141:
1302 case 0142:
1303 case 0143:
1304 data = ins->oprs[c - 0140].offset;
1305 if (is_sbyte(ins, c - 0140, 16)) {
1306 bytes[0] = data;
1307 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1308 NO_SEG);
1309 offset++;
1310 } else {
1311 if (ins->oprs[c - 0140].segment == NO_SEG &&
1312 ins->oprs[c - 0140].wrt == NO_SEG &&
1313 (data < -65536L || data > 65535L)) {
1314 errfunc(ERR_WARNING, "word value exceeds bounds");
1315 }
1316 out(offset, segment, &data, OUT_ADDRESS + 2,
1317 ins->oprs[c - 0140].segment, ins->oprs[c - 0140].wrt);
1318 offset += 2;
1319 }
1320 break;
1321
1322 case 0144:
1323 case 0145:
1324 case 0146:
1325 case 0147:
1326 EMIT_REX();
1327 codes++;
1328 bytes[0] = *codes++;
1329 if (is_sbyte(ins, c - 0144, 16))
1330 bytes[0] |= 2; /* s-bit */
1331 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1332 offset++;
1333 break;
1334
1335 case 0150:
1336 case 0151:
1337 case 0152:
1338 case 0153:
1339 data = ins->oprs[c - 0150].offset;
1340 if (is_sbyte(ins, c - 0150, 32)) {
1341 bytes[0] = data;
1342 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1343 NO_SEG);
1344 offset++;
1345 } else {
1346 out(offset, segment, &data, OUT_ADDRESS + 4,
1347 ins->oprs[c - 0150].segment, ins->oprs[c - 0150].wrt);
1348 offset += 4;
1349 }
1350 break;
1351
1352 case 0154:
1353 case 0155:
1354 case 0156:
1355 case 0157:
1356 EMIT_REX();
1357 codes++;
1358 bytes[0] = *codes++;
1359 if (is_sbyte(ins, c - 0154, 32))
1360 bytes[0] |= 2; /* s-bit */
1361 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1362 offset++;
1363 break;
1364
1365 case 0160:
1366 case 0161:
1367 case 0162:
1368 case 0163:
1369 case 0164:
1370 case 0165:
1371 case 0166:
1372 case 0167:
1373 break;
1374
1375 case 0170:
1376 bytes[0] = 0;
1377 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1378 offset += 1;
1379 break;
1380
1381 case 0171:
1382 bytes[0] =
1383 (ins->drexdst << 4) |
1384 (ins->rex & REX_OC ? 0x08 : 0) |
1385 (ins->rex & (REX_R|REX_X|REX_B));
1386 ins->rex = 0;
1387 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1388 offset++;
1389 break;
1390
1391 case 0300:
1392 case 0301:
1393 case 0302:
1394 case 0303:
1395 if (chsize(&ins->oprs[c - 0300], bits)) {
1396 *bytes = 0x67;
1397 out(offset, segment, bytes,
1398 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1399 offset += 1;
1400 } else
1401 offset += 0;
1402 break;
1403
1404 case 0310:
1405 if (bits != 16) {
1406 *bytes = 0x67;
1407 out(offset, segment, bytes,
1408 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1409 offset += 1;
1410 } else
1411 offset += 0;
1412 break;
1413
1414 case 0311:
1415 if (bits != 32) {
1416 *bytes = 0x67;
1417 out(offset, segment, bytes,
1418 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1419 offset += 1;
1420 } else
1421 offset += 0;
1422 break;
1423
1424 case 0312:
1425 break;
1426
1427 case 0313:
1428 ins->rex = 0;
1429 break;
1430
1431 case 0320:
1432 if (bits != 16) {
1433 *bytes = 0x66;
1434 out(offset, segment, bytes,
1435 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1436 offset += 1;
1437 } else
1438 offset += 0;
1439 break;
1440
1441 case 0321:
1442 if (bits == 16) {
1443 *bytes = 0x66;
1444 out(offset, segment, bytes,
1445 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1446 offset += 1;
1447 } else
1448 offset += 0;
1449 break;
1450
1451 case 0322:
1452 case 0323:
1453 break;
1454
1455 case 0324:
1456 ins->rex |= REX_W;
1457 break;
1458
1459 case 0330:
1460 *bytes = *codes++ ^ condval[ins->condition];
1461 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1462 offset += 1;
1463 break;
1464
1465 case 0331:
1466 break;
1467
1468 case 0332:
1469 case 0333:
1470 *bytes = c - 0332 + 0xF2;
1471 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1472 offset += 1;
1473 break;
1474
1475 case 0334:
1476 if (ins->rex & REX_R) {
1477 *bytes = 0xF0;
1478 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1479 offset += 1;
1480 }
1481 ins->rex &= ~(REX_L|REX_R);
1482 break;
1483
1484 case 0335:
1485 break;
1486
1487 case 0340:
1488 case 0341:
1489 case 0342:
1490 if (ins->oprs[0].segment != NO_SEG)
1491 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1492 else {
1493 int32_t size = ins->oprs[0].offset << (c - 0340);
1494 if (size > 0)
1495 out(offset, segment, NULL,
1496 OUT_RESERVE + size, NO_SEG, NO_SEG);
1497 offset += size;
1498 }
1499 break;
1500
1501 case 0364:
1502 case 0365:
1503 break;
1504
1505 case 0366:
1506 case 0367:
1507 *bytes = c - 0366 + 0x66;
1508 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1509 offset += 1;
1510 break;
1511
1512 case 0370:
1513 case 0371:
1514 case 0372:
1515 break;
1516
1517 case 0373:
1518 *bytes = bits == 16 ? 3 : 5;
1519 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1520 offset += 1;
1521 break;
1522
1523 default: /* can't do it by 'case' statements */
1524 if (c >= 0100 && c <= 0277) { /* it's an EA */
1525 ea ea_data;
1526 int rfield;
1527 int32_t rflags;
1528 uint8_t *p;
1529 int32_t s;
1530
1531 if (c <= 0177) {
1532 /* pick rfield from operand b */
1533 rflags = regflag(&ins->oprs[c & 7]);
1534 rfield = regvals[ins->oprs[c & 7].basereg];
1535 } else {
1536 /* rfield is constant */
1537 rflags = 0;
1538 rfield = c & 7;
1539 }
1540
1541 if (!process_ea
1542 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1543 rfield, rflags, ins->forw_ref)) {
1544 errfunc(ERR_NONFATAL, "invalid effective address");
1545 }
1546
1547 p = bytes;
1548 *p++ = ea_data.modrm;
1549 if (ea_data.sib_present)
1550 *p++ = ea_data.sib;
1551
1552 /* DREX suffixes come between the SIB and the displacement */
1553 if (ins->rex & REX_D) {
1554 *p++ =
1555 (ins->drexdst << 4) |
1556 (ins->rex & REX_OC ? 0x08 : 0) |
1557 (ins->rex & (REX_R|REX_X|REX_B));
1558 ins->rex = 0;
1559 }
1560
1561 s = p - bytes;
1562 out(offset, segment, bytes, OUT_RAWDATA + s,
1563 NO_SEG, NO_SEG);
1564
1565 switch (ea_data.bytes) {
1566 case 0:
1567 break;
1568 case 1:
1569 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1570 data = ins->oprs[(c >> 3) & 7].offset;
1571 out(offset, segment, &data, OUT_ADDRESS + 1,
1572 ins->oprs[(c >> 3) & 7].segment,
1573 ins->oprs[(c >> 3) & 7].wrt);
1574 } else {
1575 *bytes = ins->oprs[(c >> 3) & 7].offset;
1576 out(offset, segment, bytes, OUT_RAWDATA + 1,
1577 NO_SEG, NO_SEG);
1578 }
1579 s++;
1580 break;
1581 case 8:
1582 case 2:
1583 case 4:
1584 data = ins->oprs[(c >> 3) & 7].offset;
1585 if (ea_data.rip && (ins->oprs[(c >> 3) & 7].segment == 0xFFFFFFFF))
1586 ea_data.rip = 0; /* Make distinction between Symbols and Immediates */
1587 out(offset, segment, &data, /* RIP = Relative, not Absolute */
1588 (ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS) + ea_data.bytes,
1589 ins->oprs[(c >> 3) & 7].segment,
1590 ins->oprs[(c >> 3) & 7].wrt);
1591 s += ea_data.bytes;
1592 break;
1593 }
1594 offset += s;
1595 } else
1596 errfunc(ERR_PANIC, "internal instruction table corrupt"
1597 ": instruction code 0x%02X given", c);
1598 }
1599 }
1600
1601 static int32_t regflag(const operand * o)
1602 {
1603 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1604 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1605 }
1606 return reg_flags[o->basereg];
1607 }
1608
1609 static int32_t regval(const operand * o)
1610 {
1611 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1612 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1613 }
1614 return regvals[o->basereg];
1615 }
1616
1617 static int op_rexflags(const operand * o, int mask)
1618 {
1619 int32_t flags;
1620 int val;
1621
1622 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1623 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1624 }
1625
1626 flags = reg_flags[o->basereg];
1627 val = regvals[o->basereg];
1628
1629 return rexflags(val, flags, mask);
1630 }
1631
1632 static int rexflags(int val, int32_t flags, int mask)
1633 {
1634 int rex = 0;
1635
1636 if (val >= 8)
1637 rex |= REX_B|REX_X|REX_R;
1638 if (flags & BITS64)
1639 rex |= REX_W;
1640 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1641 rex |= REX_H;
1642 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1643 rex |= REX_P;
1644
1645 return rex & mask;
1646 }
1647
1648 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1649 {
1650 int i, size[MAX_OPERANDS], asize, oprs, ret;
1651
1652 ret = 100;
1653
1654 /*
1655 * Check the opcode
1656 */
1657 if (itemp->opcode != instruction->opcode)
1658 return 0;
1659
1660 /*
1661 * Count the operands
1662 */
1663 if (itemp->operands != instruction->operands)
1664 return 0;
1665
1666 /*
1667 * Check that no spurious colons or TOs are present
1668 */
1669 for (i = 0; i < itemp->operands; i++)
1670 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1671 return 0;
1672
1673 /*
1674 * Check that the operand flags all match up
1675 */
1676 for (i = 0; i < itemp->operands; i++) {
1677 if (itemp->opd[i] & SAME_AS) {
1678 int j = itemp->opd[i] & ~SAME_AS;
1679 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1680 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1681 return 0;
1682 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1683 ((itemp->opd[i] & SIZE_MASK) &&
1684 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1685 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1686 (instruction->oprs[i].type & SIZE_MASK))
1687 return 0;
1688 else
1689 return 1;
1690 }
1691 }
1692
1693 /*
1694 * Check operand sizes
1695 */
1696 if (itemp->flags & IF_ARMASK) {
1697 memset(size, 0, sizeof size);
1698
1699 switch (itemp->flags & IF_ARMASK) {
1700 case IF_AR0:
1701 i = 0;
1702 break;
1703 case IF_AR1:
1704 i = 1;
1705 break;
1706 case IF_AR2:
1707 i = 2;
1708 break;
1709 case IF_AR3:
1710 i = 3;
1711 break;
1712 default:
1713 break; /* Shouldn't happen */
1714 }
1715 switch (itemp->flags & IF_SMASK) {
1716 case IF_SB:
1717 size[i] = BITS8;
1718 break;
1719 case IF_SW:
1720 size[i] = BITS16;
1721 break;
1722 case IF_SD:
1723 size[i] = BITS32;
1724 break;
1725 case IF_SQ:
1726 size[i] = BITS64;
1727 break;
1728 case IF_SO:
1729 size[i] = BITS128;
1730 break;
1731 default:
1732 break;
1733 }
1734 } else {
1735 asize = 0;
1736 switch (itemp->flags & IF_SMASK) {
1737 case IF_SB:
1738 asize = BITS8;
1739 oprs = itemp->operands;
1740 break;
1741 case IF_SW:
1742 asize = BITS16;
1743 oprs = itemp->operands;
1744 break;
1745 case IF_SD:
1746 asize = BITS32;
1747 oprs = itemp->operands;
1748 break;
1749 case IF_SQ:
1750 asize = BITS64;
1751 oprs = itemp->operands;
1752 break;
1753 case IF_SO:
1754 asize = BITS128;
1755 oprs = itemp->operands;
1756 break;
1757 default:
1758 break;
1759 }
1760 for (i = 0; i < MAX_OPERANDS; i++)
1761 size[i] = asize;
1762 }
1763
1764 if (itemp->flags & (IF_SM | IF_SM2)) {
1765 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1766 asize = 0;
1767 for (i = 0; i < oprs; i++) {
1768 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1769 int j;
1770 for (j = 0; j < oprs; j++)
1771 size[j] = asize;
1772 break;
1773 }
1774 }
1775 } else {
1776 oprs = itemp->operands;
1777 }
1778
1779 for (i = 0; i < itemp->operands; i++) {
1780 if (!(itemp->opd[i] & SIZE_MASK) &&
1781 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1782 return 2;
1783 }
1784
1785 /*
1786 * Check template is okay at the set cpu level
1787 */
1788 if (((itemp->flags & IF_PLEVEL) > cpu))
1789 return 3;
1790
1791 /*
1792 * Check if instruction is available in long mode
1793 */
1794 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1795 return 4;
1796
1797 /*
1798 * Check if special handling needed for Jumps
1799 */
1800 if ((uint8_t)(itemp->code[0]) >= 0370)
1801 return 99;
1802
1803 return ret;
1804 }
1805
1806 static ea *process_ea(operand * input, ea * output, int addrbits,
1807 int rfield, int32_t rflags, int forw_ref)
1808 {
1809 output->rip = FALSE;
1810
1811 /* REX flags for the rfield operand */
1812 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1813
1814 if (!(REGISTER & ~input->type)) { /* register direct */
1815 int i;
1816 int32_t f;
1817
1818 if (input->basereg < EXPR_REG_START /* Verify as Register */
1819 || input->basereg >= REG_ENUM_LIMIT)
1820 return NULL;
1821 f = regflag(input);
1822 i = regvals[input->basereg];
1823
1824 if (REG_EA & ~f)
1825 return NULL; /* Invalid EA register */
1826
1827 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1828
1829 output->sib_present = FALSE; /* no SIB necessary */
1830 output->bytes = 0; /* no offset necessary either */
1831 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1832 } else { /* it's a memory reference */
1833 if (input->basereg == -1
1834 && (input->indexreg == -1 || input->scale == 0)) {
1835 /* it's a pure offset */
1836 if (input->addr_size)
1837 addrbits = input->addr_size;
1838
1839 if (globalbits == 64 && (~input->type & IP_REL)) {
1840 int scale, index, base;
1841 output->sib_present = TRUE;
1842 scale = 0;
1843 index = 4;
1844 base = 5;
1845 output->sib = (scale << 6) | (index << 3) | base;
1846 output->bytes = 4;
1847 output->modrm = 4 | ((rfield & 7) << 3);
1848 output->rip = FALSE;
1849 } else {
1850 output->sib_present = FALSE;
1851 output->bytes = (addrbits != 16 ? 4 : 2);
1852 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1853 output->rip = globalbits == 64;
1854 }
1855 } else { /* it's an indirection */
1856 int i = input->indexreg, b = input->basereg, s = input->scale;
1857 int32_t o = input->offset, seg = input->segment;
1858 int hb = input->hintbase, ht = input->hinttype;
1859 int t;
1860 int it, bt;
1861 int32_t ix, bx; /* register flags */
1862
1863 if (s == 0)
1864 i = -1; /* make this easy, at least */
1865
1866 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1867 it = regvals[i];
1868 ix = reg_flags[i];
1869 } else {
1870 it = -1;
1871 ix = 0;
1872 }
1873
1874 if (b != -1 && b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1875 bt = regvals[b];
1876 bx = reg_flags[b];
1877 } else {
1878 bt = -1;
1879 bx = 0;
1880 }
1881
1882 /* check for a 32/64-bit memory reference... */
1883 if ((ix|bx) & (BITS32|BITS64)) {
1884 /* it must be a 32/64-bit memory reference. Firstly we have
1885 * to check that all registers involved are type E/Rxx. */
1886 int32_t sok = BITS32|BITS64;
1887
1888 if (it != -1) {
1889 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1890 sok &= ix;
1891 else
1892 return NULL;
1893 }
1894
1895 if (bt != -1) {
1896 if (REG_GPR & ~bx)
1897 return NULL; /* Invalid register */
1898 if (~sok & bx & SIZE_MASK)
1899 return NULL; /* Invalid size */
1900 sok &= ~bx;
1901 }
1902
1903 /* While we're here, ensure the user didn't specify WORD. */
1904 if (input->addr_size == 16 ||
1905 (input->addr_size == 32 && !(sok & BITS32)) ||
1906 (input->addr_size == 64 && !(sok & BITS64)))
1907 return NULL;
1908
1909 /* now reorganize base/index */
1910 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1911 ((hb == b && ht == EAH_NOTBASE)
1912 || (hb == i && ht == EAH_MAKEBASE))) {
1913 /* swap if hints say so */
1914 t = bt, bt = it, it = t;
1915 t = bx, bx = ix, ix = t;
1916 }
1917 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1918 bt = -1, bx = 0, s++;
1919 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1920 /* make single reg base, unless hint */
1921 bt = it, bx = ix, it = -1, ix = 0;
1922 }
1923 if (((s == 2 && it != REG_NUM_ESP
1924 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
1925 || s == 5 || s == 9) && bt == -1)
1926 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
1927 if (it == -1 && (bt & 7) != REG_NUM_ESP
1928 && (input->eaflags & EAF_TIMESTWO))
1929 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
1930 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
1931 if (s == 1 && it == REG_NUM_ESP) {
1932 /* swap ESP into base if scale is 1 */
1933 t = it, it = bt, bt = t;
1934 t = ix, ix = bx, bx = t;
1935 }
1936 if (it == REG_NUM_ESP
1937 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
1938 return NULL; /* wrong, for various reasons */
1939
1940 output->rex |= rexflags(it, ix, REX_X);
1941 output->rex |= rexflags(bt, bx, REX_B);
1942
1943 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
1944 /* no SIB needed */
1945 int mod, rm;
1946
1947 if (bt == -1) {
1948 rm = 5;
1949 mod = 0;
1950 } else {
1951 rm = (bt & 7);
1952 if (rm != REG_NUM_EBP && o == 0 &&
1953 seg == NO_SEG && !forw_ref &&
1954 !(input->eaflags &
1955 (EAF_BYTEOFFS | EAF_WORDOFFS)))
1956 mod = 0;
1957 else if (input->eaflags & EAF_BYTEOFFS ||
1958 (o >= -128 && o <= 127 && seg == NO_SEG
1959 && !forw_ref
1960 && !(input->eaflags & EAF_WORDOFFS)))
1961 mod = 1;
1962 else
1963 mod = 2;
1964 }
1965
1966 output->sib_present = FALSE;
1967 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
1968 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
1969 } else {
1970 /* we need a SIB */
1971 int mod, scale, index, base;
1972
1973 if (it == -1)
1974 index = 4, s = 1;
1975 else
1976 index = (it & 7);
1977
1978 switch (s) {
1979 case 1:
1980 scale = 0;
1981 break;
1982 case 2:
1983 scale = 1;
1984 break;
1985 case 4:
1986 scale = 2;
1987 break;
1988 case 8:
1989 scale = 3;
1990 break;
1991 default: /* then what the smeg is it? */
1992 return NULL; /* panic */
1993 }
1994
1995 if (bt == -1) {
1996 base = 5;
1997 mod = 0;
1998 } else {
1999 base = (bt & 7);
2000 if (base != REG_NUM_EBP && o == 0 &&
2001 seg == NO_SEG && !forw_ref &&
2002 !(input->eaflags &
2003 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2004 mod = 0;
2005 else if (input->eaflags & EAF_BYTEOFFS ||
2006 (o >= -128 && o <= 127 && seg == NO_SEG
2007 && !forw_ref
2008 && !(input->eaflags & EAF_WORDOFFS)))
2009 mod = 1;
2010 else
2011 mod = 2;
2012 }
2013
2014 output->sib_present = TRUE;
2015 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2016 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2017 output->sib = (scale << 6) | (index << 3) | base;
2018 }
2019 } else { /* it's 16-bit */
2020 int mod, rm;
2021
2022 /* check for 64-bit long mode */
2023 if (addrbits == 64)
2024 return NULL;
2025
2026 /* check all registers are BX, BP, SI or DI */
2027 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2028 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2029 && i != R_SI && i != R_DI))
2030 return NULL;
2031
2032 /* ensure the user didn't specify DWORD/QWORD */
2033 if (input->addr_size == 32 || input->addr_size == 64)
2034 return NULL;
2035
2036 if (s != 1 && i != -1)
2037 return NULL; /* no can do, in 16-bit EA */
2038 if (b == -1 && i != -1) {
2039 int tmp = b;
2040 b = i;
2041 i = tmp;
2042 } /* swap */
2043 if ((b == R_SI || b == R_DI) && i != -1) {
2044 int tmp = b;
2045 b = i;
2046 i = tmp;
2047 }
2048 /* have BX/BP as base, SI/DI index */
2049 if (b == i)
2050 return NULL; /* shouldn't ever happen, in theory */
2051 if (i != -1 && b != -1 &&
2052 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2053 return NULL; /* invalid combinations */
2054 if (b == -1) /* pure offset: handled above */
2055 return NULL; /* so if it gets to here, panic! */
2056
2057 rm = -1;
2058 if (i != -1)
2059 switch (i * 256 + b) {
2060 case R_SI * 256 + R_BX:
2061 rm = 0;
2062 break;
2063 case R_DI * 256 + R_BX:
2064 rm = 1;
2065 break;
2066 case R_SI * 256 + R_BP:
2067 rm = 2;
2068 break;
2069 case R_DI * 256 + R_BP:
2070 rm = 3;
2071 break;
2072 } else
2073 switch (b) {
2074 case R_SI:
2075 rm = 4;
2076 break;
2077 case R_DI:
2078 rm = 5;
2079 break;
2080 case R_BP:
2081 rm = 6;
2082 break;
2083 case R_BX:
2084 rm = 7;
2085 break;
2086 }
2087 if (rm == -1) /* can't happen, in theory */
2088 return NULL; /* so panic if it does */
2089
2090 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2091 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2092 mod = 0;
2093 else if (input->eaflags & EAF_BYTEOFFS ||
2094 (o >= -128 && o <= 127 && seg == NO_SEG
2095 && !forw_ref
2096 && !(input->eaflags & EAF_WORDOFFS)))
2097 mod = 1;
2098 else
2099 mod = 2;
2100
2101 output->sib_present = FALSE; /* no SIB - it's 16-bit */
2102 output->bytes = mod; /* bytes of offset needed */
2103 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2104 }
2105 }
2106 }
2107
2108 output->size = 1 + output->sib_present + output->bytes;
2109 return output;
2110 }
2111
2112 static int chsize(operand * input, int addrbits)
2113 {
2114 if (!(MEMORY & ~input->type)) {
2115 int32_t i, b;
2116
2117 if (input->indexreg < EXPR_REG_START /* Verify as Register */
2118 || input->indexreg >= REG_ENUM_LIMIT)
2119 i = 0;
2120 else
2121 i = reg_flags[input->indexreg];
2122
2123 if (input->basereg < EXPR_REG_START /* Verify as Register */
2124 || input->basereg >= REG_ENUM_LIMIT)
2125 b = 0;
2126 else
2127 b = reg_flags[input->basereg];
2128
2129 if (input->scale == 0)
2130 i = 0;
2131
2132 if (!i && !b) /* pure offset */
2133 return (input->addr_size != 0 && input->addr_size != addrbits);
2134
2135 if (!(REG32 & ~i) || !(REG32 & ~b))
2136 return (addrbits != 32);
2137 else
2138 return (addrbits == 32);
2139 } else {
2140 return 0;
2141 }
2142 }
Adding AVX-512 features