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Version 0.99.03
[nasm/avx512.git] / disasm.c
bloba6c1c7294405246584745b41014bc2642fa9291a
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include <stdio.h>
12 #include <string.h>
13 #include <limits.h>
14 #include <inttypes.h>
15
16 #include "nasm.h"
17 #include "disasm.h"
18 #include "sync.h"
19 #include "insns.h"
20
21 #include "names.c"
22
23 /*
24 * Flags that go into the `segment' field of `insn' structures
25 * during disassembly.
26 */
27 #define SEG_RELATIVE 1
28 #define SEG_32BIT 2
29 #define SEG_RMREG 4
30 #define SEG_DISP8 8
31 #define SEG_DISP16 16
32 #define SEG_DISP32 32
33 #define SEG_NODISP 64
34 #define SEG_SIGNED 128
35 #define SEG_64BIT 256
36
37 #include "regdis.c"
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t rex; /* Rex prefix present */
51 };
52
53 #define getu8(x) (*(uint8_t *)(x))
54 #if defined(__i386__) || defined(__x86_64__)
55 /* Littleendian CPU which can handle unaligned references */
56 #define getu16(x) (*(uint16_t *)(x))
57 #define getu32(x) (*(uint32_t *)(x))
58 #define getu64(x) (*(uint64_t *)(x))
59 #else
60 static uint16_t getu16(uint8_t *data)
61 {
62 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
63 }
64 static uint32_t getu32(uint8_t *data)
65 {
66 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
67 }
68 static uint64_t getu64(uint8_t *data)
69 {
70 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
71 }
72 #endif
73
74 #define gets8(x) ((int8_t)getu8(x))
75 #define gets16(x) ((int16_t)getu16(x))
76 #define gets32(x) ((int32_t)getu32(x))
77 #define gets64(x) ((int64_t)getu64(x))
78
79 /* Important: regval must already have been adjusted for rex extensions */
80 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
81 {
82 if (!(regflags & (REGISTER|REGMEM)))
83 return 0; /* Registers not permissible?! */
84
85 regflags |= REGISTER;
86
87 if (!(REG_AL & ~regflags))
88 return R_AL;
89 if (!(REG_AX & ~regflags))
90 return R_AX;
91 if (!(REG_EAX & ~regflags))
92 return R_EAX;
93 if (!(REG_RAX & ~regflags))
94 return R_RAX;
95 if (!(REG_DL & ~regflags))
96 return R_DL;
97 if (!(REG_DX & ~regflags))
98 return R_DX;
99 if (!(REG_EDX & ~regflags))
100 return R_EDX;
101 if (!(REG_RDX & ~regflags))
102 return R_RDX;
103 if (!(REG_CL & ~regflags))
104 return R_CL;
105 if (!(REG_CX & ~regflags))
106 return R_CX;
107 if (!(REG_ECX & ~regflags))
108 return R_ECX;
109 if (!(REG_RCX & ~regflags))
110 return R_RCX;
111 if (!(FPU0 & ~regflags))
112 return R_ST0;
113 if (!(REG_CS & ~regflags))
114 return (regval == 1) ? R_CS : 0;
115 if (!(REG_DESS & ~regflags))
116 return (regval == 0 || regval == 2
117 || regval == 3 ? rd_sreg[regval] : 0);
118 if (!(REG_FSGS & ~regflags))
119 return (regval == 4 || regval == 5 ? rd_sreg[regval] : 0);
120 if (!(REG_SEG67 & ~regflags))
121 return (regval == 6 || regval == 7 ? rd_sreg[regval] : 0);
122
123 /* All the entries below look up regval in an 16-entry array */
124 if (regval < 0 || regval > 15)
125 return 0;
126
127 if (!(REG8 & ~regflags)) {
128 if (rex & REX_P)
129 return rd_reg8_rex[regval];
130 else
131 return rd_reg8[regval];
132 }
133 if (!(REG16 & ~regflags))
134 return rd_reg16[regval];
135 if (!(REG32 & ~regflags))
136 return rd_reg32[regval];
137 if (!(REG64 & ~regflags))
138 return rd_reg64[regval];
139 if (!(REG_SREG & ~regflags))
140 return rd_sreg[regval & 7]; /* Ignore REX */
141 if (!(REG_CREG & ~regflags))
142 return rd_creg[regval];
143 if (!(REG_DREG & ~regflags))
144 return rd_dreg[regval];
145 if (!(REG_TREG & ~regflags)) {
146 if (rex & REX_P)
147 return 0; /* TR registers are ill-defined with rex */
148 return rd_treg[regval];
149 }
150 if (!(FPUREG & ~regflags))
151 return rd_fpureg[regval & 7]; /* Ignore REX */
152 if (!(MMXREG & ~regflags))
153 return rd_mmxreg[regval & 7]; /* Ignore REX */
154 if (!(XMMREG & ~regflags))
155 return rd_xmmreg[regval];
156
157 return 0;
158 }
159
160 static const char *whichcond(int condval)
161 {
162 static int conds[] = {
163 C_O, C_NO, C_C, C_NC, C_Z, C_NZ, C_NA, C_A,
164 C_S, C_NS, C_PE, C_PO, C_L, C_NL, C_NG, C_G
165 };
166 return conditions[conds[condval]];
167 }
168
169 /*
170 * Process a DREX suffix
171 */
172 static uint8_t *do_drex(uint8_t *data, insn *ins)
173 {
174 uint8_t drex = *data++;
175 operand *dst = &ins->oprs[ins->drexdst];
176
177 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
178 return NULL; /* OC0 mismatch */
179 ins->rex = (ins->rex & ~7) | (drex & 7);
180
181 dst->segment = SEG_RMREG;
182 dst->basereg = drex >> 4;
183 return data;
184 }
185
186
187 /*
188 * Process an effective address (ModRM) specification.
189 */
190 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
191 int segsize, operand * op, insn *ins)
192 {
193 int mod, rm, scale, index, base;
194 int rex;
195 uint8_t sib = 0;
196
197 mod = (modrm >> 6) & 03;
198 rm = modrm & 07;
199
200 if (mod != 3 && rm == 4 && asize != 16)
201 sib = *data++;
202
203 if (ins->rex & REX_D) {
204 data = do_drex(data, ins);
205 if (!data)
206 return NULL;
207 }
208 rex = ins->rex;
209
210 if (mod == 3) { /* pure register version */
211 op->basereg = rm+(rex & REX_B ? 8 : 0);
212 op->segment |= SEG_RMREG;
213 return data;
214 }
215
216 op->addr_size = 0;
217 op->eaflags = 0;
218
219 if (asize == 16) {
220 /*
221 * <mod> specifies the displacement size (none, byte or
222 * word), and <rm> specifies the register combination.
223 * Exception: mod=0,rm=6 does not specify [BP] as one might
224 * expect, but instead specifies [disp16].
225 */
226 op->indexreg = op->basereg = -1;
227 op->scale = 1; /* always, in 16 bits */
228 switch (rm) {
229 case 0:
230 op->basereg = R_BX;
231 op->indexreg = R_SI;
232 break;
233 case 1:
234 op->basereg = R_BX;
235 op->indexreg = R_DI;
236 break;
237 case 2:
238 op->basereg = R_BP;
239 op->indexreg = R_SI;
240 break;
241 case 3:
242 op->basereg = R_BP;
243 op->indexreg = R_DI;
244 break;
245 case 4:
246 op->basereg = R_SI;
247 break;
248 case 5:
249 op->basereg = R_DI;
250 break;
251 case 6:
252 op->basereg = R_BP;
253 break;
254 case 7:
255 op->basereg = R_BX;
256 break;
257 }
258 if (rm == 6 && mod == 0) { /* special case */
259 op->basereg = -1;
260 if (segsize != 16)
261 op->addr_size = 16;
262 mod = 2; /* fake disp16 */
263 }
264 switch (mod) {
265 case 0:
266 op->segment |= SEG_NODISP;
267 break;
268 case 1:
269 op->segment |= SEG_DISP8;
270 op->offset = (int8_t)*data++;
271 break;
272 case 2:
273 op->segment |= SEG_DISP16;
274 op->offset = *data++;
275 op->offset |= ((unsigned)*data++) << 8;
276 break;
277 }
278 return data;
279 } else {
280 /*
281 * Once again, <mod> specifies displacement size (this time
282 * none, byte or *dword*), while <rm> specifies the base
283 * register. Again, [EBP] is missing, replaced by a pure
284 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
285 * and RIP-relative addressing in 64-bit mode.
286 *
287 * However, rm=4
288 * indicates not a single base register, but instead the
289 * presence of a SIB byte...
290 */
291 int a64 = asize == 64;
292
293 op->indexreg = -1;
294
295 if (a64)
296 op->basereg = rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
297 else
298 op->basereg = rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
299
300 if (rm == 5 && mod == 0) {
301 if (segsize == 64) {
302 op->eaflags |= EAF_REL;
303 op->segment |= SEG_RELATIVE;
304 mod = 2; /* fake disp32 */
305 }
306
307 if (asize != 64)
308 op->addr_size = asize;
309
310 op->basereg = -1;
311 mod = 2; /* fake disp32 */
312 }
313
314 if (rm == 4) { /* process SIB */
315 scale = (sib >> 6) & 03;
316 index = (sib >> 3) & 07;
317 base = sib & 07;
318
319 op->scale = 1 << scale;
320
321 if (index == 4)
322 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
323 else if (a64)
324 op->indexreg = rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
325 else
326 op->indexreg = rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
327
328 if (base == 5 && mod == 0) {
329 op->basereg = -1;
330 mod = 2; /* Fake disp32 */
331 } else if (a64)
332 op->basereg = rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
333 else
334 op->basereg = rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
335
336 if (segsize != 32)
337 op->addr_size = 32;
338 }
339
340 switch (mod) {
341 case 0:
342 op->segment |= SEG_NODISP;
343 break;
344 case 1:
345 op->segment |= SEG_DISP8;
346 op->offset = gets8(data);
347 data++;
348 break;
349 case 2:
350 op->segment |= SEG_DISP32;
351 op->offset = getu32(data);
352 data += 4;
353 break;
354 }
355 return data;
356 }
357 }
358
359 /*
360 * Determine whether the instruction template in t corresponds to the data
361 * stream in data. Return the number of bytes matched if so.
362 */
363 static int matches(const struct itemplate *t, uint8_t *data,
364 const struct prefix_info *prefix, int segsize, insn *ins)
365 {
366 uint8_t *r = (uint8_t *)(t->code);
367 uint8_t *origdata = data;
368 int a_used = FALSE, o_used = FALSE;
369 enum prefixes drep = 0;
370 uint8_t lock = prefix->lock;
371 int osize = prefix->osize;
372 int asize = prefix->asize;
373 int i;
374
375 for (i = 0; i < MAX_OPERANDS; i++) {
376 ins->oprs[i].segment = ins->oprs[i].addr_size =
377 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
378 }
379 ins->condition = -1;
380 ins->rex = prefix->rex;
381
382 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
383 return FALSE;
384
385 if (prefix->rep == 0xF2)
386 drep = P_REPNE;
387 else if (prefix->rep == 0xF3)
388 drep = P_REP;
389
390 while (*r) {
391 int c = *r++;
392
393 /* FIX: change this into a switch */
394 if (c >= 01 && c <= 03) {
395 while (c--)
396 if (*r++ != *data++)
397 return FALSE;
398 } else if (c == 04) {
399 switch (*data++) {
400 case 0x07:
401 ins->oprs[0].basereg = 0;
402 break;
403 case 0x17:
404 ins->oprs[0].basereg = 2;
405 break;
406 case 0x1F:
407 ins->oprs[0].basereg = 3;
408 break;
409 default:
410 return FALSE;
411 }
412 } else if (c == 05) {
413 switch (*data++) {
414 case 0xA1:
415 ins->oprs[0].basereg = 4;
416 break;
417 case 0xA9:
418 ins->oprs[0].basereg = 5;
419 break;
420 default:
421 return FALSE;
422 }
423 } else if (c == 06) {
424 switch (*data++) {
425 case 0x06:
426 ins->oprs[0].basereg = 0;
427 break;
428 case 0x0E:
429 ins->oprs[0].basereg = 1;
430 break;
431 case 0x16:
432 ins->oprs[0].basereg = 2;
433 break;
434 case 0x1E:
435 ins->oprs[0].basereg = 3;
436 break;
437 default:
438 return FALSE;
439 }
440 } else if (c == 07) {
441 switch (*data++) {
442 case 0xA0:
443 ins->oprs[0].basereg = 4;
444 break;
445 case 0xA8:
446 ins->oprs[0].basereg = 5;
447 break;
448 default:
449 return FALSE;
450 }
451 } else if (c >= 010 && c <= 013) {
452 int t = *r++, d = *data++;
453 if (d < t || d > t + 7)
454 return FALSE;
455 else {
456 ins->oprs[c - 010].basereg = (d-t)+
457 (ins->rex & REX_B ? 8 : 0);
458 ins->oprs[c - 010].segment |= SEG_RMREG;
459 }
460 } else if (c >= 014 && c <= 017) {
461 ins->oprs[c - 014].offset = (int8_t)*data++;
462 ins->oprs[c - 014].segment |= SEG_SIGNED;
463 } else if (c >= 020 && c <= 023) {
464 ins->oprs[c - 020].offset = *data++;
465 } else if (c >= 024 && c <= 027) {
466 ins->oprs[c - 024].offset = *data++;
467 } else if (c >= 030 && c <= 033) {
468 ins->oprs[c - 030].offset = getu16(data);
469 data += 2;
470 } else if (c >= 034 && c <= 037) {
471 if (osize == 32) {
472 ins->oprs[c - 034].offset = getu32(data);
473 data += 4;
474 } else {
475 ins->oprs[c - 034].offset = getu16(data);
476 data += 2;
477 }
478 if (segsize != asize)
479 ins->oprs[c - 034].addr_size = asize;
480 } else if (c >= 040 && c <= 043) {
481 ins->oprs[c - 040].offset = getu32(data);
482 data += 4;
483 } else if (c >= 044 && c <= 047) {
484 switch (asize) {
485 case 16:
486 ins->oprs[c - 044].offset = getu16(data);
487 data += 2;
488 break;
489 case 32:
490 ins->oprs[c - 044].offset = getu32(data);
491 data += 4;
492 break;
493 case 64:
494 ins->oprs[c - 044].offset = getu64(data);
495 data += 8;
496 break;
497 }
498 if (segsize != asize)
499 ins->oprs[c - 044].addr_size = asize;
500 } else if (c >= 050 && c <= 053) {
501 ins->oprs[c - 050].offset = gets8(data++);
502 ins->oprs[c - 050].segment |= SEG_RELATIVE;
503 } else if (c >= 054 && c <= 057) {
504 ins->oprs[c - 054].offset = getu64(data);
505 data += 8;
506 } else if (c >= 060 && c <= 063) {
507 ins->oprs[c - 060].offset = gets16(data);
508 data += 2;
509 ins->oprs[c - 060].segment |= SEG_RELATIVE;
510 ins->oprs[c - 060].segment &= ~SEG_32BIT;
511 } else if (c >= 064 && c <= 067) {
512 if (osize == 16) {
513 ins->oprs[c - 064].offset = getu16(data);
514 data += 2;
515 ins->oprs[c - 064].segment &= ~(SEG_32BIT|SEG_64BIT);
516 } else if (osize == 32) {
517 ins->oprs[c - 064].offset = getu32(data);
518 data += 4;
519 ins->oprs[c - 064].segment &= ~SEG_64BIT;
520 ins->oprs[c - 064].segment |= SEG_32BIT;
521 }
522 if (segsize != osize) {
523 ins->oprs[c - 064].type =
524 (ins->oprs[c - 064].type & ~SIZE_MASK)
525 | ((osize == 16) ? BITS16 : BITS32);
526 }
527 } else if (c >= 070 && c <= 073) {
528 ins->oprs[c - 070].offset = getu32(data);
529 data += 4;
530 ins->oprs[c - 070].segment |= SEG_32BIT | SEG_RELATIVE;
531 } else if (c >= 0100 && c < 0140) {
532 int modrm = *data++;
533 ins->oprs[c & 07].segment |= SEG_RMREG;
534 data = do_ea(data, modrm, asize, segsize,
535 &ins->oprs[(c >> 3) & 07], ins);
536 if (!data)
537 return FALSE;
538 ins->oprs[c & 07].basereg = ((modrm >> 3)&7)+
539 (ins->rex & REX_R ? 8 : 0);
540 } else if (c >= 0140 && c <= 0143) {
541 ins->oprs[c - 0140].offset = getu16(data);
542 data += 2;
543 } else if (c >= 0150 && c <= 0153) {
544 ins->oprs[c - 0150].offset = getu32(data);
545 data += 4;
546 } else if (c >= 0160 && c <= 0167) {
547 ins->rex |= (c & 4) ? REX_D|REX_OC : REX_D;
548 ins->drexdst = c & 3;
549 } else if (c == 0170) {
550 if (*data++)
551 return FALSE;
552 } else if (c == 0171) {
553 data = do_drex(data, ins);
554 if (!data)
555 return FALSE;
556 } else if (c >= 0200 && c <= 0277) {
557 int modrm = *data++;
558 if (((modrm >> 3) & 07) != (c & 07))
559 return FALSE; /* spare field doesn't match up */
560 data = do_ea(data, modrm, asize, segsize,
561 &ins->oprs[(c >> 3) & 07], ins);
562 if (!data)
563 return FALSE;
564 } else if (c >= 0300 && c <= 0303) {
565 a_used = TRUE;
566 } else if (c == 0310) {
567 if (asize != 16)
568 return FALSE;
569 else
570 a_used = TRUE;
571 } else if (c == 0311) {
572 if (asize == 16)
573 return FALSE;
574 else
575 a_used = TRUE;
576 } else if (c == 0312) {
577 if (asize != segsize)
578 return FALSE;
579 else
580 a_used = TRUE;
581 } else if (c == 0313) {
582 if (asize != 64)
583 return FALSE;
584 else
585 a_used = TRUE;
586 } else if (c == 0320) {
587 if (osize != 16)
588 return FALSE;
589 else
590 o_used = TRUE;
591 } else if (c == 0321) {
592 if (osize != 32)
593 return FALSE;
594 else
595 o_used = TRUE;
596 } else if (c == 0322) {
597 if (osize != (segsize == 16) ? 16 : 32)
598 return FALSE;
599 else
600 o_used = TRUE;
601 } else if (c == 0323) {
602 ins->rex |= REX_W; /* 64-bit only instruction */
603 osize = 64;
604 } else if (c == 0324) {
605 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
606 return FALSE;
607 } else if (c == 0330) {
608 int t = *r++, d = *data++;
609 if (d < t || d > t + 15)
610 return FALSE;
611 else
612 ins->condition = d - t;
613 } else if (c == 0331) {
614 if (prefix->rep)
615 return FALSE;
616 } else if (c == 0332) {
617 if (prefix->rep != 0xF2)
618 return FALSE;
619 } else if (c == 0333) {
620 if (prefix->rep != 0xF3)
621 return FALSE;
622 drep = 0;
623 } else if (c == 0334) {
624 if (lock) {
625 ins->rex |= REX_R;
626 lock = 0;
627 }
628 } else if (c == 0335) {
629 if (drep == P_REP)
630 drep = P_REPE;
631 } else if (c == 0364) {
632 if (prefix->osp)
633 return FALSE;
634 } else if (c == 0365) {
635 if (prefix->asp)
636 return FALSE;
637 } else if (c == 0366) {
638 if (!prefix->osp)
639 return FALSE;
640 o_used = TRUE;
641 } else if (c == 0367) {
642 if (!prefix->asp)
643 return FALSE;
644 o_used = TRUE;
645 }
646 }
647
648 /* REX cannot be combined with DREX */
649 if ((ins->rex & REX_D) && (prefix->rex))
650 return FALSE;
651
652 /*
653 * Check for unused rep or a/o prefixes.
654 */
655 ins->nprefix = 0;
656 if (lock)
657 ins->prefixes[ins->nprefix++] = P_LOCK;
658 if (drep)
659 ins->prefixes[ins->nprefix++] = drep;
660 if (!a_used && asize != segsize)
661 ins->prefixes[ins->nprefix++] = asize == 16 ? P_A16 : P_A32;
662 if (!o_used && osize == ((segsize == 16) ? 32 : 16))
663 ins->prefixes[ins->nprefix++] = osize == 16 ? P_O16 : P_O32;
664
665 /* Fix: check for redundant REX prefixes */
666
667 return data - origdata;
668 }
669
670 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
671 int32_t offset, int autosync, uint32_t prefer)
672 {
673 const struct itemplate * const *p, * const *best_p;
674 const struct disasm_index *ix;
675 uint8_t *dp;
676 int length, best_length = 0;
677 char *segover;
678 int i, slen, colon, n;
679 uint8_t *origdata;
680 int works;
681 insn tmp_ins, ins;
682 uint32_t goodness, best;
683 int best_pref;
684 struct prefix_info prefix;
685
686 memset(&ins, 0, sizeof ins);
687
688 /*
689 * Scan for prefixes.
690 */
691 memset(&prefix, 0, sizeof prefix);
692 prefix.asize = segsize;
693 prefix.osize = (segsize == 64) ? 32 : segsize;
694 segover = NULL;
695 origdata = data;
696 for (;;) {
697 if (*data == 0xF3 || *data == 0xF2)
698 prefix.rep = *data++;
699 else if (*data == 0xF0)
700 prefix.lock = *data++;
701 else if (*data == 0x2E)
702 segover = "cs", prefix.seg = *data++;
703 else if (*data == 0x36)
704 segover = "ss", prefix.seg = *data++;
705 else if (*data == 0x3E)
706 segover = "ds", prefix.seg = *data++;
707 else if (*data == 0x26)
708 segover = "es", prefix.seg = *data++;
709 else if (*data == 0x64)
710 segover = "fs", prefix.seg = *data++;
711 else if (*data == 0x65)
712 segover = "gs", prefix.seg = *data++;
713 else if (*data == 0x66) {
714 prefix.osize = (segsize == 16) ? 32 : 16;
715 prefix.osp = *data++;
716 } else if (*data == 0x67) {
717 prefix.asize = (segsize == 32) ? 16 : 32;
718 prefix.asp = *data++;
719 } else if (segsize == 64 && (*data & 0xf0) == REX_P) {
720 prefix.rex = *data++;
721 if (prefix.rex & REX_W)
722 prefix.osize = 64;
723 break; /* REX is always the last prefix */
724 } else {
725 break;
726 }
727 }
728
729 best = -1; /* Worst possible */
730 best_p = NULL;
731 best_pref = INT_MAX;
732
733 dp = data;
734 ix = itable + *dp++;
735 while (ix->n == (size_t)-1) {
736 ix = (const struct disasm_index *)ix->p + *dp++;
737 }
738
739 p = (const struct itemplate * const *)ix->p;
740 for (n = ix->n; n; n--, p++) {
741 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
742 works = TRUE;
743 /*
744 * Final check to make sure the types of r/m match up.
745 * XXX: Need to make sure this is actually correct.
746 */
747 for (i = 0; i < (*p)->operands; i++) {
748 if (!((*p)->opd[i] & SAME_AS) &&
749 (
750 /* If it's a mem-only EA but we have a register, die. */
751 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
752 !(MEMORY & ~(*p)->opd[i])) ||
753 /* If it's a reg-only EA but we have a memory ref, die. */
754 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
755 !(REG_EA & ~(*p)->opd[i]) &&
756 !((*p)->opd[i] & REG_SMASK)) ||
757 /* Register type mismatch (eg FS vs REG_DESS): die. */
758 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
759 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
760 !whichreg((*p)->opd[i],
761 tmp_ins.oprs[i].basereg, tmp_ins.rex))
762 )) {
763 works = FALSE;
764 break;
765 }
766 }
767
768 /*
769 * Note: we always prefer instructions which incorporate
770 * prefixes in the instructions themselves. This is to allow
771 * e.g. PAUSE to be preferred to REP NOP, and deal with
772 * MMX/SSE instructions where prefixes are used to select
773 * between MMX and SSE register sets or outright opcode
774 * selection.
775 */
776 if (works) {
777 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
778 if (tmp_ins.nprefix < best_pref ||
779 (tmp_ins.nprefix == best_pref && goodness < best)) {
780 /* This is the best one found so far */
781 best = goodness;
782 best_p = p;
783 best_pref = tmp_ins.nprefix;
784 best_length = length;
785 ins = tmp_ins;
786 }
787 }
788 }
789 }
790
791 if (!best_p)
792 return 0; /* no instruction was matched */
793
794 /* Pick the best match */
795 p = best_p;
796 length = best_length;
797
798 slen = 0;
799
800 /* TODO: snprintf returns the value that the string would have if
801 * the buffer were long enough, and not the actual length of
802 * the returned string, so each instance of using the return
803 * value of snprintf should actually be checked to assure that
804 * the return value is "sane." Maybe a macro wrapper could
805 * be used for that purpose.
806 */
807 for (i = 0; i < ins.nprefix; i++)
808 switch (ins.prefixes[i]) {
809 case P_LOCK:
810 slen += snprintf(output + slen, outbufsize - slen, "lock ");
811 break;
812 case P_REP:
813 slen += snprintf(output + slen, outbufsize - slen, "rep ");
814 break;
815 case P_REPE:
816 slen += snprintf(output + slen, outbufsize - slen, "repe ");
817 break;
818 case P_REPNE:
819 slen += snprintf(output + slen, outbufsize - slen, "repne ");
820 break;
821 case P_A16:
822 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
823 break;
824 case P_A32:
825 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
826 break;
827 case P_O16:
828 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
829 break;
830 case P_O32:
831 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
832 break;
833 default:
834 break;
835 }
836
837 for (i = 0; i < (int)elements(ico); i++)
838 if ((*p)->opcode == ico[i]) {
839 slen +=
840 snprintf(output + slen, outbufsize - slen, "%s%s", icn[i],
841 whichcond(ins.condition));
842 break;
843 }
844 if (i >= (int)elements(ico))
845 slen +=
846 snprintf(output + slen, outbufsize - slen, "%s",
847 insn_names[(*p)->opcode]);
848 colon = FALSE;
849 length += data - origdata; /* fix up for prefixes */
850 for (i = 0; i < (*p)->operands; i++) {
851 opflags_t t = (*p)->opd[i];
852 const operand *o = &ins.oprs[i];
853 int64_t offs;
854
855 if (t & SAME_AS) {
856 o = &ins.oprs[t & ~SAME_AS];
857 t = (*p)->opd[t & ~SAME_AS];
858 }
859
860 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
861
862 offs = o->offset;
863 if (o->segment & SEG_RELATIVE) {
864 offs += offset + length;
865 /*
866 * sort out wraparound
867 */
868 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
869 offs &= 0xffff;
870 /*
871 * add sync marker, if autosync is on
872 */
873 if (autosync)
874 add_sync(offs, 0L);
875 }
876
877 if (t & COLON)
878 colon = TRUE;
879 else
880 colon = FALSE;
881
882 if ((t & (REGISTER | FPUREG)) ||
883 (o->segment & SEG_RMREG)) {
884 enum reg_enum reg;
885 reg = whichreg(t, o->basereg, ins.rex);
886 if (t & TO)
887 slen += snprintf(output + slen, outbufsize - slen, "to ");
888 slen += snprintf(output + slen, outbufsize - slen, "%s",
889 reg_names[reg - EXPR_REG_START]);
890 } else if (!(UNITY & ~t)) {
891 output[slen++] = '1';
892 } else if (t & IMMEDIATE) {
893 if (t & BITS8) {
894 slen +=
895 snprintf(output + slen, outbufsize - slen, "byte ");
896 if (o->segment & SEG_SIGNED) {
897 if (offs < 0) {
898 offs *= -1;
899 output[slen++] = '-';
900 } else
901 output[slen++] = '+';
902 }
903 } else if (t & BITS16) {
904 slen +=
905 snprintf(output + slen, outbufsize - slen, "word ");
906 } else if (t & BITS32) {
907 slen +=
908 snprintf(output + slen, outbufsize - slen, "dword ");
909 } else if (t & BITS64) {
910 slen +=
911 snprintf(output + slen, outbufsize - slen, "qword ");
912 } else if (t & NEAR) {
913 slen +=
914 snprintf(output + slen, outbufsize - slen, "near ");
915 } else if (t & SHORT) {
916 slen +=
917 snprintf(output + slen, outbufsize - slen, "short ");
918 }
919 slen +=
920 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
921 offs);
922 } else if (!(MEM_OFFS & ~t)) {
923 slen +=
924 snprintf(output + slen, outbufsize - slen, "[%s%s%s0x%"PRIx64"]",
925 (segover ? segover : ""),
926 (segover ? ":" : ""),
927 (o->addr_size ==
928 32 ? "dword " : o->addr_size ==
929 16 ? "word " : ""), offs);
930 segover = NULL;
931 } else if (!(REGMEM & ~t)) {
932 int started = FALSE;
933 if (t & BITS8)
934 slen +=
935 snprintf(output + slen, outbufsize - slen, "byte ");
936 if (t & BITS16)
937 slen +=
938 snprintf(output + slen, outbufsize - slen, "word ");
939 if (t & BITS32)
940 slen +=
941 snprintf(output + slen, outbufsize - slen, "dword ");
942 if (t & BITS64)
943 slen +=
944 snprintf(output + slen, outbufsize - slen, "qword ");
945 if (t & BITS80)
946 slen +=
947 snprintf(output + slen, outbufsize - slen, "tword ");
948 if (t & FAR)
949 slen += snprintf(output + slen, outbufsize - slen, "far ");
950 if (t & NEAR)
951 slen +=
952 snprintf(output + slen, outbufsize - slen, "near ");
953 output[slen++] = '[';
954 if (o->addr_size)
955 slen += snprintf(output + slen, outbufsize - slen, "%s",
956 (o->addr_size == 64 ? "qword " :
957 o->addr_size == 32 ? "dword " :
958 o->addr_size == 16 ? "word " :
959 ""));
960 if (o->eaflags & EAF_REL)
961 slen += snprintf(output + slen, outbufsize - slen, "rel ");
962 if (segover) {
963 slen +=
964 snprintf(output + slen, outbufsize - slen, "%s:",
965 segover);
966 segover = NULL;
967 }
968 if (o->basereg != -1) {
969 slen += snprintf(output + slen, outbufsize - slen, "%s",
970 reg_names[(o->basereg -
971 EXPR_REG_START)]);
972 started = TRUE;
973 }
974 if (o->indexreg != -1) {
975 if (started)
976 output[slen++] = '+';
977 slen += snprintf(output + slen, outbufsize - slen, "%s",
978 reg_names[(o->indexreg -
979 EXPR_REG_START)]);
980 if (o->scale > 1)
981 slen +=
982 snprintf(output + slen, outbufsize - slen, "*%d",
983 o->scale);
984 started = TRUE;
985 }
986 if (o->segment & SEG_DISP8) {
987 int minus = 0;
988 int8_t offset = offs;
989 if (offset < 0) {
990 minus = 1;
991 offset = -offset;
992 }
993 slen +=
994 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
995 minus ? "-" : "+", offset);
996 } else if (o->segment & SEG_DISP16) {
997 int minus = 0;
998 int16_t offset = offs;
999 if (offset < 0) {
1000 minus = 1;
1001 offset = -offset;
1002 }
1003 slen +=
1004 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx16"",
1005 minus ? "-" : started ? "+" : "", offset);
1006 } else if (o->segment & SEG_DISP32) {
1007 char *prefix = "";
1008 int32_t offset = offs;
1009 if (offset < 0) {
1010 offset = -offset;
1011 prefix = "-";
1012 } else {
1013 prefix = started ? "+" : "";
1014 }
1015 slen +=
1016 snprintf(output + slen, outbufsize - slen,
1017 "%s0x%"PRIx32"", prefix, offset);
1018 }
1019 output[slen++] = ']';
1020 } else {
1021 slen +=
1022 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1023 i);
1024 }
1025 }
1026 output[slen] = '\0';
1027 if (segover) { /* unused segment override */
1028 char *p = output;
1029 int count = slen + 1;
1030 while (count--)
1031 p[count + 3] = p[count];
1032 strncpy(output, segover, 2);
1033 output[2] = ' ';
1034 }
1035 return length;
1036 }
1037
1038 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1039 {
1040 snprintf(output, outbufsize, "db 0x%02X", *data);
1041 return 1;
1042 }
Adding AVX-512 features