?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
BR 2557903: fix disassembly of a set of SSE MOV* instructions
[nasm/avx512.git] / disasm.c
blob63fd37be8f484f8c470b5c441371b980cc6b434a
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t wait; /* WAIT "prefix" present */
50 uint8_t lock; /* Lock prefix present */
51 uint8_t vex[3]; /* VEX prefix present */
52 uint8_t vex_m; /* VEX.M field */
53 uint8_t vex_v;
54 uint8_t vex_lp; /* VEX.LP fields */
55 uint32_t rex; /* REX prefix present */
56 };
57
58 #define getu8(x) (*(uint8_t *)(x))
59 #if X86_MEMORY
60 /* Littleendian CPU which can handle unaligned references */
61 #define getu16(x) (*(uint16_t *)(x))
62 #define getu32(x) (*(uint32_t *)(x))
63 #define getu64(x) (*(uint64_t *)(x))
64 #else
65 static uint16_t getu16(uint8_t *data)
66 {
67 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
68 }
69 static uint32_t getu32(uint8_t *data)
70 {
71 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
72 }
73 static uint64_t getu64(uint8_t *data)
74 {
75 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
76 }
77 #endif
78
79 #define gets8(x) ((int8_t)getu8(x))
80 #define gets16(x) ((int16_t)getu16(x))
81 #define gets32(x) ((int32_t)getu32(x))
82 #define gets64(x) ((int64_t)getu64(x))
83
84 /* Important: regval must already have been adjusted for rex extensions */
85 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
86 {
87 if (!(regflags & (REGISTER|REGMEM)))
88 return 0; /* Registers not permissible?! */
89
90 regflags |= REGISTER;
91
92 if (!(REG_AL & ~regflags))
93 return R_AL;
94 if (!(REG_AX & ~regflags))
95 return R_AX;
96 if (!(REG_EAX & ~regflags))
97 return R_EAX;
98 if (!(REG_RAX & ~regflags))
99 return R_RAX;
100 if (!(REG_DL & ~regflags))
101 return R_DL;
102 if (!(REG_DX & ~regflags))
103 return R_DX;
104 if (!(REG_EDX & ~regflags))
105 return R_EDX;
106 if (!(REG_RDX & ~regflags))
107 return R_RDX;
108 if (!(REG_CL & ~regflags))
109 return R_CL;
110 if (!(REG_CX & ~regflags))
111 return R_CX;
112 if (!(REG_ECX & ~regflags))
113 return R_ECX;
114 if (!(REG_RCX & ~regflags))
115 return R_RCX;
116 if (!(FPU0 & ~regflags))
117 return R_ST0;
118 if (!(XMM0 & ~regflags))
119 return R_XMM0;
120 if (!(YMM0 & ~regflags))
121 return R_YMM0;
122 if (!(REG_CS & ~regflags))
123 return (regval == 1) ? R_CS : 0;
124 if (!(REG_DESS & ~regflags))
125 return (regval == 0 || regval == 2
126 || regval == 3 ? nasm_rd_sreg[regval] : 0);
127 if (!(REG_FSGS & ~regflags))
128 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
129 if (!(REG_SEG67 & ~regflags))
130 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
131
132 /* All the entries below look up regval in an 16-entry array */
133 if (regval < 0 || regval > 15)
134 return 0;
135
136 if (!(REG8 & ~regflags)) {
137 if (rex & REX_P)
138 return nasm_rd_reg8_rex[regval];
139 else
140 return nasm_rd_reg8[regval];
141 }
142 if (!(REG16 & ~regflags))
143 return nasm_rd_reg16[regval];
144 if (!(REG32 & ~regflags))
145 return nasm_rd_reg32[regval];
146 if (!(REG64 & ~regflags))
147 return nasm_rd_reg64[regval];
148 if (!(REG_SREG & ~regflags))
149 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
150 if (!(REG_CREG & ~regflags))
151 return nasm_rd_creg[regval];
152 if (!(REG_DREG & ~regflags))
153 return nasm_rd_dreg[regval];
154 if (!(REG_TREG & ~regflags)) {
155 if (rex & REX_P)
156 return 0; /* TR registers are ill-defined with rex */
157 return nasm_rd_treg[regval];
158 }
159 if (!(FPUREG & ~regflags))
160 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
161 if (!(MMXREG & ~regflags))
162 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
163 if (!(XMMREG & ~regflags))
164 return nasm_rd_xmmreg[regval];
165 if (!(YMMREG & ~regflags))
166 return nasm_rd_ymmreg[regval];
167
168 return 0;
169 }
170
171 /*
172 * Process a DREX suffix
173 */
174 static uint8_t *do_drex(uint8_t *data, insn *ins)
175 {
176 uint8_t drex = *data++;
177 operand *dst = &ins->oprs[ins->drexdst];
178
179 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
180 return NULL; /* OC0 mismatch */
181 ins->rex = (ins->rex & ~7) | (drex & 7);
182
183 dst->segment = SEG_RMREG;
184 dst->basereg = drex >> 4;
185 return data;
186 }
187
188
189 /*
190 * Process an effective address (ModRM) specification.
191 */
192 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
193 int segsize, operand * op, insn *ins)
194 {
195 int mod, rm, scale, index, base;
196 int rex;
197 uint8_t sib = 0;
198
199 mod = (modrm >> 6) & 03;
200 rm = modrm & 07;
201
202 if (mod != 3 && rm == 4 && asize != 16)
203 sib = *data++;
204
205 if (ins->rex & REX_D) {
206 data = do_drex(data, ins);
207 if (!data)
208 return NULL;
209 }
210 rex = ins->rex;
211
212 if (mod == 3) { /* pure register version */
213 op->basereg = rm+(rex & REX_B ? 8 : 0);
214 op->segment |= SEG_RMREG;
215 return data;
216 }
217
218 op->disp_size = 0;
219 op->eaflags = 0;
220
221 if (asize == 16) {
222 /*
223 * <mod> specifies the displacement size (none, byte or
224 * word), and <rm> specifies the register combination.
225 * Exception: mod=0,rm=6 does not specify [BP] as one might
226 * expect, but instead specifies [disp16].
227 */
228 op->indexreg = op->basereg = -1;
229 op->scale = 1; /* always, in 16 bits */
230 switch (rm) {
231 case 0:
232 op->basereg = R_BX;
233 op->indexreg = R_SI;
234 break;
235 case 1:
236 op->basereg = R_BX;
237 op->indexreg = R_DI;
238 break;
239 case 2:
240 op->basereg = R_BP;
241 op->indexreg = R_SI;
242 break;
243 case 3:
244 op->basereg = R_BP;
245 op->indexreg = R_DI;
246 break;
247 case 4:
248 op->basereg = R_SI;
249 break;
250 case 5:
251 op->basereg = R_DI;
252 break;
253 case 6:
254 op->basereg = R_BP;
255 break;
256 case 7:
257 op->basereg = R_BX;
258 break;
259 }
260 if (rm == 6 && mod == 0) { /* special case */
261 op->basereg = -1;
262 if (segsize != 16)
263 op->disp_size = 16;
264 mod = 2; /* fake disp16 */
265 }
266 switch (mod) {
267 case 0:
268 op->segment |= SEG_NODISP;
269 break;
270 case 1:
271 op->segment |= SEG_DISP8;
272 op->offset = (int8_t)*data++;
273 break;
274 case 2:
275 op->segment |= SEG_DISP16;
276 op->offset = *data++;
277 op->offset |= ((unsigned)*data++) << 8;
278 break;
279 }
280 return data;
281 } else {
282 /*
283 * Once again, <mod> specifies displacement size (this time
284 * none, byte or *dword*), while <rm> specifies the base
285 * register. Again, [EBP] is missing, replaced by a pure
286 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
287 * and RIP-relative addressing in 64-bit mode.
288 *
289 * However, rm=4
290 * indicates not a single base register, but instead the
291 * presence of a SIB byte...
292 */
293 int a64 = asize == 64;
294
295 op->indexreg = -1;
296
297 if (a64)
298 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
299 else
300 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
301
302 if (rm == 5 && mod == 0) {
303 if (segsize == 64) {
304 op->eaflags |= EAF_REL;
305 op->segment |= SEG_RELATIVE;
306 mod = 2; /* fake disp32 */
307 }
308
309 if (asize != 64)
310 op->disp_size = asize;
311
312 op->basereg = -1;
313 mod = 2; /* fake disp32 */
314 }
315
316 if (rm == 4) { /* process SIB */
317 scale = (sib >> 6) & 03;
318 index = (sib >> 3) & 07;
319 base = sib & 07;
320
321 op->scale = 1 << scale;
322
323 if (index == 4 && !(rex & REX_X))
324 op->indexreg = -1; /* ESP/RSP cannot be an index */
325 else if (a64)
326 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
327 else
328 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
329
330 if (base == 5 && mod == 0) {
331 op->basereg = -1;
332 mod = 2; /* Fake disp32 */
333 } else if (a64)
334 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
335 else
336 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
337
338 if (segsize == 16)
339 op->disp_size = 32;
340 }
341
342 switch (mod) {
343 case 0:
344 op->segment |= SEG_NODISP;
345 break;
346 case 1:
347 op->segment |= SEG_DISP8;
348 op->offset = gets8(data);
349 data++;
350 break;
351 case 2:
352 op->segment |= SEG_DISP32;
353 op->offset = gets32(data);
354 data += 4;
355 break;
356 }
357 return data;
358 }
359 }
360
361 /*
362 * Determine whether the instruction template in t corresponds to the data
363 * stream in data. Return the number of bytes matched if so.
364 */
365 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
366
367 static int matches(const struct itemplate *t, uint8_t *data,
368 const struct prefix_info *prefix, int segsize, insn *ins)
369 {
370 uint8_t *r = (uint8_t *)(t->code);
371 uint8_t *origdata = data;
372 bool a_used = false, o_used = false;
373 enum prefixes drep = 0;
374 enum prefixes dwait = 0;
375 uint8_t lock = prefix->lock;
376 int osize = prefix->osize;
377 int asize = prefix->asize;
378 int i, c;
379 int op1, op2;
380 struct operand *opx, *opy;
381 uint8_t opex = 0;
382 int s_field_for = -1; /* No 144/154 series code encountered */
383 bool vex_ok = false;
384 int regmask = (segsize == 64) ? 15 : 7;
385
386 for (i = 0; i < MAX_OPERANDS; i++) {
387 ins->oprs[i].segment = ins->oprs[i].disp_size =
388 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
389 }
390 ins->condition = -1;
391 ins->rex = prefix->rex;
392 memset(ins->prefixes, 0, sizeof ins->prefixes);
393
394 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
395 return false;
396
397 if (prefix->rep == 0xF2)
398 drep = P_REPNE;
399 else if (prefix->rep == 0xF3)
400 drep = P_REP;
401
402 dwait = prefix->wait ? P_WAIT : 0;
403
404 while ((c = *r++) != 0) {
405 op1 = (c & 3) + ((opex & 1) << 2);
406 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
407 opx = &ins->oprs[op1];
408 opy = &ins->oprs[op2];
409 opex = 0;
410
411 switch (c) {
412 case 01:
413 case 02:
414 case 03:
415 case 04:
416 while (c--)
417 if (*r++ != *data++)
418 return false;
419 break;
420
421 case 05:
422 case 06:
423 case 07:
424 opex = c;
425 break;
426
427 case4(010):
428 {
429 int t = *r++, d = *data++;
430 if (d < t || d > t + 7)
431 return false;
432 else {
433 opx->basereg = (d-t)+
434 (ins->rex & REX_B ? 8 : 0);
435 opx->segment |= SEG_RMREG;
436 }
437 break;
438 }
439
440 case4(014):
441 case4(0274):
442 opx->offset = (int8_t)*data++;
443 opx->segment |= SEG_SIGNED;
444 break;
445
446 case4(020):
447 opx->offset = *data++;
448 break;
449
450 case4(024):
451 opx->offset = *data++;
452 break;
453
454 case4(030):
455 opx->offset = getu16(data);
456 data += 2;
457 break;
458
459 case4(034):
460 if (osize == 32) {
461 opx->offset = getu32(data);
462 data += 4;
463 } else {
464 opx->offset = getu16(data);
465 data += 2;
466 }
467 if (segsize != asize)
468 opx->disp_size = asize;
469 break;
470
471 case4(040):
472 case4(0254):
473 opx->offset = getu32(data);
474 data += 4;
475 break;
476
477 case4(044):
478 switch (asize) {
479 case 16:
480 opx->offset = getu16(data);
481 data += 2;
482 if (segsize != 16)
483 opx->disp_size = 16;
484 break;
485 case 32:
486 opx->offset = getu32(data);
487 data += 4;
488 if (segsize == 16)
489 opx->disp_size = 32;
490 break;
491 case 64:
492 opx->offset = getu64(data);
493 opx->disp_size = 64;
494 data += 8;
495 break;
496 }
497 break;
498
499 case4(050):
500 opx->offset = gets8(data++);
501 opx->segment |= SEG_RELATIVE;
502 break;
503
504 case4(054):
505 opx->offset = getu64(data);
506 data += 8;
507 break;
508
509 case4(060):
510 opx->offset = gets16(data);
511 data += 2;
512 opx->segment |= SEG_RELATIVE;
513 opx->segment &= ~SEG_32BIT;
514 break;
515
516 case4(064):
517 opx->segment |= SEG_RELATIVE;
518 if (osize == 16) {
519 opx->offset = gets16(data);
520 data += 2;
521 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
522 } else if (osize == 32) {
523 opx->offset = gets32(data);
524 data += 4;
525 opx->segment &= ~SEG_64BIT;
526 opx->segment |= SEG_32BIT;
527 }
528 if (segsize != osize) {
529 opx->type =
530 (opx->type & ~SIZE_MASK)
531 | ((osize == 16) ? BITS16 : BITS32);
532 }
533 break;
534
535 case4(070):
536 opx->offset = gets32(data);
537 data += 4;
538 opx->segment |= SEG_32BIT | SEG_RELATIVE;
539 break;
540
541 case4(0100):
542 case4(0110):
543 case4(0120):
544 case4(0130):
545 {
546 int modrm = *data++;
547 opx->segment |= SEG_RMREG;
548 data = do_ea(data, modrm, asize, segsize, opy, ins);
549 if (!data)
550 return false;
551 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
552 break;
553 }
554
555 case4(0140):
556 if (s_field_for == op1) {
557 opx->offset = gets8(data);
558 data++;
559 } else {
560 opx->offset = getu16(data);
561 data += 2;
562 }
563 break;
564
565 case4(0144):
566 case4(0154):
567 s_field_for = (*data & 0x02) ? op1 : -1;
568 if ((*data++ & ~0x02) != *r++)
569 return false;
570 break;
571
572 case4(0150):
573 if (s_field_for == op1) {
574 opx->offset = gets8(data);
575 data++;
576 } else {
577 opx->offset = getu32(data);
578 data += 4;
579 }
580 break;
581
582 case4(0160):
583 ins->rex |= REX_D;
584 ins->drexdst = op1;
585 break;
586
587 case4(0164):
588 ins->rex |= REX_D|REX_OC;
589 ins->drexdst = op1;
590 break;
591
592 case 0171:
593 data = do_drex(data, ins);
594 if (!data)
595 return false;
596 break;
597
598 case 0172:
599 {
600 uint8_t ximm = *data++;
601 c = *r++;
602 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
603 ins->oprs[c >> 3].segment |= SEG_RMREG;
604 ins->oprs[c & 7].offset = ximm & 15;
605 }
606 break;
607
608 case 0173:
609 {
610 uint8_t ximm = *data++;
611 c = *r++;
612
613 if ((c ^ ximm) & 15)
614 return false;
615
616 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
617 ins->oprs[c >> 4].segment |= SEG_RMREG;
618 }
619 break;
620
621 case 0174:
622 {
623 uint8_t ximm = *data++;
624 c = *r++;
625
626 ins->oprs[c].basereg = (ximm >> 4) & regmask;
627 ins->oprs[c].segment |= SEG_RMREG;
628 }
629 break;
630
631 case4(0200):
632 case4(0204):
633 case4(0210):
634 case4(0214):
635 case4(0220):
636 case4(0224):
637 case4(0230):
638 case4(0234):
639 {
640 int modrm = *data++;
641 if (((modrm >> 3) & 07) != (c & 07))
642 return false; /* spare field doesn't match up */
643 data = do_ea(data, modrm, asize, segsize, opy, ins);
644 if (!data)
645 return false;
646 break;
647 }
648
649 case4(0260):
650 {
651 int vexm = *r++;
652 int vexwlp = *r++;
653 ins->rex |= REX_V;
654 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
655 return false;
656
657 if ((vexm & 0x1f) != prefix->vex_m)
658 return false;
659
660 switch (vexwlp & 030) {
661 case 000:
662 if (prefix->rex & REX_W)
663 return false;
664 break;
665 case 010:
666 if (!(prefix->rex & REX_W))
667 return false;
668 ins->rex &= ~REX_W;
669 break;
670 case 020: /* VEX.W is a don't care */
671 ins->rex &= ~REX_W;
672 break;
673 case 030:
674 break;
675 }
676
677 if ((vexwlp & 007) != prefix->vex_lp)
678 return false;
679
680 opx->segment |= SEG_RMREG;
681 opx->basereg = prefix->vex_v;
682 vex_ok = true;
683 break;
684 }
685
686 case 0270:
687 {
688 int vexm = *r++;
689 int vexwlp = *r++;
690 ins->rex |= REX_V;
691 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
692 return false;
693
694 if ((vexm & 0x1f) != prefix->vex_m)
695 return false;
696
697 switch (vexwlp & 030) {
698 case 000:
699 if (ins->rex & REX_W)
700 return false;
701 break;
702 case 010:
703 if (!(ins->rex & REX_W))
704 return false;
705 break;
706 default:
707 break; /* Need to do anything special here? */
708 }
709
710 if ((vexwlp & 007) != prefix->vex_lp)
711 return false;
712
713 if (prefix->vex_v != 0)
714 return false;
715
716 vex_ok = true;
717 break;
718 }
719
720 case 0310:
721 if (asize != 16)
722 return false;
723 else
724 a_used = true;
725 break;
726
727 case 0311:
728 if (asize == 16)
729 return false;
730 else
731 a_used = true;
732 break;
733
734 case 0312:
735 if (asize != segsize)
736 return false;
737 else
738 a_used = true;
739 break;
740
741 case 0313:
742 if (asize != 64)
743 return false;
744 else
745 a_used = true;
746 break;
747
748 case 0314:
749 if (prefix->rex & REX_B)
750 return false;
751 break;
752
753 case 0315:
754 if (prefix->rex & REX_X)
755 return false;
756 break;
757
758 case 0316:
759 if (prefix->rex & REX_R)
760 return false;
761 break;
762
763 case 0317:
764 if (prefix->rex & REX_W)
765 return false;
766 break;
767
768 case 0320:
769 if (osize != 16)
770 return false;
771 else
772 o_used = true;
773 break;
774
775 case 0321:
776 if (osize != 32)
777 return false;
778 else
779 o_used = true;
780 break;
781
782 case 0322:
783 if (osize != (segsize == 16) ? 16 : 32)
784 return false;
785 else
786 o_used = true;
787 break;
788
789 case 0323:
790 ins->rex |= REX_W; /* 64-bit only instruction */
791 osize = 64;
792 o_used = true;
793 break;
794
795 case 0324:
796 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
797 return false;
798 o_used = true;
799 break;
800
801 case 0330:
802 {
803 int t = *r++, d = *data++;
804 if (d < t || d > t + 15)
805 return false;
806 else
807 ins->condition = d - t;
808 break;
809 }
810
811 case 0331:
812 if (prefix->rep)
813 return false;
814 break;
815
816 case 0332:
817 if (prefix->rep != 0xF2)
818 return false;
819 drep = 0;
820 break;
821
822 case 0333:
823 if (prefix->rep != 0xF3)
824 return false;
825 drep = 0;
826 break;
827
828 case 0334:
829 if (lock) {
830 ins->rex |= REX_R;
831 lock = 0;
832 }
833 break;
834
835 case 0335:
836 if (drep == P_REP)
837 drep = P_REPE;
838 break;
839
840 case 0336:
841 case 0337:
842 break;
843
844 case 0340:
845 return false;
846
847 case 0341:
848 if (prefix->wait != 0x9B)
849 return false;
850 dwait = 0;
851 break;
852
853 case4(0344):
854 ins->oprs[0].basereg = (*data++ >> 3) & 7;
855 break;
856
857 case 0360:
858 if (prefix->osp || prefix->rep)
859 return false;
860 break;
861
862 case 0361:
863 if (!prefix->osp || prefix->rep)
864 return false;
865 o_used = true;
866 break;
867
868 case 0362:
869 if (prefix->osp || prefix->rep != 0xf2)
870 return false;
871 drep = 0;
872 break;
873
874 case 0363:
875 if (prefix->osp || prefix->rep != 0xf3)
876 return false;
877 drep = 0;
878 break;
879
880 case 0364:
881 if (prefix->osp)
882 return false;
883 break;
884
885 case 0365:
886 if (prefix->asp)
887 return false;
888 break;
889
890 case 0366:
891 if (!prefix->osp)
892 return false;
893 o_used = true;
894 break;
895
896 case 0367:
897 if (!prefix->asp)
898 return false;
899 a_used = true;
900 break;
901
902 default:
903 return false; /* Unknown code */
904 }
905 }
906
907 if (!vex_ok && (ins->rex & REX_V))
908 return false;
909
910 /* REX cannot be combined with DREX or VEX */
911 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
912 return false;
913
914 /*
915 * Check for unused rep or a/o prefixes.
916 */
917 for (i = 0; i < t->operands; i++) {
918 if (ins->oprs[i].segment != SEG_RMREG)
919 a_used = true;
920 }
921
922 if (lock) {
923 if (ins->prefixes[PPS_LREP])
924 return false;
925 ins->prefixes[PPS_LREP] = P_LOCK;
926 }
927 if (drep) {
928 if (ins->prefixes[PPS_LREP])
929 return false;
930 ins->prefixes[PPS_LREP] = drep;
931 }
932 ins->prefixes[PPS_WAIT] = dwait;
933 if (!o_used) {
934 if (osize != ((segsize == 16) ? 16 : 32)) {
935 enum prefixes pfx = 0;
936
937 switch (osize) {
938 case 16:
939 pfx = P_O16;
940 break;
941 case 32:
942 pfx = P_O32;
943 break;
944 case 64:
945 pfx = P_O64;
946 break;
947 }
948
949 if (ins->prefixes[PPS_OSIZE])
950 return false;
951 ins->prefixes[PPS_OSIZE] = pfx;
952 }
953 }
954 if (!a_used && asize != segsize) {
955 if (ins->prefixes[PPS_ASIZE])
956 return false;
957 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
958 }
959
960 /* Fix: check for redundant REX prefixes */
961
962 return data - origdata;
963 }
964
965 /* Condition names for disassembly, sorted by x86 code */
966 static const char * const condition_name[16] = {
967 "o", "no", "c", "nc", "z", "nz", "na", "a",
968 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
969 };
970
971 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
972 int32_t offset, int autosync, uint32_t prefer)
973 {
974 const struct itemplate * const *p, * const *best_p;
975 const struct disasm_index *ix;
976 uint8_t *dp;
977 int length, best_length = 0;
978 char *segover;
979 int i, slen, colon, n;
980 uint8_t *origdata;
981 int works;
982 insn tmp_ins, ins;
983 uint32_t goodness, best;
984 int best_pref;
985 struct prefix_info prefix;
986 bool end_prefix;
987
988 memset(&ins, 0, sizeof ins);
989
990 /*
991 * Scan for prefixes.
992 */
993 memset(&prefix, 0, sizeof prefix);
994 prefix.asize = segsize;
995 prefix.osize = (segsize == 64) ? 32 : segsize;
996 segover = NULL;
997 origdata = data;
998
999 ix = itable;
1000
1001 end_prefix = false;
1002 while (!end_prefix) {
1003 switch (*data) {
1004 case 0xF2:
1005 case 0xF3:
1006 prefix.rep = *data++;
1007 break;
1008
1009 case 0x9B:
1010 prefix.wait = *data++;
1011 break;
1012
1013 case 0xF0:
1014 prefix.lock = *data++;
1015 break;
1016
1017 case 0x2E:
1018 segover = "cs", prefix.seg = *data++;
1019 break;
1020 case 0x36:
1021 segover = "ss", prefix.seg = *data++;
1022 break;
1023 case 0x3E:
1024 segover = "ds", prefix.seg = *data++;
1025 break;
1026 case 0x26:
1027 segover = "es", prefix.seg = *data++;
1028 break;
1029 case 0x64:
1030 segover = "fs", prefix.seg = *data++;
1031 break;
1032 case 0x65:
1033 segover = "gs", prefix.seg = *data++;
1034 break;
1035
1036 case 0x66:
1037 prefix.osize = (segsize == 16) ? 32 : 16;
1038 prefix.osp = *data++;
1039 break;
1040 case 0x67:
1041 prefix.asize = (segsize == 32) ? 16 : 32;
1042 prefix.asp = *data++;
1043 break;
1044
1045 case 0xC4:
1046 case 0xC5:
1047 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1048 prefix.vex[0] = *data++;
1049 prefix.vex[1] = *data++;
1050
1051 prefix.rex = REX_V;
1052
1053 if (prefix.vex[0] == 0xc4) {
1054 prefix.vex[2] = *data++;
1055 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1056 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1057 prefix.vex_m = prefix.vex[1] & 0x1f;
1058 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1059 prefix.vex_lp = prefix.vex[2] & 7;
1060 } else {
1061 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1062 prefix.vex_m = 1;
1063 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1064 prefix.vex_lp = prefix.vex[1] & 7;
1065 }
1066
1067 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1068 }
1069 end_prefix = true;
1070 break;
1071
1072 case REX_P + 0x0:
1073 case REX_P + 0x1:
1074 case REX_P + 0x2:
1075 case REX_P + 0x3:
1076 case REX_P + 0x4:
1077 case REX_P + 0x5:
1078 case REX_P + 0x6:
1079 case REX_P + 0x7:
1080 case REX_P + 0x8:
1081 case REX_P + 0x9:
1082 case REX_P + 0xA:
1083 case REX_P + 0xB:
1084 case REX_P + 0xC:
1085 case REX_P + 0xD:
1086 case REX_P + 0xE:
1087 case REX_P + 0xF:
1088 if (segsize == 64) {
1089 prefix.rex = *data++;
1090 if (prefix.rex & REX_W)
1091 prefix.osize = 64;
1092 }
1093 end_prefix = true;
1094 break;
1095
1096 default:
1097 end_prefix = true;
1098 break;
1099 }
1100 }
1101
1102 best = -1; /* Worst possible */
1103 best_p = NULL;
1104 best_pref = INT_MAX;
1105
1106 if (!ix)
1107 return 0; /* No instruction table at all... */
1108
1109 dp = data;
1110 ix += *dp++;
1111 while (ix->n == -1) {
1112 ix = (const struct disasm_index *)ix->p + *dp++;
1113 }
1114
1115 p = (const struct itemplate * const *)ix->p;
1116 for (n = ix->n; n; n--, p++) {
1117 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1118 works = true;
1119 /*
1120 * Final check to make sure the types of r/m match up.
1121 * XXX: Need to make sure this is actually correct.
1122 */
1123 for (i = 0; i < (*p)->operands; i++) {
1124 if (!((*p)->opd[i] & SAME_AS) &&
1125 (
1126 /* If it's a mem-only EA but we have a
1127 register, die. */
1128 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1129 !(MEMORY & ~(*p)->opd[i])) ||
1130 /* If it's a reg-only EA but we have a memory
1131 ref, die. */
1132 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1133 !(REG_EA & ~(*p)->opd[i]) &&
1134 !((*p)->opd[i] & REG_SMASK)) ||
1135 /* Register type mismatch (eg FS vs REG_DESS):
1136 die. */
1137 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1138 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1139 !whichreg((*p)->opd[i],
1140 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1141 )) {
1142 works = false;
1143 break;
1144 }
1145 }
1146
1147 /*
1148 * Note: we always prefer instructions which incorporate
1149 * prefixes in the instructions themselves. This is to allow
1150 * e.g. PAUSE to be preferred to REP NOP, and deal with
1151 * MMX/SSE instructions where prefixes are used to select
1152 * between MMX and SSE register sets or outright opcode
1153 * selection.
1154 */
1155 if (works) {
1156 int i, nprefix;
1157 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1158 nprefix = 0;
1159 for (i = 0; i < MAXPREFIX; i++)
1160 if (tmp_ins.prefixes[i])
1161 nprefix++;
1162 if (nprefix < best_pref ||
1163 (nprefix == best_pref && goodness < best)) {
1164 /* This is the best one found so far */
1165 best = goodness;
1166 best_p = p;
1167 best_pref = nprefix;
1168 best_length = length;
1169 ins = tmp_ins;
1170 }
1171 }
1172 }
1173 }
1174
1175 if (!best_p)
1176 return 0; /* no instruction was matched */
1177
1178 /* Pick the best match */
1179 p = best_p;
1180 length = best_length;
1181
1182 slen = 0;
1183
1184 /* TODO: snprintf returns the value that the string would have if
1185 * the buffer were long enough, and not the actual length of
1186 * the returned string, so each instance of using the return
1187 * value of snprintf should actually be checked to assure that
1188 * the return value is "sane." Maybe a macro wrapper could
1189 * be used for that purpose.
1190 */
1191 for (i = 0; i < MAXPREFIX; i++) {
1192 const char *prefix = prefix_name(ins.prefixes[i]);
1193 if (prefix)
1194 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1195 }
1196
1197 i = (*p)->opcode;
1198 if (i >= FIRST_COND_OPCODE)
1199 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1200 nasm_insn_names[i], condition_name[ins.condition]);
1201 else
1202 slen += snprintf(output + slen, outbufsize - slen, "%s",
1203 nasm_insn_names[i]);
1204
1205 colon = false;
1206 length += data - origdata; /* fix up for prefixes */
1207 for (i = 0; i < (*p)->operands; i++) {
1208 opflags_t t = (*p)->opd[i];
1209 const operand *o = &ins.oprs[i];
1210 int64_t offs;
1211
1212 if (t & SAME_AS) {
1213 o = &ins.oprs[t & ~SAME_AS];
1214 t = (*p)->opd[t & ~SAME_AS];
1215 }
1216
1217 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1218
1219 offs = o->offset;
1220 if (o->segment & SEG_RELATIVE) {
1221 offs += offset + length;
1222 /*
1223 * sort out wraparound
1224 */
1225 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1226 offs &= 0xffff;
1227 else if (segsize != 64)
1228 offs &= 0xffffffff;
1229
1230 /*
1231 * add sync marker, if autosync is on
1232 */
1233 if (autosync)
1234 add_sync(offs, 0L);
1235 }
1236
1237 if (t & COLON)
1238 colon = true;
1239 else
1240 colon = false;
1241
1242 if ((t & (REGISTER | FPUREG)) ||
1243 (o->segment & SEG_RMREG)) {
1244 enum reg_enum reg;
1245 reg = whichreg(t, o->basereg, ins.rex);
1246 if (t & TO)
1247 slen += snprintf(output + slen, outbufsize - slen, "to ");
1248 slen += snprintf(output + slen, outbufsize - slen, "%s",
1249 nasm_reg_names[reg-EXPR_REG_START]);
1250 } else if (!(UNITY & ~t)) {
1251 output[slen++] = '1';
1252 } else if (t & IMMEDIATE) {
1253 if (t & BITS8) {
1254 slen +=
1255 snprintf(output + slen, outbufsize - slen, "byte ");
1256 if (o->segment & SEG_SIGNED) {
1257 if (offs < 0) {
1258 offs *= -1;
1259 output[slen++] = '-';
1260 } else
1261 output[slen++] = '+';
1262 }
1263 } else if (t & BITS16) {
1264 slen +=
1265 snprintf(output + slen, outbufsize - slen, "word ");
1266 } else if (t & BITS32) {
1267 slen +=
1268 snprintf(output + slen, outbufsize - slen, "dword ");
1269 } else if (t & BITS64) {
1270 slen +=
1271 snprintf(output + slen, outbufsize - slen, "qword ");
1272 } else if (t & NEAR) {
1273 slen +=
1274 snprintf(output + slen, outbufsize - slen, "near ");
1275 } else if (t & SHORT) {
1276 slen +=
1277 snprintf(output + slen, outbufsize - slen, "short ");
1278 }
1279 slen +=
1280 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1281 offs);
1282 } else if (!(MEM_OFFS & ~t)) {
1283 slen +=
1284 snprintf(output + slen, outbufsize - slen,
1285 "[%s%s%s0x%"PRIx64"]",
1286 (segover ? segover : ""),
1287 (segover ? ":" : ""),
1288 (o->disp_size == 64 ? "qword " :
1289 o->disp_size == 32 ? "dword " :
1290 o->disp_size == 16 ? "word " : ""), offs);
1291 segover = NULL;
1292 } else if (!(REGMEM & ~t)) {
1293 int started = false;
1294 if (t & BITS8)
1295 slen +=
1296 snprintf(output + slen, outbufsize - slen, "byte ");
1297 if (t & BITS16)
1298 slen +=
1299 snprintf(output + slen, outbufsize - slen, "word ");
1300 if (t & BITS32)
1301 slen +=
1302 snprintf(output + slen, outbufsize - slen, "dword ");
1303 if (t & BITS64)
1304 slen +=
1305 snprintf(output + slen, outbufsize - slen, "qword ");
1306 if (t & BITS80)
1307 slen +=
1308 snprintf(output + slen, outbufsize - slen, "tword ");
1309 if (t & BITS128)
1310 slen +=
1311 snprintf(output + slen, outbufsize - slen, "oword ");
1312 if (t & BITS256)
1313 slen +=
1314 snprintf(output + slen, outbufsize - slen, "yword ");
1315 if (t & FAR)
1316 slen += snprintf(output + slen, outbufsize - slen, "far ");
1317 if (t & NEAR)
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "near ");
1320 output[slen++] = '[';
1321 if (o->disp_size)
1322 slen += snprintf(output + slen, outbufsize - slen, "%s",
1323 (o->disp_size == 64 ? "qword " :
1324 o->disp_size == 32 ? "dword " :
1325 o->disp_size == 16 ? "word " :
1326 ""));
1327 if (o->eaflags & EAF_REL)
1328 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1329 if (segover) {
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "%s:",
1332 segover);
1333 segover = NULL;
1334 }
1335 if (o->basereg != -1) {
1336 slen += snprintf(output + slen, outbufsize - slen, "%s",
1337 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1338 started = true;
1339 }
1340 if (o->indexreg != -1) {
1341 if (started)
1342 output[slen++] = '+';
1343 slen += snprintf(output + slen, outbufsize - slen, "%s",
1344 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1345 if (o->scale > 1)
1346 slen +=
1347 snprintf(output + slen, outbufsize - slen, "*%d",
1348 o->scale);
1349 started = true;
1350 }
1351
1352
1353 if (o->segment & SEG_DISP8) {
1354 const char *prefix;
1355 uint8_t offset = offs;
1356 if ((int8_t)offset < 0) {
1357 prefix = "-";
1358 offset = -offset;
1359 } else {
1360 prefix = "+";
1361 }
1362 slen +=
1363 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1364 prefix, offset);
1365 } else if (o->segment & SEG_DISP16) {
1366 const char *prefix;
1367 uint16_t offset = offs;
1368 if ((int16_t)offset < 0 && started) {
1369 offset = -offset;
1370 prefix = "-";
1371 } else {
1372 prefix = started ? "+" : "";
1373 }
1374 slen +=
1375 snprintf(output + slen, outbufsize - slen,
1376 "%s0x%"PRIx16"", prefix, offset);
1377 } else if (o->segment & SEG_DISP32) {
1378 if (prefix.asize == 64) {
1379 const char *prefix;
1380 uint64_t offset = (int64_t)(int32_t)offs;
1381 if ((int32_t)offs < 0 && started) {
1382 offset = -offset;
1383 prefix = "-";
1384 } else {
1385 prefix = started ? "+" : "";
1386 }
1387 slen +=
1388 snprintf(output + slen, outbufsize - slen,
1389 "%s0x%"PRIx64"", prefix, offset);
1390 } else {
1391 const char *prefix;
1392 uint32_t offset = offs;
1393 if ((int32_t) offset < 0 && started) {
1394 offset = -offset;
1395 prefix = "-";
1396 } else {
1397 prefix = started ? "+" : "";
1398 }
1399 slen +=
1400 snprintf(output + slen, outbufsize - slen,
1401 "%s0x%"PRIx32"", prefix, offset);
1402 }
1403 }
1404 output[slen++] = ']';
1405 } else {
1406 slen +=
1407 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1408 i);
1409 }
1410 }
1411 output[slen] = '\0';
1412 if (segover) { /* unused segment override */
1413 char *p = output;
1414 int count = slen + 1;
1415 while (count--)
1416 p[count + 3] = p[count];
1417 strncpy(output, segover, 2);
1418 output[2] = ' ';
1419 }
1420 return length;
1421 }
1422
1423 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1424 {
1425 snprintf(output, outbufsize, "db 0x%02X", *data);
1426 return 1;
1427 }
Adding AVX-512 features