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AVX-512: Add {evex} instruction prefix
[nasm/avx512.git] / assemble.c
blob11a7db625982d6d8907eb903413f73464b59b9d2
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
170 */
171
172 #include "compiler.h"
173
174 #include <stdio.h>
175 #include <string.h>
176 #include <inttypes.h>
177
178 #include "nasm.h"
179 #include "nasmlib.h"
180 #include "assemble.h"
181 #include "insns.h"
182 #include "tables.h"
183
184 enum match_result {
185 /*
186 * Matching errors. These should be sorted so that more specific
187 * errors come later in the sequence.
188 */
189 MERR_INVALOP,
190 MERR_OPSIZEMISSING,
191 MERR_OPSIZEMISMATCH,
192 MERR_BADCPU,
193 MERR_BADMODE,
194 MERR_BADHLE,
195 MERR_ENCMISMATCH,
196 MERR_BADBND,
197 /*
198 * Matching success; the conditional ones first
199 */
200 MOK_JUMP, /* Matching OK but needs jmp_match() */
201 MOK_GOOD /* Matching unconditionally OK */
202 };
203
204 typedef struct {
205 enum ea_type type; /* what kind of EA is this? */
206 int sib_present; /* is a SIB byte necessary? */
207 int bytes; /* # of bytes of offset needed */
208 int size; /* lazy - this is sib+bytes+1 */
209 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
210 int8_t disp8; /* compressed displacement for EVEX */
211 } ea;
212
213 #define GEN_SIB(scale, index, base) \
214 (((scale) << 6) | ((index) << 3) | ((base)))
215
216 #define GEN_MODRM(mod, reg, rm) \
217 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
218
219 static iflags_t cpu; /* cpu level received from nasm.c */
220 static efunc errfunc;
221 static struct ofmt *outfmt;
222 static ListGen *list;
223
224 static int64_t calcsize(int32_t, int64_t, int, insn *,
225 const struct itemplate *);
226 static void gencode(int32_t segment, int64_t offset, int bits,
227 insn * ins, const struct itemplate *temp,
228 int64_t insn_end);
229 static enum match_result find_match(const struct itemplate **tempp,
230 insn *instruction,
231 int32_t segment, int64_t offset, int bits);
232 static enum match_result matches(const struct itemplate *, insn *, int bits);
233 static opflags_t regflag(const operand *);
234 static int32_t regval(const operand *);
235 static int rexflags(int, opflags_t, int);
236 static int op_rexflags(const operand *, int);
237 static int op_evexflags(const operand *, int, uint8_t);
238 static void add_asp(insn *, int);
239
240 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
241
242 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
243 {
244 return ins->prefixes[pos] == prefix;
245 }
246
247 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
248 {
249 if (ins->prefixes[pos])
250 errfunc(ERR_NONFATAL, "invalid %s prefix",
251 prefix_name(ins->prefixes[pos]));
252 }
253
254 static const char *size_name(int size)
255 {
256 switch (size) {
257 case 1:
258 return "byte";
259 case 2:
260 return "word";
261 case 4:
262 return "dword";
263 case 8:
264 return "qword";
265 case 10:
266 return "tword";
267 case 16:
268 return "oword";
269 case 32:
270 return "yword";
271 case 64:
272 return "zword";
273 default:
274 return "???";
275 }
276 }
277
278 static void warn_overflow(int pass, int size)
279 {
280 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
281 "%s data exceeds bounds", size_name(size));
282 }
283
284 static void warn_overflow_const(int64_t data, int size)
285 {
286 if (overflow_general(data, size))
287 warn_overflow(ERR_PASS1, size);
288 }
289
290 static void warn_overflow_opd(const struct operand *o, int size)
291 {
292 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
293 if (overflow_general(o->offset, size))
294 warn_overflow(ERR_PASS2, size);
295 }
296 }
297
298 /*
299 * This routine wrappers the real output format's output routine,
300 * in order to pass a copy of the data off to the listing file
301 * generator at the same time.
302 */
303 static void out(int64_t offset, int32_t segto, const void *data,
304 enum out_type type, uint64_t size,
305 int32_t segment, int32_t wrt)
306 {
307 static int32_t lineno = 0; /* static!!! */
308 static char *lnfname = NULL;
309 uint8_t p[8];
310
311 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
312 /*
313 * This is a non-relocated address, and we're going to
314 * convert it into RAWDATA format.
315 */
316 uint8_t *q = p;
317
318 if (size > 8) {
319 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
320 return;
321 }
322
323 WRITEADDR(q, *(int64_t *)data, size);
324 data = p;
325 type = OUT_RAWDATA;
326 }
327
328 list->output(offset, data, type, size);
329
330 /*
331 * this call to src_get determines when we call the
332 * debug-format-specific "linenum" function
333 * it updates lineno and lnfname to the current values
334 * returning 0 if "same as last time", -2 if lnfname
335 * changed, and the amount by which lineno changed,
336 * if it did. thus, these variables must be static
337 */
338
339 if (src_get(&lineno, &lnfname))
340 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
341
342 outfmt->output(segto, data, type, size, segment, wrt);
343 }
344
345 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
346 {
347 if (opx->segment != NO_SEG) {
348 uint64_t data = opx->offset;
349 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
350 } else {
351 uint8_t byte = opx->offset;
352 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
353 }
354 }
355
356 static bool jmp_match(int32_t segment, int64_t offset, int bits,
357 insn * ins, const struct itemplate *temp)
358 {
359 int64_t isize;
360 const uint8_t *code = temp->code;
361 uint8_t c = code[0];
362
363 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
364 return false;
365 if (!optimizing)
366 return false;
367 if (optimizing < 0 && c == 0371)
368 return false;
369
370 isize = calcsize(segment, offset, bits, ins, temp);
371
372 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
373 /* Be optimistic in pass 1 */
374 return true;
375
376 if (ins->oprs[0].segment != segment)
377 return false;
378
379 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
380 return (isize >= -128 && isize <= 127); /* is it byte size? */
381 }
382
383 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
384 insn * instruction, struct ofmt *output, efunc error,
385 ListGen * listgen)
386 {
387 const struct itemplate *temp;
388 int j;
389 enum match_result m;
390 int64_t insn_end;
391 int32_t itimes;
392 int64_t start = offset;
393 int64_t wsize; /* size for DB etc. */
394
395 errfunc = error; /* to pass to other functions */
396 cpu = cp;
397 outfmt = output; /* likewise */
398 list = listgen; /* and again */
399
400 wsize = idata_bytes(instruction->opcode);
401 if (wsize == -1)
402 return 0;
403
404 if (wsize) {
405 extop *e;
406 int32_t t = instruction->times;
407 if (t < 0)
408 errfunc(ERR_PANIC,
409 "instruction->times < 0 (%ld) in assemble()", t);
410
411 while (t--) { /* repeat TIMES times */
412 list_for_each(e, instruction->eops) {
413 if (e->type == EOT_DB_NUMBER) {
414 if (wsize > 8) {
415 errfunc(ERR_NONFATAL,
416 "integer supplied to a DT, DO or DY"
417 " instruction");
418 } else {
419 out(offset, segment, &e->offset,
420 OUT_ADDRESS, wsize, e->segment, e->wrt);
421 offset += wsize;
422 }
423 } else if (e->type == EOT_DB_STRING ||
424 e->type == EOT_DB_STRING_FREE) {
425 int align;
426
427 out(offset, segment, e->stringval,
428 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
429 align = e->stringlen % wsize;
430
431 if (align) {
432 align = wsize - align;
433 out(offset, segment, zero_buffer,
434 OUT_RAWDATA, align, NO_SEG, NO_SEG);
435 }
436 offset += e->stringlen + align;
437 }
438 }
439 if (t > 0 && t == instruction->times - 1) {
440 /*
441 * Dummy call to list->output to give the offset to the
442 * listing module.
443 */
444 list->output(offset, NULL, OUT_RAWDATA, 0);
445 list->uplevel(LIST_TIMES);
446 }
447 }
448 if (instruction->times > 1)
449 list->downlevel(LIST_TIMES);
450 return offset - start;
451 }
452
453 if (instruction->opcode == I_INCBIN) {
454 const char *fname = instruction->eops->stringval;
455 FILE *fp;
456
457 fp = fopen(fname, "rb");
458 if (!fp) {
459 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
460 fname);
461 } else if (fseek(fp, 0L, SEEK_END) < 0) {
462 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
463 fname);
464 fclose(fp);
465 } else {
466 static char buf[4096];
467 size_t t = instruction->times;
468 size_t base = 0;
469 size_t len;
470
471 len = ftell(fp);
472 if (instruction->eops->next) {
473 base = instruction->eops->next->offset;
474 len -= base;
475 if (instruction->eops->next->next &&
476 len > (size_t)instruction->eops->next->next->offset)
477 len = (size_t)instruction->eops->next->next->offset;
478 }
479 /*
480 * Dummy call to list->output to give the offset to the
481 * listing module.
482 */
483 list->output(offset, NULL, OUT_RAWDATA, 0);
484 list->uplevel(LIST_INCBIN);
485 while (t--) {
486 size_t l;
487
488 fseek(fp, base, SEEK_SET);
489 l = len;
490 while (l > 0) {
491 int32_t m;
492 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
493 if (!m) {
494 /*
495 * This shouldn't happen unless the file
496 * actually changes while we are reading
497 * it.
498 */
499 error(ERR_NONFATAL,
500 "`incbin': unexpected EOF while"
501 " reading file `%s'", fname);
502 t = 0; /* Try to exit cleanly */
503 break;
504 }
505 out(offset, segment, buf, OUT_RAWDATA, m,
506 NO_SEG, NO_SEG);
507 l -= m;
508 }
509 }
510 list->downlevel(LIST_INCBIN);
511 if (instruction->times > 1) {
512 /*
513 * Dummy call to list->output to give the offset to the
514 * listing module.
515 */
516 list->output(offset, NULL, OUT_RAWDATA, 0);
517 list->uplevel(LIST_TIMES);
518 list->downlevel(LIST_TIMES);
519 }
520 fclose(fp);
521 return instruction->times * len;
522 }
523 return 0; /* if we're here, there's an error */
524 }
525
526 /* Check to see if we need an address-size prefix */
527 add_asp(instruction, bits);
528
529 m = find_match(&temp, instruction, segment, offset, bits);
530
531 if (m == MOK_GOOD) {
532 /* Matches! */
533 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
534 itimes = instruction->times;
535 if (insn_size < 0) /* shouldn't be, on pass two */
536 error(ERR_PANIC, "errors made it through from pass one");
537 else
538 while (itimes--) {
539 for (j = 0; j < MAXPREFIX; j++) {
540 uint8_t c = 0;
541 switch (instruction->prefixes[j]) {
542 case P_WAIT:
543 c = 0x9B;
544 break;
545 case P_LOCK:
546 c = 0xF0;
547 break;
548 case P_REPNE:
549 case P_REPNZ:
550 case P_XACQUIRE:
551 case P_BND:
552 c = 0xF2;
553 break;
554 case P_REPE:
555 case P_REPZ:
556 case P_REP:
557 case P_XRELEASE:
558 c = 0xF3;
559 break;
560 case R_CS:
561 if (bits == 64) {
562 error(ERR_WARNING | ERR_PASS2,
563 "cs segment base generated, but will be ignored in 64-bit mode");
564 }
565 c = 0x2E;
566 break;
567 case R_DS:
568 if (bits == 64) {
569 error(ERR_WARNING | ERR_PASS2,
570 "ds segment base generated, but will be ignored in 64-bit mode");
571 }
572 c = 0x3E;
573 break;
574 case R_ES:
575 if (bits == 64) {
576 error(ERR_WARNING | ERR_PASS2,
577 "es segment base generated, but will be ignored in 64-bit mode");
578 }
579 c = 0x26;
580 break;
581 case R_FS:
582 c = 0x64;
583 break;
584 case R_GS:
585 c = 0x65;
586 break;
587 case R_SS:
588 if (bits == 64) {
589 error(ERR_WARNING | ERR_PASS2,
590 "ss segment base generated, but will be ignored in 64-bit mode");
591 }
592 c = 0x36;
593 break;
594 case R_SEGR6:
595 case R_SEGR7:
596 error(ERR_NONFATAL,
597 "segr6 and segr7 cannot be used as prefixes");
598 break;
599 case P_A16:
600 if (bits == 64) {
601 error(ERR_NONFATAL,
602 "16-bit addressing is not supported "
603 "in 64-bit mode");
604 } else if (bits != 16)
605 c = 0x67;
606 break;
607 case P_A32:
608 if (bits != 32)
609 c = 0x67;
610 break;
611 case P_A64:
612 if (bits != 64) {
613 error(ERR_NONFATAL,
614 "64-bit addressing is only supported "
615 "in 64-bit mode");
616 }
617 break;
618 case P_ASP:
619 c = 0x67;
620 break;
621 case P_O16:
622 if (bits != 16)
623 c = 0x66;
624 break;
625 case P_O32:
626 if (bits == 16)
627 c = 0x66;
628 break;
629 case P_O64:
630 /* REX.W */
631 break;
632 case P_OSP:
633 c = 0x66;
634 break;
635 case P_EVEX:
636 /* EVEX */
637 break;
638 case P_none:
639 break;
640 default:
641 error(ERR_PANIC, "invalid instruction prefix");
642 }
643 if (c != 0) {
644 out(offset, segment, &c, OUT_RAWDATA, 1,
645 NO_SEG, NO_SEG);
646 offset++;
647 }
648 }
649 insn_end = offset + insn_size;
650 gencode(segment, offset, bits, instruction,
651 temp, insn_end);
652 offset += insn_size;
653 if (itimes > 0 && itimes == instruction->times - 1) {
654 /*
655 * Dummy call to list->output to give the offset to the
656 * listing module.
657 */
658 list->output(offset, NULL, OUT_RAWDATA, 0);
659 list->uplevel(LIST_TIMES);
660 }
661 }
662 if (instruction->times > 1)
663 list->downlevel(LIST_TIMES);
664 return offset - start;
665 } else {
666 /* No match */
667 switch (m) {
668 case MERR_OPSIZEMISSING:
669 error(ERR_NONFATAL, "operation size not specified");
670 break;
671 case MERR_OPSIZEMISMATCH:
672 error(ERR_NONFATAL, "mismatch in operand sizes");
673 break;
674 case MERR_BADCPU:
675 error(ERR_NONFATAL, "no instruction for this cpu level");
676 break;
677 case MERR_BADMODE:
678 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
679 bits);
680 break;
681 default:
682 error(ERR_NONFATAL,
683 "invalid combination of opcode and operands");
684 break;
685 }
686 }
687 return 0;
688 }
689
690 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
691 insn * instruction, efunc error)
692 {
693 const struct itemplate *temp;
694 enum match_result m;
695
696 errfunc = error; /* to pass to other functions */
697 cpu = cp;
698
699 if (instruction->opcode == I_none)
700 return 0;
701
702 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
703 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
704 instruction->opcode == I_DT || instruction->opcode == I_DO ||
705 instruction->opcode == I_DY) {
706 extop *e;
707 int32_t isize, osize, wsize;
708
709 isize = 0;
710 wsize = idata_bytes(instruction->opcode);
711
712 list_for_each(e, instruction->eops) {
713 int32_t align;
714
715 osize = 0;
716 if (e->type == EOT_DB_NUMBER) {
717 osize = 1;
718 warn_overflow_const(e->offset, wsize);
719 } else if (e->type == EOT_DB_STRING ||
720 e->type == EOT_DB_STRING_FREE)
721 osize = e->stringlen;
722
723 align = (-osize) % wsize;
724 if (align < 0)
725 align += wsize;
726 isize += osize + align;
727 }
728 return isize * instruction->times;
729 }
730
731 if (instruction->opcode == I_INCBIN) {
732 const char *fname = instruction->eops->stringval;
733 FILE *fp;
734 int64_t val = 0;
735 size_t len;
736
737 fp = fopen(fname, "rb");
738 if (!fp)
739 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
740 fname);
741 else if (fseek(fp, 0L, SEEK_END) < 0)
742 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
743 fname);
744 else {
745 len = ftell(fp);
746 if (instruction->eops->next) {
747 len -= instruction->eops->next->offset;
748 if (instruction->eops->next->next &&
749 len > (size_t)instruction->eops->next->next->offset) {
750 len = (size_t)instruction->eops->next->next->offset;
751 }
752 }
753 val = instruction->times * len;
754 }
755 if (fp)
756 fclose(fp);
757 return val;
758 }
759
760 /* Check to see if we need an address-size prefix */
761 add_asp(instruction, bits);
762
763 m = find_match(&temp, instruction, segment, offset, bits);
764 if (m == MOK_GOOD) {
765 /* we've matched an instruction. */
766 int64_t isize;
767 int j;
768
769 isize = calcsize(segment, offset, bits, instruction, temp);
770 if (isize < 0)
771 return -1;
772 for (j = 0; j < MAXPREFIX; j++) {
773 switch (instruction->prefixes[j]) {
774 case P_A16:
775 if (bits != 16)
776 isize++;
777 break;
778 case P_A32:
779 if (bits != 32)
780 isize++;
781 break;
782 case P_O16:
783 if (bits != 16)
784 isize++;
785 break;
786 case P_O32:
787 if (bits == 16)
788 isize++;
789 break;
790 case P_A64:
791 case P_O64:
792 case P_EVEX:
793 case P_none:
794 break;
795 default:
796 isize++;
797 break;
798 }
799 }
800 return isize * instruction->times;
801 } else {
802 return -1; /* didn't match any instruction */
803 }
804 }
805
806 static void bad_hle_warn(const insn * ins, uint8_t hleok)
807 {
808 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
809 enum whatwarn { w_none, w_lock, w_inval } ww;
810 static const enum whatwarn warn[2][4] =
811 {
812 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
813 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
814 };
815 unsigned int n;
816
817 n = (unsigned int)rep_pfx - P_XACQUIRE;
818 if (n > 1)
819 return; /* Not XACQUIRE/XRELEASE */
820
821 ww = warn[n][hleok];
822 if (!is_class(MEMORY, ins->oprs[0].type))
823 ww = w_inval; /* HLE requires operand 0 to be memory */
824
825 switch (ww) {
826 case w_none:
827 break;
828
829 case w_lock:
830 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
831 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
832 "%s with this instruction requires lock",
833 prefix_name(rep_pfx));
834 }
835 break;
836
837 case w_inval:
838 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
839 "%s invalid with this instruction",
840 prefix_name(rep_pfx));
841 break;
842 }
843 }
844
845 /* Common construct */
846 #define case3(x) case (x): case (x)+1: case (x)+2
847 #define case4(x) case3(x): case (x)+3
848
849 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
850 insn * ins, const struct itemplate *temp)
851 {
852 const uint8_t *codes = temp->code;
853 int64_t length = 0;
854 uint8_t c;
855 int rex_mask = ~0;
856 int op1, op2;
857 struct operand *opx;
858 uint8_t opex = 0;
859 enum ea_type eat;
860 uint8_t hleok = 0;
861 bool lockcheck = true;
862 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
863
864 ins->rex = 0; /* Ensure REX is reset */
865 eat = EA_SCALAR; /* Expect a scalar EA */
866 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
867
868 if (ins->prefixes[PPS_OSIZE] == P_O64)
869 ins->rex |= REX_W;
870
871 (void)segment; /* Don't warn that this parameter is unused */
872 (void)offset; /* Don't warn that this parameter is unused */
873
874 while (*codes) {
875 c = *codes++;
876 op1 = (c & 3) + ((opex & 1) << 2);
877 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
878 opx = &ins->oprs[op1];
879 opex = 0; /* For the next iteration */
880
881 switch (c) {
882 case4(01):
883 codes += c, length += c;
884 break;
885
886 case3(05):
887 opex = c;
888 break;
889
890 case4(010):
891 ins->rex |=
892 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
893 codes++, length++;
894 break;
895
896 case4(014):
897 /* this is an index reg of MIB operand */
898 mib_index = opx->basereg;
899 break;
900
901 case4(020):
902 case4(024):
903 length++;
904 break;
905
906 case4(030):
907 length += 2;
908 break;
909
910 case4(034):
911 if (opx->type & (BITS16 | BITS32 | BITS64))
912 length += (opx->type & BITS16) ? 2 : 4;
913 else
914 length += (bits == 16) ? 2 : 4;
915 break;
916
917 case4(040):
918 length += 4;
919 break;
920
921 case4(044):
922 length += ins->addr_size >> 3;
923 break;
924
925 case4(050):
926 length++;
927 break;
928
929 case4(054):
930 length += 8; /* MOV reg64/imm */
931 break;
932
933 case4(060):
934 length += 2;
935 break;
936
937 case4(064):
938 if (opx->type & (BITS16 | BITS32 | BITS64))
939 length += (opx->type & BITS16) ? 2 : 4;
940 else
941 length += (bits == 16) ? 2 : 4;
942 break;
943
944 case4(070):
945 length += 4;
946 break;
947
948 case4(074):
949 length += 2;
950 break;
951
952 case 0172:
953 case 0173:
954 codes++;
955 length++;
956 break;
957
958 case4(0174):
959 length++;
960 break;
961
962 case4(0240):
963 ins->rex |= REX_EV;
964 ins->vexreg = regval(opx);
965 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
966 ins->vex_cm = *codes++;
967 ins->vex_wlp = *codes++;
968 ins->evex_tuple = (*codes++ - 0300);
969 break;
970
971 case 0250:
972 ins->rex |= REX_EV;
973 ins->vexreg = 0;
974 ins->vex_cm = *codes++;
975 ins->vex_wlp = *codes++;
976 ins->evex_tuple = (*codes++ - 0300);
977 break;
978
979 case4(0254):
980 length += 4;
981 break;
982
983 case4(0260):
984 ins->rex |= REX_V;
985 ins->vexreg = regval(opx);
986 ins->vex_cm = *codes++;
987 ins->vex_wlp = *codes++;
988 break;
989
990 case 0270:
991 ins->rex |= REX_V;
992 ins->vexreg = 0;
993 ins->vex_cm = *codes++;
994 ins->vex_wlp = *codes++;
995 break;
996
997 case3(0271):
998 hleok = c & 3;
999 break;
1000
1001 case4(0274):
1002 length++;
1003 break;
1004
1005 case4(0300):
1006 break;
1007
1008 case 0310:
1009 if (bits == 64)
1010 return -1;
1011 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1012 break;
1013
1014 case 0311:
1015 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1016 break;
1017
1018 case 0312:
1019 break;
1020
1021 case 0313:
1022 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1023 has_prefix(ins, PPS_ASIZE, P_A32))
1024 return -1;
1025 break;
1026
1027 case4(0314):
1028 break;
1029
1030 case 0320:
1031 {
1032 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1033 if (pfx == P_O16)
1034 break;
1035 if (pfx != P_none)
1036 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1037 else
1038 ins->prefixes[PPS_OSIZE] = P_O16;
1039 break;
1040 }
1041
1042 case 0321:
1043 {
1044 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1045 if (pfx == P_O32)
1046 break;
1047 if (pfx != P_none)
1048 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1049 else
1050 ins->prefixes[PPS_OSIZE] = P_O32;
1051 break;
1052 }
1053
1054 case 0322:
1055 break;
1056
1057 case 0323:
1058 rex_mask &= ~REX_W;
1059 break;
1060
1061 case 0324:
1062 ins->rex |= REX_W;
1063 break;
1064
1065 case 0325:
1066 ins->rex |= REX_NH;
1067 break;
1068
1069 case 0326:
1070 break;
1071
1072 case 0330:
1073 codes++, length++;
1074 break;
1075
1076 case 0331:
1077 break;
1078
1079 case 0332:
1080 case 0333:
1081 length++;
1082 break;
1083
1084 case 0334:
1085 ins->rex |= REX_L;
1086 break;
1087
1088 case 0335:
1089 break;
1090
1091 case 0336:
1092 if (!ins->prefixes[PPS_REP])
1093 ins->prefixes[PPS_REP] = P_REP;
1094 break;
1095
1096 case 0337:
1097 if (!ins->prefixes[PPS_REP])
1098 ins->prefixes[PPS_REP] = P_REPNE;
1099 break;
1100
1101 case 0340:
1102 if (ins->oprs[0].segment != NO_SEG)
1103 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1104 " quantity of BSS space");
1105 else
1106 length += ins->oprs[0].offset;
1107 break;
1108
1109 case 0341:
1110 if (!ins->prefixes[PPS_WAIT])
1111 ins->prefixes[PPS_WAIT] = P_WAIT;
1112 break;
1113
1114 case 0360:
1115 break;
1116
1117 case 0361:
1118 length++;
1119 break;
1120
1121 case 0364:
1122 case 0365:
1123 break;
1124
1125 case 0366:
1126 case 0367:
1127 length++;
1128 break;
1129
1130 case 0370:
1131 case 0371:
1132 break;
1133
1134 case 0373:
1135 length++;
1136 break;
1137
1138 case 0374:
1139 eat = EA_XMMVSIB;
1140 break;
1141
1142 case 0375:
1143 eat = EA_YMMVSIB;
1144 break;
1145
1146 case 0376:
1147 eat = EA_ZMMVSIB;
1148 break;
1149
1150 case4(0100):
1151 case4(0110):
1152 case4(0120):
1153 case4(0130):
1154 case4(0200):
1155 case4(0204):
1156 case4(0210):
1157 case4(0214):
1158 case4(0220):
1159 case4(0224):
1160 case4(0230):
1161 case4(0234):
1162 {
1163 ea ea_data;
1164 int rfield;
1165 opflags_t rflags;
1166 struct operand *opy = &ins->oprs[op2];
1167 struct operand *op_er_sae;
1168
1169 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1170
1171 if (c <= 0177) {
1172 /* pick rfield from operand b (opx) */
1173 rflags = regflag(opx);
1174 rfield = nasm_regvals[opx->basereg];
1175 } else {
1176 rflags = 0;
1177 rfield = c & 7;
1178 }
1179
1180 /* EVEX.b1 : evex_brerop contains the operand position */
1181 op_er_sae = (ins->evex_brerop >= 0 ?
1182 &ins->oprs[ins->evex_brerop] : NULL);
1183
1184 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1185 /* set EVEX.b */
1186 ins->evex_p[2] |= EVEX_P2B;
1187 if (op_er_sae->decoflags & ER) {
1188 /* set EVEX.RC (rounding control) */
1189 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1190 & EVEX_P2RC;
1191 }
1192 } else {
1193 /* set EVEX.L'L (vector length) */
1194 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1195 if (opy->decoflags & BRDCAST_MASK) {
1196 /* set EVEX.b */
1197 ins->evex_p[2] |= EVEX_P2B;
1198 }
1199 }
1200
1201 /*
1202 * if a separate form of MIB (ICC style) is used,
1203 * the index reg info is merged into mem operand
1204 */
1205 if (mib_index != R_none) {
1206 opy->indexreg = mib_index;
1207 opy->scale = 1;
1208 opy->hintbase = mib_index;
1209 opy->hinttype = EAH_NOTBASE;
1210 }
1211
1212 /*
1213 * only for mib operands, make a single reg index [reg*1].
1214 * gas uses this form to explicitly denote index register.
1215 */
1216 if ((temp->flags & IF_MIB) &&
1217 (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
1218 opy->hinttype == EAH_NOTBASE)) {
1219 opy->indexreg = opy->basereg;
1220 opy->basereg = -1;
1221 opy->scale = 1;
1222 }
1223
1224 if (process_ea(opy, &ea_data, bits,
1225 rfield, rflags, ins) != eat) {
1226 errfunc(ERR_NONFATAL, "invalid effective address");
1227 return -1;
1228 } else {
1229 ins->rex |= ea_data.rex;
1230 length += ea_data.size;
1231 }
1232 }
1233 break;
1234
1235 default:
1236 errfunc(ERR_PANIC, "internal instruction table corrupt"
1237 ": instruction code \\%o (0x%02X) given", c, c);
1238 break;
1239 }
1240 }
1241
1242 ins->rex &= rex_mask;
1243
1244 if (ins->rex & REX_NH) {
1245 if (ins->rex & REX_H) {
1246 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1247 return -1;
1248 }
1249 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1250 }
1251
1252 if (ins->rex & (REX_V | REX_EV)) {
1253 int bad32 = REX_R|REX_W|REX_X|REX_B;
1254
1255 if (ins->rex & REX_H) {
1256 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1257 return -1;
1258 }
1259 switch (ins->vex_wlp & 060) {
1260 case 000:
1261 case 040:
1262 ins->rex &= ~REX_W;
1263 break;
1264 case 020:
1265 ins->rex |= REX_W;
1266 bad32 &= ~REX_W;
1267 break;
1268 case 060:
1269 /* Follow REX_W */
1270 break;
1271 }
1272
1273 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1274 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1275 return -1;
1276 } else if (!(ins->rex & REX_EV) &&
1277 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1278 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1279 return -1;
1280 }
1281 if (ins->rex & REX_EV)
1282 length += 4;
1283 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1284 length += 3;
1285 else
1286 length += 2;
1287 } else if (ins->rex & REX_REAL) {
1288 if (ins->rex & REX_H) {
1289 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1290 return -1;
1291 } else if (bits == 64) {
1292 length++;
1293 } else if ((ins->rex & REX_L) &&
1294 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1295 cpu >= IF_X86_64) {
1296 /* LOCK-as-REX.R */
1297 assert_no_prefix(ins, PPS_LOCK);
1298 lockcheck = false; /* Already errored, no need for warning */
1299 length++;
1300 } else {
1301 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1302 return -1;
1303 }
1304 }
1305
1306 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1307 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1308 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1309 "instruction is not lockable");
1310 }
1311
1312 bad_hle_warn(ins, hleok);
1313
1314 return length;
1315 }
1316
1317 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1318 {
1319 if (bits == 64) {
1320 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1321 ins->rex = (ins->rex & REX_REAL) | REX_P;
1322 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1323 ins->rex = 0;
1324 return 1;
1325 }
1326 }
1327
1328 return 0;
1329 }
1330
1331 static void gencode(int32_t segment, int64_t offset, int bits,
1332 insn * ins, const struct itemplate *temp,
1333 int64_t insn_end)
1334 {
1335 uint8_t c;
1336 uint8_t bytes[4];
1337 int64_t size;
1338 int64_t data;
1339 int op1, op2;
1340 struct operand *opx;
1341 const uint8_t *codes = temp->code;
1342 uint8_t opex = 0;
1343 enum ea_type eat = EA_SCALAR;
1344
1345 while (*codes) {
1346 c = *codes++;
1347 op1 = (c & 3) + ((opex & 1) << 2);
1348 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1349 opx = &ins->oprs[op1];
1350 opex = 0; /* For the next iteration */
1351
1352 switch (c) {
1353 case 01:
1354 case 02:
1355 case 03:
1356 case 04:
1357 offset += emit_rex(ins, segment, offset, bits);
1358 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1359 codes += c;
1360 offset += c;
1361 break;
1362
1363 case 05:
1364 case 06:
1365 case 07:
1366 opex = c;
1367 break;
1368
1369 case4(010):
1370 offset += emit_rex(ins, segment, offset, bits);
1371 bytes[0] = *codes++ + (regval(opx) & 7);
1372 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1373 offset += 1;
1374 break;
1375
1376 case4(014):
1377 break;
1378
1379 case4(020):
1380 if (opx->offset < -256 || opx->offset > 255) {
1381 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1382 "byte value exceeds bounds");
1383 }
1384 out_imm8(offset, segment, opx);
1385 offset += 1;
1386 break;
1387
1388 case4(024):
1389 if (opx->offset < 0 || opx->offset > 255)
1390 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1391 "unsigned byte value exceeds bounds");
1392 out_imm8(offset, segment, opx);
1393 offset += 1;
1394 break;
1395
1396 case4(030):
1397 warn_overflow_opd(opx, 2);
1398 data = opx->offset;
1399 out(offset, segment, &data, OUT_ADDRESS, 2,
1400 opx->segment, opx->wrt);
1401 offset += 2;
1402 break;
1403
1404 case4(034):
1405 if (opx->type & (BITS16 | BITS32))
1406 size = (opx->type & BITS16) ? 2 : 4;
1407 else
1408 size = (bits == 16) ? 2 : 4;
1409 warn_overflow_opd(opx, size);
1410 data = opx->offset;
1411 out(offset, segment, &data, OUT_ADDRESS, size,
1412 opx->segment, opx->wrt);
1413 offset += size;
1414 break;
1415
1416 case4(040):
1417 warn_overflow_opd(opx, 4);
1418 data = opx->offset;
1419 out(offset, segment, &data, OUT_ADDRESS, 4,
1420 opx->segment, opx->wrt);
1421 offset += 4;
1422 break;
1423
1424 case4(044):
1425 data = opx->offset;
1426 size = ins->addr_size >> 3;
1427 warn_overflow_opd(opx, size);
1428 out(offset, segment, &data, OUT_ADDRESS, size,
1429 opx->segment, opx->wrt);
1430 offset += size;
1431 break;
1432
1433 case4(050):
1434 if (opx->segment != segment) {
1435 data = opx->offset;
1436 out(offset, segment, &data,
1437 OUT_REL1ADR, insn_end - offset,
1438 opx->segment, opx->wrt);
1439 } else {
1440 data = opx->offset - insn_end;
1441 if (data > 127 || data < -128)
1442 errfunc(ERR_NONFATAL, "short jump is out of range");
1443 out(offset, segment, &data,
1444 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1445 }
1446 offset += 1;
1447 break;
1448
1449 case4(054):
1450 data = (int64_t)opx->offset;
1451 out(offset, segment, &data, OUT_ADDRESS, 8,
1452 opx->segment, opx->wrt);
1453 offset += 8;
1454 break;
1455
1456 case4(060):
1457 if (opx->segment != segment) {
1458 data = opx->offset;
1459 out(offset, segment, &data,
1460 OUT_REL2ADR, insn_end - offset,
1461 opx->segment, opx->wrt);
1462 } else {
1463 data = opx->offset - insn_end;
1464 out(offset, segment, &data,
1465 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1466 }
1467 offset += 2;
1468 break;
1469
1470 case4(064):
1471 if (opx->type & (BITS16 | BITS32 | BITS64))
1472 size = (opx->type & BITS16) ? 2 : 4;
1473 else
1474 size = (bits == 16) ? 2 : 4;
1475 if (opx->segment != segment) {
1476 data = opx->offset;
1477 out(offset, segment, &data,
1478 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1479 insn_end - offset, opx->segment, opx->wrt);
1480 } else {
1481 data = opx->offset - insn_end;
1482 out(offset, segment, &data,
1483 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1484 }
1485 offset += size;
1486 break;
1487
1488 case4(070):
1489 if (opx->segment != segment) {
1490 data = opx->offset;
1491 out(offset, segment, &data,
1492 OUT_REL4ADR, insn_end - offset,
1493 opx->segment, opx->wrt);
1494 } else {
1495 data = opx->offset - insn_end;
1496 out(offset, segment, &data,
1497 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1498 }
1499 offset += 4;
1500 break;
1501
1502 case4(074):
1503 if (opx->segment == NO_SEG)
1504 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1505 " relocatable");
1506 data = 0;
1507 out(offset, segment, &data, OUT_ADDRESS, 2,
1508 outfmt->segbase(1 + opx->segment),
1509 opx->wrt);
1510 offset += 2;
1511 break;
1512
1513 case 0172:
1514 c = *codes++;
1515 opx = &ins->oprs[c >> 3];
1516 bytes[0] = nasm_regvals[opx->basereg] << 4;
1517 opx = &ins->oprs[c & 7];
1518 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1519 errfunc(ERR_NONFATAL,
1520 "non-absolute expression not permitted as argument %d",
1521 c & 7);
1522 } else {
1523 if (opx->offset & ~15) {
1524 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1525 "four-bit argument exceeds bounds");
1526 }
1527 bytes[0] |= opx->offset & 15;
1528 }
1529 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1530 offset++;
1531 break;
1532
1533 case 0173:
1534 c = *codes++;
1535 opx = &ins->oprs[c >> 4];
1536 bytes[0] = nasm_regvals[opx->basereg] << 4;
1537 bytes[0] |= c & 15;
1538 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1539 offset++;
1540 break;
1541
1542 case4(0174):
1543 bytes[0] = nasm_regvals[opx->basereg] << 4;
1544 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1545 offset++;
1546 break;
1547
1548 case4(0254):
1549 data = opx->offset;
1550 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1551 (int32_t)data != (int64_t)data) {
1552 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1553 "signed dword immediate exceeds bounds");
1554 }
1555 out(offset, segment, &data, OUT_ADDRESS, 4,
1556 opx->segment, opx->wrt);
1557 offset += 4;
1558 break;
1559
1560 case4(0240):
1561 case 0250:
1562 codes += 3;
1563 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1564 EVEX_P2Z | EVEX_P2AAA, 2);
1565 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1566 bytes[0] = 0x62;
1567 /* EVEX.X can be set by either REX or EVEX for different reasons */
1568 bytes[1] = ((((ins->rex & 7) << 5) |
1569 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1570 (ins->vex_cm & 3);
1571 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1572 ((~ins->vexreg & 15) << 3) |
1573 (1 << 2) | (ins->vex_wlp & 3);
1574 bytes[3] = ins->evex_p[2];
1575 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1576 offset += 4;
1577 break;
1578
1579 case4(0260):
1580 case 0270:
1581 codes += 2;
1582 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1583 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1584 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1585 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1586 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1587 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1588 offset += 3;
1589 } else {
1590 bytes[0] = 0xc5;
1591 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1592 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1593 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1594 offset += 2;
1595 }
1596 break;
1597
1598 case 0271:
1599 case 0272:
1600 case 0273:
1601 break;
1602
1603 case4(0274):
1604 {
1605 uint64_t uv, um;
1606 int s;
1607
1608 if (ins->rex & REX_W)
1609 s = 64;
1610 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1611 s = 16;
1612 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1613 s = 32;
1614 else
1615 s = bits;
1616
1617 um = (uint64_t)2 << (s-1);
1618 uv = opx->offset;
1619
1620 if (uv > 127 && uv < (uint64_t)-128 &&
1621 (uv < um-128 || uv > um-1)) {
1622 /* If this wasn't explicitly byte-sized, warn as though we
1623 * had fallen through to the imm16/32/64 case.
1624 */
1625 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1626 "%s value exceeds bounds",
1627 (opx->type & BITS8) ? "signed byte" :
1628 s == 16 ? "word" :
1629 s == 32 ? "dword" :
1630 "signed dword");
1631 }
1632 if (opx->segment != NO_SEG) {
1633 data = uv;
1634 out(offset, segment, &data, OUT_ADDRESS, 1,
1635 opx->segment, opx->wrt);
1636 } else {
1637 bytes[0] = uv;
1638 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1639 NO_SEG);
1640 }
1641 offset += 1;
1642 break;
1643 }
1644
1645 case4(0300):
1646 break;
1647
1648 case 0310:
1649 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1650 *bytes = 0x67;
1651 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1652 offset += 1;
1653 } else
1654 offset += 0;
1655 break;
1656
1657 case 0311:
1658 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1659 *bytes = 0x67;
1660 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1661 offset += 1;
1662 } else
1663 offset += 0;
1664 break;
1665
1666 case 0312:
1667 break;
1668
1669 case 0313:
1670 ins->rex = 0;
1671 break;
1672
1673 case4(0314):
1674 break;
1675
1676 case 0320:
1677 case 0321:
1678 break;
1679
1680 case 0322:
1681 case 0323:
1682 break;
1683
1684 case 0324:
1685 ins->rex |= REX_W;
1686 break;
1687
1688 case 0325:
1689 break;
1690
1691 case 0326:
1692 break;
1693
1694 case 0330:
1695 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1696 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1697 offset += 1;
1698 break;
1699
1700 case 0331:
1701 break;
1702
1703 case 0332:
1704 case 0333:
1705 *bytes = c - 0332 + 0xF2;
1706 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1707 offset += 1;
1708 break;
1709
1710 case 0334:
1711 if (ins->rex & REX_R) {
1712 *bytes = 0xF0;
1713 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1714 offset += 1;
1715 }
1716 ins->rex &= ~(REX_L|REX_R);
1717 break;
1718
1719 case 0335:
1720 break;
1721
1722 case 0336:
1723 case 0337:
1724 break;
1725
1726 case 0340:
1727 if (ins->oprs[0].segment != NO_SEG)
1728 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1729 else {
1730 int64_t size = ins->oprs[0].offset;
1731 if (size > 0)
1732 out(offset, segment, NULL,
1733 OUT_RESERVE, size, NO_SEG, NO_SEG);
1734 offset += size;
1735 }
1736 break;
1737
1738 case 0341:
1739 break;
1740
1741 case 0360:
1742 break;
1743
1744 case 0361:
1745 bytes[0] = 0x66;
1746 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1747 offset += 1;
1748 break;
1749
1750 case 0364:
1751 case 0365:
1752 break;
1753
1754 case 0366:
1755 case 0367:
1756 *bytes = c - 0366 + 0x66;
1757 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1758 offset += 1;
1759 break;
1760
1761 case3(0370):
1762 break;
1763
1764 case 0373:
1765 *bytes = bits == 16 ? 3 : 5;
1766 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1767 offset += 1;
1768 break;
1769
1770 case 0374:
1771 eat = EA_XMMVSIB;
1772 break;
1773
1774 case 0375:
1775 eat = EA_YMMVSIB;
1776 break;
1777
1778 case 0376:
1779 eat = EA_ZMMVSIB;
1780 break;
1781
1782 case4(0100):
1783 case4(0110):
1784 case4(0120):
1785 case4(0130):
1786 case4(0200):
1787 case4(0204):
1788 case4(0210):
1789 case4(0214):
1790 case4(0220):
1791 case4(0224):
1792 case4(0230):
1793 case4(0234):
1794 {
1795 ea ea_data;
1796 int rfield;
1797 opflags_t rflags;
1798 uint8_t *p;
1799 int32_t s;
1800 struct operand *opy = &ins->oprs[op2];
1801
1802 if (c <= 0177) {
1803 /* pick rfield from operand b (opx) */
1804 rflags = regflag(opx);
1805 rfield = nasm_regvals[opx->basereg];
1806 } else {
1807 /* rfield is constant */
1808 rflags = 0;
1809 rfield = c & 7;
1810 }
1811
1812 if (process_ea(opy, &ea_data, bits,
1813 rfield, rflags, ins) != eat)
1814 errfunc(ERR_NONFATAL, "invalid effective address");
1815
1816 p = bytes;
1817 *p++ = ea_data.modrm;
1818 if (ea_data.sib_present)
1819 *p++ = ea_data.sib;
1820
1821 s = p - bytes;
1822 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1823
1824 /*
1825 * Make sure the address gets the right offset in case
1826 * the line breaks in the .lst file (BR 1197827)
1827 */
1828 offset += s;
1829 s = 0;
1830
1831 switch (ea_data.bytes) {
1832 case 0:
1833 break;
1834 case 1:
1835 case 2:
1836 case 4:
1837 case 8:
1838 /* use compressed displacement, if available */
1839 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1840 s += ea_data.bytes;
1841 if (ea_data.rip) {
1842 if (opy->segment == segment) {
1843 data -= insn_end;
1844 if (overflow_signed(data, ea_data.bytes))
1845 warn_overflow(ERR_PASS2, ea_data.bytes);
1846 out(offset, segment, &data, OUT_ADDRESS,
1847 ea_data.bytes, NO_SEG, NO_SEG);
1848 } else {
1849 /* overflow check in output/linker? */
1850 out(offset, segment, &data, OUT_REL4ADR,
1851 insn_end - offset, opy->segment, opy->wrt);
1852 }
1853 } else {
1854 if (overflow_general(data, ins->addr_size >> 3) ||
1855 signed_bits(data, ins->addr_size) !=
1856 signed_bits(data, ea_data.bytes * 8))
1857 warn_overflow(ERR_PASS2, ea_data.bytes);
1858
1859 out(offset, segment, &data, OUT_ADDRESS,
1860 ea_data.bytes, opy->segment, opy->wrt);
1861 }
1862 break;
1863 default:
1864 /* Impossible! */
1865 errfunc(ERR_PANIC,
1866 "Invalid amount of bytes (%d) for offset?!",
1867 ea_data.bytes);
1868 break;
1869 }
1870 offset += s;
1871 }
1872 break;
1873
1874 default:
1875 errfunc(ERR_PANIC, "internal instruction table corrupt"
1876 ": instruction code \\%o (0x%02X) given", c, c);
1877 break;
1878 }
1879 }
1880 }
1881
1882 static opflags_t regflag(const operand * o)
1883 {
1884 if (!is_register(o->basereg))
1885 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1886 return nasm_reg_flags[o->basereg];
1887 }
1888
1889 static int32_t regval(const operand * o)
1890 {
1891 if (!is_register(o->basereg))
1892 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1893 return nasm_regvals[o->basereg];
1894 }
1895
1896 static int op_rexflags(const operand * o, int mask)
1897 {
1898 opflags_t flags;
1899 int val;
1900
1901 if (!is_register(o->basereg))
1902 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1903
1904 flags = nasm_reg_flags[o->basereg];
1905 val = nasm_regvals[o->basereg];
1906
1907 return rexflags(val, flags, mask);
1908 }
1909
1910 static int rexflags(int val, opflags_t flags, int mask)
1911 {
1912 int rex = 0;
1913
1914 if (val >= 0 && val & 8)
1915 rex |= REX_B|REX_X|REX_R;
1916 if (flags & BITS64)
1917 rex |= REX_W;
1918 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1919 rex |= REX_H;
1920 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1921 rex |= REX_P;
1922
1923 return rex & mask;
1924 }
1925
1926 static int evexflags(int val, decoflags_t deco,
1927 int mask, uint8_t byte)
1928 {
1929 int evex = 0;
1930
1931 switch (byte) {
1932 case 0:
1933 if (val >= 0 && val & 16)
1934 evex |= (EVEX_P0RP | EVEX_P0X);
1935 break;
1936 case 2:
1937 if (val >= 0 && val & 16)
1938 evex |= EVEX_P2VP;
1939 if (deco & Z)
1940 evex |= EVEX_P2Z;
1941 if (deco & OPMASK_MASK)
1942 evex |= deco & EVEX_P2AAA;
1943 break;
1944 }
1945 return evex & mask;
1946 }
1947
1948 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1949 {
1950 int val;
1951
1952 if (!is_register(o->basereg))
1953 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1954
1955 val = nasm_regvals[o->basereg];
1956
1957 return evexflags(val, o->decoflags, mask, byte);
1958 }
1959
1960 static enum match_result find_match(const struct itemplate **tempp,
1961 insn *instruction,
1962 int32_t segment, int64_t offset, int bits)
1963 {
1964 const struct itemplate *temp;
1965 enum match_result m, merr;
1966 opflags_t xsizeflags[MAX_OPERANDS];
1967 bool opsizemissing = false;
1968 int8_t broadcast = instruction->evex_brerop;
1969 int i;
1970
1971 /* broadcasting uses a different data element size */
1972 for (i = 0; i < instruction->operands; i++)
1973 if (i == broadcast)
1974 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1975 else
1976 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1977
1978 merr = MERR_INVALOP;
1979
1980 for (temp = nasm_instructions[instruction->opcode];
1981 temp->opcode != I_none; temp++) {
1982 m = matches(temp, instruction, bits);
1983 if (m == MOK_JUMP) {
1984 if (jmp_match(segment, offset, bits, instruction, temp))
1985 m = MOK_GOOD;
1986 else
1987 m = MERR_INVALOP;
1988 } else if (m == MERR_OPSIZEMISSING &&
1989 (temp->flags & IF_SMASK) != IF_SX) {
1990 /*
1991 * Missing operand size and a candidate for fuzzy matching...
1992 */
1993 for (i = 0; i < temp->operands; i++)
1994 if (i == broadcast)
1995 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1996 else
1997 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1998 opsizemissing = true;
1999 }
2000 if (m > merr)
2001 merr = m;
2002 if (merr == MOK_GOOD)
2003 goto done;
2004 }
2005
2006 /* No match, but see if we can get a fuzzy operand size match... */
2007 if (!opsizemissing)
2008 goto done;
2009
2010 for (i = 0; i < instruction->operands; i++) {
2011 /*
2012 * We ignore extrinsic operand sizes on registers, so we should
2013 * never try to fuzzy-match on them. This also resolves the case
2014 * when we have e.g. "xmmrm128" in two different positions.
2015 */
2016 if (is_class(REGISTER, instruction->oprs[i].type))
2017 continue;
2018
2019 /* This tests if xsizeflags[i] has more than one bit set */
2020 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2021 goto done; /* No luck */
2022
2023 if (i == broadcast)
2024 instruction->oprs[i].decoflags |= xsizeflags[i];
2025 else
2026 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2027 }
2028
2029 /* Try matching again... */
2030 for (temp = nasm_instructions[instruction->opcode];
2031 temp->opcode != I_none; temp++) {
2032 m = matches(temp, instruction, bits);
2033 if (m == MOK_JUMP) {
2034 if (jmp_match(segment, offset, bits, instruction, temp))
2035 m = MOK_GOOD;
2036 else
2037 m = MERR_INVALOP;
2038 }
2039 if (m > merr)
2040 merr = m;
2041 if (merr == MOK_GOOD)
2042 goto done;
2043 }
2044
2045 done:
2046 *tempp = temp;
2047 return merr;
2048 }
2049
2050 static enum match_result matches(const struct itemplate *itemp,
2051 insn *instruction, int bits)
2052 {
2053 opflags_t size[MAX_OPERANDS], asize;
2054 bool opsizemissing = false;
2055 int i, oprs;
2056
2057 /*
2058 * Check the opcode
2059 */
2060 if (itemp->opcode != instruction->opcode)
2061 return MERR_INVALOP;
2062
2063 /*
2064 * Count the operands
2065 */
2066 if (itemp->operands != instruction->operands)
2067 return MERR_INVALOP;
2068
2069 /*
2070 * Is it legal?
2071 */
2072 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2073 return MERR_INVALOP;
2074
2075 /*
2076 * Check that no spurious colons or TOs are present
2077 */
2078 for (i = 0; i < itemp->operands; i++)
2079 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2080 return MERR_INVALOP;
2081
2082 /*
2083 * Process size flags
2084 */
2085 switch (itemp->flags & IF_SMASK) {
2086 case IF_SB:
2087 asize = BITS8;
2088 break;
2089 case IF_SW:
2090 asize = BITS16;
2091 break;
2092 case IF_SD:
2093 asize = BITS32;
2094 break;
2095 case IF_SQ:
2096 asize = BITS64;
2097 break;
2098 case IF_SO:
2099 asize = BITS128;
2100 break;
2101 case IF_SY:
2102 asize = BITS256;
2103 break;
2104 case IF_SZ:
2105 asize = BITS512;
2106 break;
2107 case IF_SIZE:
2108 switch (bits) {
2109 case 16:
2110 asize = BITS16;
2111 break;
2112 case 32:
2113 asize = BITS32;
2114 break;
2115 case 64:
2116 asize = BITS64;
2117 break;
2118 default:
2119 asize = 0;
2120 break;
2121 }
2122 break;
2123 default:
2124 asize = 0;
2125 break;
2126 }
2127
2128 if (itemp->flags & IF_ARMASK) {
2129 /* S- flags only apply to a specific operand */
2130 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2131 memset(size, 0, sizeof size);
2132 size[i] = asize;
2133 } else {
2134 /* S- flags apply to all operands */
2135 for (i = 0; i < MAX_OPERANDS; i++)
2136 size[i] = asize;
2137 }
2138
2139 /*
2140 * Check that the operand flags all match up,
2141 * it's a bit tricky so lets be verbose:
2142 *
2143 * 1) Find out the size of operand. If instruction
2144 * doesn't have one specified -- we're trying to
2145 * guess it either from template (IF_S* flag) or
2146 * from code bits.
2147 *
2148 * 2) If template operand do not match the instruction OR
2149 * template has an operand size specified AND this size differ
2150 * from which instruction has (perhaps we got it from code bits)
2151 * we are:
2152 * a) Check that only size of instruction and operand is differ
2153 * other characteristics do match
2154 * b) Perhaps it's a register specified in instruction so
2155 * for such a case we just mark that operand as "size
2156 * missing" and this will turn on fuzzy operand size
2157 * logic facility (handled by a caller)
2158 */
2159 for (i = 0; i < itemp->operands; i++) {
2160 opflags_t type = instruction->oprs[i].type;
2161 decoflags_t deco = instruction->oprs[i].decoflags;
2162 if (!(type & SIZE_MASK))
2163 type |= size[i];
2164
2165 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2166 (itemp->deco[i] & deco) != deco) {
2167 return MERR_INVALOP;
2168 } else if ((itemp->opd[i] & SIZE_MASK) &&
2169 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2170 if (type & SIZE_MASK) {
2171 /*
2172 * when broadcasting, the element size depends on
2173 * the instruction type. decorator flag should match.
2174 */
2175 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2176 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2177 if (!((deco & BRDCAST_MASK) &&
2178 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2179 return MERR_INVALOP;
2180 }
2181 } else if (!is_class(REGISTER, type)) {
2182 /*
2183 * Note: we don't honor extrinsic operand sizes for registers,
2184 * so "missing operand size" for a register should be
2185 * considered a wildcard match rather than an error.
2186 */
2187 opsizemissing = true;
2188 }
2189 } else if (is_register(instruction->oprs[i].basereg) &&
2190 nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2191 !(itemp->flags & IF_AVX512)) {
2192 return MERR_ENCMISMATCH;
2193 } else if (instruction->prefixes[PPS_EVEX] &&
2194 !(itemp->flags & IF_AVX512)) {
2195 return MERR_ENCMISMATCH;
2196 }
2197 }
2198
2199 if (opsizemissing)
2200 return MERR_OPSIZEMISSING;
2201
2202 /*
2203 * Check operand sizes
2204 */
2205 if (itemp->flags & (IF_SM | IF_SM2)) {
2206 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2207 for (i = 0; i < oprs; i++) {
2208 asize = itemp->opd[i] & SIZE_MASK;
2209 if (asize) {
2210 for (i = 0; i < oprs; i++)
2211 size[i] = asize;
2212 break;
2213 }
2214 }
2215 } else {
2216 oprs = itemp->operands;
2217 }
2218
2219 for (i = 0; i < itemp->operands; i++) {
2220 if (!(itemp->opd[i] & SIZE_MASK) &&
2221 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2222 return MERR_OPSIZEMISMATCH;
2223 }
2224
2225 /*
2226 * Check template is okay at the set cpu level
2227 */
2228 if (((itemp->flags & IF_PLEVEL) > cpu))
2229 return MERR_BADCPU;
2230
2231 /*
2232 * Verify the appropriate long mode flag.
2233 */
2234 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2235 return MERR_BADMODE;
2236
2237 /*
2238 * If we have a HLE prefix, look for the NOHLE flag
2239 */
2240 if ((itemp->flags & IF_NOHLE) &&
2241 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2242 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2243 return MERR_BADHLE;
2244
2245 /*
2246 * Check if special handling needed for Jumps
2247 */
2248 if ((itemp->code[0] & ~1) == 0370)
2249 return MOK_JUMP;
2250
2251 /*
2252 * Check if BND prefix is allowed
2253 */
2254 if ((IF_BND & ~itemp->flags) &&
2255 has_prefix(instruction, PPS_REP, P_BND))
2256 return MERR_BADBND;
2257
2258 return MOK_GOOD;
2259 }
2260
2261 /*
2262 * Check if offset is a multiple of N with corresponding tuple type
2263 * if Disp8*N is available, compressed displacement is stored in compdisp
2264 */
2265 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2266 {
2267 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2268 {{16, 32, 64}, {8, 8, 8}}};
2269 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2270 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2271
2272 bool evex_b = input->decoflags & BRDCAST_MASK;
2273 enum ttypes tuple = ins->evex_tuple;
2274 /* vex_wlp composed as [wwllpp] */
2275 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2276 /* wig(=2) is treated as w0(=0) */
2277 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2278 int32_t off = input->offset;
2279 uint8_t n = 0;
2280 int32_t disp8;
2281
2282 switch(tuple) {
2283 case FV:
2284 n = fv_n[evex_w][evex_b][vectlen];
2285 break;
2286 case HV:
2287 n = hv_n[evex_b][vectlen];
2288 break;
2289
2290 case FVM:
2291 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2292 n = 1 << (vectlen + 4);
2293 break;
2294 case T1S8: /* N = 1 */
2295 case T1S16: /* N = 2 */
2296 n = tuple - T1S8 + 1;
2297 break;
2298 case T1S:
2299 /* N = 4 for 32bit, 8 for 64bit */
2300 n = evex_w ? 8 : 4;
2301 break;
2302 case T1F32:
2303 case T1F64:
2304 /* N = 4 for 32bit, 8 for 64bit */
2305 n = (tuple == T1F32 ? 4 : 8);
2306 break;
2307 case T2:
2308 case T4:
2309 case T8:
2310 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2311 n = 0;
2312 else
2313 n = 1 << (tuple - T2 + evex_w + 3);
2314 break;
2315 case HVM:
2316 case QVM:
2317 case OVM:
2318 n = 1 << (OVM - tuple + vectlen + 1);
2319 break;
2320 case M128:
2321 n = 16;
2322 break;
2323 case DUP:
2324 n = dup_n[vectlen];
2325 break;
2326
2327 default:
2328 break;
2329 }
2330
2331 if (n && !(off & (n - 1))) {
2332 disp8 = off / n;
2333 /* if it fits in Disp8 */
2334 if (disp8 >= -128 && disp8 <= 127) {
2335 *compdisp = disp8;
2336 return true;
2337 }
2338 }
2339
2340 *compdisp = 0;
2341 return false;
2342 }
2343
2344 /*
2345 * Check if ModR/M.mod should/can be 01.
2346 * - EAF_BYTEOFFS is set
2347 * - offset can fit in a byte when EVEX is not used
2348 * - offset can be compressed when EVEX is used
2349 */
2350 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2351 (o >= -128 && o <= 127 && \
2352 seg == NO_SEG && !forw_ref && \
2353 !(input->eaflags & EAF_WORDOFFS) && \
2354 !(ins->rex & REX_EV)) || \
2355 (ins->rex & REX_EV && \
2356 is_disp8n(input, ins, &output->disp8)))
2357
2358 static enum ea_type process_ea(operand *input, ea *output, int bits,
2359 int rfield, opflags_t rflags, insn *ins)
2360 {
2361 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2362 int addrbits = ins->addr_size;
2363
2364 output->type = EA_SCALAR;
2365 output->rip = false;
2366 output->disp8 = 0;
2367
2368 /* REX flags for the rfield operand */
2369 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2370 /* EVEX.R' flag for the REG operand */
2371 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2372
2373 if (is_class(REGISTER, input->type)) {
2374 /*
2375 * It's a direct register.
2376 */
2377 if (!is_register(input->basereg))
2378 goto err;
2379
2380 if (!is_reg_class(REG_EA, input->basereg))
2381 goto err;
2382
2383 /* broadcasting is not available with a direct register operand. */
2384 if (input->decoflags & BRDCAST_MASK) {
2385 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2386 goto err;
2387 }
2388
2389 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2390 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2391 output->sib_present = false; /* no SIB necessary */
2392 output->bytes = 0; /* no offset necessary either */
2393 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2394 } else {
2395 /*
2396 * It's a memory reference.
2397 */
2398
2399 /* Embedded rounding or SAE is not available with a mem ref operand. */
2400 if (input->decoflags & (ER | SAE)) {
2401 nasm_error(ERR_NONFATAL,
2402 "Embedded rounding is available only with reg-reg op.");
2403 return -1;
2404 }
2405
2406 if (input->basereg == -1 &&
2407 (input->indexreg == -1 || input->scale == 0)) {
2408 /*
2409 * It's a pure offset.
2410 */
2411 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2412 input->segment == NO_SEG) {
2413 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2414 input->type &= ~IP_REL;
2415 input->type |= MEMORY;
2416 }
2417
2418 if (input->eaflags & EAF_BYTEOFFS ||
2419 (input->eaflags & EAF_WORDOFFS &&
2420 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2421 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2422 }
2423
2424 if (bits == 64 && (~input->type & IP_REL)) {
2425 output->sib_present = true;
2426 output->sib = GEN_SIB(0, 4, 5);
2427 output->bytes = 4;
2428 output->modrm = GEN_MODRM(0, rfield, 4);
2429 output->rip = false;
2430 } else {
2431 output->sib_present = false;
2432 output->bytes = (addrbits != 16 ? 4 : 2);
2433 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2434 output->rip = bits == 64;
2435 }
2436 } else {
2437 /*
2438 * It's an indirection.
2439 */
2440 int i = input->indexreg, b = input->basereg, s = input->scale;
2441 int32_t seg = input->segment;
2442 int hb = input->hintbase, ht = input->hinttype;
2443 int t, it, bt; /* register numbers */
2444 opflags_t x, ix, bx; /* register flags */
2445
2446 if (s == 0)
2447 i = -1; /* make this easy, at least */
2448
2449 if (is_register(i)) {
2450 it = nasm_regvals[i];
2451 ix = nasm_reg_flags[i];
2452 } else {
2453 it = -1;
2454 ix = 0;
2455 }
2456
2457 if (is_register(b)) {
2458 bt = nasm_regvals[b];
2459 bx = nasm_reg_flags[b];
2460 } else {
2461 bt = -1;
2462 bx = 0;
2463 }
2464
2465 /* if either one are a vector register... */
2466 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2467 opflags_t sok = BITS32 | BITS64;
2468 int32_t o = input->offset;
2469 int mod, scale, index, base;
2470
2471 /*
2472 * For a vector SIB, one has to be a vector and the other,
2473 * if present, a GPR. The vector must be the index operand.
2474 */
2475 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2476 if (s == 0)
2477 s = 1;
2478 else if (s != 1)
2479 goto err;
2480
2481 t = bt, bt = it, it = t;
2482 x = bx, bx = ix, ix = x;
2483 }
2484
2485 if (bt != -1) {
2486 if (REG_GPR & ~bx)
2487 goto err;
2488 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2489 sok &= bx;
2490 else
2491 goto err;
2492 }
2493
2494 /*
2495 * While we're here, ensure the user didn't specify
2496 * WORD or QWORD
2497 */
2498 if (input->disp_size == 16 || input->disp_size == 64)
2499 goto err;
2500
2501 if (addrbits == 16 ||
2502 (addrbits == 32 && !(sok & BITS32)) ||
2503 (addrbits == 64 && !(sok & BITS64)))
2504 goto err;
2505
2506 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2507 : ((ix & YMMREG & ~REG_EA)
2508 ? EA_YMMVSIB : EA_XMMVSIB));
2509
2510 output->rex |= rexflags(it, ix, REX_X);
2511 output->rex |= rexflags(bt, bx, REX_B);
2512 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2513
2514 index = it & 7; /* it is known to be != -1 */
2515
2516 switch (s) {
2517 case 1:
2518 scale = 0;
2519 break;
2520 case 2:
2521 scale = 1;
2522 break;
2523 case 4:
2524 scale = 2;
2525 break;
2526 case 8:
2527 scale = 3;
2528 break;
2529 default: /* then what the smeg is it? */
2530 goto err; /* panic */
2531 }
2532
2533 if (bt == -1) {
2534 base = 5;
2535 mod = 0;
2536 } else {
2537 base = (bt & 7);
2538 if (base != REG_NUM_EBP && o == 0 &&
2539 seg == NO_SEG && !forw_ref &&
2540 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2541 mod = 0;
2542 else if (IS_MOD_01())
2543 mod = 1;
2544 else
2545 mod = 2;
2546 }
2547
2548 output->sib_present = true;
2549 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2550 output->modrm = GEN_MODRM(mod, rfield, 4);
2551 output->sib = GEN_SIB(scale, index, base);
2552 } else if ((ix|bx) & (BITS32|BITS64)) {
2553 /*
2554 * it must be a 32/64-bit memory reference. Firstly we have
2555 * to check that all registers involved are type E/Rxx.
2556 */
2557 opflags_t sok = BITS32 | BITS64;
2558 int32_t o = input->offset;
2559
2560 if (it != -1) {
2561 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2562 sok &= ix;
2563 else
2564 goto err;
2565 }
2566
2567 if (bt != -1) {
2568 if (REG_GPR & ~bx)
2569 goto err; /* Invalid register */
2570 if (~sok & bx & SIZE_MASK)
2571 goto err; /* Invalid size */
2572 sok &= bx;
2573 }
2574
2575 /*
2576 * While we're here, ensure the user didn't specify
2577 * WORD or QWORD
2578 */
2579 if (input->disp_size == 16 || input->disp_size == 64)
2580 goto err;
2581
2582 if (addrbits == 16 ||
2583 (addrbits == 32 && !(sok & BITS32)) ||
2584 (addrbits == 64 && !(sok & BITS64)))
2585 goto err;
2586
2587 /* now reorganize base/index */
2588 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2589 ((hb == b && ht == EAH_NOTBASE) ||
2590 (hb == i && ht == EAH_MAKEBASE))) {
2591 /* swap if hints say so */
2592 t = bt, bt = it, it = t;
2593 x = bx, bx = ix, ix = x;
2594 }
2595 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2596 bt = -1, bx = 0, s++;
2597 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2598 /* make single reg base, unless hint */
2599 bt = it, bx = ix, it = -1, ix = 0;
2600 }
2601 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2602 s == 3 || s == 5 || s == 9) && bt == -1)
2603 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2604 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2605 (input->eaflags & EAF_TIMESTWO))
2606 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2607 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2608 if (s == 1 && it == REG_NUM_ESP) {
2609 /* swap ESP into base if scale is 1 */
2610 t = it, it = bt, bt = t;
2611 x = ix, ix = bx, bx = x;
2612 }
2613 if (it == REG_NUM_ESP ||
2614 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2615 goto err; /* wrong, for various reasons */
2616
2617 output->rex |= rexflags(it, ix, REX_X);
2618 output->rex |= rexflags(bt, bx, REX_B);
2619
2620 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2621 /* no SIB needed */
2622 int mod, rm;
2623
2624 if (bt == -1) {
2625 rm = 5;
2626 mod = 0;
2627 } else {
2628 rm = (bt & 7);
2629 if (rm != REG_NUM_EBP && o == 0 &&
2630 seg == NO_SEG && !forw_ref &&
2631 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2632 mod = 0;
2633 else if (IS_MOD_01())
2634 mod = 1;
2635 else
2636 mod = 2;
2637 }
2638
2639 output->sib_present = false;
2640 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2641 output->modrm = GEN_MODRM(mod, rfield, rm);
2642 } else {
2643 /* we need a SIB */
2644 int mod, scale, index, base;
2645
2646 if (it == -1)
2647 index = 4, s = 1;
2648 else
2649 index = (it & 7);
2650
2651 switch (s) {
2652 case 1:
2653 scale = 0;
2654 break;
2655 case 2:
2656 scale = 1;
2657 break;
2658 case 4:
2659 scale = 2;
2660 break;
2661 case 8:
2662 scale = 3;
2663 break;
2664 default: /* then what the smeg is it? */
2665 goto err; /* panic */
2666 }
2667
2668 if (bt == -1) {
2669 base = 5;
2670 mod = 0;
2671 } else {
2672 base = (bt & 7);
2673 if (base != REG_NUM_EBP && o == 0 &&
2674 seg == NO_SEG && !forw_ref &&
2675 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2676 mod = 0;
2677 else if (IS_MOD_01())
2678 mod = 1;
2679 else
2680 mod = 2;
2681 }
2682
2683 output->sib_present = true;
2684 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2685 output->modrm = GEN_MODRM(mod, rfield, 4);
2686 output->sib = GEN_SIB(scale, index, base);
2687 }
2688 } else { /* it's 16-bit */
2689 int mod, rm;
2690 int16_t o = input->offset;
2691
2692 /* check for 64-bit long mode */
2693 if (addrbits == 64)
2694 goto err;
2695
2696 /* check all registers are BX, BP, SI or DI */
2697 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2698 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2699 goto err;
2700
2701 /* ensure the user didn't specify DWORD/QWORD */
2702 if (input->disp_size == 32 || input->disp_size == 64)
2703 goto err;
2704
2705 if (s != 1 && i != -1)
2706 goto err; /* no can do, in 16-bit EA */
2707 if (b == -1 && i != -1) {
2708 int tmp = b;
2709 b = i;
2710 i = tmp;
2711 } /* swap */
2712 if ((b == R_SI || b == R_DI) && i != -1) {
2713 int tmp = b;
2714 b = i;
2715 i = tmp;
2716 }
2717 /* have BX/BP as base, SI/DI index */
2718 if (b == i)
2719 goto err; /* shouldn't ever happen, in theory */
2720 if (i != -1 && b != -1 &&
2721 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2722 goto err; /* invalid combinations */
2723 if (b == -1) /* pure offset: handled above */
2724 goto err; /* so if it gets to here, panic! */
2725
2726 rm = -1;
2727 if (i != -1)
2728 switch (i * 256 + b) {
2729 case R_SI * 256 + R_BX:
2730 rm = 0;
2731 break;
2732 case R_DI * 256 + R_BX:
2733 rm = 1;
2734 break;
2735 case R_SI * 256 + R_BP:
2736 rm = 2;
2737 break;
2738 case R_DI * 256 + R_BP:
2739 rm = 3;
2740 break;
2741 } else
2742 switch (b) {
2743 case R_SI:
2744 rm = 4;
2745 break;
2746 case R_DI:
2747 rm = 5;
2748 break;
2749 case R_BP:
2750 rm = 6;
2751 break;
2752 case R_BX:
2753 rm = 7;
2754 break;
2755 }
2756 if (rm == -1) /* can't happen, in theory */
2757 goto err; /* so panic if it does */
2758
2759 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2760 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2761 mod = 0;
2762 else if (IS_MOD_01())
2763 mod = 1;
2764 else
2765 mod = 2;
2766
2767 output->sib_present = false; /* no SIB - it's 16-bit */
2768 output->bytes = mod; /* bytes of offset needed */
2769 output->modrm = GEN_MODRM(mod, rfield, rm);
2770 }
2771 }
2772 }
2773
2774 output->size = 1 + output->sib_present + output->bytes;
2775 return output->type;
2776
2777 err:
2778 return output->type = EA_INVALID;
2779 }
2780
2781 static void add_asp(insn *ins, int addrbits)
2782 {
2783 int j, valid;
2784 int defdisp;
2785
2786 valid = (addrbits == 64) ? 64|32 : 32|16;
2787
2788 switch (ins->prefixes[PPS_ASIZE]) {
2789 case P_A16:
2790 valid &= 16;
2791 break;
2792 case P_A32:
2793 valid &= 32;
2794 break;
2795 case P_A64:
2796 valid &= 64;
2797 break;
2798 case P_ASP:
2799 valid &= (addrbits == 32) ? 16 : 32;
2800 break;
2801 default:
2802 break;
2803 }
2804
2805 for (j = 0; j < ins->operands; j++) {
2806 if (is_class(MEMORY, ins->oprs[j].type)) {
2807 opflags_t i, b;
2808
2809 /* Verify as Register */
2810 if (!is_register(ins->oprs[j].indexreg))
2811 i = 0;
2812 else
2813 i = nasm_reg_flags[ins->oprs[j].indexreg];
2814
2815 /* Verify as Register */
2816 if (!is_register(ins->oprs[j].basereg))
2817 b = 0;
2818 else
2819 b = nasm_reg_flags[ins->oprs[j].basereg];
2820
2821 if (ins->oprs[j].scale == 0)
2822 i = 0;
2823
2824 if (!i && !b) {
2825 int ds = ins->oprs[j].disp_size;
2826 if ((addrbits != 64 && ds > 8) ||
2827 (addrbits == 64 && ds == 16))
2828 valid &= ds;
2829 } else {
2830 if (!(REG16 & ~b))
2831 valid &= 16;
2832 if (!(REG32 & ~b))
2833 valid &= 32;
2834 if (!(REG64 & ~b))
2835 valid &= 64;
2836
2837 if (!(REG16 & ~i))
2838 valid &= 16;
2839 if (!(REG32 & ~i))
2840 valid &= 32;
2841 if (!(REG64 & ~i))
2842 valid &= 64;
2843 }
2844 }
2845 }
2846
2847 if (valid & addrbits) {
2848 ins->addr_size = addrbits;
2849 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2850 /* Add an address size prefix */
2851 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2852 ins->addr_size = (addrbits == 32) ? 16 : 32;
2853 } else {
2854 /* Impossible... */
2855 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2856 ins->addr_size = addrbits; /* Error recovery */
2857 }
2858
2859 defdisp = ins->addr_size == 16 ? 16 : 32;
2860
2861 for (j = 0; j < ins->operands; j++) {
2862 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2863 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2864 /*
2865 * mem_offs sizes must match the address size; if not,
2866 * strip the MEM_OFFS bit and match only EA instructions
2867 */
2868 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2869 }
2870 }
2871 }
Adding AVX-512 features