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NASM 2.00rc3
[nasm/avx512.git] / assemble.c
blob30921edb514d428c7fb77c6dc46f4e365aafb020
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a word. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \314 - (disassembler only) invalid with REX.B
58 * \315 - (disassembler only) invalid with REX.X
59 * \316 - (disassembler only) invalid with REX.R
60 * \317 - (disassembler only) invalid with REX.W
61 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
62 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
63 * \322 - indicates that this instruction is only valid when the
64 * operand size is the default (instruction to disassembler,
65 * generates no code in the assembler)
66 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
67 * \324 - indicates 64-bit operand size requiring REX prefix.
68 * \330 - a literal byte follows in the code stream, to be added
69 * to the condition code value of the instruction.
70 * \331 - instruction not valid with REP prefix. Hint for
71 * disassembler only; for SSE instructions.
72 * \332 - REP prefix (0xF2 byte) used as opcode extension.
73 * \333 - REP prefix (0xF3 byte) used as opcode extension.
74 * \334 - LOCK prefix used instead of REX.R
75 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
76 * \340 - reserve <operand 0> bytes of uninitialized storage.
77 * Operand 0 had better be a segmentless constant.
78 * \364 - operand-size prefix (0x66) not permitted
79 * \365 - address-size prefix (0x67) not permitted
80 * \366 - operand-size prefix (0x66) used as opcode extension
81 * \367 - address-size prefix (0x67) used as opcode extension
82 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
83 * 370 is used for Jcc, 371 is used for JMP.
84 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
85 * used for conditional jump over longer jump
86 */
87
88 #include "compiler.h"
89
90 #include <stdio.h>
91 #include <string.h>
92 #include <inttypes.h>
93
94 #include "nasm.h"
95 #include "nasmlib.h"
96 #include "assemble.h"
97 #include "insns.h"
98 #include "preproc.h"
99 #include "regflags.c"
100 #include "regvals.c"
101
102 typedef struct {
103 int sib_present; /* is a SIB byte necessary? */
104 int bytes; /* # of bytes of offset needed */
105 int size; /* lazy - this is sib+bytes+1 */
106 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
107 } ea;
108
109 static uint32_t cpu; /* cpu level received from nasm.c */
110 static efunc errfunc;
111 static struct ofmt *outfmt;
112 static ListGen *list;
113
114 static int64_t calcsize(int32_t, int64_t, int, insn *, const char *);
115 static void gencode(int32_t, int64_t, int, insn *, const char *, int64_t);
116 static int matches(const struct itemplate *, insn *, int bits);
117 static int32_t regflag(const operand *);
118 static int32_t regval(const operand *);
119 static int rexflags(int, int32_t, int);
120 static int op_rexflags(const operand *, int);
121 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
122 static void add_asp(insn *, int);
123
124 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
125 {
126 return ins->prefixes[pos] == prefix;
127 }
128
129 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
130 {
131 if (ins->prefixes[pos])
132 errfunc(ERR_NONFATAL, "invalid %s prefix",
133 prefix_name(ins->prefixes[pos]));
134 }
135
136 static const char *size_name(int size)
137 {
138 switch (size) {
139 case 1:
140 return "byte";
141 case 2:
142 return "word";
143 case 4:
144 return "dword";
145 case 8:
146 return "qword";
147 case 10:
148 return "tword";
149 case 16:
150 return "oword";
151 default:
152 return "???";
153 }
154 }
155
156 static void warn_overflow(int size, int64_t data)
157 {
158 if (size < 8) {
159 int64_t lim = ((int64_t)1 << (size*8))-1;
160
161 if (data < ~lim || data > lim)
162 errfunc(ERR_WARNING, "%s data exceeds bounds", size_name(size));
163 }
164 }
165 /*
166 * This routine wrappers the real output format's output routine,
167 * in order to pass a copy of the data off to the listing file
168 * generator at the same time.
169 */
170 static void out(int64_t offset, int32_t segto, const void *data,
171 enum out_type type, uint64_t size,
172 int32_t segment, int32_t wrt)
173 {
174 static int32_t lineno = 0; /* static!!! */
175 static char *lnfname = NULL;
176 uint8_t p[8];
177
178 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
179 /*
180 * This is a non-relocated address, and we're going to
181 * convert it into RAWDATA format.
182 */
183 uint8_t *q = p;
184
185 if (size > 8) {
186 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
187 return;
188 }
189
190 WRITEADDR(q, *(int64_t *)data, size);
191 data = p;
192 type = OUT_RAWDATA;
193 }
194
195 list->output(offset, data, type, size);
196
197 /*
198 * this call to src_get determines when we call the
199 * debug-format-specific "linenum" function
200 * it updates lineno and lnfname to the current values
201 * returning 0 if "same as last time", -2 if lnfname
202 * changed, and the amount by which lineno changed,
203 * if it did. thus, these variables must be static
204 */
205
206 if (src_get(&lineno, &lnfname)) {
207 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
208 }
209
210 outfmt->output(segto, data, type, size, segment, wrt);
211 }
212
213 static int jmp_match(int32_t segment, int64_t offset, int bits,
214 insn * ins, const char *code)
215 {
216 int64_t isize;
217 uint8_t c = code[0];
218
219 if (c != 0370 && c != 0371)
220 return 0;
221 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
222 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
223 && c == 0370)
224 return 1;
225 else
226 return (pass0 == 0); /* match a forward reference */
227 }
228 isize = calcsize(segment, offset, bits, ins, code);
229 if (ins->oprs[0].segment != segment)
230 return 0;
231 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
232 if (isize >= -128L && isize <= 127L)
233 return 1; /* it is byte size */
234
235 return 0;
236 }
237
238 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
239 insn * instruction, struct ofmt *output, efunc error,
240 ListGen * listgen)
241 {
242 const struct itemplate *temp;
243 int j;
244 int size_prob;
245 int64_t insn_end;
246 int32_t itimes;
247 int64_t start = offset;
248 int64_t wsize = 0; /* size for DB etc. */
249
250 errfunc = error; /* to pass to other functions */
251 cpu = cp;
252 outfmt = output; /* likewise */
253 list = listgen; /* and again */
254
255 switch (instruction->opcode) {
256 case -1:
257 return 0;
258 case I_DB:
259 wsize = 1;
260 break;
261 case I_DW:
262 wsize = 2;
263 break;
264 case I_DD:
265 wsize = 4;
266 break;
267 case I_DQ:
268 wsize = 8;
269 break;
270 case I_DT:
271 wsize = 10;
272 break;
273 case I_DO:
274 wsize = 16;
275 break;
276 default:
277 break;
278 }
279
280 if (wsize) {
281 extop *e;
282 int32_t t = instruction->times;
283 if (t < 0)
284 errfunc(ERR_PANIC,
285 "instruction->times < 0 (%ld) in assemble()", t);
286
287 while (t--) { /* repeat TIMES times */
288 for (e = instruction->eops; e; e = e->next) {
289 if (e->type == EOT_DB_NUMBER) {
290 if (wsize == 1) {
291 if (e->segment != NO_SEG)
292 errfunc(ERR_NONFATAL,
293 "one-byte relocation attempted");
294 else {
295 uint8_t out_byte = e->offset;
296 out(offset, segment, &out_byte,
297 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
298 }
299 } else if (wsize > 8) {
300 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
301 " instruction");
302 } else
303 out(offset, segment, &e->offset,
304 OUT_ADDRESS, wsize, e->segment, e->wrt);
305 offset += wsize;
306 } else if (e->type == EOT_DB_STRING) {
307 int align;
308
309 out(offset, segment, e->stringval,
310 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
311 align = e->stringlen % wsize;
312
313 if (align) {
314 align = wsize - align;
315 out(offset, segment, "\0\0\0\0\0\0\0\0",
316 OUT_RAWDATA, align, NO_SEG, NO_SEG);
317 }
318 offset += e->stringlen + align;
319 }
320 }
321 if (t > 0 && t == instruction->times - 1) {
322 /*
323 * Dummy call to list->output to give the offset to the
324 * listing module.
325 */
326 list->output(offset, NULL, OUT_RAWDATA, 0);
327 list->uplevel(LIST_TIMES);
328 }
329 }
330 if (instruction->times > 1)
331 list->downlevel(LIST_TIMES);
332 return offset - start;
333 }
334
335 if (instruction->opcode == I_INCBIN) {
336 static char fname[FILENAME_MAX];
337 FILE *fp;
338 int32_t len;
339 char *prefix = "", *combine;
340 char **pPrevPath = NULL;
341
342 len = FILENAME_MAX - 1;
343 if (len > instruction->eops->stringlen)
344 len = instruction->eops->stringlen;
345 strncpy(fname, instruction->eops->stringval, len);
346 fname[len] = '\0';
347
348 while (1) { /* added by alexfru: 'incbin' uses include paths */
349 combine = nasm_malloc(strlen(prefix) + len + 1);
350 strcpy(combine, prefix);
351 strcat(combine, fname);
352
353 if ((fp = fopen(combine, "rb")) != NULL) {
354 nasm_free(combine);
355 break;
356 }
357
358 nasm_free(combine);
359 pPrevPath = pp_get_include_path_ptr(pPrevPath);
360 if (pPrevPath == NULL)
361 break;
362 prefix = *pPrevPath;
363 }
364
365 if (fp == NULL)
366 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
367 fname);
368 else if (fseek(fp, 0L, SEEK_END) < 0)
369 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
370 fname);
371 else {
372 static char buf[2048];
373 int32_t t = instruction->times;
374 int32_t base = 0;
375
376 len = ftell(fp);
377 if (instruction->eops->next) {
378 base = instruction->eops->next->offset;
379 len -= base;
380 if (instruction->eops->next->next &&
381 len > instruction->eops->next->next->offset)
382 len = instruction->eops->next->next->offset;
383 }
384 /*
385 * Dummy call to list->output to give the offset to the
386 * listing module.
387 */
388 list->output(offset, NULL, OUT_RAWDATA, 0);
389 list->uplevel(LIST_INCBIN);
390 while (t--) {
391 int32_t l;
392
393 fseek(fp, base, SEEK_SET);
394 l = len;
395 while (l > 0) {
396 int32_t m =
397 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
398 fp);
399 if (!m) {
400 /*
401 * This shouldn't happen unless the file
402 * actually changes while we are reading
403 * it.
404 */
405 error(ERR_NONFATAL,
406 "`incbin': unexpected EOF while"
407 " reading file `%s'", fname);
408 t = 0; /* Try to exit cleanly */
409 break;
410 }
411 out(offset, segment, buf, OUT_RAWDATA, m,
412 NO_SEG, NO_SEG);
413 l -= m;
414 }
415 }
416 list->downlevel(LIST_INCBIN);
417 if (instruction->times > 1) {
418 /*
419 * Dummy call to list->output to give the offset to the
420 * listing module.
421 */
422 list->output(offset, NULL, OUT_RAWDATA, 0);
423 list->uplevel(LIST_TIMES);
424 list->downlevel(LIST_TIMES);
425 }
426 fclose(fp);
427 return instruction->times * len;
428 }
429 return 0; /* if we're here, there's an error */
430 }
431
432 /* Check to see if we need an address-size prefix */
433 add_asp(instruction, bits);
434
435 size_prob = false;
436
437 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
438 int m = matches(temp, instruction, bits);
439
440 if (m == 99)
441 m += jmp_match(segment, offset, bits, instruction, temp->code);
442
443 if (m == 100) { /* matches! */
444 const char *codes = temp->code;
445 int64_t insn_size = calcsize(segment, offset, bits,
446 instruction, codes);
447 itimes = instruction->times;
448 if (insn_size < 0) /* shouldn't be, on pass two */
449 error(ERR_PANIC, "errors made it through from pass one");
450 else
451 while (itimes--) {
452 for (j = 0; j < MAXPREFIX; j++) {
453 uint8_t c = 0;
454 switch (instruction->prefixes[j]) {
455 case P_LOCK:
456 c = 0xF0;
457 break;
458 case P_REPNE:
459 case P_REPNZ:
460 c = 0xF2;
461 break;
462 case P_REPE:
463 case P_REPZ:
464 case P_REP:
465 c = 0xF3;
466 break;
467 case R_CS:
468 if (bits == 64) {
469 error(ERR_WARNING,
470 "cs segment base generated, but will be ignored in 64-bit mode");
471 }
472 c = 0x2E;
473 break;
474 case R_DS:
475 if (bits == 64) {
476 error(ERR_WARNING,
477 "ds segment base generated, but will be ignored in 64-bit mode");
478 }
479 c = 0x3E;
480 break;
481 case R_ES:
482 if (bits == 64) {
483 error(ERR_WARNING,
484 "es segment base generated, but will be ignored in 64-bit mode");
485 }
486 c = 0x26;
487 break;
488 case R_FS:
489 c = 0x64;
490 break;
491 case R_GS:
492 c = 0x65;
493 break;
494 case R_SS:
495 if (bits == 64) {
496 error(ERR_WARNING,
497 "ss segment base generated, but will be ignored in 64-bit mode");
498 }
499 c = 0x36;
500 break;
501 case R_SEGR6:
502 case R_SEGR7:
503 error(ERR_NONFATAL,
504 "segr6 and segr7 cannot be used as prefixes");
505 break;
506 case P_A16:
507 if (bits == 64) {
508 error(ERR_NONFATAL,
509 "16-bit addressing is not supported "
510 "in 64-bit mode");
511 } else if (bits != 16)
512 c = 0x67;
513 break;
514 case P_A32:
515 if (bits != 32)
516 c = 0x67;
517 break;
518 case P_A64:
519 if (bits != 64) {
520 error(ERR_NONFATAL,
521 "64-bit addressing is only supported "
522 "in 64-bit mode");
523 }
524 break;
525 case P_ASP:
526 c = 0x67;
527 break;
528 case P_O16:
529 if (bits != 16)
530 c = 0x66;
531 break;
532 case P_O32:
533 if (bits == 16)
534 c = 0x66;
535 break;
536 case P_O64:
537 /* REX.W */
538 break;
539 case P_OSP:
540 c = 0x66;
541 break;
542 case P_none:
543 break;
544 default:
545 error(ERR_PANIC, "invalid instruction prefix");
546 }
547 if (c != 0) {
548 out(offset, segment, &c, OUT_RAWDATA, 1,
549 NO_SEG, NO_SEG);
550 offset++;
551 }
552 }
553 insn_end = offset + insn_size;
554 gencode(segment, offset, bits, instruction, codes,
555 insn_end);
556 offset += insn_size;
557 if (itimes > 0 && itimes == instruction->times - 1) {
558 /*
559 * Dummy call to list->output to give the offset to the
560 * listing module.
561 */
562 list->output(offset, NULL, OUT_RAWDATA, 0);
563 list->uplevel(LIST_TIMES);
564 }
565 }
566 if (instruction->times > 1)
567 list->downlevel(LIST_TIMES);
568 return offset - start;
569 } else if (m > 0 && m > size_prob) {
570 size_prob = m;
571 }
572 // temp++;
573 }
574
575 if (temp->opcode == -1) { /* didn't match any instruction */
576 switch (size_prob) {
577 case 1:
578 error(ERR_NONFATAL, "operation size not specified");
579 break;
580 case 2:
581 error(ERR_NONFATAL, "mismatch in operand sizes");
582 break;
583 case 3:
584 error(ERR_NONFATAL, "no instruction for this cpu level");
585 break;
586 case 4:
587 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
588 break;
589 default:
590 error(ERR_NONFATAL,
591 "invalid combination of opcode and operands");
592 break;
593 }
594 }
595 return 0;
596 }
597
598 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
599 insn * instruction, efunc error)
600 {
601 const struct itemplate *temp;
602
603 errfunc = error; /* to pass to other functions */
604 cpu = cp;
605
606 if (instruction->opcode == -1)
607 return 0;
608
609 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
610 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
611 instruction->opcode == I_DT || instruction->opcode == I_DO) {
612 extop *e;
613 int32_t isize, osize, wsize = 0; /* placate gcc */
614
615 isize = 0;
616 switch (instruction->opcode) {
617 case I_DB:
618 wsize = 1;
619 break;
620 case I_DW:
621 wsize = 2;
622 break;
623 case I_DD:
624 wsize = 4;
625 break;
626 case I_DQ:
627 wsize = 8;
628 break;
629 case I_DT:
630 wsize = 10;
631 break;
632 case I_DO:
633 wsize = 16;
634 break;
635 default:
636 break;
637 }
638
639 for (e = instruction->eops; e; e = e->next) {
640 int32_t align;
641
642 osize = 0;
643 if (e->type == EOT_DB_NUMBER)
644 osize = 1;
645 else if (e->type == EOT_DB_STRING)
646 osize = e->stringlen;
647
648 align = (-osize) % wsize;
649 if (align < 0)
650 align += wsize;
651 isize += osize + align;
652 }
653 return isize * instruction->times;
654 }
655
656 if (instruction->opcode == I_INCBIN) {
657 char fname[FILENAME_MAX];
658 FILE *fp;
659 int32_t len;
660 char *prefix = "", *combine;
661 char **pPrevPath = NULL;
662
663 len = FILENAME_MAX - 1;
664 if (len > instruction->eops->stringlen)
665 len = instruction->eops->stringlen;
666 strncpy(fname, instruction->eops->stringval, len);
667 fname[len] = '\0';
668
669 /* added by alexfru: 'incbin' uses include paths */
670 while (1) {
671 combine = nasm_malloc(strlen(prefix) + len + 1);
672 strcpy(combine, prefix);
673 strcat(combine, fname);
674
675 if ((fp = fopen(combine, "rb")) != NULL) {
676 nasm_free(combine);
677 break;
678 }
679
680 nasm_free(combine);
681 pPrevPath = pp_get_include_path_ptr(pPrevPath);
682 if (pPrevPath == NULL)
683 break;
684 prefix = *pPrevPath;
685 }
686
687 if (fp == NULL)
688 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
689 fname);
690 else if (fseek(fp, 0L, SEEK_END) < 0)
691 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
692 fname);
693 else {
694 len = ftell(fp);
695 fclose(fp);
696 if (instruction->eops->next) {
697 len -= instruction->eops->next->offset;
698 if (instruction->eops->next->next &&
699 len > instruction->eops->next->next->offset) {
700 len = instruction->eops->next->next->offset;
701 }
702 }
703 return instruction->times * len;
704 }
705 return 0; /* if we're here, there's an error */
706 }
707
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction, bits);
710
711 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
712 int m = matches(temp, instruction, bits);
713 if (m == 99)
714 m += jmp_match(segment, offset, bits, instruction, temp->code);
715
716 if (m == 100) {
717 /* we've matched an instruction. */
718 int64_t isize;
719 const char *codes = temp->code;
720 int j;
721
722 isize = calcsize(segment, offset, bits, instruction, codes);
723 if (isize < 0)
724 return -1;
725 for (j = 0; j < MAXPREFIX; j++) {
726 switch (instruction->prefixes[j]) {
727 case P_A16:
728 if (bits != 16)
729 isize++;
730 break;
731 case P_A32:
732 if (bits != 32)
733 isize++;
734 break;
735 case P_O16:
736 if (bits != 16)
737 isize++;
738 break;
739 case P_O32:
740 if (bits == 16)
741 isize++;
742 break;
743 case P_A64:
744 case P_O64:
745 case P_none:
746 break;
747 default:
748 isize++;
749 break;
750 }
751 }
752 return isize * instruction->times;
753 }
754 }
755 return -1; /* didn't match any instruction */
756 }
757
758 /* check that opn[op] is a signed byte of size 16 or 32,
759 and return the signed value*/
760 static int is_sbyte(insn * ins, int op, int size)
761 {
762 int32_t v;
763 int ret;
764
765 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
766 optimizing >= 0 &&
767 !(ins->oprs[op].type & STRICT) &&
768 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
769
770 v = ins->oprs[op].offset;
771 if (size == 16)
772 v = (int16_t)v; /* sign extend if 16 bits */
773
774 return ret && v >= -128L && v <= 127L;
775 }
776
777 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
778 insn * ins, const char *codes)
779 {
780 int64_t length = 0;
781 uint8_t c;
782 int rex_mask = ~0;
783 struct operand *opx;
784
785 ins->rex = 0; /* Ensure REX is reset */
786
787 if (ins->prefixes[PPS_OSIZE] == P_O64)
788 ins->rex |= REX_W;
789
790 (void)segment; /* Don't warn that this parameter is unused */
791 (void)offset; /* Don't warn that this parameter is unused */
792
793 while (*codes) {
794 c = *codes++;
795 opx = &ins->oprs[c & 3];
796 switch (c) {
797 case 01:
798 case 02:
799 case 03:
800 codes += c, length += c;
801 break;
802 case 04:
803 case 05:
804 case 06:
805 case 07:
806 length++;
807 break;
808 case 010:
809 case 011:
810 case 012:
811 case 013:
812 ins->rex |=
813 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
814 codes++, length++;
815 break;
816 case 014:
817 case 015:
818 case 016:
819 case 017:
820 length++;
821 break;
822 case 020:
823 case 021:
824 case 022:
825 case 023:
826 length++;
827 break;
828 case 024:
829 case 025:
830 case 026:
831 case 027:
832 length++;
833 break;
834 case 030:
835 case 031:
836 case 032:
837 case 033:
838 length += 2;
839 break;
840 case 034:
841 case 035:
842 case 036:
843 case 037:
844 if (opx->type & (BITS16 | BITS32 | BITS64))
845 length += (opx->type & BITS16) ? 2 : 4;
846 else
847 length += (bits == 16) ? 2 : 4;
848 break;
849 case 040:
850 case 041:
851 case 042:
852 case 043:
853 length += 4;
854 break;
855 case 044:
856 case 045:
857 case 046:
858 case 047:
859 length += ins->addr_size >> 3;
860 break;
861 case 050:
862 case 051:
863 case 052:
864 case 053:
865 length++;
866 break;
867 case 054:
868 case 055:
869 case 056:
870 case 057:
871 length += 8; /* MOV reg64/imm */
872 break;
873 case 060:
874 case 061:
875 case 062:
876 case 063:
877 length += 2;
878 break;
879 case 064:
880 case 065:
881 case 066:
882 case 067:
883 if (opx->type & (BITS16 | BITS32 | BITS64))
884 length += (opx->type & BITS16) ? 2 : 4;
885 else
886 length += (bits == 16) ? 2 : 4;
887 break;
888 case 070:
889 case 071:
890 case 072:
891 case 073:
892 length += 4;
893 break;
894 case 074:
895 case 075:
896 case 076:
897 case 077:
898 length += 2;
899 break;
900 case 0140:
901 case 0141:
902 case 0142:
903 case 0143:
904 length += is_sbyte(ins, c & 3, 16) ? 1 : 2;
905 break;
906 case 0144:
907 case 0145:
908 case 0146:
909 case 0147:
910 codes++;
911 length++;
912 break;
913 case 0150:
914 case 0151:
915 case 0152:
916 case 0153:
917 length += is_sbyte(ins, c & 3, 32) ? 1 : 4;
918 break;
919 case 0154:
920 case 0155:
921 case 0156:
922 case 0157:
923 codes++;
924 length++;
925 break;
926 case 0160:
927 case 0161:
928 case 0162:
929 case 0163:
930 length++;
931 ins->rex |= REX_D;
932 ins->drexdst = regval(&ins->oprs[c & 3]);
933 break;
934 case 0164:
935 case 0165:
936 case 0166:
937 case 0167:
938 length++;
939 ins->rex |= REX_D|REX_OC;
940 ins->drexdst = regval(&ins->oprs[c & 3]);
941 break;
942 case 0170:
943 length++;
944 break;
945 case 0171:
946 break;
947 case 0300:
948 case 0301:
949 case 0302:
950 case 0303:
951 break;
952 case 0310:
953 if (bits == 64)
954 return -1;
955 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
956 break;
957 case 0311:
958 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
959 break;
960 case 0312:
961 break;
962 case 0313:
963 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
964 has_prefix(ins, PPS_ASIZE, P_A32))
965 return -1;
966 break;
967 case 0314:
968 case 0315:
969 case 0316:
970 case 0317:
971 break;
972 case 0320:
973 length += (bits != 16);
974 break;
975 case 0321:
976 length += (bits == 16);
977 break;
978 case 0322:
979 break;
980 case 0323:
981 rex_mask &= ~REX_W;
982 break;
983 case 0324:
984 ins->rex |= REX_W;
985 break;
986 case 0330:
987 codes++, length++;
988 break;
989 case 0331:
990 break;
991 case 0332:
992 case 0333:
993 length++;
994 break;
995 case 0334:
996 ins->rex |= REX_L;
997 break;
998 case 0335:
999 break;
1000 case 0340:
1001 if (ins->oprs[0].segment != NO_SEG)
1002 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1003 " quantity of BSS space");
1004 else
1005 length += ins->oprs[0].offset;
1006 break;
1007 case 0364:
1008 case 0365:
1009 break;
1010 case 0366:
1011 case 0367:
1012 length++;
1013 break;
1014 case 0370:
1015 case 0371:
1016 case 0372:
1017 break;
1018 case 0373:
1019 length++;
1020 break;
1021 default: /* can't do it by 'case' statements */
1022 if (c >= 0100 && c <= 0277) { /* it's an EA */
1023 ea ea_data;
1024 int rfield;
1025 int32_t rflags;
1026 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1027
1028 if (c <= 0177) {
1029 /* pick rfield from operand b */
1030 rflags = regflag(&ins->oprs[c & 7]);
1031 rfield = regvals[ins->oprs[c & 7].basereg];
1032 } else {
1033 rflags = 0;
1034 rfield = c & 7;
1035 }
1036
1037 if (!process_ea
1038 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1039 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1040 errfunc(ERR_NONFATAL, "invalid effective address");
1041 return -1;
1042 } else {
1043 ins->rex |= ea_data.rex;
1044 length += ea_data.size;
1045 }
1046 } else {
1047 errfunc(ERR_PANIC, "internal instruction table corrupt"
1048 ": instruction code 0x%02X given", c);
1049 }
1050 }
1051 }
1052
1053 ins->rex &= rex_mask;
1054
1055 if (ins->rex & REX_D) {
1056 if (ins->rex & REX_H) {
1057 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1058 return -1;
1059 }
1060 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
1061 ins->drexdst > 7)) {
1062 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1063 return -1;
1064 }
1065 length++;
1066 } else if (ins->rex & REX_REAL) {
1067 if (ins->rex & REX_H) {
1068 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1069 return -1;
1070 } else if (bits == 64) {
1071 length++;
1072 } else if ((ins->rex & REX_L) &&
1073 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1074 cpu >= IF_X86_64) {
1075 /* LOCK-as-REX.R */
1076 assert_no_prefix(ins, PPS_LREP);
1077 length++;
1078 } else {
1079 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1080 return -1;
1081 }
1082 }
1083
1084 return length;
1085 }
1086
1087 #define EMIT_REX() \
1088 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1089 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1090 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1091 ins->rex = 0; \
1092 offset += 1; \
1093 }
1094
1095 static void gencode(int32_t segment, int64_t offset, int bits,
1096 insn * ins, const char *codes, int64_t insn_end)
1097 {
1098 static char condval[] = { /* conditional opcodes */
1099 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1100 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1101 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1102 };
1103 uint8_t c;
1104 uint8_t bytes[4];
1105 int64_t size;
1106 int64_t data;
1107 struct operand *opx;
1108
1109 while (*codes) {
1110 c = *codes++;
1111 opx = &ins->oprs[c & 3];
1112 switch (c) {
1113 case 01:
1114 case 02:
1115 case 03:
1116 EMIT_REX();
1117 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1118 codes += c;
1119 offset += c;
1120 break;
1121
1122 case 04:
1123 case 06:
1124 switch (ins->oprs[0].basereg) {
1125 case R_CS:
1126 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1127 break;
1128 case R_DS:
1129 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1130 break;
1131 case R_ES:
1132 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1133 break;
1134 case R_SS:
1135 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1136 break;
1137 default:
1138 errfunc(ERR_PANIC,
1139 "bizarre 8086 segment register received");
1140 }
1141 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1142 offset++;
1143 break;
1144
1145 case 05:
1146 case 07:
1147 switch (ins->oprs[0].basereg) {
1148 case R_FS:
1149 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1150 break;
1151 case R_GS:
1152 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1153 break;
1154 default:
1155 errfunc(ERR_PANIC,
1156 "bizarre 386 segment register received");
1157 }
1158 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1159 offset++;
1160 break;
1161
1162 case 010:
1163 case 011:
1164 case 012:
1165 case 013:
1166 EMIT_REX();
1167 bytes[0] = *codes++ + ((regval(opx)) & 7);
1168 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1169 offset += 1;
1170 break;
1171
1172 case 014:
1173 case 015:
1174 case 016:
1175 case 017:
1176 if (opx->offset < -128 || opx->offset > 127) {
1177 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1178 }
1179
1180 if (opx->segment != NO_SEG) {
1181 data = opx->offset;
1182 out(offset, segment, &data, OUT_ADDRESS, 1,
1183 opx->segment, opx->wrt);
1184 } else {
1185 bytes[0] = opx->offset;
1186 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1187 NO_SEG);
1188 }
1189 offset += 1;
1190 break;
1191
1192 case 020:
1193 case 021:
1194 case 022:
1195 case 023:
1196 if (opx->offset < -256 || opx->offset > 255) {
1197 errfunc(ERR_WARNING, "byte value exceeds bounds");
1198 }
1199 if (opx->segment != NO_SEG) {
1200 data = opx->offset;
1201 out(offset, segment, &data, OUT_ADDRESS, 1,
1202 opx->segment, opx->wrt);
1203 } else {
1204 bytes[0] = opx->offset;
1205 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1206 NO_SEG);
1207 }
1208 offset += 1;
1209 break;
1210
1211 case 024:
1212 case 025:
1213 case 026:
1214 case 027:
1215 if (opx->offset < 0 || opx->offset > 255)
1216 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1217 if (opx->segment != NO_SEG) {
1218 data = opx->offset;
1219 out(offset, segment, &data, OUT_ADDRESS, 1,
1220 opx->segment, opx->wrt);
1221 } else {
1222 bytes[0] = opx->offset;
1223 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1224 NO_SEG);
1225 }
1226 offset += 1;
1227 break;
1228
1229 case 030:
1230 case 031:
1231 case 032:
1232 case 033:
1233 data = opx->offset;
1234 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1235 warn_overflow(2, data);
1236 out(offset, segment, &data, OUT_ADDRESS, 2,
1237 opx->segment, opx->wrt);
1238 offset += 2;
1239 break;
1240
1241 case 034:
1242 case 035:
1243 case 036:
1244 case 037:
1245 if (opx->type & (BITS16 | BITS32))
1246 size = (opx->type & BITS16) ? 2 : 4;
1247 else
1248 size = (bits == 16) ? 2 : 4;
1249 data = opx->offset;
1250 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1251 warn_overflow(size, data);
1252 out(offset, segment, &data, OUT_ADDRESS, size,
1253 opx->segment, opx->wrt);
1254 offset += size;
1255 break;
1256
1257 case 040:
1258 case 041:
1259 case 042:
1260 case 043:
1261 data = opx->offset;
1262 out(offset, segment, &data, OUT_ADDRESS, 4,
1263 opx->segment, opx->wrt);
1264 offset += 4;
1265 break;
1266
1267 case 044:
1268 case 045:
1269 case 046:
1270 case 047:
1271 data = opx->offset;
1272 size = ins->addr_size >> 3;
1273 if (opx->segment == NO_SEG &&
1274 opx->wrt == NO_SEG)
1275 warn_overflow(size, data);
1276 out(offset, segment, &data, OUT_ADDRESS, size,
1277 opx->segment, opx->wrt);
1278 offset += size;
1279 break;
1280
1281 case 050:
1282 case 051:
1283 case 052:
1284 case 053:
1285 if (opx->segment != segment)
1286 errfunc(ERR_NONFATAL,
1287 "short relative jump outside segment");
1288 data = opx->offset - insn_end;
1289 if (data > 127 || data < -128)
1290 errfunc(ERR_NONFATAL, "short jump is out of range");
1291 bytes[0] = data;
1292 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1293 offset += 1;
1294 break;
1295
1296 case 054:
1297 case 055:
1298 case 056:
1299 case 057:
1300 data = (int64_t)opx->offset;
1301 out(offset, segment, &data, OUT_ADDRESS, 8,
1302 opx->segment, opx->wrt);
1303 offset += 8;
1304 break;
1305
1306 case 060:
1307 case 061:
1308 case 062:
1309 case 063:
1310 if (opx->segment != segment) {
1311 data = opx->offset;
1312 out(offset, segment, &data,
1313 OUT_REL2ADR, insn_end - offset,
1314 opx->segment, opx->wrt);
1315 } else {
1316 data = opx->offset - insn_end;
1317 out(offset, segment, &data,
1318 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1319 }
1320 offset += 2;
1321 break;
1322
1323 case 064:
1324 case 065:
1325 case 066:
1326 case 067:
1327 if (opx->type & (BITS16 | BITS32 | BITS64))
1328 size = (opx->type & BITS16) ? 2 : 4;
1329 else
1330 size = (bits == 16) ? 2 : 4;
1331 if (opx->segment != segment) {
1332 data = opx->offset;
1333 out(offset, segment, &data,
1334 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1335 insn_end - offset, opx->segment, opx->wrt);
1336 } else {
1337 data = opx->offset - insn_end;
1338 out(offset, segment, &data,
1339 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1340 }
1341 offset += size;
1342 break;
1343
1344 case 070:
1345 case 071:
1346 case 072:
1347 case 073:
1348 if (opx->segment != segment) {
1349 data = opx->offset;
1350 out(offset, segment, &data,
1351 OUT_REL4ADR, insn_end - offset,
1352 opx->segment, opx->wrt);
1353 } else {
1354 data = opx->offset - insn_end;
1355 out(offset, segment, &data,
1356 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1357 }
1358 offset += 4;
1359 break;
1360
1361 case 074:
1362 case 075:
1363 case 076:
1364 case 077:
1365 if (opx->segment == NO_SEG)
1366 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1367 " relocatable");
1368 data = 0L;
1369 out(offset, segment, &data, OUT_ADDRESS, 2,
1370 outfmt->segbase(1 + opx->segment),
1371 opx->wrt);
1372 offset += 2;
1373 break;
1374
1375 case 0140:
1376 case 0141:
1377 case 0142:
1378 case 0143:
1379 data = opx->offset;
1380 if (is_sbyte(ins, c & 3, 16)) {
1381 bytes[0] = data;
1382 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1383 NO_SEG);
1384 offset++;
1385 } else {
1386 if (opx->segment == NO_SEG &&
1387 opx->wrt == NO_SEG)
1388 warn_overflow(2, data);
1389 out(offset, segment, &data, OUT_ADDRESS, 2,
1390 opx->segment, opx->wrt);
1391 offset += 2;
1392 }
1393 break;
1394
1395 case 0144:
1396 case 0145:
1397 case 0146:
1398 case 0147:
1399 EMIT_REX();
1400 bytes[0] = *codes++;
1401 if (is_sbyte(ins, c & 3, 16))
1402 bytes[0] |= 2; /* s-bit */
1403 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1404 offset++;
1405 break;
1406
1407 case 0150:
1408 case 0151:
1409 case 0152:
1410 case 0153:
1411 data = opx->offset;
1412 if (is_sbyte(ins, c & 3, 32)) {
1413 bytes[0] = data;
1414 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1415 NO_SEG);
1416 offset++;
1417 } else {
1418 out(offset, segment, &data, OUT_ADDRESS, 4,
1419 opx->segment, opx->wrt);
1420 offset += 4;
1421 }
1422 break;
1423
1424 case 0154:
1425 case 0155:
1426 case 0156:
1427 case 0157:
1428 EMIT_REX();
1429 bytes[0] = *codes++;
1430 if (is_sbyte(ins, c & 3, 32))
1431 bytes[0] |= 2; /* s-bit */
1432 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1433 offset++;
1434 break;
1435
1436 case 0160:
1437 case 0161:
1438 case 0162:
1439 case 0163:
1440 case 0164:
1441 case 0165:
1442 case 0166:
1443 case 0167:
1444 break;
1445
1446 case 0170:
1447 EMIT_REX();
1448 bytes[0] = 0;
1449 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1450 offset += 1;
1451 break;
1452
1453 case 0171:
1454 bytes[0] =
1455 (ins->drexdst << 4) |
1456 (ins->rex & REX_OC ? 0x08 : 0) |
1457 (ins->rex & (REX_R|REX_X|REX_B));
1458 ins->rex = 0;
1459 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1460 offset++;
1461 break;
1462
1463 case 0300:
1464 case 0301:
1465 case 0302:
1466 case 0303:
1467 break;
1468
1469 case 0310:
1470 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1471 *bytes = 0x67;
1472 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1473 offset += 1;
1474 } else
1475 offset += 0;
1476 break;
1477
1478 case 0311:
1479 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1480 *bytes = 0x67;
1481 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1482 offset += 1;
1483 } else
1484 offset += 0;
1485 break;
1486
1487 case 0312:
1488 break;
1489
1490 case 0313:
1491 ins->rex = 0;
1492 break;
1493
1494 case 0314:
1495 case 0315:
1496 case 0316:
1497 case 0317:
1498 break;
1499
1500 case 0320:
1501 if (bits != 16) {
1502 *bytes = 0x66;
1503 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1504 offset += 1;
1505 } else
1506 offset += 0;
1507 break;
1508
1509 case 0321:
1510 if (bits == 16) {
1511 *bytes = 0x66;
1512 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1513 offset += 1;
1514 } else
1515 offset += 0;
1516 break;
1517
1518 case 0322:
1519 case 0323:
1520 break;
1521
1522 case 0324:
1523 ins->rex |= REX_W;
1524 break;
1525
1526 case 0330:
1527 *bytes = *codes++ ^ condval[ins->condition];
1528 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1529 offset += 1;
1530 break;
1531
1532 case 0331:
1533 break;
1534
1535 case 0332:
1536 case 0333:
1537 *bytes = c - 0332 + 0xF2;
1538 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1539 offset += 1;
1540 break;
1541
1542 case 0334:
1543 if (ins->rex & REX_R) {
1544 *bytes = 0xF0;
1545 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1546 offset += 1;
1547 }
1548 ins->rex &= ~(REX_L|REX_R);
1549 break;
1550
1551 case 0335:
1552 break;
1553
1554 case 0340:
1555 if (ins->oprs[0].segment != NO_SEG)
1556 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1557 else {
1558 int64_t size = ins->oprs[0].offset;
1559 if (size > 0)
1560 out(offset, segment, NULL,
1561 OUT_RESERVE, size, NO_SEG, NO_SEG);
1562 offset += size;
1563 }
1564 break;
1565
1566 case 0364:
1567 case 0365:
1568 break;
1569
1570 case 0366:
1571 case 0367:
1572 *bytes = c - 0366 + 0x66;
1573 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1574 offset += 1;
1575 break;
1576
1577 case 0370:
1578 case 0371:
1579 case 0372:
1580 break;
1581
1582 case 0373:
1583 *bytes = bits == 16 ? 3 : 5;
1584 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1585 offset += 1;
1586 break;
1587
1588 default: /* can't do it by 'case' statements */
1589 if (c >= 0100 && c <= 0277) { /* it's an EA */
1590 ea ea_data;
1591 int rfield;
1592 int32_t rflags;
1593 uint8_t *p;
1594 int32_t s;
1595
1596 if (c <= 0177) {
1597 /* pick rfield from operand b */
1598 rflags = regflag(&ins->oprs[c & 7]);
1599 rfield = regvals[ins->oprs[c & 7].basereg];
1600 } else {
1601 /* rfield is constant */
1602 rflags = 0;
1603 rfield = c & 7;
1604 }
1605
1606 if (!process_ea
1607 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1608 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1609 errfunc(ERR_NONFATAL, "invalid effective address");
1610 }
1611
1612
1613 p = bytes;
1614 *p++ = ea_data.modrm;
1615 if (ea_data.sib_present)
1616 *p++ = ea_data.sib;
1617
1618 /* DREX suffixes come between the SIB and the displacement */
1619 if (ins->rex & REX_D) {
1620 *p++ =
1621 (ins->drexdst << 4) |
1622 (ins->rex & REX_OC ? 0x08 : 0) |
1623 (ins->rex & (REX_R|REX_X|REX_B));
1624 ins->rex = 0;
1625 }
1626
1627 s = p - bytes;
1628 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1629
1630 switch (ea_data.bytes) {
1631 case 0:
1632 break;
1633 case 1:
1634 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1635 data = ins->oprs[(c >> 3) & 7].offset;
1636 out(offset, segment, &data, OUT_ADDRESS, 1,
1637 ins->oprs[(c >> 3) & 7].segment,
1638 ins->oprs[(c >> 3) & 7].wrt);
1639 } else {
1640 *bytes = ins->oprs[(c >> 3) & 7].offset;
1641 out(offset, segment, bytes, OUT_RAWDATA, 1,
1642 NO_SEG, NO_SEG);
1643 }
1644 s++;
1645 break;
1646 case 8:
1647 case 2:
1648 case 4:
1649 data = ins->oprs[(c >> 3) & 7].offset;
1650 warn_overflow(ea_data.bytes, data);
1651 out(offset, segment, &data,
1652 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1653 ea_data.bytes,
1654 ins->oprs[(c >> 3) & 7].segment,
1655 ins->oprs[(c >> 3) & 7].wrt);
1656 s += ea_data.bytes;
1657 break;
1658 }
1659 offset += s;
1660 } else {
1661 errfunc(ERR_PANIC, "internal instruction table corrupt"
1662 ": instruction code 0x%02X given", c);
1663 }
1664 }
1665 }
1666 }
1667
1668 static int32_t regflag(const operand * o)
1669 {
1670 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1671 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1672 }
1673 return reg_flags[o->basereg];
1674 }
1675
1676 static int32_t regval(const operand * o)
1677 {
1678 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1679 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1680 }
1681 return regvals[o->basereg];
1682 }
1683
1684 static int op_rexflags(const operand * o, int mask)
1685 {
1686 int32_t flags;
1687 int val;
1688
1689 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1690 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1691 }
1692
1693 flags = reg_flags[o->basereg];
1694 val = regvals[o->basereg];
1695
1696 return rexflags(val, flags, mask);
1697 }
1698
1699 static int rexflags(int val, int32_t flags, int mask)
1700 {
1701 int rex = 0;
1702
1703 if (val >= 8)
1704 rex |= REX_B|REX_X|REX_R;
1705 if (flags & BITS64)
1706 rex |= REX_W;
1707 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1708 rex |= REX_H;
1709 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1710 rex |= REX_P;
1711
1712 return rex & mask;
1713 }
1714
1715 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1716 {
1717 int i, size[MAX_OPERANDS], asize, oprs, ret;
1718
1719 ret = 100;
1720
1721 /*
1722 * Check the opcode
1723 */
1724 if (itemp->opcode != instruction->opcode)
1725 return 0;
1726
1727 /*
1728 * Count the operands
1729 */
1730 if (itemp->operands != instruction->operands)
1731 return 0;
1732
1733 /*
1734 * Check that no spurious colons or TOs are present
1735 */
1736 for (i = 0; i < itemp->operands; i++)
1737 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1738 return 0;
1739
1740 /*
1741 * Check that the operand flags all match up
1742 */
1743 for (i = 0; i < itemp->operands; i++) {
1744 if (itemp->opd[i] & SAME_AS) {
1745 int j = itemp->opd[i] & ~SAME_AS;
1746 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1747 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1748 return 0;
1749 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1750 ((itemp->opd[i] & SIZE_MASK) &&
1751 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1752 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1753 (instruction->oprs[i].type & SIZE_MASK))
1754 return 0;
1755 else
1756 return 1;
1757 }
1758 }
1759
1760 /*
1761 * Check operand sizes
1762 */
1763 if (itemp->flags & IF_ARMASK) {
1764 memset(size, 0, sizeof size);
1765
1766 switch (itemp->flags & IF_ARMASK) {
1767 case IF_AR0:
1768 i = 0;
1769 break;
1770 case IF_AR1:
1771 i = 1;
1772 break;
1773 case IF_AR2:
1774 i = 2;
1775 break;
1776 case IF_AR3:
1777 i = 3;
1778 break;
1779 default:
1780 break; /* Shouldn't happen */
1781 }
1782 switch (itemp->flags & IF_SMASK) {
1783 case IF_SB:
1784 size[i] = BITS8;
1785 break;
1786 case IF_SW:
1787 size[i] = BITS16;
1788 break;
1789 case IF_SD:
1790 size[i] = BITS32;
1791 break;
1792 case IF_SQ:
1793 size[i] = BITS64;
1794 break;
1795 case IF_SO:
1796 size[i] = BITS128;
1797 break;
1798 default:
1799 break;
1800 }
1801 } else {
1802 asize = 0;
1803 switch (itemp->flags & IF_SMASK) {
1804 case IF_SB:
1805 asize = BITS8;
1806 oprs = itemp->operands;
1807 break;
1808 case IF_SW:
1809 asize = BITS16;
1810 oprs = itemp->operands;
1811 break;
1812 case IF_SD:
1813 asize = BITS32;
1814 oprs = itemp->operands;
1815 break;
1816 case IF_SQ:
1817 asize = BITS64;
1818 oprs = itemp->operands;
1819 break;
1820 case IF_SO:
1821 asize = BITS128;
1822 oprs = itemp->operands;
1823 break;
1824 default:
1825 break;
1826 }
1827 for (i = 0; i < MAX_OPERANDS; i++)
1828 size[i] = asize;
1829 }
1830
1831 if (itemp->flags & (IF_SM | IF_SM2)) {
1832 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1833 asize = 0;
1834 for (i = 0; i < oprs; i++) {
1835 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1836 int j;
1837 for (j = 0; j < oprs; j++)
1838 size[j] = asize;
1839 break;
1840 }
1841 }
1842 } else {
1843 oprs = itemp->operands;
1844 }
1845
1846 for (i = 0; i < itemp->operands; i++) {
1847 if (!(itemp->opd[i] & SIZE_MASK) &&
1848 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1849 return 2;
1850 }
1851
1852 /*
1853 * Check template is okay at the set cpu level
1854 */
1855 if (((itemp->flags & IF_PLEVEL) > cpu))
1856 return 3;
1857
1858 /*
1859 * Check if instruction is available in long mode
1860 */
1861 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1862 return 4;
1863
1864 /*
1865 * Check if special handling needed for Jumps
1866 */
1867 if ((uint8_t)(itemp->code[0]) >= 0370)
1868 return 99;
1869
1870 return ret;
1871 }
1872
1873 static ea *process_ea(operand * input, ea * output, int bits,
1874 int addrbits, int rfield, int32_t rflags, int forw_ref)
1875 {
1876 output->rip = false;
1877
1878 /* REX flags for the rfield operand */
1879 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1880
1881 if (!(REGISTER & ~input->type)) { /* register direct */
1882 int i;
1883 int32_t f;
1884
1885 if (input->basereg < EXPR_REG_START /* Verify as Register */
1886 || input->basereg >= REG_ENUM_LIMIT)
1887 return NULL;
1888 f = regflag(input);
1889 i = regvals[input->basereg];
1890
1891 if (REG_EA & ~f)
1892 return NULL; /* Invalid EA register */
1893
1894 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1895
1896 output->sib_present = false; /* no SIB necessary */
1897 output->bytes = 0; /* no offset necessary either */
1898 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1899 } else { /* it's a memory reference */
1900 if (input->basereg == -1
1901 && (input->indexreg == -1 || input->scale == 0)) {
1902 /* it's a pure offset */
1903 if (bits == 64 && (~input->type & IP_REL)) {
1904 int scale, index, base;
1905 output->sib_present = true;
1906 scale = 0;
1907 index = 4;
1908 base = 5;
1909 output->sib = (scale << 6) | (index << 3) | base;
1910 output->bytes = 4;
1911 output->modrm = 4 | ((rfield & 7) << 3);
1912 output->rip = false;
1913 } else {
1914 output->sib_present = false;
1915 output->bytes = (addrbits != 16 ? 4 : 2);
1916 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1917 output->rip = bits == 64;
1918 }
1919 } else { /* it's an indirection */
1920 int i = input->indexreg, b = input->basereg, s = input->scale;
1921 int32_t o = input->offset, seg = input->segment;
1922 int hb = input->hintbase, ht = input->hinttype;
1923 int t;
1924 int it, bt;
1925 int32_t ix, bx; /* register flags */
1926
1927 if (s == 0)
1928 i = -1; /* make this easy, at least */
1929
1930 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1931 it = regvals[i];
1932 ix = reg_flags[i];
1933 } else {
1934 it = -1;
1935 ix = 0;
1936 }
1937
1938 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1939 bt = regvals[b];
1940 bx = reg_flags[b];
1941 } else {
1942 bt = -1;
1943 bx = 0;
1944 }
1945
1946 /* check for a 32/64-bit memory reference... */
1947 if ((ix|bx) & (BITS32|BITS64)) {
1948 /* it must be a 32/64-bit memory reference. Firstly we have
1949 * to check that all registers involved are type E/Rxx. */
1950 int32_t sok = BITS32|BITS64;
1951
1952 if (it != -1) {
1953 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1954 sok &= ix;
1955 else
1956 return NULL;
1957 }
1958
1959 if (bt != -1) {
1960 if (REG_GPR & ~bx)
1961 return NULL; /* Invalid register */
1962 if (~sok & bx & SIZE_MASK)
1963 return NULL; /* Invalid size */
1964 sok &= bx;
1965 }
1966
1967 /* While we're here, ensure the user didn't specify
1968 WORD or QWORD. */
1969 if (input->disp_size == 16 || input->disp_size == 64)
1970 return NULL;
1971
1972 if (addrbits == 16 ||
1973 (addrbits == 32 && !(sok & BITS32)) ||
1974 (addrbits == 64 && !(sok & BITS64)))
1975 return NULL;
1976
1977 /* now reorganize base/index */
1978 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1979 ((hb == b && ht == EAH_NOTBASE)
1980 || (hb == i && ht == EAH_MAKEBASE))) {
1981 /* swap if hints say so */
1982 t = bt, bt = it, it = t;
1983 t = bx, bx = ix, ix = t;
1984 }
1985 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1986 bt = -1, bx = 0, s++;
1987 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1988 /* make single reg base, unless hint */
1989 bt = it, bx = ix, it = -1, ix = 0;
1990 }
1991 if (((s == 2 && it != REG_NUM_ESP
1992 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
1993 || s == 5 || s == 9) && bt == -1)
1994 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
1995 if (it == -1 && (bt & 7) != REG_NUM_ESP
1996 && (input->eaflags & EAF_TIMESTWO))
1997 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
1998 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
1999 if (s == 1 && it == REG_NUM_ESP) {
2000 /* swap ESP into base if scale is 1 */
2001 t = it, it = bt, bt = t;
2002 t = ix, ix = bx, bx = t;
2003 }
2004 if (it == REG_NUM_ESP
2005 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2006 return NULL; /* wrong, for various reasons */
2007
2008 output->rex |= rexflags(it, ix, REX_X);
2009 output->rex |= rexflags(bt, bx, REX_B);
2010
2011 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2012 /* no SIB needed */
2013 int mod, rm;
2014
2015 if (bt == -1) {
2016 rm = 5;
2017 mod = 0;
2018 } else {
2019 rm = (bt & 7);
2020 if (rm != REG_NUM_EBP && o == 0 &&
2021 seg == NO_SEG && !forw_ref &&
2022 !(input->eaflags &
2023 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2024 mod = 0;
2025 else if (input->eaflags & EAF_BYTEOFFS ||
2026 (o >= -128 && o <= 127 && seg == NO_SEG
2027 && !forw_ref
2028 && !(input->eaflags & EAF_WORDOFFS)))
2029 mod = 1;
2030 else
2031 mod = 2;
2032 }
2033
2034 output->sib_present = false;
2035 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2036 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2037 } else {
2038 /* we need a SIB */
2039 int mod, scale, index, base;
2040
2041 if (it == -1)
2042 index = 4, s = 1;
2043 else
2044 index = (it & 7);
2045
2046 switch (s) {
2047 case 1:
2048 scale = 0;
2049 break;
2050 case 2:
2051 scale = 1;
2052 break;
2053 case 4:
2054 scale = 2;
2055 break;
2056 case 8:
2057 scale = 3;
2058 break;
2059 default: /* then what the smeg is it? */
2060 return NULL; /* panic */
2061 }
2062
2063 if (bt == -1) {
2064 base = 5;
2065 mod = 0;
2066 } else {
2067 base = (bt & 7);
2068 if (base != REG_NUM_EBP && o == 0 &&
2069 seg == NO_SEG && !forw_ref &&
2070 !(input->eaflags &
2071 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2072 mod = 0;
2073 else if (input->eaflags & EAF_BYTEOFFS ||
2074 (o >= -128 && o <= 127 && seg == NO_SEG
2075 && !forw_ref
2076 && !(input->eaflags & EAF_WORDOFFS)))
2077 mod = 1;
2078 else
2079 mod = 2;
2080 }
2081
2082 output->sib_present = true;
2083 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2084 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2085 output->sib = (scale << 6) | (index << 3) | base;
2086 }
2087 } else { /* it's 16-bit */
2088 int mod, rm;
2089
2090 /* check for 64-bit long mode */
2091 if (addrbits == 64)
2092 return NULL;
2093
2094 /* check all registers are BX, BP, SI or DI */
2095 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2096 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2097 && i != R_SI && i != R_DI))
2098 return NULL;
2099
2100 /* ensure the user didn't specify DWORD/QWORD */
2101 if (input->disp_size == 32 || input->disp_size == 64)
2102 return NULL;
2103
2104 if (s != 1 && i != -1)
2105 return NULL; /* no can do, in 16-bit EA */
2106 if (b == -1 && i != -1) {
2107 int tmp = b;
2108 b = i;
2109 i = tmp;
2110 } /* swap */
2111 if ((b == R_SI || b == R_DI) && i != -1) {
2112 int tmp = b;
2113 b = i;
2114 i = tmp;
2115 }
2116 /* have BX/BP as base, SI/DI index */
2117 if (b == i)
2118 return NULL; /* shouldn't ever happen, in theory */
2119 if (i != -1 && b != -1 &&
2120 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2121 return NULL; /* invalid combinations */
2122 if (b == -1) /* pure offset: handled above */
2123 return NULL; /* so if it gets to here, panic! */
2124
2125 rm = -1;
2126 if (i != -1)
2127 switch (i * 256 + b) {
2128 case R_SI * 256 + R_BX:
2129 rm = 0;
2130 break;
2131 case R_DI * 256 + R_BX:
2132 rm = 1;
2133 break;
2134 case R_SI * 256 + R_BP:
2135 rm = 2;
2136 break;
2137 case R_DI * 256 + R_BP:
2138 rm = 3;
2139 break;
2140 } else
2141 switch (b) {
2142 case R_SI:
2143 rm = 4;
2144 break;
2145 case R_DI:
2146 rm = 5;
2147 break;
2148 case R_BP:
2149 rm = 6;
2150 break;
2151 case R_BX:
2152 rm = 7;
2153 break;
2154 }
2155 if (rm == -1) /* can't happen, in theory */
2156 return NULL; /* so panic if it does */
2157
2158 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2159 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2160 mod = 0;
2161 else if (input->eaflags & EAF_BYTEOFFS ||
2162 (o >= -128 && o <= 127 && seg == NO_SEG
2163 && !forw_ref
2164 && !(input->eaflags & EAF_WORDOFFS)))
2165 mod = 1;
2166 else
2167 mod = 2;
2168
2169 output->sib_present = false; /* no SIB - it's 16-bit */
2170 output->bytes = mod; /* bytes of offset needed */
2171 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2172 }
2173 }
2174 }
2175
2176 output->size = 1 + output->sib_present + output->bytes;
2177 return output;
2178 }
2179
2180 static void add_asp(insn *ins, int addrbits)
2181 {
2182 int j, valid;
2183 int defdisp;
2184
2185 valid = (addrbits == 64) ? 64|32 : 32|16;
2186
2187 switch (ins->prefixes[PPS_ASIZE]) {
2188 case P_A16:
2189 valid &= 16;
2190 break;
2191 case P_A32:
2192 valid &= 32;
2193 break;
2194 case P_A64:
2195 valid &= 64;
2196 break;
2197 case P_ASP:
2198 valid &= (addrbits == 32) ? 16 : 32;
2199 break;
2200 default:
2201 break;
2202 }
2203
2204 for (j = 0; j < ins->operands; j++) {
2205 if (!(MEMORY & ~ins->oprs[j].type)) {
2206 int32_t i, b;
2207
2208 /* Verify as Register */
2209 if (ins->oprs[j].indexreg < EXPR_REG_START
2210 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2211 i = 0;
2212 else
2213 i = reg_flags[ins->oprs[j].indexreg];
2214
2215 /* Verify as Register */
2216 if (ins->oprs[j].basereg < EXPR_REG_START
2217 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2218 b = 0;
2219 else
2220 b = reg_flags[ins->oprs[j].basereg];
2221
2222 if (ins->oprs[j].scale == 0)
2223 i = 0;
2224
2225 if (!i && !b) {
2226 int ds = ins->oprs[j].disp_size;
2227 if ((addrbits != 64 && ds > 8) ||
2228 (addrbits == 64 && ds == 16))
2229 valid &= ds;
2230 } else {
2231 if (!(REG16 & ~b))
2232 valid &= 16;
2233 if (!(REG32 & ~b))
2234 valid &= 32;
2235 if (!(REG64 & ~b))
2236 valid &= 64;
2237
2238 if (!(REG16 & ~i))
2239 valid &= 16;
2240 if (!(REG32 & ~i))
2241 valid &= 32;
2242 if (!(REG64 & ~i))
2243 valid &= 64;
2244 }
2245 }
2246 }
2247
2248 if (valid & addrbits) {
2249 ins->addr_size = addrbits;
2250 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2251 /* Add an address size prefix */
2252 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2253 ins->prefixes[PPS_ASIZE] = pref;
2254 ins->addr_size = (addrbits == 32) ? 16 : 32;
2255 } else {
2256 /* Impossible... */
2257 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2258 ins->addr_size = addrbits; /* Error recovery */
2259 }
2260
2261 defdisp = ins->addr_size == 16 ? 16 : 32;
2262
2263 for (j = 0; j < ins->operands; j++) {
2264 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2265 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2266 != ins->addr_size) {
2267 /* mem_offs sizes must match the address size; if not,
2268 strip the MEM_OFFS bit and match only EA instructions */
2269 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2270 }
2271 }
2272 }
Adding AVX-512 features