?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
NASM 2.03rc7
[nasm/avx512.git] / assemble.c
blob442ed2a4c7021aeb18b3a67b6f276b07693081f5
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \171 - placement of DREX suffix in the absence of an EA
48 * \172\ab - the register number from operand a in bits 7..4, with
49 * the 4-bit immediate from operand b in bits 3..0.
50 * \173\xab - the register number from operand a in bits 7..4, with
51 * the value b in bits 3..0.
52 * \174\a - the register number from operand a in bits 7..4, and
53 * an arbitrary value in bits 3..0 (assembled as zero.)
54 * \2ab - a ModRM, calculated on EA in operand a, with the spare
55 * field equal to digit b.
56 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
57 * is not equal to the truncated and sign-extended 32-bit
58 * operand; used for 32-bit immediates in 64-bit mode.
59 * \260..\263 - this instruction uses VEX rather than REX, with the
60 * V field taken from operand 0..3.
61 * \270 - this instruction uses VEX rather than REX, with the
62 * V field set to 1111b.
63 *
64 * VEX prefixes are followed by the sequence:
65 * \mm\wlp where mm is the M field; and wlp is:
66 * 00 0ww lpp
67 * [w0] ww = 0 for W = 0
68 * [w1] ww = 1 for W = 1
69 * [wx] ww = 2 for W don't care (always assembled as 0)
70 * [ww] ww = 3 for W used as REX.W
71 *
72 *
73 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
74 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
75 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
76 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
77 * \314 - (disassembler only) invalid with REX.B
78 * \315 - (disassembler only) invalid with REX.X
79 * \316 - (disassembler only) invalid with REX.R
80 * \317 - (disassembler only) invalid with REX.W
81 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
82 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
83 * \322 - indicates that this instruction is only valid when the
84 * operand size is the default (instruction to disassembler,
85 * generates no code in the assembler)
86 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
87 * \324 - indicates 64-bit operand size requiring REX prefix.
88 * \330 - a literal byte follows in the code stream, to be added
89 * to the condition code value of the instruction.
90 * \331 - instruction not valid with REP prefix. Hint for
91 * disassembler only; for SSE instructions.
92 * \332 - REP prefix (0xF2 byte) used as opcode extension.
93 * \333 - REP prefix (0xF3 byte) used as opcode extension.
94 * \334 - LOCK prefix used instead of REX.R
95 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
96 * \340 - reserve <operand 0> bytes of uninitialized storage.
97 * Operand 0 had better be a segmentless constant.
98 * \360 - no SSE prefix (== \364\331)
99 * \361 - 66 SSE prefix (== \366\331)
100 * \362 - F2 SSE prefix (== \364\332)
101 * \363 - F3 SSE prefix (== \364\333)
102 * \364 - operand-size prefix (0x66) not permitted
103 * \365 - address-size prefix (0x67) not permitted
104 * \366 - operand-size prefix (0x66) used as opcode extension
105 * \367 - address-size prefix (0x67) used as opcode extension
106 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
107 * 370 is used for Jcc, 371 is used for JMP.
108 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
109 * used for conditional jump over longer jump
110 */
111
112 #include "compiler.h"
113
114 #include <stdio.h>
115 #include <string.h>
116 #include <inttypes.h>
117
118 #include "nasm.h"
119 #include "nasmlib.h"
120 #include "assemble.h"
121 #include "insns.h"
122 #include "tables.h"
123
124 /* Initialized to zero by the C standard */
125 static const uint8_t const_zero_buf[256];
126
127 typedef struct {
128 int sib_present; /* is a SIB byte necessary? */
129 int bytes; /* # of bytes of offset needed */
130 int size; /* lazy - this is sib+bytes+1 */
131 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
132 } ea;
133
134 static uint32_t cpu; /* cpu level received from nasm.c */
135 static efunc errfunc;
136 static struct ofmt *outfmt;
137 static ListGen *list;
138
139 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
140 static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t);
141 static int matches(const struct itemplate *, insn *, int bits);
142 static int32_t regflag(const operand *);
143 static int32_t regval(const operand *);
144 static int rexflags(int, int32_t, int);
145 static int op_rexflags(const operand *, int);
146 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
147 static void add_asp(insn *, int);
148
149 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
150 {
151 return ins->prefixes[pos] == prefix;
152 }
153
154 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
155 {
156 if (ins->prefixes[pos])
157 errfunc(ERR_NONFATAL, "invalid %s prefix",
158 prefix_name(ins->prefixes[pos]));
159 }
160
161 static const char *size_name(int size)
162 {
163 switch (size) {
164 case 1:
165 return "byte";
166 case 2:
167 return "word";
168 case 4:
169 return "dword";
170 case 8:
171 return "qword";
172 case 10:
173 return "tword";
174 case 16:
175 return "oword";
176 case 32:
177 return "yword";
178 default:
179 return "???";
180 }
181 }
182
183 static void warn_overflow(int size, int64_t data)
184 {
185 if (size < 8) {
186 int64_t lim = ((int64_t)1 << (size*8))-1;
187
188 if (data < ~lim || data > lim)
189 errfunc(ERR_WARNING | ERR_WARN_NOV,
190 "%s data exceeds bounds", size_name(size));
191 }
192 }
193 /*
194 * This routine wrappers the real output format's output routine,
195 * in order to pass a copy of the data off to the listing file
196 * generator at the same time.
197 */
198 static void out(int64_t offset, int32_t segto, const void *data,
199 enum out_type type, uint64_t size,
200 int32_t segment, int32_t wrt)
201 {
202 static int32_t lineno = 0; /* static!!! */
203 static char *lnfname = NULL;
204 uint8_t p[8];
205
206 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
207 /*
208 * This is a non-relocated address, and we're going to
209 * convert it into RAWDATA format.
210 */
211 uint8_t *q = p;
212
213 if (size > 8) {
214 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
215 return;
216 }
217
218 WRITEADDR(q, *(int64_t *)data, size);
219 data = p;
220 type = OUT_RAWDATA;
221 }
222
223 list->output(offset, data, type, size);
224
225 /*
226 * this call to src_get determines when we call the
227 * debug-format-specific "linenum" function
228 * it updates lineno and lnfname to the current values
229 * returning 0 if "same as last time", -2 if lnfname
230 * changed, and the amount by which lineno changed,
231 * if it did. thus, these variables must be static
232 */
233
234 if (src_get(&lineno, &lnfname)) {
235 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
236 }
237
238 outfmt->output(segto, data, type, size, segment, wrt);
239 }
240
241 static int jmp_match(int32_t segment, int64_t offset, int bits,
242 insn * ins, const uint8_t *code)
243 {
244 int64_t isize;
245 uint8_t c = code[0];
246
247 if (c != 0370 && c != 0371)
248 return 0;
249 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
250 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
251 && c == 0370)
252 return 1;
253 else
254 return (pass0 == 0); /* match a forward reference */
255 }
256 isize = calcsize(segment, offset, bits, ins, code);
257 if (ins->oprs[0].segment != segment)
258 return 0;
259 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
260 if (isize >= -128L && isize <= 127L)
261 return 1; /* it is byte size */
262
263 return 0;
264 }
265
266 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
267 insn * instruction, struct ofmt *output, efunc error,
268 ListGen * listgen)
269 {
270 const struct itemplate *temp;
271 int j;
272 int size_prob;
273 int64_t insn_end;
274 int32_t itimes;
275 int64_t start = offset;
276 int64_t wsize = 0; /* size for DB etc. */
277
278 errfunc = error; /* to pass to other functions */
279 cpu = cp;
280 outfmt = output; /* likewise */
281 list = listgen; /* and again */
282
283 switch (instruction->opcode) {
284 case -1:
285 return 0;
286 case I_DB:
287 wsize = 1;
288 break;
289 case I_DW:
290 wsize = 2;
291 break;
292 case I_DD:
293 wsize = 4;
294 break;
295 case I_DQ:
296 wsize = 8;
297 break;
298 case I_DT:
299 wsize = 10;
300 break;
301 case I_DO:
302 wsize = 16;
303 break;
304 case I_DY:
305 wsize = 32;
306 break;
307 default:
308 break;
309 }
310
311 if (wsize) {
312 extop *e;
313 int32_t t = instruction->times;
314 if (t < 0)
315 errfunc(ERR_PANIC,
316 "instruction->times < 0 (%ld) in assemble()", t);
317
318 while (t--) { /* repeat TIMES times */
319 for (e = instruction->eops; e; e = e->next) {
320 if (e->type == EOT_DB_NUMBER) {
321 if (wsize == 1) {
322 if (e->segment != NO_SEG)
323 errfunc(ERR_NONFATAL,
324 "one-byte relocation attempted");
325 else {
326 uint8_t out_byte = e->offset;
327 out(offset, segment, &out_byte,
328 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
329 }
330 } else if (wsize > 8) {
331 errfunc(ERR_NONFATAL,
332 "integer supplied to a DT, DO or DY"
333 " instruction");
334 } else
335 out(offset, segment, &e->offset,
336 OUT_ADDRESS, wsize, e->segment, e->wrt);
337 offset += wsize;
338 } else if (e->type == EOT_DB_STRING) {
339 int align;
340
341 out(offset, segment, e->stringval,
342 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
343 align = e->stringlen % wsize;
344
345 if (align) {
346 align = wsize - align;
347 out(offset, segment, const_zero_buf,
348 OUT_RAWDATA, align, NO_SEG, NO_SEG);
349 }
350 offset += e->stringlen + align;
351 }
352 }
353 if (t > 0 && t == instruction->times - 1) {
354 /*
355 * Dummy call to list->output to give the offset to the
356 * listing module.
357 */
358 list->output(offset, NULL, OUT_RAWDATA, 0);
359 list->uplevel(LIST_TIMES);
360 }
361 }
362 if (instruction->times > 1)
363 list->downlevel(LIST_TIMES);
364 return offset - start;
365 }
366
367 if (instruction->opcode == I_INCBIN) {
368 static char fname[FILENAME_MAX];
369 FILE *fp;
370 int32_t len;
371
372 len = FILENAME_MAX - 1;
373 if (len > instruction->eops->stringlen)
374 len = instruction->eops->stringlen;
375 strncpy(fname, instruction->eops->stringval, len);
376 fname[len] = '\0';
377
378 fp = fopen(fname, "rb");
379 if (!fp) {
380 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
381 fname);
382 } else if (fseek(fp, 0L, SEEK_END) < 0) {
383 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
384 fname);
385 } else {
386 static char buf[2048];
387 int32_t t = instruction->times;
388 int32_t base = 0;
389
390 len = ftell(fp);
391 if (instruction->eops->next) {
392 base = instruction->eops->next->offset;
393 len -= base;
394 if (instruction->eops->next->next &&
395 len > instruction->eops->next->next->offset)
396 len = instruction->eops->next->next->offset;
397 }
398 /*
399 * Dummy call to list->output to give the offset to the
400 * listing module.
401 */
402 list->output(offset, NULL, OUT_RAWDATA, 0);
403 list->uplevel(LIST_INCBIN);
404 while (t--) {
405 int32_t l;
406
407 fseek(fp, base, SEEK_SET);
408 l = len;
409 while (l > 0) {
410 int32_t m =
411 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
412 fp);
413 if (!m) {
414 /*
415 * This shouldn't happen unless the file
416 * actually changes while we are reading
417 * it.
418 */
419 error(ERR_NONFATAL,
420 "`incbin': unexpected EOF while"
421 " reading file `%s'", fname);
422 t = 0; /* Try to exit cleanly */
423 break;
424 }
425 out(offset, segment, buf, OUT_RAWDATA, m,
426 NO_SEG, NO_SEG);
427 l -= m;
428 }
429 }
430 list->downlevel(LIST_INCBIN);
431 if (instruction->times > 1) {
432 /*
433 * Dummy call to list->output to give the offset to the
434 * listing module.
435 */
436 list->output(offset, NULL, OUT_RAWDATA, 0);
437 list->uplevel(LIST_TIMES);
438 list->downlevel(LIST_TIMES);
439 }
440 fclose(fp);
441 return instruction->times * len;
442 }
443 return 0; /* if we're here, there's an error */
444 }
445
446 /* Check to see if we need an address-size prefix */
447 add_asp(instruction, bits);
448
449 size_prob = false;
450
451 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
452 int m = matches(temp, instruction, bits);
453
454 if (m == 99)
455 m += jmp_match(segment, offset, bits, instruction, temp->code);
456
457 if (m == 100) { /* matches! */
458 const uint8_t *codes = temp->code;
459 int64_t insn_size = calcsize(segment, offset, bits,
460 instruction, codes);
461 itimes = instruction->times;
462 if (insn_size < 0) /* shouldn't be, on pass two */
463 error(ERR_PANIC, "errors made it through from pass one");
464 else
465 while (itimes--) {
466 for (j = 0; j < MAXPREFIX; j++) {
467 uint8_t c = 0;
468 switch (instruction->prefixes[j]) {
469 case P_LOCK:
470 c = 0xF0;
471 break;
472 case P_REPNE:
473 case P_REPNZ:
474 c = 0xF2;
475 break;
476 case P_REPE:
477 case P_REPZ:
478 case P_REP:
479 c = 0xF3;
480 break;
481 case R_CS:
482 if (bits == 64) {
483 error(ERR_WARNING,
484 "cs segment base generated, but will be ignored in 64-bit mode");
485 }
486 c = 0x2E;
487 break;
488 case R_DS:
489 if (bits == 64) {
490 error(ERR_WARNING,
491 "ds segment base generated, but will be ignored in 64-bit mode");
492 }
493 c = 0x3E;
494 break;
495 case R_ES:
496 if (bits == 64) {
497 error(ERR_WARNING,
498 "es segment base generated, but will be ignored in 64-bit mode");
499 }
500 c = 0x26;
501 break;
502 case R_FS:
503 c = 0x64;
504 break;
505 case R_GS:
506 c = 0x65;
507 break;
508 case R_SS:
509 if (bits == 64) {
510 error(ERR_WARNING,
511 "ss segment base generated, but will be ignored in 64-bit mode");
512 }
513 c = 0x36;
514 break;
515 case R_SEGR6:
516 case R_SEGR7:
517 error(ERR_NONFATAL,
518 "segr6 and segr7 cannot be used as prefixes");
519 break;
520 case P_A16:
521 if (bits == 64) {
522 error(ERR_NONFATAL,
523 "16-bit addressing is not supported "
524 "in 64-bit mode");
525 } else if (bits != 16)
526 c = 0x67;
527 break;
528 case P_A32:
529 if (bits != 32)
530 c = 0x67;
531 break;
532 case P_A64:
533 if (bits != 64) {
534 error(ERR_NONFATAL,
535 "64-bit addressing is only supported "
536 "in 64-bit mode");
537 }
538 break;
539 case P_ASP:
540 c = 0x67;
541 break;
542 case P_O16:
543 if (bits != 16)
544 c = 0x66;
545 break;
546 case P_O32:
547 if (bits == 16)
548 c = 0x66;
549 break;
550 case P_O64:
551 /* REX.W */
552 break;
553 case P_OSP:
554 c = 0x66;
555 break;
556 case P_none:
557 break;
558 default:
559 error(ERR_PANIC, "invalid instruction prefix");
560 }
561 if (c != 0) {
562 out(offset, segment, &c, OUT_RAWDATA, 1,
563 NO_SEG, NO_SEG);
564 offset++;
565 }
566 }
567 insn_end = offset + insn_size;
568 gencode(segment, offset, bits, instruction, codes,
569 insn_end);
570 offset += insn_size;
571 if (itimes > 0 && itimes == instruction->times - 1) {
572 /*
573 * Dummy call to list->output to give the offset to the
574 * listing module.
575 */
576 list->output(offset, NULL, OUT_RAWDATA, 0);
577 list->uplevel(LIST_TIMES);
578 }
579 }
580 if (instruction->times > 1)
581 list->downlevel(LIST_TIMES);
582 return offset - start;
583 } else if (m > 0 && m > size_prob) {
584 size_prob = m;
585 }
586 // temp++;
587 }
588
589 if (temp->opcode == -1) { /* didn't match any instruction */
590 switch (size_prob) {
591 case 1:
592 error(ERR_NONFATAL, "operation size not specified");
593 break;
594 case 2:
595 error(ERR_NONFATAL, "mismatch in operand sizes");
596 break;
597 case 3:
598 error(ERR_NONFATAL, "no instruction for this cpu level");
599 break;
600 case 4:
601 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
602 break;
603 default:
604 error(ERR_NONFATAL,
605 "invalid combination of opcode and operands");
606 break;
607 }
608 }
609 return 0;
610 }
611
612 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
613 insn * instruction, efunc error)
614 {
615 const struct itemplate *temp;
616
617 errfunc = error; /* to pass to other functions */
618 cpu = cp;
619
620 if (instruction->opcode == -1)
621 return 0;
622
623 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
624 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
625 instruction->opcode == I_DT || instruction->opcode == I_DO ||
626 instruction->opcode == I_DY) {
627 extop *e;
628 int32_t isize, osize, wsize = 0; /* placate gcc */
629
630 isize = 0;
631 switch (instruction->opcode) {
632 case I_DB:
633 wsize = 1;
634 break;
635 case I_DW:
636 wsize = 2;
637 break;
638 case I_DD:
639 wsize = 4;
640 break;
641 case I_DQ:
642 wsize = 8;
643 break;
644 case I_DT:
645 wsize = 10;
646 break;
647 case I_DO:
648 wsize = 16;
649 break;
650 case I_DY:
651 wsize = 32;
652 break;
653 default:
654 break;
655 }
656
657 for (e = instruction->eops; e; e = e->next) {
658 int32_t align;
659
660 osize = 0;
661 if (e->type == EOT_DB_NUMBER)
662 osize = 1;
663 else if (e->type == EOT_DB_STRING)
664 osize = e->stringlen;
665
666 align = (-osize) % wsize;
667 if (align < 0)
668 align += wsize;
669 isize += osize + align;
670 }
671 return isize * instruction->times;
672 }
673
674 if (instruction->opcode == I_INCBIN) {
675 char fname[FILENAME_MAX];
676 FILE *fp;
677 int32_t len;
678
679 len = FILENAME_MAX - 1;
680 if (len > instruction->eops->stringlen)
681 len = instruction->eops->stringlen;
682 strncpy(fname, instruction->eops->stringval, len);
683 fname[len] = '\0';
684
685 fp = fopen(fname, "rb");
686 if (!fp)
687 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
688 fname);
689 else if (fseek(fp, 0L, SEEK_END) < 0)
690 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
691 fname);
692 else {
693 len = ftell(fp);
694 fclose(fp);
695 if (instruction->eops->next) {
696 len -= instruction->eops->next->offset;
697 if (instruction->eops->next->next &&
698 len > instruction->eops->next->next->offset) {
699 len = instruction->eops->next->next->offset;
700 }
701 }
702 return instruction->times * len;
703 }
704 return 0; /* if we're here, there's an error */
705 }
706
707 /* Check to see if we need an address-size prefix */
708 add_asp(instruction, bits);
709
710 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
711 int m = matches(temp, instruction, bits);
712 if (m == 99)
713 m += jmp_match(segment, offset, bits, instruction, temp->code);
714
715 if (m == 100) {
716 /* we've matched an instruction. */
717 int64_t isize;
718 const uint8_t *codes = temp->code;
719 int j;
720
721 isize = calcsize(segment, offset, bits, instruction, codes);
722 if (isize < 0)
723 return -1;
724 for (j = 0; j < MAXPREFIX; j++) {
725 switch (instruction->prefixes[j]) {
726 case P_A16:
727 if (bits != 16)
728 isize++;
729 break;
730 case P_A32:
731 if (bits != 32)
732 isize++;
733 break;
734 case P_O16:
735 if (bits != 16)
736 isize++;
737 break;
738 case P_O32:
739 if (bits == 16)
740 isize++;
741 break;
742 case P_A64:
743 case P_O64:
744 case P_none:
745 break;
746 default:
747 isize++;
748 break;
749 }
750 }
751 return isize * instruction->times;
752 }
753 }
754 return -1; /* didn't match any instruction */
755 }
756
757 static bool possible_sbyte(insn * ins, int op)
758 {
759 return !(ins->forw_ref && ins->oprs[op].opflags) &&
760 optimizing >= 0 &&
761 !(ins->oprs[op].type & STRICT) &&
762 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
763 }
764
765 /* check that opn[op] is a signed byte of size 16 or 32 */
766 static bool is_sbyte16(insn * ins, int op)
767 {
768 int16_t v;
769
770 if (!possible_sbyte(ins, op))
771 return false;
772
773 v = ins->oprs[op].offset;
774 return v >= -128 && v <= 127;
775 }
776
777 static bool is_sbyte32(insn * ins, int op)
778 {
779 int32_t v;
780
781 if (!possible_sbyte(ins, op))
782 return false;
783
784 v = ins->oprs[op].offset;
785 return v >= -128 && v <= 127;
786 }
787
788 /* check that opn[op] is a signed byte of size 32; warn if this is not
789 the original value when extended to 64 bits */
790 static bool is_sbyte64(insn * ins, int op)
791 {
792 int64_t v64;
793 int32_t v32;
794
795 /* dead in the water on forward reference or External */
796 if (!possible_sbyte(ins, op))
797 return false;
798
799 v64 = ins->oprs[op].offset;
800 v32 = (int32_t)v64;
801
802 warn_overflow(32, v64);
803
804 return v32 >= -128 && v32 <= 127;
805 }
806 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
807 insn * ins, const uint8_t *codes)
808 {
809 int64_t length = 0;
810 uint8_t c;
811 int rex_mask = ~0;
812 struct operand *opx;
813
814 ins->rex = 0; /* Ensure REX is reset */
815
816 if (ins->prefixes[PPS_OSIZE] == P_O64)
817 ins->rex |= REX_W;
818
819 (void)segment; /* Don't warn that this parameter is unused */
820 (void)offset; /* Don't warn that this parameter is unused */
821
822 while (*codes) {
823 c = *codes++;
824 opx = &ins->oprs[c & 3];
825 switch (c) {
826 case 01:
827 case 02:
828 case 03:
829 codes += c, length += c;
830 break;
831 case 04:
832 case 05:
833 case 06:
834 case 07:
835 length++;
836 break;
837 case 010:
838 case 011:
839 case 012:
840 case 013:
841 ins->rex |=
842 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
843 codes++, length++;
844 break;
845 case 014:
846 case 015:
847 case 016:
848 case 017:
849 length++;
850 break;
851 case 020:
852 case 021:
853 case 022:
854 case 023:
855 length++;
856 break;
857 case 024:
858 case 025:
859 case 026:
860 case 027:
861 length++;
862 break;
863 case 030:
864 case 031:
865 case 032:
866 case 033:
867 length += 2;
868 break;
869 case 034:
870 case 035:
871 case 036:
872 case 037:
873 if (opx->type & (BITS16 | BITS32 | BITS64))
874 length += (opx->type & BITS16) ? 2 : 4;
875 else
876 length += (bits == 16) ? 2 : 4;
877 break;
878 case 040:
879 case 041:
880 case 042:
881 case 043:
882 length += 4;
883 break;
884 case 044:
885 case 045:
886 case 046:
887 case 047:
888 length += ins->addr_size >> 3;
889 break;
890 case 050:
891 case 051:
892 case 052:
893 case 053:
894 length++;
895 break;
896 case 054:
897 case 055:
898 case 056:
899 case 057:
900 length += 8; /* MOV reg64/imm */
901 break;
902 case 060:
903 case 061:
904 case 062:
905 case 063:
906 length += 2;
907 break;
908 case 064:
909 case 065:
910 case 066:
911 case 067:
912 if (opx->type & (BITS16 | BITS32 | BITS64))
913 length += (opx->type & BITS16) ? 2 : 4;
914 else
915 length += (bits == 16) ? 2 : 4;
916 break;
917 case 070:
918 case 071:
919 case 072:
920 case 073:
921 length += 4;
922 break;
923 case 074:
924 case 075:
925 case 076:
926 case 077:
927 length += 2;
928 break;
929 case 0140:
930 case 0141:
931 case 0142:
932 case 0143:
933 length += is_sbyte16(ins, c & 3) ? 1 : 2;
934 break;
935 case 0144:
936 case 0145:
937 case 0146:
938 case 0147:
939 codes++;
940 length++;
941 break;
942 case 0150:
943 case 0151:
944 case 0152:
945 case 0153:
946 length += is_sbyte32(ins, c & 3) ? 1 : 4;
947 break;
948 case 0154:
949 case 0155:
950 case 0156:
951 case 0157:
952 codes++;
953 length++;
954 break;
955 case 0160:
956 case 0161:
957 case 0162:
958 case 0163:
959 length++;
960 ins->rex |= REX_D;
961 ins->drexdst = regval(opx);
962 break;
963 case 0164:
964 case 0165:
965 case 0166:
966 case 0167:
967 length++;
968 ins->rex |= REX_D|REX_OC;
969 ins->drexdst = regval(opx);
970 break;
971 case 0171:
972 break;
973 case 0172:
974 case 0173:
975 case 0174:
976 codes++;
977 length++;
978 break;
979 case 0250:
980 case 0251:
981 case 0252:
982 case 0253:
983 length += is_sbyte64(ins, c & 3) ? 1 : 4;
984 break;
985 case 0260:
986 case 0261:
987 case 0262:
988 case 0263:
989 length += 2;
990 ins->rex |= REX_V;
991 ins->drexdst = regval(opx);
992 ins->vex_m = *codes++;
993 ins->vex_wlp = *codes++;
994 break;
995 case 0270:
996 length += 2;
997 ins->rex |= REX_V;
998 ins->drexdst = 0;
999 ins->vex_m = *codes++;
1000 ins->vex_wlp = *codes++;
1001 break;
1002 case 0300:
1003 case 0301:
1004 case 0302:
1005 case 0303:
1006 break;
1007 case 0310:
1008 if (bits == 64)
1009 return -1;
1010 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1011 break;
1012 case 0311:
1013 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1014 break;
1015 case 0312:
1016 break;
1017 case 0313:
1018 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1019 has_prefix(ins, PPS_ASIZE, P_A32))
1020 return -1;
1021 break;
1022 case 0314:
1023 case 0315:
1024 case 0316:
1025 case 0317:
1026 break;
1027 case 0320:
1028 length += (bits != 16);
1029 break;
1030 case 0321:
1031 length += (bits == 16);
1032 break;
1033 case 0322:
1034 break;
1035 case 0323:
1036 rex_mask &= ~REX_W;
1037 break;
1038 case 0324:
1039 ins->rex |= REX_W;
1040 break;
1041 case 0330:
1042 codes++, length++;
1043 break;
1044 case 0331:
1045 break;
1046 case 0332:
1047 case 0333:
1048 length++;
1049 break;
1050 case 0334:
1051 ins->rex |= REX_L;
1052 break;
1053 case 0335:
1054 break;
1055 case 0340:
1056 if (ins->oprs[0].segment != NO_SEG)
1057 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1058 " quantity of BSS space");
1059 else
1060 length += ins->oprs[0].offset;
1061 break;
1062 case 0360:
1063 break;
1064 case 0361:
1065 case 0362:
1066 case 0363:
1067 length++;
1068 break;
1069 case 0364:
1070 case 0365:
1071 break;
1072 case 0366:
1073 case 0367:
1074 length++;
1075 break;
1076 case 0370:
1077 case 0371:
1078 case 0372:
1079 break;
1080 case 0373:
1081 length++;
1082 break;
1083 default: /* can't do it by 'case' statements */
1084 if (c >= 0100 && c <= 0277) { /* it's an EA */
1085 ea ea_data;
1086 int rfield;
1087 int32_t rflags;
1088 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1089
1090 if (c <= 0177) {
1091 /* pick rfield from operand b */
1092 rflags = regflag(&ins->oprs[c & 7]);
1093 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1094 } else {
1095 rflags = 0;
1096 rfield = c & 7;
1097 }
1098
1099 if (!process_ea
1100 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1101 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1102 errfunc(ERR_NONFATAL, "invalid effective address");
1103 return -1;
1104 } else {
1105 ins->rex |= ea_data.rex;
1106 length += ea_data.size;
1107 }
1108 } else {
1109 errfunc(ERR_PANIC, "internal instruction table corrupt"
1110 ": instruction code 0x%02X given", c);
1111 }
1112 }
1113 }
1114
1115 ins->rex &= rex_mask;
1116
1117 if (ins->rex & REX_V) {
1118 int bad32 = REX_R|REX_W|REX_X|REX_B;
1119
1120 if (ins->rex & REX_H) {
1121 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1122 return -1;
1123 }
1124 switch (ins->vex_wlp & 030) {
1125 case 000:
1126 case 020:
1127 ins->rex &= ~REX_W;
1128 break;
1129 case 010:
1130 ins->rex |= REX_W;
1131 bad32 &= ~REX_W;
1132 break;
1133 case 030:
1134 /* Follow REX_W */
1135 break;
1136 }
1137
1138 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1139 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1140 return -1;
1141 }
1142 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1143 length += 3;
1144 else
1145 length += 2;
1146 } else if (ins->rex & REX_D) {
1147 if (ins->rex & REX_H) {
1148 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1149 return -1;
1150 }
1151 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1152 ins->drexdst > 7)) {
1153 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1154 return -1;
1155 }
1156 length++;
1157 } else if (ins->rex & REX_REAL) {
1158 if (ins->rex & REX_H) {
1159 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1160 return -1;
1161 } else if (bits == 64) {
1162 length++;
1163 } else if ((ins->rex & REX_L) &&
1164 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1165 cpu >= IF_X86_64) {
1166 /* LOCK-as-REX.R */
1167 assert_no_prefix(ins, PPS_LREP);
1168 length++;
1169 } else {
1170 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1171 return -1;
1172 }
1173 }
1174
1175 return length;
1176 }
1177
1178 #define EMIT_REX() \
1179 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1180 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1181 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1182 ins->rex = 0; \
1183 offset += 1; \
1184 }
1185
1186 static void gencode(int32_t segment, int64_t offset, int bits,
1187 insn * ins, const uint8_t *codes, int64_t insn_end)
1188 {
1189 static char condval[] = { /* conditional opcodes */
1190 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1191 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1192 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1193 };
1194 uint8_t c;
1195 uint8_t bytes[4];
1196 int64_t size;
1197 int64_t data;
1198 struct operand *opx;
1199
1200 while (*codes) {
1201 c = *codes++;
1202 opx = &ins->oprs[c & 3];
1203 switch (c) {
1204 case 01:
1205 case 02:
1206 case 03:
1207 EMIT_REX();
1208 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1209 codes += c;
1210 offset += c;
1211 break;
1212
1213 case 04:
1214 case 06:
1215 switch (ins->oprs[0].basereg) {
1216 case R_CS:
1217 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1218 break;
1219 case R_DS:
1220 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1221 break;
1222 case R_ES:
1223 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1224 break;
1225 case R_SS:
1226 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1227 break;
1228 default:
1229 errfunc(ERR_PANIC,
1230 "bizarre 8086 segment register received");
1231 }
1232 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1233 offset++;
1234 break;
1235
1236 case 05:
1237 case 07:
1238 switch (ins->oprs[0].basereg) {
1239 case R_FS:
1240 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1241 break;
1242 case R_GS:
1243 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1244 break;
1245 default:
1246 errfunc(ERR_PANIC,
1247 "bizarre 386 segment register received");
1248 }
1249 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1250 offset++;
1251 break;
1252
1253 case 010:
1254 case 011:
1255 case 012:
1256 case 013:
1257 EMIT_REX();
1258 bytes[0] = *codes++ + ((regval(opx)) & 7);
1259 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1260 offset += 1;
1261 break;
1262
1263 case 014:
1264 case 015:
1265 case 016:
1266 case 017:
1267 /* XXX: warns for legitimate optimizer actions */
1268 if (opx->offset < -128 || opx->offset > 127) {
1269 errfunc(ERR_WARNING | ERR_WARN_NOV,
1270 "signed byte value exceeds bounds");
1271 }
1272
1273 if (opx->segment != NO_SEG) {
1274 data = opx->offset;
1275 out(offset, segment, &data, OUT_ADDRESS, 1,
1276 opx->segment, opx->wrt);
1277 } else {
1278 bytes[0] = opx->offset;
1279 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1280 NO_SEG);
1281 }
1282 offset += 1;
1283 break;
1284
1285 case 020:
1286 case 021:
1287 case 022:
1288 case 023:
1289 if (opx->offset < -256 || opx->offset > 255) {
1290 errfunc(ERR_WARNING | ERR_WARN_NOV,
1291 "byte value exceeds bounds");
1292 }
1293 if (opx->segment != NO_SEG) {
1294 data = opx->offset;
1295 out(offset, segment, &data, OUT_ADDRESS, 1,
1296 opx->segment, opx->wrt);
1297 } else {
1298 bytes[0] = opx->offset;
1299 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1300 NO_SEG);
1301 }
1302 offset += 1;
1303 break;
1304
1305 case 024:
1306 case 025:
1307 case 026:
1308 case 027:
1309 if (opx->offset < 0 || opx->offset > 255)
1310 errfunc(ERR_WARNING | ERR_WARN_NOV,
1311 "unsigned byte value exceeds bounds");
1312 if (opx->segment != NO_SEG) {
1313 data = opx->offset;
1314 out(offset, segment, &data, OUT_ADDRESS, 1,
1315 opx->segment, opx->wrt);
1316 } else {
1317 bytes[0] = opx->offset;
1318 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1319 NO_SEG);
1320 }
1321 offset += 1;
1322 break;
1323
1324 case 030:
1325 case 031:
1326 case 032:
1327 case 033:
1328 data = opx->offset;
1329 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1330 warn_overflow(2, data);
1331 out(offset, segment, &data, OUT_ADDRESS, 2,
1332 opx->segment, opx->wrt);
1333 offset += 2;
1334 break;
1335
1336 case 034:
1337 case 035:
1338 case 036:
1339 case 037:
1340 if (opx->type & (BITS16 | BITS32))
1341 size = (opx->type & BITS16) ? 2 : 4;
1342 else
1343 size = (bits == 16) ? 2 : 4;
1344 data = opx->offset;
1345 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1346 warn_overflow(size, data);
1347 out(offset, segment, &data, OUT_ADDRESS, size,
1348 opx->segment, opx->wrt);
1349 offset += size;
1350 break;
1351
1352 case 040:
1353 case 041:
1354 case 042:
1355 case 043:
1356 data = opx->offset;
1357 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1358 warn_overflow(4, data);
1359 out(offset, segment, &data, OUT_ADDRESS, 4,
1360 opx->segment, opx->wrt);
1361 offset += 4;
1362 break;
1363
1364 case 044:
1365 case 045:
1366 case 046:
1367 case 047:
1368 data = opx->offset;
1369 size = ins->addr_size >> 3;
1370 if (opx->segment == NO_SEG &&
1371 opx->wrt == NO_SEG)
1372 warn_overflow(size, data);
1373 out(offset, segment, &data, OUT_ADDRESS, size,
1374 opx->segment, opx->wrt);
1375 offset += size;
1376 break;
1377
1378 case 050:
1379 case 051:
1380 case 052:
1381 case 053:
1382 if (opx->segment != segment)
1383 errfunc(ERR_NONFATAL,
1384 "short relative jump outside segment");
1385 data = opx->offset - insn_end;
1386 if (data > 127 || data < -128)
1387 errfunc(ERR_NONFATAL, "short jump is out of range");
1388 bytes[0] = data;
1389 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1390 offset += 1;
1391 break;
1392
1393 case 054:
1394 case 055:
1395 case 056:
1396 case 057:
1397 data = (int64_t)opx->offset;
1398 out(offset, segment, &data, OUT_ADDRESS, 8,
1399 opx->segment, opx->wrt);
1400 offset += 8;
1401 break;
1402
1403 case 060:
1404 case 061:
1405 case 062:
1406 case 063:
1407 if (opx->segment != segment) {
1408 data = opx->offset;
1409 out(offset, segment, &data,
1410 OUT_REL2ADR, insn_end - offset,
1411 opx->segment, opx->wrt);
1412 } else {
1413 data = opx->offset - insn_end;
1414 out(offset, segment, &data,
1415 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1416 }
1417 offset += 2;
1418 break;
1419
1420 case 064:
1421 case 065:
1422 case 066:
1423 case 067:
1424 if (opx->type & (BITS16 | BITS32 | BITS64))
1425 size = (opx->type & BITS16) ? 2 : 4;
1426 else
1427 size = (bits == 16) ? 2 : 4;
1428 if (opx->segment != segment) {
1429 data = opx->offset;
1430 out(offset, segment, &data,
1431 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1432 insn_end - offset, opx->segment, opx->wrt);
1433 } else {
1434 data = opx->offset - insn_end;
1435 out(offset, segment, &data,
1436 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1437 }
1438 offset += size;
1439 break;
1440
1441 case 070:
1442 case 071:
1443 case 072:
1444 case 073:
1445 if (opx->segment != segment) {
1446 data = opx->offset;
1447 out(offset, segment, &data,
1448 OUT_REL4ADR, insn_end - offset,
1449 opx->segment, opx->wrt);
1450 } else {
1451 data = opx->offset - insn_end;
1452 out(offset, segment, &data,
1453 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1454 }
1455 offset += 4;
1456 break;
1457
1458 case 074:
1459 case 075:
1460 case 076:
1461 case 077:
1462 if (opx->segment == NO_SEG)
1463 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1464 " relocatable");
1465 data = 0;
1466 out(offset, segment, &data, OUT_ADDRESS, 2,
1467 outfmt->segbase(1 + opx->segment),
1468 opx->wrt);
1469 offset += 2;
1470 break;
1471
1472 case 0140:
1473 case 0141:
1474 case 0142:
1475 case 0143:
1476 data = opx->offset;
1477 if (is_sbyte16(ins, c & 3)) {
1478 bytes[0] = data;
1479 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1480 NO_SEG);
1481 offset++;
1482 } else {
1483 if (opx->segment == NO_SEG &&
1484 opx->wrt == NO_SEG)
1485 warn_overflow(2, data);
1486 out(offset, segment, &data, OUT_ADDRESS, 2,
1487 opx->segment, opx->wrt);
1488 offset += 2;
1489 }
1490 break;
1491
1492 case 0144:
1493 case 0145:
1494 case 0146:
1495 case 0147:
1496 EMIT_REX();
1497 bytes[0] = *codes++;
1498 if (is_sbyte16(ins, c & 3))
1499 bytes[0] |= 2; /* s-bit */
1500 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1501 offset++;
1502 break;
1503
1504 case 0150:
1505 case 0151:
1506 case 0152:
1507 case 0153:
1508 data = opx->offset;
1509 if (is_sbyte32(ins, c & 3)) {
1510 bytes[0] = data;
1511 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1512 NO_SEG);
1513 offset++;
1514 } else {
1515 out(offset, segment, &data, OUT_ADDRESS, 4,
1516 opx->segment, opx->wrt);
1517 offset += 4;
1518 }
1519 break;
1520
1521 case 0154:
1522 case 0155:
1523 case 0156:
1524 case 0157:
1525 EMIT_REX();
1526 bytes[0] = *codes++;
1527 if (is_sbyte32(ins, c & 3))
1528 bytes[0] |= 2; /* s-bit */
1529 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1530 offset++;
1531 break;
1532
1533 case 0160:
1534 case 0161:
1535 case 0162:
1536 case 0163:
1537 case 0164:
1538 case 0165:
1539 case 0166:
1540 case 0167:
1541 break;
1542
1543 case 0171:
1544 bytes[0] =
1545 (ins->drexdst << 4) |
1546 (ins->rex & REX_OC ? 0x08 : 0) |
1547 (ins->rex & (REX_R|REX_X|REX_B));
1548 ins->rex = 0;
1549 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1550 offset++;
1551 break;
1552
1553 case 0172:
1554 c = *codes++;
1555 opx = &ins->oprs[c >> 3];
1556 bytes[0] = nasm_regvals[opx->basereg] << 4;
1557 opx = &ins->oprs[c & 7];
1558 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1559 errfunc(ERR_NONFATAL,
1560 "non-absolute expression not permitted as argument %d",
1561 c & 7);
1562 } else {
1563 if (opx->offset & ~15) {
1564 errfunc(ERR_WARNING | ERR_WARN_NOV,
1565 "four-bit argument exceeds bounds");
1566 }
1567 bytes[0] |= opx->offset & 15;
1568 }
1569 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1570 offset++;
1571 break;
1572
1573 case 0173:
1574 c = *codes++;
1575 opx = &ins->oprs[c >> 4];
1576 bytes[0] = nasm_regvals[opx->basereg] << 4;
1577 bytes[0] |= c & 15;
1578 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1579 offset++;
1580 break;
1581
1582 case 0174:
1583 c = *codes++;
1584 opx = &ins->oprs[c];
1585 bytes[0] = nasm_regvals[opx->basereg] << 4;
1586 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1587 offset++;
1588 break;
1589
1590 case 0250:
1591 case 0251:
1592 case 0252:
1593 case 0253:
1594 data = opx->offset;
1595 /* is_sbyte32() is right here, we have already warned */
1596 if (is_sbyte32(ins, c & 3)) {
1597 bytes[0] = data;
1598 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1599 NO_SEG);
1600 offset++;
1601 } else {
1602 out(offset, segment, &data, OUT_ADDRESS, 4,
1603 opx->segment, opx->wrt);
1604 offset += 4;
1605 }
1606 break;
1607
1608 case 0260:
1609 case 0261:
1610 case 0262:
1611 case 0263:
1612 case 0270:
1613 codes += 2;
1614 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1615 bytes[0] = 0xc4;
1616 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1617 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1618 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1619 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1620 offset += 3;
1621 } else {
1622 bytes[0] = 0xc5;
1623 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1624 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1625 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1626 offset += 2;
1627 }
1628 break;
1629
1630 case 0300:
1631 case 0301:
1632 case 0302:
1633 case 0303:
1634 break;
1635
1636 case 0310:
1637 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1638 *bytes = 0x67;
1639 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1640 offset += 1;
1641 } else
1642 offset += 0;
1643 break;
1644
1645 case 0311:
1646 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1647 *bytes = 0x67;
1648 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1649 offset += 1;
1650 } else
1651 offset += 0;
1652 break;
1653
1654 case 0312:
1655 break;
1656
1657 case 0313:
1658 ins->rex = 0;
1659 break;
1660
1661 case 0314:
1662 case 0315:
1663 case 0316:
1664 case 0317:
1665 break;
1666
1667 case 0320:
1668 if (bits != 16) {
1669 *bytes = 0x66;
1670 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1671 offset += 1;
1672 } else
1673 offset += 0;
1674 break;
1675
1676 case 0321:
1677 if (bits == 16) {
1678 *bytes = 0x66;
1679 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1680 offset += 1;
1681 } else
1682 offset += 0;
1683 break;
1684
1685 case 0322:
1686 case 0323:
1687 break;
1688
1689 case 0324:
1690 ins->rex |= REX_W;
1691 break;
1692
1693 case 0330:
1694 *bytes = *codes++ ^ condval[ins->condition];
1695 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1696 offset += 1;
1697 break;
1698
1699 case 0331:
1700 break;
1701
1702 case 0332:
1703 case 0333:
1704 *bytes = c - 0332 + 0xF2;
1705 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1706 offset += 1;
1707 break;
1708
1709 case 0334:
1710 if (ins->rex & REX_R) {
1711 *bytes = 0xF0;
1712 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1713 offset += 1;
1714 }
1715 ins->rex &= ~(REX_L|REX_R);
1716 break;
1717
1718 case 0335:
1719 break;
1720
1721 case 0340:
1722 if (ins->oprs[0].segment != NO_SEG)
1723 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1724 else {
1725 int64_t size = ins->oprs[0].offset;
1726 if (size > 0)
1727 out(offset, segment, NULL,
1728 OUT_RESERVE, size, NO_SEG, NO_SEG);
1729 offset += size;
1730 }
1731 break;
1732
1733 case 0360:
1734 break;
1735
1736 case 0361:
1737 bytes[0] = 0x66;
1738 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1739 offset += 1;
1740 break;
1741
1742 case 0362:
1743 case 0363:
1744 bytes[0] = c - 0362 + 0xf2;
1745 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1746 offset += 1;
1747 break;
1748
1749 case 0364:
1750 case 0365:
1751 break;
1752
1753 case 0366:
1754 case 0367:
1755 *bytes = c - 0366 + 0x66;
1756 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1757 offset += 1;
1758 break;
1759
1760 case 0370:
1761 case 0371:
1762 case 0372:
1763 break;
1764
1765 case 0373:
1766 *bytes = bits == 16 ? 3 : 5;
1767 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1768 offset += 1;
1769 break;
1770
1771 default: /* can't do it by 'case' statements */
1772 if (c >= 0100 && c <= 0277) { /* it's an EA */
1773 ea ea_data;
1774 int rfield;
1775 int32_t rflags;
1776 uint8_t *p;
1777 int32_t s;
1778
1779 if (c <= 0177) {
1780 /* pick rfield from operand b */
1781 rflags = regflag(&ins->oprs[c & 7]);
1782 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1783 } else {
1784 /* rfield is constant */
1785 rflags = 0;
1786 rfield = c & 7;
1787 }
1788
1789 if (!process_ea
1790 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1791 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1792 errfunc(ERR_NONFATAL, "invalid effective address");
1793 }
1794
1795
1796 p = bytes;
1797 *p++ = ea_data.modrm;
1798 if (ea_data.sib_present)
1799 *p++ = ea_data.sib;
1800
1801 /* DREX suffixes come between the SIB and the displacement */
1802 if (ins->rex & REX_D) {
1803 *p++ =
1804 (ins->drexdst << 4) |
1805 (ins->rex & REX_OC ? 0x08 : 0) |
1806 (ins->rex & (REX_R|REX_X|REX_B));
1807 ins->rex = 0;
1808 }
1809
1810 s = p - bytes;
1811 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1812
1813 switch (ea_data.bytes) {
1814 case 0:
1815 break;
1816 case 1:
1817 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1818 data = ins->oprs[(c >> 3) & 7].offset;
1819 out(offset, segment, &data, OUT_ADDRESS, 1,
1820 ins->oprs[(c >> 3) & 7].segment,
1821 ins->oprs[(c >> 3) & 7].wrt);
1822 } else {
1823 *bytes = ins->oprs[(c >> 3) & 7].offset;
1824 out(offset, segment, bytes, OUT_RAWDATA, 1,
1825 NO_SEG, NO_SEG);
1826 }
1827 s++;
1828 break;
1829 case 8:
1830 case 2:
1831 case 4:
1832 data = ins->oprs[(c >> 3) & 7].offset;
1833 warn_overflow(ea_data.bytes, data);
1834 out(offset, segment, &data,
1835 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1836 ea_data.bytes,
1837 ins->oprs[(c >> 3) & 7].segment,
1838 ins->oprs[(c >> 3) & 7].wrt);
1839 s += ea_data.bytes;
1840 break;
1841 }
1842 offset += s;
1843 } else {
1844 errfunc(ERR_PANIC, "internal instruction table corrupt"
1845 ": instruction code 0x%02X given", c);
1846 }
1847 }
1848 }
1849 }
1850
1851 static int32_t regflag(const operand * o)
1852 {
1853 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1854 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1855 }
1856 return nasm_reg_flags[o->basereg];
1857 }
1858
1859 static int32_t regval(const operand * o)
1860 {
1861 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1862 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1863 }
1864 return nasm_regvals[o->basereg];
1865 }
1866
1867 static int op_rexflags(const operand * o, int mask)
1868 {
1869 int32_t flags;
1870 int val;
1871
1872 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1873 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1874 }
1875
1876 flags = nasm_reg_flags[o->basereg];
1877 val = nasm_regvals[o->basereg];
1878
1879 return rexflags(val, flags, mask);
1880 }
1881
1882 static int rexflags(int val, int32_t flags, int mask)
1883 {
1884 int rex = 0;
1885
1886 if (val >= 8)
1887 rex |= REX_B|REX_X|REX_R;
1888 if (flags & BITS64)
1889 rex |= REX_W;
1890 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1891 rex |= REX_H;
1892 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1893 rex |= REX_P;
1894
1895 return rex & mask;
1896 }
1897
1898 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1899 {
1900 int i, size[MAX_OPERANDS], asize, oprs, ret;
1901
1902 ret = 100;
1903
1904 /*
1905 * Check the opcode
1906 */
1907 if (itemp->opcode != instruction->opcode)
1908 return 0;
1909
1910 /*
1911 * Count the operands
1912 */
1913 if (itemp->operands != instruction->operands)
1914 return 0;
1915
1916 /*
1917 * Check that no spurious colons or TOs are present
1918 */
1919 for (i = 0; i < itemp->operands; i++)
1920 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1921 return 0;
1922
1923 /*
1924 * Process size flags
1925 */
1926 if (itemp->flags & IF_ARMASK) {
1927 memset(size, 0, sizeof size);
1928
1929 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1930
1931 switch (itemp->flags & IF_SMASK) {
1932 case IF_SB:
1933 size[i] = BITS8;
1934 break;
1935 case IF_SW:
1936 size[i] = BITS16;
1937 break;
1938 case IF_SD:
1939 size[i] = BITS32;
1940 break;
1941 case IF_SQ:
1942 size[i] = BITS64;
1943 break;
1944 case IF_SO:
1945 size[i] = BITS128;
1946 break;
1947 case IF_SY:
1948 size[i] = BITS256;
1949 break;
1950 case IF_SZ:
1951 switch (bits) {
1952 case 16:
1953 size[i] = BITS16;
1954 break;
1955 case 32:
1956 size[i] = BITS32;
1957 break;
1958 case 64:
1959 size[i] = BITS64;
1960 break;
1961 }
1962 break;
1963 default:
1964 break;
1965 }
1966 } else {
1967 asize = 0;
1968 switch (itemp->flags & IF_SMASK) {
1969 case IF_SB:
1970 asize = BITS8;
1971 break;
1972 case IF_SW:
1973 asize = BITS16;
1974 break;
1975 case IF_SD:
1976 asize = BITS32;
1977 break;
1978 case IF_SQ:
1979 asize = BITS64;
1980 break;
1981 case IF_SO:
1982 asize = BITS128;
1983 break;
1984 case IF_SY:
1985 asize = BITS256;
1986 break;
1987 case IF_SZ:
1988 switch (bits) {
1989 case 16:
1990 asize = BITS16;
1991 break;
1992 case 32:
1993 asize = BITS32;
1994 break;
1995 case 64:
1996 asize = BITS64;
1997 break;
1998 }
1999 break;
2000 default:
2001 break;
2002 }
2003 for (i = 0; i < MAX_OPERANDS; i++)
2004 size[i] = asize;
2005 }
2006
2007 /*
2008 * Check that the operand flags all match up
2009 */
2010 for (i = 0; i < itemp->operands; i++) {
2011 int32_t type = instruction->oprs[i].type;
2012 if (!(type & SIZE_MASK))
2013 type |= size[i];
2014
2015 if (itemp->opd[i] & SAME_AS) {
2016 int j = itemp->opd[i] & ~SAME_AS;
2017 if (type != instruction->oprs[j].type ||
2018 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2019 return 0;
2020 } else if (itemp->opd[i] & ~type ||
2021 ((itemp->opd[i] & SIZE_MASK) &&
2022 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2023 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2024 (type & SIZE_MASK))
2025 return 0;
2026 else
2027 return 1;
2028 }
2029 }
2030
2031 /*
2032 * Check operand sizes
2033 */
2034 if (itemp->flags & (IF_SM | IF_SM2)) {
2035 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2036 asize = 0;
2037 for (i = 0; i < oprs; i++) {
2038 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2039 int j;
2040 for (j = 0; j < oprs; j++)
2041 size[j] = asize;
2042 break;
2043 }
2044 }
2045 } else {
2046 oprs = itemp->operands;
2047 }
2048
2049 for (i = 0; i < itemp->operands; i++) {
2050 if (!(itemp->opd[i] & SIZE_MASK) &&
2051 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2052 return 2;
2053 }
2054
2055 /*
2056 * Check template is okay at the set cpu level
2057 */
2058 if (((itemp->flags & IF_PLEVEL) > cpu))
2059 return 3;
2060
2061 /*
2062 * Check if instruction is available in long mode
2063 */
2064 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2065 return 4;
2066
2067 /*
2068 * Check if special handling needed for Jumps
2069 */
2070 if ((uint8_t)(itemp->code[0]) >= 0370)
2071 return 99;
2072
2073 return ret;
2074 }
2075
2076 static ea *process_ea(operand * input, ea * output, int bits,
2077 int addrbits, int rfield, int32_t rflags, int forw_ref)
2078 {
2079 output->rip = false;
2080
2081 /* REX flags for the rfield operand */
2082 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2083
2084 if (!(REGISTER & ~input->type)) { /* register direct */
2085 int i;
2086 int32_t f;
2087
2088 if (input->basereg < EXPR_REG_START /* Verify as Register */
2089 || input->basereg >= REG_ENUM_LIMIT)
2090 return NULL;
2091 f = regflag(input);
2092 i = nasm_regvals[input->basereg];
2093
2094 if (REG_EA & ~f)
2095 return NULL; /* Invalid EA register */
2096
2097 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2098
2099 output->sib_present = false; /* no SIB necessary */
2100 output->bytes = 0; /* no offset necessary either */
2101 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2102 } else { /* it's a memory reference */
2103 if (input->basereg == -1
2104 && (input->indexreg == -1 || input->scale == 0)) {
2105 /* it's a pure offset */
2106 if (bits == 64 && (~input->type & IP_REL)) {
2107 int scale, index, base;
2108 output->sib_present = true;
2109 scale = 0;
2110 index = 4;
2111 base = 5;
2112 output->sib = (scale << 6) | (index << 3) | base;
2113 output->bytes = 4;
2114 output->modrm = 4 | ((rfield & 7) << 3);
2115 output->rip = false;
2116 } else {
2117 output->sib_present = false;
2118 output->bytes = (addrbits != 16 ? 4 : 2);
2119 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2120 output->rip = bits == 64;
2121 }
2122 } else { /* it's an indirection */
2123 int i = input->indexreg, b = input->basereg, s = input->scale;
2124 int32_t o = input->offset, seg = input->segment;
2125 int hb = input->hintbase, ht = input->hinttype;
2126 int t;
2127 int it, bt;
2128 int32_t ix, bx; /* register flags */
2129
2130 if (s == 0)
2131 i = -1; /* make this easy, at least */
2132
2133 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2134 it = nasm_regvals[i];
2135 ix = nasm_reg_flags[i];
2136 } else {
2137 it = -1;
2138 ix = 0;
2139 }
2140
2141 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2142 bt = nasm_regvals[b];
2143 bx = nasm_reg_flags[b];
2144 } else {
2145 bt = -1;
2146 bx = 0;
2147 }
2148
2149 /* check for a 32/64-bit memory reference... */
2150 if ((ix|bx) & (BITS32|BITS64)) {
2151 /* it must be a 32/64-bit memory reference. Firstly we have
2152 * to check that all registers involved are type E/Rxx. */
2153 int32_t sok = BITS32|BITS64;
2154
2155 if (it != -1) {
2156 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2157 sok &= ix;
2158 else
2159 return NULL;
2160 }
2161
2162 if (bt != -1) {
2163 if (REG_GPR & ~bx)
2164 return NULL; /* Invalid register */
2165 if (~sok & bx & SIZE_MASK)
2166 return NULL; /* Invalid size */
2167 sok &= bx;
2168 }
2169
2170 /* While we're here, ensure the user didn't specify
2171 WORD or QWORD. */
2172 if (input->disp_size == 16 || input->disp_size == 64)
2173 return NULL;
2174
2175 if (addrbits == 16 ||
2176 (addrbits == 32 && !(sok & BITS32)) ||
2177 (addrbits == 64 && !(sok & BITS64)))
2178 return NULL;
2179
2180 /* now reorganize base/index */
2181 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2182 ((hb == b && ht == EAH_NOTBASE)
2183 || (hb == i && ht == EAH_MAKEBASE))) {
2184 /* swap if hints say so */
2185 t = bt, bt = it, it = t;
2186 t = bx, bx = ix, ix = t;
2187 }
2188 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2189 bt = -1, bx = 0, s++;
2190 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2191 /* make single reg base, unless hint */
2192 bt = it, bx = ix, it = -1, ix = 0;
2193 }
2194 if (((s == 2 && it != REG_NUM_ESP
2195 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2196 || s == 5 || s == 9) && bt == -1)
2197 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2198 if (it == -1 && (bt & 7) != REG_NUM_ESP
2199 && (input->eaflags & EAF_TIMESTWO))
2200 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2201 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2202 if (s == 1 && it == REG_NUM_ESP) {
2203 /* swap ESP into base if scale is 1 */
2204 t = it, it = bt, bt = t;
2205 t = ix, ix = bx, bx = t;
2206 }
2207 if (it == REG_NUM_ESP
2208 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2209 return NULL; /* wrong, for various reasons */
2210
2211 output->rex |= rexflags(it, ix, REX_X);
2212 output->rex |= rexflags(bt, bx, REX_B);
2213
2214 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2215 /* no SIB needed */
2216 int mod, rm;
2217
2218 if (bt == -1) {
2219 rm = 5;
2220 mod = 0;
2221 } else {
2222 rm = (bt & 7);
2223 if (rm != REG_NUM_EBP && o == 0 &&
2224 seg == NO_SEG && !forw_ref &&
2225 !(input->eaflags &
2226 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2227 mod = 0;
2228 else if (input->eaflags & EAF_BYTEOFFS ||
2229 (o >= -128 && o <= 127 && seg == NO_SEG
2230 && !forw_ref
2231 && !(input->eaflags & EAF_WORDOFFS)))
2232 mod = 1;
2233 else
2234 mod = 2;
2235 }
2236
2237 output->sib_present = false;
2238 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2239 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2240 } else {
2241 /* we need a SIB */
2242 int mod, scale, index, base;
2243
2244 if (it == -1)
2245 index = 4, s = 1;
2246 else
2247 index = (it & 7);
2248
2249 switch (s) {
2250 case 1:
2251 scale = 0;
2252 break;
2253 case 2:
2254 scale = 1;
2255 break;
2256 case 4:
2257 scale = 2;
2258 break;
2259 case 8:
2260 scale = 3;
2261 break;
2262 default: /* then what the smeg is it? */
2263 return NULL; /* panic */
2264 }
2265
2266 if (bt == -1) {
2267 base = 5;
2268 mod = 0;
2269 } else {
2270 base = (bt & 7);
2271 if (base != REG_NUM_EBP && o == 0 &&
2272 seg == NO_SEG && !forw_ref &&
2273 !(input->eaflags &
2274 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2275 mod = 0;
2276 else if (input->eaflags & EAF_BYTEOFFS ||
2277 (o >= -128 && o <= 127 && seg == NO_SEG
2278 && !forw_ref
2279 && !(input->eaflags & EAF_WORDOFFS)))
2280 mod = 1;
2281 else
2282 mod = 2;
2283 }
2284
2285 output->sib_present = true;
2286 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2287 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2288 output->sib = (scale << 6) | (index << 3) | base;
2289 }
2290 } else { /* it's 16-bit */
2291 int mod, rm;
2292
2293 /* check for 64-bit long mode */
2294 if (addrbits == 64)
2295 return NULL;
2296
2297 /* check all registers are BX, BP, SI or DI */
2298 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2299 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2300 && i != R_SI && i != R_DI))
2301 return NULL;
2302
2303 /* ensure the user didn't specify DWORD/QWORD */
2304 if (input->disp_size == 32 || input->disp_size == 64)
2305 return NULL;
2306
2307 if (s != 1 && i != -1)
2308 return NULL; /* no can do, in 16-bit EA */
2309 if (b == -1 && i != -1) {
2310 int tmp = b;
2311 b = i;
2312 i = tmp;
2313 } /* swap */
2314 if ((b == R_SI || b == R_DI) && i != -1) {
2315 int tmp = b;
2316 b = i;
2317 i = tmp;
2318 }
2319 /* have BX/BP as base, SI/DI index */
2320 if (b == i)
2321 return NULL; /* shouldn't ever happen, in theory */
2322 if (i != -1 && b != -1 &&
2323 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2324 return NULL; /* invalid combinations */
2325 if (b == -1) /* pure offset: handled above */
2326 return NULL; /* so if it gets to here, panic! */
2327
2328 rm = -1;
2329 if (i != -1)
2330 switch (i * 256 + b) {
2331 case R_SI * 256 + R_BX:
2332 rm = 0;
2333 break;
2334 case R_DI * 256 + R_BX:
2335 rm = 1;
2336 break;
2337 case R_SI * 256 + R_BP:
2338 rm = 2;
2339 break;
2340 case R_DI * 256 + R_BP:
2341 rm = 3;
2342 break;
2343 } else
2344 switch (b) {
2345 case R_SI:
2346 rm = 4;
2347 break;
2348 case R_DI:
2349 rm = 5;
2350 break;
2351 case R_BP:
2352 rm = 6;
2353 break;
2354 case R_BX:
2355 rm = 7;
2356 break;
2357 }
2358 if (rm == -1) /* can't happen, in theory */
2359 return NULL; /* so panic if it does */
2360
2361 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2362 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2363 mod = 0;
2364 else if (input->eaflags & EAF_BYTEOFFS ||
2365 (o >= -128 && o <= 127 && seg == NO_SEG
2366 && !forw_ref
2367 && !(input->eaflags & EAF_WORDOFFS)))
2368 mod = 1;
2369 else
2370 mod = 2;
2371
2372 output->sib_present = false; /* no SIB - it's 16-bit */
2373 output->bytes = mod; /* bytes of offset needed */
2374 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2375 }
2376 }
2377 }
2378
2379 output->size = 1 + output->sib_present + output->bytes;
2380 return output;
2381 }
2382
2383 static void add_asp(insn *ins, int addrbits)
2384 {
2385 int j, valid;
2386 int defdisp;
2387
2388 valid = (addrbits == 64) ? 64|32 : 32|16;
2389
2390 switch (ins->prefixes[PPS_ASIZE]) {
2391 case P_A16:
2392 valid &= 16;
2393 break;
2394 case P_A32:
2395 valid &= 32;
2396 break;
2397 case P_A64:
2398 valid &= 64;
2399 break;
2400 case P_ASP:
2401 valid &= (addrbits == 32) ? 16 : 32;
2402 break;
2403 default:
2404 break;
2405 }
2406
2407 for (j = 0; j < ins->operands; j++) {
2408 if (!(MEMORY & ~ins->oprs[j].type)) {
2409 int32_t i, b;
2410
2411 /* Verify as Register */
2412 if (ins->oprs[j].indexreg < EXPR_REG_START
2413 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2414 i = 0;
2415 else
2416 i = nasm_reg_flags[ins->oprs[j].indexreg];
2417
2418 /* Verify as Register */
2419 if (ins->oprs[j].basereg < EXPR_REG_START
2420 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2421 b = 0;
2422 else
2423 b = nasm_reg_flags[ins->oprs[j].basereg];
2424
2425 if (ins->oprs[j].scale == 0)
2426 i = 0;
2427
2428 if (!i && !b) {
2429 int ds = ins->oprs[j].disp_size;
2430 if ((addrbits != 64 && ds > 8) ||
2431 (addrbits == 64 && ds == 16))
2432 valid &= ds;
2433 } else {
2434 if (!(REG16 & ~b))
2435 valid &= 16;
2436 if (!(REG32 & ~b))
2437 valid &= 32;
2438 if (!(REG64 & ~b))
2439 valid &= 64;
2440
2441 if (!(REG16 & ~i))
2442 valid &= 16;
2443 if (!(REG32 & ~i))
2444 valid &= 32;
2445 if (!(REG64 & ~i))
2446 valid &= 64;
2447 }
2448 }
2449 }
2450
2451 if (valid & addrbits) {
2452 ins->addr_size = addrbits;
2453 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2454 /* Add an address size prefix */
2455 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2456 ins->prefixes[PPS_ASIZE] = pref;
2457 ins->addr_size = (addrbits == 32) ? 16 : 32;
2458 } else {
2459 /* Impossible... */
2460 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2461 ins->addr_size = addrbits; /* Error recovery */
2462 }
2463
2464 defdisp = ins->addr_size == 16 ? 16 : 32;
2465
2466 for (j = 0; j < ins->operands; j++) {
2467 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2468 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2469 != ins->addr_size) {
2470 /* mem_offs sizes must match the address size; if not,
2471 strip the MEM_OFFS bit and match only EA instructions */
2472 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2473 }
2474 }
2475 }
Adding AVX-512 features