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NASM 2.05rc3
[nasm/avx512.git] / disasm.c
blob0ff40fc1018f445436b7ff9a979c98b55efa0a4e
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 struct operand *opx;
378 int s_field_for = -1; /* No 144/154 series code encountered */
379 bool vex_ok = false;
380 int regmask = (segsize == 64) ? 15 : 7;
381
382 for (i = 0; i < MAX_OPERANDS; i++) {
383 ins->oprs[i].segment = ins->oprs[i].disp_size =
384 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
385 }
386 ins->condition = -1;
387 ins->rex = prefix->rex;
388 memset(ins->prefixes, 0, sizeof ins->prefixes);
389
390 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
391 return false;
392
393 if (prefix->rep == 0xF2)
394 drep = P_REPNE;
395 else if (prefix->rep == 0xF3)
396 drep = P_REP;
397
398 while ((c = *r++) != 0) {
399 opx = &ins->oprs[c & 3];
400
401 switch (c) {
402 case 01:
403 case 02:
404 case 03:
405 while (c--)
406 if (*r++ != *data++)
407 return false;
408 break;
409
410 case 04:
411 switch (*data++) {
412 case 0x07:
413 ins->oprs[0].basereg = 0;
414 break;
415 case 0x17:
416 ins->oprs[0].basereg = 2;
417 break;
418 case 0x1F:
419 ins->oprs[0].basereg = 3;
420 break;
421 default:
422 return false;
423 }
424 break;
425
426 case 05:
427 switch (*data++) {
428 case 0xA1:
429 ins->oprs[0].basereg = 4;
430 break;
431 case 0xA9:
432 ins->oprs[0].basereg = 5;
433 break;
434 default:
435 return false;
436 }
437 break;
438
439 case 06:
440 switch (*data++) {
441 case 0x06:
442 ins->oprs[0].basereg = 0;
443 break;
444 case 0x0E:
445 ins->oprs[0].basereg = 1;
446 break;
447 case 0x16:
448 ins->oprs[0].basereg = 2;
449 break;
450 case 0x1E:
451 ins->oprs[0].basereg = 3;
452 break;
453 default:
454 return false;
455 }
456 break;
457
458 case 07:
459 switch (*data++) {
460 case 0xA0:
461 ins->oprs[0].basereg = 4;
462 break;
463 case 0xA8:
464 ins->oprs[0].basereg = 5;
465 break;
466 default:
467 return false;
468 }
469 break;
470
471 case4(010):
472 {
473 int t = *r++, d = *data++;
474 if (d < t || d > t + 7)
475 return false;
476 else {
477 opx->basereg = (d-t)+
478 (ins->rex & REX_B ? 8 : 0);
479 opx->segment |= SEG_RMREG;
480 }
481 break;
482 }
483
484 case4(014):
485 case4(0274):
486 opx->offset = (int8_t)*data++;
487 opx->segment |= SEG_SIGNED;
488 break;
489
490 case4(020):
491 opx->offset = *data++;
492 break;
493
494 case4(024):
495 opx->offset = *data++;
496 break;
497
498 case4(030):
499 opx->offset = getu16(data);
500 data += 2;
501 break;
502
503 case4(034):
504 if (osize == 32) {
505 opx->offset = getu32(data);
506 data += 4;
507 } else {
508 opx->offset = getu16(data);
509 data += 2;
510 }
511 if (segsize != asize)
512 opx->disp_size = asize;
513 break;
514
515 case4(040):
516 case4(0254):
517 opx->offset = getu32(data);
518 data += 4;
519 break;
520
521 case4(044):
522 switch (asize) {
523 case 16:
524 opx->offset = getu16(data);
525 data += 2;
526 if (segsize != 16)
527 opx->disp_size = 16;
528 break;
529 case 32:
530 opx->offset = getu32(data);
531 data += 4;
532 if (segsize == 16)
533 opx->disp_size = 32;
534 break;
535 case 64:
536 opx->offset = getu64(data);
537 opx->disp_size = 64;
538 data += 8;
539 break;
540 }
541 break;
542
543 case4(050):
544 opx->offset = gets8(data++);
545 opx->segment |= SEG_RELATIVE;
546 break;
547
548 case4(054):
549 opx->offset = getu64(data);
550 data += 8;
551 break;
552
553 case4(060):
554 opx->offset = gets16(data);
555 data += 2;
556 opx->segment |= SEG_RELATIVE;
557 opx->segment &= ~SEG_32BIT;
558 break;
559
560 case4(064):
561 opx->segment |= SEG_RELATIVE;
562 if (osize == 16) {
563 opx->offset = gets16(data);
564 data += 2;
565 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
566 } else if (osize == 32) {
567 opx->offset = gets32(data);
568 data += 4;
569 opx->segment &= ~SEG_64BIT;
570 opx->segment |= SEG_32BIT;
571 }
572 if (segsize != osize) {
573 opx->type =
574 (opx->type & ~SIZE_MASK)
575 | ((osize == 16) ? BITS16 : BITS32);
576 }
577 break;
578
579 case4(070):
580 opx->offset = gets32(data);
581 data += 4;
582 opx->segment |= SEG_32BIT | SEG_RELATIVE;
583 break;
584
585 case4(0100):
586 case4(0110):
587 case4(0120):
588 case4(0130):
589 {
590 int modrm = *data++;
591 opx->segment |= SEG_RMREG;
592 data = do_ea(data, modrm, asize, segsize,
593 &ins->oprs[(c >> 3) & 3], ins);
594 if (!data)
595 return false;
596 opx->basereg = ((modrm >> 3)&7)+
597 (ins->rex & REX_R ? 8 : 0);
598 break;
599 }
600
601 case4(0140):
602 if (s_field_for == (c & 3)) {
603 opx->offset = gets8(data);
604 data++;
605 } else {
606 opx->offset = getu16(data);
607 data += 2;
608 }
609 break;
610
611 case4(0144):
612 case4(0154):
613 s_field_for = (*data & 0x02) ? c & 3 : -1;
614 if ((*data++ & ~0x02) != *r++)
615 return false;
616 break;
617
618 case4(0150):
619 if (s_field_for == (c & 3)) {
620 opx->offset = gets8(data);
621 data++;
622 } else {
623 opx->offset = getu32(data);
624 data += 4;
625 }
626 break;
627
628 case4(0160):
629 ins->rex |= REX_D;
630 ins->drexdst = c & 3;
631 break;
632
633 case4(0164):
634 ins->rex |= REX_D|REX_OC;
635 ins->drexdst = c & 3;
636 break;
637
638 case 0171:
639 data = do_drex(data, ins);
640 if (!data)
641 return false;
642 break;
643
644 case 0172:
645 {
646 uint8_t ximm = *data++;
647 c = *r++;
648 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
649 ins->oprs[c >> 3].segment |= SEG_RMREG;
650 ins->oprs[c & 7].offset = ximm & 15;
651 }
652 break;
653
654 case 0173:
655 {
656 uint8_t ximm = *data++;
657 c = *r++;
658
659 if ((c ^ ximm) & 15)
660 return false;
661
662 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
663 ins->oprs[c >> 4].segment |= SEG_RMREG;
664 }
665 break;
666
667 case 0174:
668 {
669 uint8_t ximm = *data++;
670 c = *r++;
671
672 ins->oprs[c].basereg = (ximm >> 4) & regmask;
673 ins->oprs[c].segment |= SEG_RMREG;
674 }
675 break;
676
677 case4(0200):
678 case4(0204):
679 case4(0210):
680 case4(0214):
681 case4(0220):
682 case4(0224):
683 case4(0230):
684 case4(0234):
685 {
686 int modrm = *data++;
687 if (((modrm >> 3) & 07) != (c & 07))
688 return false; /* spare field doesn't match up */
689 data = do_ea(data, modrm, asize, segsize,
690 &ins->oprs[(c >> 3) & 07], ins);
691 if (!data)
692 return false;
693 break;
694 }
695
696 case4(0260):
697 {
698 int vexm = *r++;
699 int vexwlp = *r++;
700 ins->rex |= REX_V;
701 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
702 return false;
703
704 if ((vexm & 0x1f) != prefix->vex_m)
705 return false;
706
707 switch (vexwlp & 030) {
708 case 000:
709 if (prefix->rex & REX_W)
710 return false;
711 break;
712 case 010:
713 if (!(prefix->rex & REX_W))
714 return false;
715 ins->rex &= ~REX_W;
716 break;
717 case 020: /* VEX.W is a don't care */
718 ins->rex &= ~REX_W;
719 break;
720 case 030:
721 break;
722 }
723
724 if ((vexwlp & 007) != prefix->vex_lp)
725 return false;
726
727 opx->segment |= SEG_RMREG;
728 opx->basereg = prefix->vex_v;
729 vex_ok = true;
730 break;
731 }
732
733 case 0270:
734 {
735 int vexm = *r++;
736 int vexwlp = *r++;
737 ins->rex |= REX_V;
738 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
739 return false;
740
741 if ((vexm & 0x1f) != prefix->vex_m)
742 return false;
743
744 switch (vexwlp & 030) {
745 case 000:
746 if (ins->rex & REX_W)
747 return false;
748 break;
749 case 010:
750 if (!(ins->rex & REX_W))
751 return false;
752 break;
753 default:
754 break; /* Need to do anything special here? */
755 }
756
757 if ((vexwlp & 007) != prefix->vex_lp)
758 return false;
759
760 if (prefix->vex_v != 0)
761 return false;
762
763 vex_ok = true;
764 break;
765 }
766
767 case 0310:
768 if (asize != 16)
769 return false;
770 else
771 a_used = true;
772 break;
773
774 case 0311:
775 if (asize == 16)
776 return false;
777 else
778 a_used = true;
779 break;
780
781 case 0312:
782 if (asize != segsize)
783 return false;
784 else
785 a_used = true;
786 break;
787
788 case 0313:
789 if (asize != 64)
790 return false;
791 else
792 a_used = true;
793 break;
794
795 case 0314:
796 if (prefix->rex & REX_B)
797 return false;
798 break;
799
800 case 0315:
801 if (prefix->rex & REX_X)
802 return false;
803 break;
804
805 case 0316:
806 if (prefix->rex & REX_R)
807 return false;
808 break;
809
810 case 0317:
811 if (prefix->rex & REX_W)
812 return false;
813 break;
814
815 case 0320:
816 if (osize != 16)
817 return false;
818 else
819 o_used = true;
820 break;
821
822 case 0321:
823 if (osize != 32)
824 return false;
825 else
826 o_used = true;
827 break;
828
829 case 0322:
830 if (osize != (segsize == 16) ? 16 : 32)
831 return false;
832 else
833 o_used = true;
834 break;
835
836 case 0323:
837 ins->rex |= REX_W; /* 64-bit only instruction */
838 osize = 64;
839 o_used = true;
840 break;
841
842 case 0324:
843 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
844 return false;
845 o_used = true;
846 break;
847
848 case 0330:
849 {
850 int t = *r++, d = *data++;
851 if (d < t || d > t + 15)
852 return false;
853 else
854 ins->condition = d - t;
855 break;
856 }
857
858 case 0331:
859 if (prefix->rep)
860 return false;
861 break;
862
863 case 0332:
864 if (prefix->rep != 0xF2)
865 return false;
866 drep = 0;
867 break;
868
869 case 0333:
870 if (prefix->rep != 0xF3)
871 return false;
872 drep = 0;
873 break;
874
875 case 0334:
876 if (lock) {
877 ins->rex |= REX_R;
878 lock = 0;
879 }
880 break;
881
882 case 0335:
883 if (drep == P_REP)
884 drep = P_REPE;
885 break;
886
887 case 0336:
888 case 0337:
889 break;
890
891 case 0340:
892 return false;
893
894 case 0360:
895 if (prefix->osp || prefix->rep)
896 return false;
897 break;
898
899 case 0361:
900 if (!prefix->osp || prefix->rep)
901 return false;
902 o_used = true;
903 break;
904
905 case 0362:
906 if (prefix->osp || prefix->rep != 0xf2)
907 return false;
908 drep = 0;
909 break;
910
911 case 0363:
912 if (prefix->osp || prefix->rep != 0xf3)
913 return false;
914 drep = 0;
915 break;
916
917 case 0364:
918 if (prefix->osp)
919 return false;
920 break;
921
922 case 0365:
923 if (prefix->asp)
924 return false;
925 break;
926
927 case 0366:
928 if (!prefix->osp)
929 return false;
930 o_used = true;
931 break;
932
933 case 0367:
934 if (!prefix->asp)
935 return false;
936 a_used = true;
937 break;
938
939 default:
940 return false; /* Unknown code */
941 }
942 }
943
944 if (!vex_ok && (ins->rex & REX_V))
945 return false;
946
947 /* REX cannot be combined with DREX or VEX */
948 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
949 return false;
950
951 /*
952 * Check for unused rep or a/o prefixes.
953 */
954 for (i = 0; i < t->operands; i++) {
955 if (ins->oprs[i].segment != SEG_RMREG)
956 a_used = true;
957 }
958
959 if (lock) {
960 if (ins->prefixes[PPS_LREP])
961 return false;
962 ins->prefixes[PPS_LREP] = P_LOCK;
963 }
964 if (drep) {
965 if (ins->prefixes[PPS_LREP])
966 return false;
967 ins->prefixes[PPS_LREP] = drep;
968 }
969 if (!o_used) {
970 if (osize != ((segsize == 16) ? 16 : 32)) {
971 enum prefixes pfx = 0;
972
973 switch (osize) {
974 case 16:
975 pfx = P_O16;
976 break;
977 case 32:
978 pfx = P_O32;
979 break;
980 case 64:
981 pfx = P_O64;
982 break;
983 }
984
985 if (ins->prefixes[PPS_OSIZE])
986 return false;
987 ins->prefixes[PPS_OSIZE] = pfx;
988 }
989 }
990 if (!a_used && asize != segsize) {
991 if (ins->prefixes[PPS_ASIZE])
992 return false;
993 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
994 }
995
996 /* Fix: check for redundant REX prefixes */
997
998 return data - origdata;
999 }
1000
1001 /* Condition names for disassembly, sorted by x86 code */
1002 static const char * const condition_name[16] = {
1003 "o", "no", "c", "nc", "z", "nz", "na", "a",
1004 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1005 };
1006
1007 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1008 int32_t offset, int autosync, uint32_t prefer)
1009 {
1010 const struct itemplate * const *p, * const *best_p;
1011 const struct disasm_index *ix;
1012 uint8_t *dp;
1013 int length, best_length = 0;
1014 char *segover;
1015 int i, slen, colon, n;
1016 uint8_t *origdata;
1017 int works;
1018 insn tmp_ins, ins;
1019 uint32_t goodness, best;
1020 int best_pref;
1021 struct prefix_info prefix;
1022 bool end_prefix;
1023
1024 memset(&ins, 0, sizeof ins);
1025
1026 /*
1027 * Scan for prefixes.
1028 */
1029 memset(&prefix, 0, sizeof prefix);
1030 prefix.asize = segsize;
1031 prefix.osize = (segsize == 64) ? 32 : segsize;
1032 segover = NULL;
1033 origdata = data;
1034
1035 ix = itable;
1036
1037 end_prefix = false;
1038 while (!end_prefix) {
1039 switch (*data) {
1040 case 0xF2:
1041 case 0xF3:
1042 prefix.rep = *data++;
1043 break;
1044
1045 case 0xF0:
1046 prefix.lock = *data++;
1047 break;
1048
1049 case 0x2E:
1050 segover = "cs", prefix.seg = *data++;
1051 break;
1052 case 0x36:
1053 segover = "ss", prefix.seg = *data++;
1054 break;
1055 case 0x3E:
1056 segover = "ds", prefix.seg = *data++;
1057 break;
1058 case 0x26:
1059 segover = "es", prefix.seg = *data++;
1060 break;
1061 case 0x64:
1062 segover = "fs", prefix.seg = *data++;
1063 break;
1064 case 0x65:
1065 segover = "gs", prefix.seg = *data++;
1066 break;
1067
1068 case 0x66:
1069 prefix.osize = (segsize == 16) ? 32 : 16;
1070 prefix.osp = *data++;
1071 break;
1072 case 0x67:
1073 prefix.asize = (segsize == 32) ? 16 : 32;
1074 prefix.asp = *data++;
1075 break;
1076
1077 case 0xC4:
1078 case 0xC5:
1079 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1080 prefix.vex[0] = *data++;
1081 prefix.vex[1] = *data++;
1082
1083 prefix.rex = REX_V;
1084
1085 if (prefix.vex[0] == 0xc4) {
1086 prefix.vex[2] = *data++;
1087 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1088 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1089 prefix.vex_m = prefix.vex[1] & 0x1f;
1090 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1091 prefix.vex_lp = prefix.vex[2] & 7;
1092 } else {
1093 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1094 prefix.vex_m = 1;
1095 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1096 prefix.vex_lp = prefix.vex[1] & 7;
1097 }
1098
1099 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1100 }
1101 end_prefix = true;
1102 break;
1103
1104 case REX_P + 0x0:
1105 case REX_P + 0x1:
1106 case REX_P + 0x2:
1107 case REX_P + 0x3:
1108 case REX_P + 0x4:
1109 case REX_P + 0x5:
1110 case REX_P + 0x6:
1111 case REX_P + 0x7:
1112 case REX_P + 0x8:
1113 case REX_P + 0x9:
1114 case REX_P + 0xA:
1115 case REX_P + 0xB:
1116 case REX_P + 0xC:
1117 case REX_P + 0xD:
1118 case REX_P + 0xE:
1119 case REX_P + 0xF:
1120 if (segsize == 64) {
1121 prefix.rex = *data++;
1122 if (prefix.rex & REX_W)
1123 prefix.osize = 64;
1124 }
1125 end_prefix = true;
1126 break;
1127
1128 default:
1129 end_prefix = true;
1130 break;
1131 }
1132 }
1133
1134 best = -1; /* Worst possible */
1135 best_p = NULL;
1136 best_pref = INT_MAX;
1137
1138 if (!ix)
1139 return 0; /* No instruction table at all... */
1140
1141 dp = data;
1142 ix += *dp++;
1143 while (ix->n == -1) {
1144 ix = (const struct disasm_index *)ix->p + *dp++;
1145 }
1146
1147 p = (const struct itemplate * const *)ix->p;
1148 for (n = ix->n; n; n--, p++) {
1149 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1150 works = true;
1151 /*
1152 * Final check to make sure the types of r/m match up.
1153 * XXX: Need to make sure this is actually correct.
1154 */
1155 for (i = 0; i < (*p)->operands; i++) {
1156 if (!((*p)->opd[i] & SAME_AS) &&
1157 (
1158 /* If it's a mem-only EA but we have a
1159 register, die. */
1160 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1161 !(MEMORY & ~(*p)->opd[i])) ||
1162 /* If it's a reg-only EA but we have a memory
1163 ref, die. */
1164 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1165 !(REG_EA & ~(*p)->opd[i]) &&
1166 !((*p)->opd[i] & REG_SMASK)) ||
1167 /* Register type mismatch (eg FS vs REG_DESS):
1168 die. */
1169 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1170 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1171 !whichreg((*p)->opd[i],
1172 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1173 )) {
1174 works = false;
1175 break;
1176 }
1177 }
1178
1179 /*
1180 * Note: we always prefer instructions which incorporate
1181 * prefixes in the instructions themselves. This is to allow
1182 * e.g. PAUSE to be preferred to REP NOP, and deal with
1183 * MMX/SSE instructions where prefixes are used to select
1184 * between MMX and SSE register sets or outright opcode
1185 * selection.
1186 */
1187 if (works) {
1188 int i, nprefix;
1189 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1190 nprefix = 0;
1191 for (i = 0; i < MAXPREFIX; i++)
1192 if (tmp_ins.prefixes[i])
1193 nprefix++;
1194 if (nprefix < best_pref ||
1195 (nprefix == best_pref && goodness < best)) {
1196 /* This is the best one found so far */
1197 best = goodness;
1198 best_p = p;
1199 best_pref = nprefix;
1200 best_length = length;
1201 ins = tmp_ins;
1202 }
1203 }
1204 }
1205 }
1206
1207 if (!best_p)
1208 return 0; /* no instruction was matched */
1209
1210 /* Pick the best match */
1211 p = best_p;
1212 length = best_length;
1213
1214 slen = 0;
1215
1216 /* TODO: snprintf returns the value that the string would have if
1217 * the buffer were long enough, and not the actual length of
1218 * the returned string, so each instance of using the return
1219 * value of snprintf should actually be checked to assure that
1220 * the return value is "sane." Maybe a macro wrapper could
1221 * be used for that purpose.
1222 */
1223 for (i = 0; i < MAXPREFIX; i++)
1224 switch (ins.prefixes[i]) {
1225 case P_LOCK:
1226 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1227 break;
1228 case P_REP:
1229 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1230 break;
1231 case P_REPE:
1232 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1233 break;
1234 case P_REPNE:
1235 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1236 break;
1237 case P_A16:
1238 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1239 break;
1240 case P_A32:
1241 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1242 break;
1243 case P_A64:
1244 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1245 break;
1246 case P_O16:
1247 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1248 break;
1249 case P_O32:
1250 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1251 break;
1252 case P_O64:
1253 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1254 break;
1255 default:
1256 break;
1257 }
1258
1259 i = (*p)->opcode;
1260 if (i >= FIRST_COND_OPCODE)
1261 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1262 nasm_insn_names[i], condition_name[ins.condition]);
1263 else
1264 slen += snprintf(output + slen, outbufsize - slen, "%s",
1265 nasm_insn_names[i]);
1266
1267 colon = false;
1268 length += data - origdata; /* fix up for prefixes */
1269 for (i = 0; i < (*p)->operands; i++) {
1270 opflags_t t = (*p)->opd[i];
1271 const operand *o = &ins.oprs[i];
1272 int64_t offs;
1273
1274 if (t & SAME_AS) {
1275 o = &ins.oprs[t & ~SAME_AS];
1276 t = (*p)->opd[t & ~SAME_AS];
1277 }
1278
1279 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1280
1281 offs = o->offset;
1282 if (o->segment & SEG_RELATIVE) {
1283 offs += offset + length;
1284 /*
1285 * sort out wraparound
1286 */
1287 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1288 offs &= 0xffff;
1289 else if (segsize != 64)
1290 offs &= 0xffffffff;
1291
1292 /*
1293 * add sync marker, if autosync is on
1294 */
1295 if (autosync)
1296 add_sync(offs, 0L);
1297 }
1298
1299 if (t & COLON)
1300 colon = true;
1301 else
1302 colon = false;
1303
1304 if ((t & (REGISTER | FPUREG)) ||
1305 (o->segment & SEG_RMREG)) {
1306 enum reg_enum reg;
1307 reg = whichreg(t, o->basereg, ins.rex);
1308 if (t & TO)
1309 slen += snprintf(output + slen, outbufsize - slen, "to ");
1310 slen += snprintf(output + slen, outbufsize - slen, "%s",
1311 nasm_reg_names[reg-EXPR_REG_START]);
1312 } else if (!(UNITY & ~t)) {
1313 output[slen++] = '1';
1314 } else if (t & IMMEDIATE) {
1315 if (t & BITS8) {
1316 slen +=
1317 snprintf(output + slen, outbufsize - slen, "byte ");
1318 if (o->segment & SEG_SIGNED) {
1319 if (offs < 0) {
1320 offs *= -1;
1321 output[slen++] = '-';
1322 } else
1323 output[slen++] = '+';
1324 }
1325 } else if (t & BITS16) {
1326 slen +=
1327 snprintf(output + slen, outbufsize - slen, "word ");
1328 } else if (t & BITS32) {
1329 slen +=
1330 snprintf(output + slen, outbufsize - slen, "dword ");
1331 } else if (t & BITS64) {
1332 slen +=
1333 snprintf(output + slen, outbufsize - slen, "qword ");
1334 } else if (t & NEAR) {
1335 slen +=
1336 snprintf(output + slen, outbufsize - slen, "near ");
1337 } else if (t & SHORT) {
1338 slen +=
1339 snprintf(output + slen, outbufsize - slen, "short ");
1340 }
1341 slen +=
1342 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1343 offs);
1344 } else if (!(MEM_OFFS & ~t)) {
1345 slen +=
1346 snprintf(output + slen, outbufsize - slen,
1347 "[%s%s%s0x%"PRIx64"]",
1348 (segover ? segover : ""),
1349 (segover ? ":" : ""),
1350 (o->disp_size == 64 ? "qword " :
1351 o->disp_size == 32 ? "dword " :
1352 o->disp_size == 16 ? "word " : ""), offs);
1353 segover = NULL;
1354 } else if (!(REGMEM & ~t)) {
1355 int started = false;
1356 if (t & BITS8)
1357 slen +=
1358 snprintf(output + slen, outbufsize - slen, "byte ");
1359 if (t & BITS16)
1360 slen +=
1361 snprintf(output + slen, outbufsize - slen, "word ");
1362 if (t & BITS32)
1363 slen +=
1364 snprintf(output + slen, outbufsize - slen, "dword ");
1365 if (t & BITS64)
1366 slen +=
1367 snprintf(output + slen, outbufsize - slen, "qword ");
1368 if (t & BITS80)
1369 slen +=
1370 snprintf(output + slen, outbufsize - slen, "tword ");
1371 if (t & BITS128)
1372 slen +=
1373 snprintf(output + slen, outbufsize - slen, "oword ");
1374 if (t & BITS256)
1375 slen +=
1376 snprintf(output + slen, outbufsize - slen, "yword ");
1377 if (t & FAR)
1378 slen += snprintf(output + slen, outbufsize - slen, "far ");
1379 if (t & NEAR)
1380 slen +=
1381 snprintf(output + slen, outbufsize - slen, "near ");
1382 output[slen++] = '[';
1383 if (o->disp_size)
1384 slen += snprintf(output + slen, outbufsize - slen, "%s",
1385 (o->disp_size == 64 ? "qword " :
1386 o->disp_size == 32 ? "dword " :
1387 o->disp_size == 16 ? "word " :
1388 ""));
1389 if (o->eaflags & EAF_REL)
1390 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1391 if (segover) {
1392 slen +=
1393 snprintf(output + slen, outbufsize - slen, "%s:",
1394 segover);
1395 segover = NULL;
1396 }
1397 if (o->basereg != -1) {
1398 slen += snprintf(output + slen, outbufsize - slen, "%s",
1399 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1400 started = true;
1401 }
1402 if (o->indexreg != -1) {
1403 if (started)
1404 output[slen++] = '+';
1405 slen += snprintf(output + slen, outbufsize - slen, "%s",
1406 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1407 if (o->scale > 1)
1408 slen +=
1409 snprintf(output + slen, outbufsize - slen, "*%d",
1410 o->scale);
1411 started = true;
1412 }
1413
1414
1415 if (o->segment & SEG_DISP8) {
1416 const char *prefix;
1417 uint8_t offset = offs;
1418 if ((int8_t)offset < 0) {
1419 prefix = "-";
1420 offset = -offset;
1421 } else {
1422 prefix = "+";
1423 }
1424 slen +=
1425 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1426 prefix, offset);
1427 } else if (o->segment & SEG_DISP16) {
1428 const char *prefix;
1429 uint16_t offset = offs;
1430 if ((int16_t)offset < 0 && started) {
1431 offset = -offset;
1432 prefix = "-";
1433 } else {
1434 prefix = started ? "+" : "";
1435 }
1436 slen +=
1437 snprintf(output + slen, outbufsize - slen,
1438 "%s0x%"PRIx16"", prefix, offset);
1439 } else if (o->segment & SEG_DISP32) {
1440 if (prefix.asize == 64) {
1441 const char *prefix;
1442 uint64_t offset = (int64_t)(int32_t)offs;
1443 if ((int32_t)offs < 0 && started) {
1444 offset = -offset;
1445 prefix = "-";
1446 } else {
1447 prefix = started ? "+" : "";
1448 }
1449 slen +=
1450 snprintf(output + slen, outbufsize - slen,
1451 "%s0x%"PRIx64"", prefix, offset);
1452 } else {
1453 const char *prefix;
1454 uint32_t offset = offs;
1455 if ((int32_t) offset < 0 && started) {
1456 offset = -offset;
1457 prefix = "-";
1458 } else {
1459 prefix = started ? "+" : "";
1460 }
1461 slen +=
1462 snprintf(output + slen, outbufsize - slen,
1463 "%s0x%"PRIx32"", prefix, offset);
1464 }
1465 }
1466 output[slen++] = ']';
1467 } else {
1468 slen +=
1469 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1470 i);
1471 }
1472 }
1473 output[slen] = '\0';
1474 if (segover) { /* unused segment override */
1475 char *p = output;
1476 int count = slen + 1;
1477 while (count--)
1478 p[count + 3] = p[count];
1479 strncpy(output, segover, 2);
1480 output[2] = ' ';
1481 }
1482 return length;
1483 }
1484
1485 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1486 {
1487 snprintf(output, outbufsize, "db 0x%02X", *data);
1488 return 1;
1489 }
Adding AVX-512 features